From 7fe60435bce6595a9c58a9bfd8244d74b5320e96 Mon Sep 17 00:00:00 2001 From: Benjamin Franzke Date: Tue, 15 Jan 2013 08:46:13 +0100 Subject: Import DirectFB141_2k11R3_beta5 --- Source/DirectFB/gfxdrivers/Makefile.am | 151 + Source/DirectFB/gfxdrivers/Makefile.in | 622 +++ Source/DirectFB/gfxdrivers/ati128/Makefile.am | 41 + Source/DirectFB/gfxdrivers/ati128/Makefile.in | 603 +++ Source/DirectFB/gfxdrivers/ati128/ati128.c | 842 ++++ Source/DirectFB/gfxdrivers/ati128/ati128.h | 76 + Source/DirectFB/gfxdrivers/ati128/ati128_overlay.c | 447 ++ Source/DirectFB/gfxdrivers/ati128/ati128_state.c | 314 ++ Source/DirectFB/gfxdrivers/ati128/ati128_state.h | 62 + Source/DirectFB/gfxdrivers/ati128/mmio.h | 121 + Source/DirectFB/gfxdrivers/ati128/regs.h | 919 ++++ Source/DirectFB/gfxdrivers/cle266/Makefile.am | 47 + Source/DirectFB/gfxdrivers/cle266/Makefile.in | 619 +++ Source/DirectFB/gfxdrivers/cle266/mmio.h | 43 + Source/DirectFB/gfxdrivers/cle266/regs2d.h | 197 + Source/DirectFB/gfxdrivers/cle266/regs3d.h | 1641 +++++++ Source/DirectFB/gfxdrivers/cle266/uc_accel.c | 504 ++ Source/DirectFB/gfxdrivers/cle266/uc_accel.h | 119 + Source/DirectFB/gfxdrivers/cle266/uc_fifo.c | 198 + Source/DirectFB/gfxdrivers/cle266/uc_fifo.h | 268 ++ Source/DirectFB/gfxdrivers/cle266/uc_hw.h | 93 + Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c | 357 ++ Source/DirectFB/gfxdrivers/cle266/uc_hwset.c | 419 ++ Source/DirectFB/gfxdrivers/cle266/uc_overlay.c | 320 ++ Source/DirectFB/gfxdrivers/cle266/uc_overlay.h | 85 + Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c | 560 +++ Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c | 266 ++ Source/DirectFB/gfxdrivers/cle266/uc_primary.c | 176 + Source/DirectFB/gfxdrivers/cle266/uc_state.c | 269 ++ Source/DirectFB/gfxdrivers/cle266/uc_state.h | 68 + Source/DirectFB/gfxdrivers/cle266/unichrome.c | 548 +++ Source/DirectFB/gfxdrivers/cle266/unichrome.h | 140 + Source/DirectFB/gfxdrivers/cle266/vidregs.h | 498 ++ Source/DirectFB/gfxdrivers/cyber5k/Makefile.am | 41 + Source/DirectFB/gfxdrivers/cyber5k/Makefile.in | 607 +++ Source/DirectFB/gfxdrivers/cyber5k/cyber5k.c | 824 ++++ Source/DirectFB/gfxdrivers/cyber5k/cyber5k.h | 63 + Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.c | 260 ++ Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.h | 64 + .../DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.c | 376 ++ .../DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.h | 92 + .../DirectFB/gfxdrivers/cyber5k/cyber5k_underlay.c | 301 ++ Source/DirectFB/gfxdrivers/cyber5k/mmio.h | 126 + Source/DirectFB/gfxdrivers/cyber5k/regs.h | 387 ++ Source/DirectFB/gfxdrivers/davinci/Makefile.am | 77 + Source/DirectFB/gfxdrivers/davinci/Makefile.in | 771 +++ Source/DirectFB/gfxdrivers/davinci/Makefile.kernel | 6 + Source/DirectFB/gfxdrivers/davinci/c64xdump.c | 117 + Source/DirectFB/gfxdrivers/davinci/davinci_2d.c | 1050 +++++ Source/DirectFB/gfxdrivers/davinci/davinci_2d.h | 79 + Source/DirectFB/gfxdrivers/davinci/davinci_c64x.c | 2053 ++++++++ Source/DirectFB/gfxdrivers/davinci/davinci_c64x.h | 935 ++++ .../gfxdrivers/davinci/davinci_gfxdriver.c | 343 ++ .../gfxdrivers/davinci/davinci_gfxdriver.h | 169 + Source/DirectFB/gfxdrivers/davinci/davinci_osd.c | 681 +++ Source/DirectFB/gfxdrivers/davinci/davinci_osd.h | 53 + .../DirectFB/gfxdrivers/davinci/davinci_osd_pool.c | 394 ++ .../DirectFB/gfxdrivers/davinci/davinci_osd_pool.h | 39 + .../DirectFB/gfxdrivers/davinci/davinci_screen.c | 124 + .../DirectFB/gfxdrivers/davinci/davinci_screen.h | 39 + Source/DirectFB/gfxdrivers/davinci/davinci_video.c | 744 +++ Source/DirectFB/gfxdrivers/davinci/davinci_video.h | 58 + .../gfxdrivers/davinci/davinci_video_pool.c | 393 ++ .../gfxdrivers/davinci/davinci_video_pool.h | 39 + Source/DirectFB/gfxdrivers/davinci/davincifb.h | 581 +++ Source/DirectFB/gfxdrivers/davinci/directfbrc | 56 + .../gfxdrivers/davinci/kernel-module/Makefile | 34 + .../gfxdrivers/davinci/kernel-module/c64x/Makefile | 2 + .../gfxdrivers/davinci/kernel-module/c64x/c64x.c | 507 ++ .../davinci/kernel-module/include/linux/c64x.h | 281 ++ .../ti-davinci-2.6.10-mvl401-fbio_set_start.patch | 123 + Source/DirectFB/gfxdrivers/ep9x/Makefile.am | 33 + Source/DirectFB/gfxdrivers/ep9x/Makefile.in | 595 +++ Source/DirectFB/gfxdrivers/ep9x/ep9x.c | 474 ++ Source/DirectFB/gfxdrivers/ep9x/ep9x.h | 87 + Source/DirectFB/gfxdrivers/gl/Makefile.am | 36 + Source/DirectFB/gfxdrivers/gl/Makefile.in | 598 +++ Source/DirectFB/gfxdrivers/gl/gl_2d.c | 928 ++++ Source/DirectFB/gfxdrivers/gl/gl_2d.h | 93 + Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.c | 217 + Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.h | 63 + Source/DirectFB/gfxdrivers/i810/Makefile.am | 35 + Source/DirectFB/gfxdrivers/i810/Makefile.in | 597 +++ Source/DirectFB/gfxdrivers/i810/i810.c | 1044 +++++ Source/DirectFB/gfxdrivers/i810/i810.h | 832 ++++ Source/DirectFB/gfxdrivers/i810/i810_overlay.c | 598 +++ Source/DirectFB/gfxdrivers/i830/Makefile.am | 35 + Source/DirectFB/gfxdrivers/i830/Makefile.in | 597 +++ Source/DirectFB/gfxdrivers/i830/i830.c | 635 +++ Source/DirectFB/gfxdrivers/i830/i830.h | 406 ++ Source/DirectFB/gfxdrivers/i830/i830_overlay.c | 807 ++++ Source/DirectFB/gfxdrivers/mach64/Makefile.am | 39 + Source/DirectFB/gfxdrivers/mach64/Makefile.in | 603 +++ Source/DirectFB/gfxdrivers/mach64/mach64.c | 1640 +++++++ Source/DirectFB/gfxdrivers/mach64/mach64.h | 120 + Source/DirectFB/gfxdrivers/mach64/mach64_overlay.c | 724 +++ Source/DirectFB/gfxdrivers/mach64/mach64_state.c | 654 +++ Source/DirectFB/gfxdrivers/mach64/mach64_state.h | 90 + Source/DirectFB/gfxdrivers/mach64/mmio.h | 198 + Source/DirectFB/gfxdrivers/mach64/regs.h | 883 ++++ Source/DirectFB/gfxdrivers/matrox/Makefile.am | 47 + Source/DirectFB/gfxdrivers/matrox/Makefile.in | 618 +++ Source/DirectFB/gfxdrivers/matrox/matrox.c | 2930 ++++++++++++ Source/DirectFB/gfxdrivers/matrox/matrox.h | 157 + Source/DirectFB/gfxdrivers/matrox/matrox_3d.c | 627 +++ Source/DirectFB/gfxdrivers/matrox/matrox_3d.h | 36 + Source/DirectFB/gfxdrivers/matrox/matrox_bes.c | 783 ++++ Source/DirectFB/gfxdrivers/matrox/matrox_crtc2.c | 751 +++ Source/DirectFB/gfxdrivers/matrox/matrox_maven.c | 785 ++++ Source/DirectFB/gfxdrivers/matrox/matrox_maven.h | 64 + .../gfxdrivers/matrox/matrox_screen_crtc2.c | 279 ++ Source/DirectFB/gfxdrivers/matrox/matrox_spic.c | 314 ++ Source/DirectFB/gfxdrivers/matrox/matrox_state.c | 810 ++++ Source/DirectFB/gfxdrivers/matrox/matrox_state.h | 70 + Source/DirectFB/gfxdrivers/matrox/mmio.h | 118 + Source/DirectFB/gfxdrivers/matrox/regs.h | 454 ++ Source/DirectFB/gfxdrivers/neomagic/Makefile.am | 35 + Source/DirectFB/gfxdrivers/neomagic/Makefile.in | 601 +++ Source/DirectFB/gfxdrivers/neomagic/neo2200.c | 570 +++ Source/DirectFB/gfxdrivers/neomagic/neo_overlay.c | 349 ++ Source/DirectFB/gfxdrivers/neomagic/neomagic.c | 223 + Source/DirectFB/gfxdrivers/neomagic/neomagic.h | 147 + Source/DirectFB/gfxdrivers/nsc/Makefile.am | 40 + Source/DirectFB/gfxdrivers/nsc/Makefile.in | 714 +++ Source/DirectFB/gfxdrivers/nsc/include/Makefile.am | 5 + Source/DirectFB/gfxdrivers/nsc/include/Makefile.in | 403 ++ Source/DirectFB/gfxdrivers/nsc/include/gfx_regs.h | 1733 +++++++ Source/DirectFB/gfxdrivers/nsc/include/gfx_type.h | 426 ++ .../DirectFB/gfxdrivers/nsc/include/nsc_galproto.h | 1987 ++++++++ Source/DirectFB/gfxdrivers/nsc/include/pnl_defs.h | 201 + Source/DirectFB/gfxdrivers/nsc/nsc.c | 592 +++ Source/DirectFB/gfxdrivers/nsc/nsc_galfns.c | 4905 ++++++++++++++++++++ Source/DirectFB/gfxdrivers/nvidia/Makefile.am | 45 + Source/DirectFB/gfxdrivers/nvidia/Makefile.in | 614 +++ Source/DirectFB/gfxdrivers/nvidia/nvidia.c | 2046 ++++++++ Source/DirectFB/gfxdrivers/nvidia/nvidia.h | 238 + Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c | 549 +++ Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h | 48 + Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c | 522 +++ Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h | 36 + Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h | 246 + Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h | 160 + Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c | 566 +++ Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c | 189 + Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h | 1636 +++++++ Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c | 730 +++ Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h | 58 + Source/DirectFB/gfxdrivers/omap/Makefile.am | 34 + Source/DirectFB/gfxdrivers/omap/Makefile.in | 598 +++ Source/DirectFB/gfxdrivers/omap/omap.c | 142 + Source/DirectFB/gfxdrivers/omap/omap.h | 48 + Source/DirectFB/gfxdrivers/omap/omap_primary.c | 102 + Source/DirectFB/gfxdrivers/omap/omapfb.h | 163 + Source/DirectFB/gfxdrivers/radeon/Makefile.am | 52 + Source/DirectFB/gfxdrivers/radeon/Makefile.in | 625 +++ Source/DirectFB/gfxdrivers/radeon/r100_3d.c | 523 +++ Source/DirectFB/gfxdrivers/radeon/r100_state.c | 954 ++++ Source/DirectFB/gfxdrivers/radeon/r200_3d.c | 508 ++ Source/DirectFB/gfxdrivers/radeon/r200_state.c | 985 ++++ Source/DirectFB/gfxdrivers/radeon/r300_3d.c | 492 ++ Source/DirectFB/gfxdrivers/radeon/r300_program.h | 151 + Source/DirectFB/gfxdrivers/radeon/r300_state.c | 1103 +++++ Source/DirectFB/gfxdrivers/radeon/radeon.c | 1753 +++++++ Source/DirectFB/gfxdrivers/radeon/radeon.h | 224 + Source/DirectFB/gfxdrivers/radeon/radeon_2d.c | 397 ++ Source/DirectFB/gfxdrivers/radeon/radeon_2d.h | 38 + Source/DirectFB/gfxdrivers/radeon/radeon_3d.h | 81 + .../DirectFB/gfxdrivers/radeon/radeon_chipsets.h | 169 + Source/DirectFB/gfxdrivers/radeon/radeon_crtc1.c | 171 + Source/DirectFB/gfxdrivers/radeon/radeon_crtc2.c | 1011 ++++ Source/DirectFB/gfxdrivers/radeon/radeon_mmio.h | 163 + Source/DirectFB/gfxdrivers/radeon/radeon_overlay.c | 983 ++++ Source/DirectFB/gfxdrivers/radeon/radeon_regs.h | 4364 +++++++++++++++++ Source/DirectFB/gfxdrivers/radeon/radeon_state.h | 160 + Source/DirectFB/gfxdrivers/radeon/vertex_shader.h | 83 + Source/DirectFB/gfxdrivers/savage/Makefile.am | 45 + Source/DirectFB/gfxdrivers/savage/Makefile.in | 611 +++ Source/DirectFB/gfxdrivers/savage/mmio.h | 98 + Source/DirectFB/gfxdrivers/savage/savage.c | 346 ++ Source/DirectFB/gfxdrivers/savage/savage.h | 145 + Source/DirectFB/gfxdrivers/savage/savage2000.c | 199 + Source/DirectFB/gfxdrivers/savage/savage2000.h | 105 + Source/DirectFB/gfxdrivers/savage/savage3d.c | 561 +++ Source/DirectFB/gfxdrivers/savage/savage3d.h | 121 + Source/DirectFB/gfxdrivers/savage/savage4.c | 599 +++ Source/DirectFB/gfxdrivers/savage/savage4.h | 146 + Source/DirectFB/gfxdrivers/savage/savage_bci.h | 208 + .../gfxdrivers/savage/savage_streams_old.c | 916 ++++ .../gfxdrivers/savage/savage_streams_old.h | 142 + Source/DirectFB/gfxdrivers/sh772x/Makefile.am | 80 + Source/DirectFB/gfxdrivers/sh772x/Makefile.in | 726 +++ Source/DirectFB/gfxdrivers/sh772x/Makefile.kernel | 61 + Source/DirectFB/gfxdrivers/sh772x/README.sh7722 | 172 + .../DirectFB/gfxdrivers/sh772x/directfbrc.sh7722 | 10 + .../DirectFB/gfxdrivers/sh772x/directfbrc.sh7723 | 10 + .../gfxdrivers/sh772x/kernel-module/Makefile | 3 + .../gfxdrivers/sh772x/kernel-module/sh7722.c | 1192 +++++ .../gfxdrivers/sh772x/kernel-module/sh7722.h | 21 + .../gfxdrivers/sh772x/kernel-module/sh7723.c | 566 +++ .../gfxdrivers/sh772x/kernel-module/sh7723.h | 21 + .../sh772x/kernel-module/sh772x_driver.c | 82 + .../gfxdrivers/sh772x/kernel-module/sh772x_gfx.h | 105 + Source/DirectFB/gfxdrivers/sh772x/sh7722.c | 490 ++ Source/DirectFB/gfxdrivers/sh772x/sh7722.h | 131 + Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.c | 2013 ++++++++ Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.h | 214 + Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeg.c | 395 ++ Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.c | 1654 +++++++ Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.h | 47 + .../DirectFB/gfxdrivers/sh772x/sh7722_jpegtool.c | 142 + Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.c | 529 +++ Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.h | 11 + Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.c | 172 + Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.h | 17 + Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.c | 412 ++ Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.h | 11 + Source/DirectFB/gfxdrivers/sh772x/sh7722_regs.h | 624 +++ Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.c | 85 + Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.h | 9 + Source/DirectFB/gfxdrivers/sh772x/sh7722_types.h | 136 + Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.c | 890 ++++ Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.h | 239 + Source/DirectFB/gfxdrivers/sis315/Makefile.am | 42 + Source/DirectFB/gfxdrivers/sis315/Makefile.in | 607 +++ Source/DirectFB/gfxdrivers/sis315/sis315.c | 355 ++ Source/DirectFB/gfxdrivers/sis315/sis315.h | 59 + Source/DirectFB/gfxdrivers/sis315/sis315_accel.c | 250 + Source/DirectFB/gfxdrivers/sis315/sis315_accel.h | 32 + Source/DirectFB/gfxdrivers/sis315/sis315_compat.h | 89 + Source/DirectFB/gfxdrivers/sis315/sis315_mmio.c | 51 + Source/DirectFB/gfxdrivers/sis315/sis315_mmio.h | 37 + Source/DirectFB/gfxdrivers/sis315/sis315_regs.h | 161 + Source/DirectFB/gfxdrivers/sis315/sis315_state.c | 164 + Source/DirectFB/gfxdrivers/sis315/sis315_state.h | 34 + Source/DirectFB/gfxdrivers/tdfx/Makefile.am | 34 + Source/DirectFB/gfxdrivers/tdfx/Makefile.in | 595 +++ Source/DirectFB/gfxdrivers/tdfx/tdfx.c | 884 ++++ Source/DirectFB/gfxdrivers/tdfx/tdfx.h | 250 + Source/DirectFB/gfxdrivers/unichrome/Makefile.am | 50 + Source/DirectFB/gfxdrivers/unichrome/Makefile.in | 626 +++ Source/DirectFB/gfxdrivers/unichrome/mmio.h | 43 + Source/DirectFB/gfxdrivers/unichrome/regs2d.h | 197 + Source/DirectFB/gfxdrivers/unichrome/regs3d.h | 1642 +++++++ Source/DirectFB/gfxdrivers/unichrome/uc_accel.c | 578 +++ Source/DirectFB/gfxdrivers/unichrome/uc_accel.h | 123 + Source/DirectFB/gfxdrivers/unichrome/uc_fifo.c | 198 + Source/DirectFB/gfxdrivers/unichrome/uc_fifo.h | 268 ++ Source/DirectFB/gfxdrivers/unichrome/uc_hw.h | 105 + Source/DirectFB/gfxdrivers/unichrome/uc_hwmap.c | 362 ++ Source/DirectFB/gfxdrivers/unichrome/uc_hwset.c | 446 ++ Source/DirectFB/gfxdrivers/unichrome/uc_ioctl.h | 35 + Source/DirectFB/gfxdrivers/unichrome/uc_overlay.c | 405 ++ Source/DirectFB/gfxdrivers/unichrome/uc_overlay.h | 98 + .../DirectFB/gfxdrivers/unichrome/uc_ovl_hwmap.c | 609 +++ .../DirectFB/gfxdrivers/unichrome/uc_ovl_hwset.c | 283 ++ Source/DirectFB/gfxdrivers/unichrome/uc_primary.c | 182 + Source/DirectFB/gfxdrivers/unichrome/uc_probe.h | 42 + Source/DirectFB/gfxdrivers/unichrome/uc_spic.c | 193 + Source/DirectFB/gfxdrivers/unichrome/uc_state.c | 350 ++ Source/DirectFB/gfxdrivers/unichrome/uc_state.h | 68 + Source/DirectFB/gfxdrivers/unichrome/unichrome.c | 596 +++ Source/DirectFB/gfxdrivers/unichrome/unichrome.h | 151 + Source/DirectFB/gfxdrivers/unichrome/vidregs.h | 499 ++ Source/DirectFB/gfxdrivers/vmware/Makefile.am | 36 + Source/DirectFB/gfxdrivers/vmware/Makefile.in | 598 +++ Source/DirectFB/gfxdrivers/vmware/vmware_2d.c | 402 ++ Source/DirectFB/gfxdrivers/vmware/vmware_2d.h | 67 + .../DirectFB/gfxdrivers/vmware/vmware_gfxdriver.c | 128 + .../DirectFB/gfxdrivers/vmware/vmware_gfxdriver.h | 58 + 269 files changed, 112311 insertions(+) create mode 100755 Source/DirectFB/gfxdrivers/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/ati128/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/ati128/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/ati128/ati128.c create mode 100755 Source/DirectFB/gfxdrivers/ati128/ati128.h create mode 100755 Source/DirectFB/gfxdrivers/ati128/ati128_overlay.c create mode 100755 Source/DirectFB/gfxdrivers/ati128/ati128_state.c create mode 100755 Source/DirectFB/gfxdrivers/ati128/ati128_state.h create mode 100755 Source/DirectFB/gfxdrivers/ati128/mmio.h create mode 100755 Source/DirectFB/gfxdrivers/ati128/regs.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/cle266/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/cle266/mmio.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/regs2d.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/regs3d.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_accel.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_accel.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_fifo.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_fifo.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_hw.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_hwset.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_overlay.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_overlay.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_primary.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_state.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/uc_state.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/unichrome.c create mode 100755 Source/DirectFB/gfxdrivers/cle266/unichrome.h create mode 100755 Source/DirectFB/gfxdrivers/cle266/vidregs.h create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k.c create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k.h create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.c create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.h create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.c create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.h create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/cyber5k_underlay.c create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/mmio.h create mode 100755 Source/DirectFB/gfxdrivers/cyber5k/regs.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/davinci/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/davinci/Makefile.kernel create mode 100755 Source/DirectFB/gfxdrivers/davinci/c64xdump.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_2d.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_2d.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_c64x.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_c64x.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_osd.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_osd.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_screen.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_screen.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_video.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_video.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/davincifb.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/directfbrc create mode 100755 Source/DirectFB/gfxdrivers/davinci/kernel-module/Makefile create mode 100755 Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/Makefile create mode 100755 Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/c64x.c create mode 100755 Source/DirectFB/gfxdrivers/davinci/kernel-module/include/linux/c64x.h create mode 100755 Source/DirectFB/gfxdrivers/davinci/patches/ti-davinci-2.6.10-mvl401-fbio_set_start.patch create mode 100755 Source/DirectFB/gfxdrivers/ep9x/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/ep9x/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/ep9x/ep9x.c create mode 100755 Source/DirectFB/gfxdrivers/ep9x/ep9x.h create mode 100755 Source/DirectFB/gfxdrivers/gl/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/gl/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/gl/gl_2d.c create mode 100755 Source/DirectFB/gfxdrivers/gl/gl_2d.h create mode 100755 Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.c create mode 100755 Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.h create mode 100755 Source/DirectFB/gfxdrivers/i810/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/i810/Makefile.in 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create mode 100755 Source/DirectFB/gfxdrivers/unichrome/unichrome.h create mode 100755 Source/DirectFB/gfxdrivers/unichrome/vidregs.h create mode 100755 Source/DirectFB/gfxdrivers/vmware/Makefile.am create mode 100755 Source/DirectFB/gfxdrivers/vmware/Makefile.in create mode 100755 Source/DirectFB/gfxdrivers/vmware/vmware_2d.c create mode 100755 Source/DirectFB/gfxdrivers/vmware/vmware_2d.h create mode 100755 Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.c create mode 100755 Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.h (limited to 'Source/DirectFB/gfxdrivers') diff --git a/Source/DirectFB/gfxdrivers/Makefile.am b/Source/DirectFB/gfxdrivers/Makefile.am new file mode 100755 index 0000000..270cf31 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/Makefile.am @@ -0,0 +1,151 @@ +## Makefile.am for DirectFB/gfxdrivers + +if GFX_ATI128 +ATI128_DIR = ati128 +else +ATI128_DIR = +endif + +if GFX_CLE266 +CLE266_DIR = cle266 +else +CLE266_DIR = +endif + +if GFX_CYBER5K +CYBER5K_DIR = cyber5k +else +CYBER5K_DIR = +endif + +if GFX_DAVINCI +DAVINCI_DIR = davinci +else +DAVINCI_DIR = +endif + +if GFX_GL +GL_DIR = gl +else +GL_DIR = +endif + +if GFX_I810 +I810_DIR = i810 +else +I810_DIR = +endif + +if GFX_I830 +I830_DIR = i830 +else +I830_DIR = +endif + +if GFX_MACH64 +MACH64_DIR = mach64 +else +MACH64_DIR = +endif + +if GFX_MATROX +MATROX_DIR = matrox +else +MATROX_DIR = +endif + +if GFX_NEOMAGIC +NEOMAGIC_DIR = neomagic +else +NEOMAGIC_DIR = +endif + +if GFX_NSC +NSC_DIR = nsc +else +NSC_DIR = +endif + +if GFX_NVIDIA +NVIDIA_DIR = nvidia +else +NVIDIA_DIR = +endif + +if GFX_OMAP +OMAP_DIR = omap +else +OMAP_DIR = +endif + +if GFX_RADEON +RADEON_DIR = radeon +else +RADEON_DIR = +endif + +if GFX_SAVAGE +SAVAGE_DIR = savage +else +SAVAGE_DIR = +endif + +if GFX_SH772X +SH772X_DIR = sh772x +else +SH772X_DIR = +endif + +if GFX_SIS315 +SIS315_DIR = sis315 +else +SIS315_DIR = +endif + +if GFX_TDFX +TDFX_DIR = tdfx +else +TDFX_DIR = +endif + +if GFX_UNICHROME +UNICHROME_DIR = unichrome +else +UNICHROME_DIR = +endif + +if GFX_VMWARE +VMWARE_DIR = vmware +else +VMWARE_DIR = +endif + +if GFX_EP9X +EP9X_DIR = ep9x +else +EP9X_DIR = +endif + + +SUBDIRS = \ + $(ATI128_DIR) \ + $(CLE266_DIR) \ + $(CYBER5K_DIR) \ + $(DAVINCI_DIR) \ + $(EP9X_DIR) \ + $(GL_DIR) \ + $(I810_DIR) \ + $(I830_DIR) \ + $(MACH64_DIR) \ + $(MATROX_DIR) \ + $(NEOMAGIC_DIR) \ + $(NSC_DIR) \ + $(NVIDIA_DIR) \ + $(OMAP_DIR) \ + $(RADEON_DIR) \ + $(SAVAGE_DIR) \ + $(SH772X_DIR) \ + $(SIS315_DIR) \ + $(TDFX_DIR) \ + $(UNICHROME_DIR) \ + $(VMWARE_DIR) diff --git a/Source/DirectFB/gfxdrivers/Makefile.in b/Source/DirectFB/gfxdrivers/Makefile.in new file mode 100755 index 0000000..b9a2671 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/Makefile.in @@ -0,0 +1,622 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +subdir = gfxdrivers +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +SOURCES = +DIST_SOURCES = +RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ + html-recursive info-recursive install-data-recursive \ + install-dvi-recursive install-exec-recursive \ + install-html-recursive install-info-recursive \ + install-pdf-recursive install-ps-recursive install-recursive \ + installcheck-recursive installdirs-recursive pdf-recursive \ + ps-recursive uninstall-recursive +RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \ + distclean-recursive maintainer-clean-recursive +ETAGS = etags +CTAGS = ctags +DIST_SUBDIRS = ati128 cle266 cyber5k davinci ep9x gl i810 i830 mach64 \ + matrox neomagic nsc nvidia omap radeon savage sh772x sis315 \ + tdfx unichrome vmware +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ 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mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ + uninstall-am uninstall-ati128DATA uninstall-ati128LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/ati128/ati128.c b/Source/DirectFB/gfxdrivers/ati128/ati128.c new file mode 100755 index 0000000..4ae34c6 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/ati128.c @@ -0,0 +1,842 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include + + +DFB_GRAPHICS_DRIVER( ati128 ) + + +#include "regs.h" +#include "mmio.h" +#include "ati128_state.h" +#include "ati128.h" + + +/* driver capability flags */ + + +#ifndef __powerpc__ +#define ATI128_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) +#else +#define ATI128_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_NOFX) +#endif + +#define ATI128_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE) + +#define ATI128_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY | DSBLIT_BLEND_ALPHACHANNEL) + +#define ATI128_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) + + +/* macro for S12.0 and S14.0 format */ +#define S12(val) (((u16)((s16)(val)))&0x3fff) +#define S14(val) (((u16)((s16)(val)))&0x3fff) + +/** CARD FUNCTIONS **/ +static bool ati128FillRectangle( void *drv, void *dev, DFBRectangle *rect ); +static bool ati128FillBlendRectangle( void *drv, void *dev, DFBRectangle *rect ); +static bool ati128DrawRectangle( void *drv, void *dev, DFBRectangle *rect ); +static bool ati128DrawBlendRectangle( void *drv, void *dev, DFBRectangle *rect ); + +/* required implementations */ + +static DFBResult ati128EngineSync( void *drv, void *dev ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + + ati128_waitidle( adrv, adev ); + + return DFB_OK; +} + +static bool ati128_check_blend( CardState *state ) +{ + if (state->dst_blend == DSBF_SRCALPHASAT) + return false; + + return true; +} + +static void ati128CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + /* check for the special drawing function that does not support + the usually supported drawingflags */ + if (accel == DFXL_DRAWLINE && state->drawingflags != DSDRAW_NOFX) + return; + + /* if there are no other drawing flags than the supported */ + if (!(accel & ~ATI128_SUPPORTED_DRAWINGFUNCTIONS) && + !(state->drawingflags & ~ATI128_SUPPORTED_DRAWINGFLAGS)) { + if (state->drawingflags & DSDRAW_BLEND && + !ati128_check_blend( state )) + return; + + state->accel |= ATI128_SUPPORTED_DRAWINGFUNCTIONS; + } + + /* if there are no other blitting flags than the supported + and the source has the minimum size */ + if (!(accel & ~ATI128_SUPPORTED_BLITTINGFUNCTIONS) && + !(state->blittingflags & ~ATI128_SUPPORTED_BLITTINGFLAGS) && + state->source && + state->source->config.size.w >= 8 && + state->source->config.size.h >= 8 ) + { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && + !ati128_check_blend( state )) + return; + + switch (state->source->config.format) { + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + state->accel |= ATI128_SUPPORTED_BLITTINGFUNCTIONS; + default: + ; + } + } +} + + +static void ati128SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + + if (state->mod_hw & SMF_SOURCE) + adev->v_source = 0; + + if (state->mod_hw & SMF_DESTINATION) + adev->v_destination = adev->v_color = 0; + + if (state->mod_hw & SMF_COLOR) + adev->v_color = 0; + + if (state->mod_hw & SMF_SRC_COLORKEY) + adev->v_src_colorkey = 0; + + if (state->mod_hw & SMF_BLITTING_FLAGS) + adev->v_blittingflags = 0; + + if (state->mod_hw & (SMF_SRC_BLEND | SMF_DST_BLEND)) + adev->v_blending_function = 0; + + ati128_set_destination( adrv, adev, state); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + if (state->drawingflags & DSDRAW_BLEND) { + ati128_set_blending_function( adrv, adev, state ); + funcs->FillRectangle = ati128FillBlendRectangle; + funcs->DrawRectangle = ati128DrawBlendRectangle; + } + else { + funcs->FillRectangle = ati128FillRectangle; + funcs->DrawRectangle = ati128DrawRectangle; + } + case DFXL_DRAWLINE: + ati128_set_color( adrv, adev, state ); + state->set |= DFXL_FILLRECTANGLE | DFXL_DRAWLINE | DFXL_DRAWRECTANGLE ; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + ati128_set_source( adrv, adev, state ); + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + ati128_set_blending_function( adrv, adev, state ); + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + ati128_set_src_colorkey( adrv, adev, state ); + ati128_set_blittingflags( adrv, adev, state ); + state->set |= DFXL_BLIT | DFXL_STRETCHBLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + if (state->mod_hw & SMF_CLIP) + ati128_set_clip( adrv, adev, state); + + state->mod_hw = 0; +} + +static bool ati128FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + ati128_waitfifo( adrv, adev, 5 ); + /* set the destination datatype */ + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | BRUSH_SOLIDCOLOR ); + /* set direction */ + ati128_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); + /* set the drawing command */ + ati128_out32( mmio, DP_MIX, ROP3_PATCOPY | DP_SRC_RECT ); + /* set parameters */ + ati128_out32( mmio, DST_Y_X, (S14(rect->y) << 16) | S12(rect->x) ); + /* this executes the drawing command */ + ati128_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | rect->w ); + + return true; +} + +static bool ati128FillBlendRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + u32 fts = adev->ATI_fake_texture_src + (adev->fake_texture_number & 7)*4; + ati128_waitidle( adrv, adev ); + *((u32*) dfb_gfxcard_memory_virtual(NULL,fts) ) = adev->fake_texture_color; + ati128_waitidle( adrv, adev ); + + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_32BPP ); + ati128_out32( mmio, SCALE_PITCH, 1 ); + /* enable scaling with filtering */ + ati128_out32( mmio, SCALE_3D_CNTL, adev->ATI_blend_function ); + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | SRC_DSTCOLOR ); + ati128_out32( mmio, DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT ); + /* flush the texture cache */ + ati128_out32( mmio, TEX_CNTL, TEX_CNTL_ALPHA_EN_ON | TEX_CNTL_TEX_CACHE_FLUSH_ON); + /* set source offset */ + ati128_out32( mmio, SCALE_OFFSET_0, fts ) ; + /* set height and width of the source */ + ati128_out32( mmio, SCALE_SRC_HEIGHT_WIDTH, (8 << 16) | 8); + /* set the scaling increment registers */ + ati128_out32( mmio, SCALE_X_INC, 0 ); + ati128_out32( mmio, SCALE_Y_INC, 0 ); + /* reset accumulator regs */ + ati128_out32( mmio, SCALE_HACC, 0x00000000 ); + ati128_out32( mmio, SCALE_VACC, 0x00000000 ); + /* set the destination coordinates */ + ati128_out32( mmio, SCALE_DST_X_Y, (S12(rect->x) << 16) | S14(rect->y) ); + /* set destination height and width and perform the blit */ + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, (rect->h << 16) | rect->w ); + /*reset scaling and texture control register */ + ati128_out32( mmio, SCALE_3D_CNTL, 0x00000000 ); + ati128_out32( mmio, TEX_CNTL, 0); + adev->fake_texture_number++; + + return true; +} + +static bool ati128DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + ati128_waitfifo( adrv, adev, 3 ); + /* set the destination datatype */ + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | BRUSH_SOLIDCOLOR ); + /* set direction */ + ati128_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); + /* set the drawing command */ + ati128_out32( mmio, DP_MIX, ROP3_PATCOPY | DP_SRC_RECT ); + + ati128_waitfifo( adrv, adev, 7 ); + /* first line */ + ati128_out32( mmio, DST_Y_X, (S14(rect->y) << 16) | S12(rect->x)); + ati128_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | 1); + /* second line */ + ati128_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | rect->w ); + /* third line */ + ati128_out32( mmio, DST_Y_X, (S14(rect->y+rect->h-1) << 16) | S12(rect->x)); + ati128_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | rect->w ); + /* fourth line */ + ati128_out32( mmio, DST_Y_X, (S14(rect->y) << 16) | S12(rect->x+rect->w-1)); + ati128_out32( mmio, DST_HEIGHT_WIDTH, rect->h << 16 | 1); + + return true; +} + +static bool ati128DrawBlendRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + u32 fts = adev->ATI_fake_texture_src + (adev->fake_texture_number & 7)*4; + + ati128_waitidle( adrv, adev ); + *((u32*) dfb_gfxcard_memory_virtual(NULL,fts) ) = adev->fake_texture_color; + ati128_waitidle( adrv, adev ); + + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_32BPP ); + ati128_out32( mmio, SCALE_PITCH, 1 ); + + /* enable scaling with filtering */ + ati128_out32( mmio, SCALE_3D_CNTL, adev->ATI_blend_function ); + ati128_out32( mmio, TEX_CNTL, TEX_CNTL_ALPHA_EN_ON | TEX_CNTL_TEX_CACHE_FLUSH_ON); + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | SRC_DSTCOLOR ); + ati128_out32( mmio, DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT ); + /* set source offset */ + ati128_out32( mmio, SCALE_OFFSET_0, adev->ATI_fake_texture_src ); + /* set height and width of the source */ + ati128_out32( mmio, SCALE_SRC_HEIGHT_WIDTH, (8 << 16) | 8); + /* set the scaling increment registers */ + ati128_out32( mmio, SCALE_X_INC, 0 ); + ati128_out32( mmio, SCALE_Y_INC, 0 ); + /* reset accumulator regs */ + ati128_out32( mmio, SCALE_HACC, 0x00000000 ); + ati128_out32( mmio, SCALE_VACC, 0x00000000 ); + /* set the destination coordinates */ + + /*-----------------------*/ + /* first line */ + ati128_out32( mmio, SCALE_DST_X_Y, (S12(rect->x) << 16) | S14(rect->y) ); + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, (rect->h << 16) | 1); + /* second line */ + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, (1 << 16) | rect->w ); + /* third line */ + ati128_out32( mmio, SCALE_DST_X_Y, (S12(rect->x) << 16) | S14(rect->y+rect->h-1)); + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, (1 << 16) | rect->w ); + /* fourth line */ + ati128_out32( mmio, SCALE_DST_X_Y, (S12(rect->x+rect->w-1) << 16) | S14(rect->y)); + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, rect->h << 16 | 1); + /*-----------------------*/ + + /* reset scaling and texture control register */ + ati128_out32( mmio, SCALE_3D_CNTL, 0x00000000 ); + ati128_out32( mmio, TEX_CNTL, 0 ); + adev->fake_texture_number++; + + return true; +} + + +static bool ati128DrawLine( void *drv, void *dev, DFBRegion *line ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + int dx, dy; + int small, large; + int x_dir, y_dir, y_major; + int err, inc, dec; + + /* Determine x & y deltas and x & y direction bits. */ + if (line->x1 < line->x2) { + dx = line->x2 - line->x1; + x_dir = 1 << 31; + } + else { + dx = line->x1 - line->x2; + x_dir = 0 << 31; + } + + if (line->y1 < line->y2) { + dy = line->y2 - line->y1; + y_dir = 1 << 15; + } + else { + dy = line->y1 - line->y2; + y_dir = 0 << 15; + } + + /* Determine x & y min and max values; also determine y major bit. */ + if (dx < dy) { + small = dx; + large = dy; + y_major = 1 << 2; + } + else { + small = dy; + large = dx; + y_major = 0 << 2; + } + + /* Calculate Bresenham parameters and draw line. */ + err = -large; + inc = small * 2; + dec = large *(-2); + + ati128_waitfifo( adrv, adev, 8 ); + /* set the destination datatype */ + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | BRUSH_SOLIDCOLOR | ROP3_SRCCOPY ); + ati128_out32( mmio, DP_MIX, ROP3_PATCOPY ); + + /* set start coorinates */ + ati128_out32( mmio, DST_Y_X, (S14(line->y1) << 16) | S12(line->x1)); + /* allow setting of last pel bit and polygon + outline bit for line drawing */ + ati128_out32( mmio, DP_CNTL_XDIR_YDIR_YMAJOR, + y_major | y_dir | x_dir ); + /* set bresenham registers and start drawing */ + ati128_out32( mmio, DST_BRES_ERR, err ); + ati128_out32( mmio, DST_BRES_INC, inc ); + ati128_out32( mmio, DST_BRES_DEC, dec ); + ati128_out32( mmio, DST_BRES_LNTH, large + 1 ); + + return true; +} + +static bool ati128StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + u32 src = 0; + + u32 scalex = (u32)(((double)sr->w/(double)dr->w) * 65536); + u32 scaley = (u32)(((double)sr->h/(double)dr->h) * 65536); + + ati128_waitfifo( adrv, adev, 9 ); + + /* make sure that color compare register is restored to last state */ + + ati128_out32( mmio, CLR_CMP_CNTL, adev->ATI_color_compare ); + + switch (adev->source->config.format) { + case DSPF_RGB332: + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_8BPP_RGB332 ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>3); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x; + + ati128_out32( mmio, TEX_CNTL, 0); + + break; + case DSPF_ARGB1555: /* FIXME: alpha channel will be zero ;( */ + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_15BPP ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>4); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x*2; + + ati128_out32( mmio, TEX_CNTL, 0); + + break; + case DSPF_RGB16: + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_16BPP ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>4); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x*2; + + ati128_out32( mmio, TEX_CNTL, 0); + + break; + case DSPF_RGB24: + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_24BPP ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>3); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x*3; + + ati128_out32( mmio, TEX_CNTL, 0); + + break; + case DSPF_RGB32: + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_32BPP ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>5); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x*4; + + ati128_out32( mmio, TEX_CNTL, 0); + + break; + case DSPF_ARGB: + ati128_out32( mmio, SCALE_3D_DATATYPE, DST_32BPP ); + + ati128_out32( mmio, SCALE_PITCH, + adev->src->pitch >>5); + + src = adev->src->offset + + sr->y * + adev->src->pitch + sr->x*4; + + if (adev->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + ati128_out32( mmio, TEX_CNTL, TEX_CNTL_ALPHA_EN_ON ); + else + ati128_out32( mmio, TEX_CNTL, 0 ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + return false; + } + + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | SRC_DSTCOLOR ); + + /* set the blend function */ + if (adev->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + ati128_out32( mmio, SCALE_3D_CNTL, adev->ATI_blend_function ); + else + ati128_out32( mmio, SCALE_3D_CNTL, SCALE_3D_CNTL_SCALE_3D_FN_SCALE ); + + /* set up source data and copy type */ + ati128_out32( mmio, DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT ); + /* set source offset */ + ati128_out32( mmio, SCALE_OFFSET_0, src); + /* set height and width of the source */ + ati128_out32( mmio, SCALE_SRC_HEIGHT_WIDTH, (sr->h << 16) | sr->w); + + ati128_waitfifo( adrv, adev, 9 ); + /* set the scaling increment registers */ + ati128_out32( mmio, SCALE_X_INC, scalex ); + ati128_out32( mmio, SCALE_Y_INC, scaley ); + /* reset accumulator regs */ + ati128_out32( mmio, SCALE_HACC, 0x00000000 ); + ati128_out32( mmio, SCALE_VACC, 0x00000000 ); + /* set the destination coordinates */ + ati128_out32( mmio, SCALE_DST_X_Y, (S12(dr->x) << 16) | S14(dr->y) ); + /* set destination height and width and perform the blit */ + ati128_out32( mmio, SCALE_DST_HEIGHT_WIDTH, (dr->h << 16) | dr->w ); + /*reset scaling and texture control register */ + ati128_out32( mmio, SCALE_3D_CNTL, 0x00000000 ); + ati128_out32( mmio, TEX_CNTL, 0x00000000 ); + + /* set CLR_CMP_CNTL to zero, to insure that drawing funcions work corrently */ + if (adev->ATI_color_compare) + ati128_out32( mmio, CLR_CMP_CNTL, 0 ); + + return true; +} + +static bool ati128Blit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) drv; + ATI128DeviceData *adev = (ATI128DeviceData*) dev; + volatile u8 *mmio = adrv->mmio_base; + + u32 dir_cmd = 0; + + if ((adev->source->config.format != adev->destination->config.format) || + (adev->blittingflags & DSBLIT_BLEND_ALPHACHANNEL)) + { + DFBRectangle sr = { rect->x, rect->y, rect->w, rect->h }; + DFBRectangle dr = { dx, dy, rect->w, rect->h }; + ati128StretchBlit( adrv, adev, &sr, &dr ); + return true; + } + + /* check which blitting direction should be used */ + if (rect->x <= dx) { + dir_cmd |= DST_X_RIGHT_TO_LEFT; + rect->x += rect->w-1; + dx += rect->w-1; + } + else { + dir_cmd |= DST_X_LEFT_TO_RIGHT; + } + if (rect->y <= dy) { + dir_cmd |= DST_Y_BOTTOM_TO_TOP; + rect->y += rect->h-1; + dy += rect->h-1; + } + else { + dir_cmd |= DST_Y_TOP_TO_BOTTOM; + } + + ati128_waitfifo( adrv, adev, 9 ); + + /* make sure that color compare register is restored to last state */ + ati128_out32( mmio, CLR_CMP_CNTL, adev->ATI_color_compare ); + + /* set blitting direction */ + ati128_out32( mmio, DP_CNTL, dir_cmd ); + + ati128_out32( mmio, DP_DATATYPE, adev->ATI_dst_bpp | SRC_DSTCOLOR ); + ati128_out32( mmio, DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT ); + + ati128_out32( mmio, SRC_Y_X, (rect->y << 16) | rect->x); + ati128_out32( mmio, DST_Y_X, (S14(dy) << 16) | S12(dx) ); + ati128_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | rect->w); + + /* set CLR_CMP_CNTL to zero, to insure that drawing funcions work corrently */ + if (adev->ATI_color_compare) + ati128_out32( mmio, CLR_CMP_CNTL, 0 ); + + if (dir_cmd != (DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT)) { + ati128_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | + DST_Y_TOP_TO_BOTTOM ); + } + + return true; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_ATI_RAGE128: /* ATI Rage 128 */ + return 1; + } + + return 0; +} + + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "ATI Rage 128 Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + info->version.major = 0; + info->version.minor = 2; + + info->driver_data_size = sizeof (ATI128DriverData); + info->device_data_size = sizeof (ATI128DeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + + adrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!adrv->mmio_base) + return DFB_IO; + + funcs->CheckState = ati128CheckState; + funcs->SetState = ati128SetState; + funcs->EngineSync = ati128EngineSync; + + funcs->FillRectangle = ati128FillRectangle; + funcs->DrawRectangle = ati128DrawRectangle; + funcs->DrawLine = ati128DrawLine; + funcs->Blit = ati128Blit; + funcs->StretchBlit = ati128StretchBlit; + + /* overlay support */ + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &atiOverlayFuncs ); + + return DFB_OK; +} + + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + ATI128DeviceData *adev = (ATI128DeviceData*) device_data; + volatile u8 *mmio = adrv->mmio_base; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Rage 128" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "ATI" ); + + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = ATI128_SUPPORTED_DRAWINGFUNCTIONS | + ATI128_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = ATI128_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = ATI128_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + + /* initialize card */ + ati128_waitfifo( adrv, adev, 6 ); + + ati128_out32( mmio, DP_GUI_MASTER_CNTL, + GMC_SRC_PITCH_OFFSET_DEFAULT | + GMC_DST_PITCH_OFFSET_DEFAULT | + GMC_SRC_CLIP_DEFAULT | + GMC_DST_CLIP_DEFAULT | + GMC_BRUSH_SOLIDCOLOR | + GMC_SRC_DSTCOLOR | + GMC_BYTE_ORDER_MSB_TO_LSB | + GMC_DP_CONVERSION_TEMP_6500 | + ROP3_PATCOPY | + GMC_DP_SRC_RECT | + GMC_3D_FCN_EN_CLR | + GMC_DST_CLR_CMP_FCN_CLEAR | + GMC_AUX_CLIP_CLEAR | + GMC_WRITE_MASK_SET); + + ati128_out32( mmio, SCALE_3D_CNTL, 0x00000000 ); + ati128_out32( mmio, TEX_CNTL, 0x00000000 ); + + /* reserve 32bit pixel for fake texture at end of framebuffer */ + adev->ATI_fake_texture_src = dfb_gfxcard_reserve_memory( device, 4*32 ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + ATI128DeviceData *adev = (ATI128DeviceData*) device_data; + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + volatile u8 *mmio = adrv->mmio_base; + + D_DEBUG( "DirectFB/ATI128: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/ATI128: %9d ati128_waitfifo calls\n", + adev->waitfifo_calls ); + D_DEBUG( "DirectFB/ATI128: %9d register writes (ati128_waitfifo sum)\n", + adev->waitfifo_sum ); + D_DEBUG( "DirectFB/ATI128: %9d FIFO wait cycles (depends on CPU)\n", + adev->fifo_waitcycles ); + D_DEBUG( "DirectFB/ATI128: %9d IDLE wait cycles (depends on CPU)\n", + adev->idle_waitcycles ); + D_DEBUG( "DirectFB/ATI128: %9d FIFO space cache hits(depends on CPU)\n", + adev->fifo_cache_hits ); + D_DEBUG( "DirectFB/ATI128: Conclusion:\n" ); + D_DEBUG( "DirectFB/ATI128: Average register writes/ati128_waitfifo" + "call:%.2f\n", + adev->waitfifo_sum/(float)(adev->waitfifo_calls) ); + D_DEBUG( "DirectFB/ATI128: Average wait cycles/ati128_waitfifo call:" + " %.2f\n", + adev->fifo_waitcycles/(float)(adev->waitfifo_calls) ); + D_DEBUG( "DirectFB/ATI128: Average fifo space cache hits: %02d%%\n", + (int)(100 * adev->fifo_cache_hits/ + (float)(adev->waitfifo_calls)) ); + + /* clean up, make sure that aty128fb does not hang in kernel space + afterwards */ + ati128_waitfifo( adrv, adev, 3 ); + + ati128_out32( mmio, DP_GUI_MASTER_CNTL, + GMC_SRC_PITCH_OFFSET_DEFAULT | + GMC_DST_PITCH_OFFSET_DEFAULT | + GMC_SRC_CLIP_DEFAULT | + GMC_DST_CLIP_DEFAULT | + GMC_BRUSH_SOLIDCOLOR | + GMC_SRC_DSTCOLOR | + GMC_BYTE_ORDER_MSB_TO_LSB | + GMC_DP_CONVERSION_TEMP_6500 | + ROP3_PATCOPY | + GMC_DP_SRC_RECT | + GMC_3D_FCN_EN_CLR | + GMC_DST_CLR_CMP_FCN_CLEAR | + GMC_AUX_CLIP_CLEAR | + GMC_WRITE_MASK_SET); + + ati128_out32( mmio, SCALE_3D_CNTL, 0x00000000 ); + ati128_out32( mmio, TEX_CNTL, 0x00000000 ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, adrv->mmio_base, -1 ); +} diff --git a/Source/DirectFB/gfxdrivers/ati128/ati128.h b/Source/DirectFB/gfxdrivers/ati128/ati128.h new file mode 100755 index 0000000..9b6d149 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/ati128.h @@ -0,0 +1,76 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___ATI128_H__ +#define ___ATI128_H__ + +#include +#include +#include + +typedef struct { + volatile u8 *mmio_base; +} ATI128DriverData; + +typedef struct { + CoreSurface *source; + CoreSurface *destination; + CoreSurfaceBufferLock *src; + DFBSurfaceBlittingFlags blittingflags; + + /* store some ATI register values in native format */ + u32 ATI_dst_bpp; + u32 ATI_color_compare; + u32 ATI_blend_function; + + /* used for the fake texture hack */ + u32 ATI_fake_texture_src; + u32 fake_texture_color; + unsigned int fake_texture_number; + + /* state validation */ + int v_destination; + int v_color; + int v_blending_function; + int v_source; + int v_src_colorkey; + int v_blittingflags; + + /* for fifo/performance monitoring */ + unsigned int fifo_space; + + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; +} ATI128DeviceData; + +extern DisplayLayerFuncs atiOverlayFuncs; + +#endif diff --git a/Source/DirectFB/gfxdrivers/ati128/ati128_overlay.c b/Source/DirectFB/gfxdrivers/ati128/ati128_overlay.c new file mode 100755 index 0000000..0a96f7c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/ati128_overlay.c @@ -0,0 +1,447 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include +#include + +#include "regs.h" +#include "mmio.h" +#include "ati128.h" + +typedef struct { + CoreLayerRegionConfig config; + + /* overlay registers */ + struct { + u32 H_INC; + u32 STEP_BY; + u32 Y_X_START; + u32 Y_X_END; + u32 V_INC; + u32 P1_BLANK_LINES_AT_TOP; + u32 P23_BLANK_LINES_AT_TOP; + u32 VID_BUF_PITCH0_VALUE; + u32 VID_BUF_PITCH1_VALUE; + u32 P1_X_START_END; + u32 P2_X_START_END; + u32 P3_X_START_END; + u32 VID_BUF0_BASE_ADRS; + u32 VID_BUF1_BASE_ADRS; + u32 VID_BUF2_BASE_ADRS; + u32 P1_V_ACCUM_INIT; + u32 P23_V_ACCUM_INIT; + u32 P1_H_ACCUM_INIT; + u32 P23_H_ACCUM_INIT; + u32 SCALE_CNTL; + } regs; +} ATIOverlayLayerData; + +static void ov0_set_regs( ATI128DriverData *adrv, ATIOverlayLayerData *aov0 ); +static void ov0_calc_regs( ATI128DriverData *adrv, ATIOverlayLayerData *aov0, + CoreLayerRegionConfig *config, CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +#define OV0_SUPPORTED_OPTIONS (DLOP_NONE) + +/**********************/ + +static int +ov0LayerDataSize( void ) +{ + return sizeof(ATIOverlayLayerData); +} + +static DFBResult +ov0InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + volatile u8 *mmio = adrv->mmio_base; + + /* set capabilities and type */ + description->caps = DLCAPS_SCREEN_LOCATION | DLCAPS_SURFACE; + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "ATI128 Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags = DCAF_NONE; + + /* reset overlay */ + ati128_out32( mmio, OV0_SCALE_CNTL, 0x80000000 ); + ati128_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 ); + ati128_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 ); + ati128_out32( mmio, OV0_FILTER_CNTL, 0x0000000f ); + ati128_out32( mmio, OV0_COLOR_CNTL, 0x00101000 ); + ati128_out32( mmio, OV0_KEY_CNTL, 0x10 ); + ati128_out32( mmio, OV0_TEST, 0 ); + + return DFB_OK; +} + + +static void +ov0OnOff( ATI128DriverData *adrv, + ATIOverlayLayerData *aov0, + int on ) +{ + /* set/clear enable bit */ + if (on) + aov0->regs.SCALE_CNTL |= R128_SCALER_ENABLE; + else + aov0->regs.SCALE_CNTL &= ~R128_SCALER_ENABLE; + + /* write back to card */ + ati128_out32( adrv->mmio_base, OV0_SCALE_CNTL, aov0->regs.SCALE_CNTL ); +} + +static DFBResult +ov0TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + /* check for unsupported options */ + if (config->options & ~OV0_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* check pixel format */ + switch (config->format) { + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + break; + + default: + fail |= CLRCF_FORMAT; + } + + /* check width */ + if (config->width > 2048 || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 1024 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ov0SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + ATIOverlayLayerData *aov0 = (ATIOverlayLayerData*) layer_data; + + /* remember configuration */ + aov0->config = *config; + + ov0_calc_regs( adrv, aov0, config, surface, lock ); + ov0_set_regs( adrv, aov0 ); + + /* enable overlay */ + ov0OnOff( adrv, aov0, 1 ); + + return DFB_OK; +} + +static DFBResult +ov0RemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + ATIOverlayLayerData *aov0 = (ATIOverlayLayerData*) layer_data; + + /* disable overlay */ + ov0OnOff( adrv, aov0, 0 ); + + return DFB_OK; +} + +static DFBResult +ov0FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + ATI128DriverData *adrv = (ATI128DriverData*) driver_data; + ATIOverlayLayerData *aov0 = (ATIOverlayLayerData*) layer_data; + + dfb_surface_flip( surface, false ); + + ov0_calc_regs( adrv, aov0, &aov0->config, surface, lock ); + ov0_set_regs( adrv, aov0 ); + + return DFB_OK; +} + + +DisplayLayerFuncs atiOverlayFuncs = { + .LayerDataSize = ov0LayerDataSize, + .InitLayer = ov0InitLayer, + + .TestRegion = ov0TestRegion, + .SetRegion = ov0SetRegion, + .RemoveRegion = ov0RemoveRegion, + .FlipRegion = ov0FlipRegion, +}; + +/* internal */ + +static void ov0_set_regs( ATI128DriverData *adrv, ATIOverlayLayerData *aov0 ) +{ + volatile u8 *mmio = adrv->mmio_base; + + ati128_out32( mmio, OV0_REG_LOAD_CNTL, 1 ); + while (!(ati128_in32( mmio, OV0_REG_LOAD_CNTL ) & (1 << 3))); + + ati128_out32( mmio, OV0_H_INC, + aov0->regs.H_INC ); + + ati128_out32( mmio, OV0_STEP_BY, + aov0->regs.STEP_BY ); + + ati128_out32( mmio, OV0_Y_X_START, + aov0->regs.Y_X_START ); + + ati128_out32( mmio, OV0_Y_X_END, + aov0->regs.Y_X_END ); + + ati128_out32( mmio, OV0_V_INC, + aov0->regs.V_INC ); + + ati128_out32( mmio, OV0_P1_BLANK_LINES_AT_TOP, + aov0->regs.P1_BLANK_LINES_AT_TOP ); + + ati128_out32( mmio, OV0_P23_BLANK_LINES_AT_TOP, + aov0->regs.P23_BLANK_LINES_AT_TOP ); + + ati128_out32( mmio, OV0_VID_BUF_PITCH0_VALUE, + aov0->regs.VID_BUF_PITCH0_VALUE ); + + ati128_out32( mmio, OV0_VID_BUF_PITCH1_VALUE, + aov0->regs.VID_BUF_PITCH1_VALUE ); + + ati128_out32( mmio, OV0_P1_X_START_END, + aov0->regs.P1_X_START_END ); + + ati128_out32( mmio, OV0_P2_X_START_END, + aov0->regs.P2_X_START_END ); + + ati128_out32( mmio, OV0_P3_X_START_END, + aov0->regs.P3_X_START_END ); + + ati128_out32( mmio, OV0_VID_BUF0_BASE_ADRS, + aov0->regs.VID_BUF0_BASE_ADRS ); + + ati128_out32( mmio, OV0_VID_BUF1_BASE_ADRS, + aov0->regs.VID_BUF1_BASE_ADRS ); + + ati128_out32( mmio, OV0_VID_BUF2_BASE_ADRS, + aov0->regs.VID_BUF2_BASE_ADRS ); + + ati128_out32( mmio, OV0_P1_V_ACCUM_INIT, + aov0->regs.P1_V_ACCUM_INIT ); + + ati128_out32( mmio, OV0_P23_V_ACCUM_INIT, + aov0->regs.P23_V_ACCUM_INIT ); + + ati128_out32( mmio, OV0_P1_H_ACCUM_INIT, + aov0->regs.P1_H_ACCUM_INIT ); + + ati128_out32( mmio, OV0_P23_H_ACCUM_INIT, + aov0->regs.P23_H_ACCUM_INIT ); + + ati128_out32( mmio, OV0_SCALE_CNTL, + aov0->regs.SCALE_CNTL ); + + ati128_out32( mmio, OV0_REG_LOAD_CNTL, 0 ); +} + +static void ov0_calc_regs( ATI128DriverData *adrv, + ATIOverlayLayerData *aov0, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + int h_inc, v_inc, step_by, tmp; + int p1_h_accum_init, p23_h_accum_init; + int p1_v_accum_init, p23_v_accum_init; + + DFBRegion dstBox; + int dst_w; + int dst_h; + u32 offset_u = 0, offset_v = 0; + + /* destination box */ + dstBox.x1 = config->dest.x; + dstBox.y1 = config->dest.y; + dstBox.x2 = config->dest.x + config->dest.w; + dstBox.y2 = config->dest.y + config->dest.h; + + /* destination size */ + dst_w = config->dest.w; + dst_h = config->dest.h; + + /* clear everything but the enable bit that may be set*/ + aov0->regs.SCALE_CNTL &= R128_SCALER_ENABLE; + + + /* calculate incrementors */ + h_inc = (surface->config.size.w << 12) / dst_w; + v_inc = (surface->config.size.h << 20) / dst_h; + step_by = 1; + + while (h_inc >= (2 << 12)) { + step_by++; + h_inc >>= 1; + } + + /* calculate values for horizontal accumulators */ + tmp = 0x00028000 + (h_inc << 3); + p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000); + + tmp = 0x00028000 + (h_inc << 2); + p23_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0x70000000); + + /* calculate values for vertical accumulators */ + tmp = 0x00018000; + p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; + + tmp = 0x00018000; + p23_v_accum_init = ((tmp << 4) & 0x01ff8000) | 0x00000001; + + /* choose pixel format and calculate buffer offsets for planar modes */ + switch (surface->config.format) { + case DSPF_UYVY: + aov0->regs.SCALE_CNTL = R128_SCALER_SOURCE_YVYU422; + break; + + case DSPF_YUY2: + aov0->regs.SCALE_CNTL = R128_SCALER_SOURCE_VYUY422; + break; + + case DSPF_I420: + aov0->regs.SCALE_CNTL = R128_SCALER_SOURCE_YUV12; + + offset_u = lock->offset + + surface->config.size.h * lock->pitch; + offset_v = offset_u + + (surface->config.size.h >> 1) * (lock->pitch >> 1); + break; + + case DSPF_YV12: + aov0->regs.SCALE_CNTL = R128_SCALER_SOURCE_YUV12; + + offset_v = lock->offset + + surface->config.size.h * lock->pitch; + offset_u = offset_v + + (surface->config.size.h >> 1) * (lock->pitch >> 1); + break; + + default: + D_BUG("unexpected pixelformat"); + aov0->regs.SCALE_CNTL = 0; + return; + } + + aov0->regs.SCALE_CNTL |= R128_SCALER_DOUBLE_BUFFER | + R128_SCALER_BURST_PER_PLANE | + R128_SCALER_Y2R_TEMP | + R128_SCALER_PIX_EXPAND; + + aov0->regs.H_INC = h_inc | ((h_inc >> 1) << 16); + aov0->regs.V_INC = v_inc; + aov0->regs.STEP_BY = step_by | (step_by << 8); + aov0->regs.Y_X_START = dstBox.x1 | (dstBox.y1 << 16); + aov0->regs.Y_X_END = dstBox.x2 | (dstBox.y2 << 16); + aov0->regs.P1_BLANK_LINES_AT_TOP = 0x00000fff | ((surface->config.size.h - 1) << 16); + aov0->regs.P23_BLANK_LINES_AT_TOP = 0x000007ff | ((((surface->config.size.h + 1) >> 1) - 1) << 16); + aov0->regs.VID_BUF_PITCH0_VALUE = lock->pitch; + aov0->regs.VID_BUF_PITCH1_VALUE = lock->pitch >> 1; + aov0->regs.P1_X_START_END = surface->config.size.w - 1; + aov0->regs.P2_X_START_END = (surface->config.size.w >> 1) - 1; + aov0->regs.P3_X_START_END = (surface->config.size.w >> 1) - 1; + aov0->regs.VID_BUF0_BASE_ADRS = lock->offset & 0x03fffff0; + aov0->regs.VID_BUF1_BASE_ADRS = (offset_u & 0x03fffff0) | 1; + aov0->regs.VID_BUF2_BASE_ADRS = (offset_v & 0x03fffff0) | 1; + aov0->regs.P1_H_ACCUM_INIT = p1_h_accum_init; + aov0->regs.P23_H_ACCUM_INIT = p23_h_accum_init; + aov0->regs.P1_V_ACCUM_INIT = p1_v_accum_init; + aov0->regs.P23_V_ACCUM_INIT = p23_v_accum_init; +} + diff --git a/Source/DirectFB/gfxdrivers/ati128/ati128_state.c b/Source/DirectFB/gfxdrivers/ati128/ati128_state.c new file mode 100755 index 0000000..ebe52d7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/ati128_state.c @@ -0,0 +1,314 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "ati128.h" + +#include "ati128_state.h" + + +static u32 ati128SourceBlend[] = { + SCALE_3D_CNTL_ALPHA_BLEND_SRC_ZERO, /* DSBF_ZERO */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_ONE, /* DSBF_ONE */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_SRCCOLOR, /* DSBF_SRCCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVSRCCOLOR, /* DSBF_INVSRCCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_SRCALPHA, /* DSBF_SRCALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVSRCALPHA, /* DSBF_INVSRCALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_DSTALPHA, /* DSBF_DESTALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVDSTALPHA, /* DSBF_INVDESTALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_DSTCOLOR, /* DSBF_DESTCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVDSTCOLOR, /* DSBF_INVDESTCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_SRC_SAT /* DSBF_SRCALPHASAT */ +}; + +static u32 ati128DestBlend[] = { + SCALE_3D_CNTL_ALPHA_BLEND_DST_ZERO, /* DSBF_ZERO */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_ONE, /* DSBF_ONE */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_SRCCOLOR, /* DSBF_SRCCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_INVSRCCOLOR, /* DSBF_INVSRCCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_SRCALPHA, /* DSBF_SRCALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_INVSRCALPHA, /* DSBF_INVSRCALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_DSTALPHA, /* DSBF_DESTALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_INVDSTALPHA, /* DSBF_INVDESTALPHA */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_DSTCOLOR, /* DSBF_DESTCOLOR */ + SCALE_3D_CNTL_ALPHA_BLEND_DST_INVDSTCOLOR, /* DSBF_INVDESTCOLOR */ + 0 /* DSBF_SRCALPHASAT */ +}; + +void ati128_set_destination( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + CoreSurface *destination = state->destination; + + if (adev->v_destination) + return; + + ati128_waitfifo( adrv, adev, 1 ); + + switch (destination->config.format) { + case DSPF_RGB332: + ati128_out32( adrv->mmio_base, DST_PITCH_OFFSET, + ((state->dst.pitch >> 3) << 21) | + (state->dst.offset >> 5)); + + adev->ATI_dst_bpp = DST_8BPP_RGB332; + break; + case DSPF_ARGB1555: + ati128_out32( adrv->mmio_base, DST_PITCH_OFFSET, + ((state->dst.pitch >> 4) << 21) | + (state->dst.offset >> 5)); + + adev->ATI_dst_bpp = DST_15BPP; + break; + case DSPF_RGB16: + ati128_out32( adrv->mmio_base, DST_PITCH_OFFSET, + ((state->dst.pitch >> 4) << 21) | + (state->dst.offset >> 5)); + + adev->ATI_dst_bpp = DST_16BPP; + break; + case DSPF_RGB24: + ati128_out32( adrv->mmio_base, DST_PITCH_OFFSET, + ((state->dst.pitch >> 3) << 21) | + (state->dst.offset >> 5)); + + adev->ATI_dst_bpp = DST_24BPP; + break; + case DSPF_RGB32: + case DSPF_ARGB: + ati128_out32( adrv->mmio_base, DST_PITCH_OFFSET, + ((state->dst.pitch >> 5) << 21) | + (state->dst.offset >> 5)); + + adev->ATI_dst_bpp = DST_32BPP; + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + adev->destination = destination; + + adev->v_destination = 1; +} + +void ati128_set_source( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + + if (adev->v_source) + return; + + ati128_waitfifo( adrv, adev, 3 ); + + switch (state->source->config.format) { + case DSPF_RGB332: + ati128_out32( adrv->mmio_base, SRC_PITCH, + state->src.pitch >> 3); + + ati128_out32( adrv->mmio_base, CLR_CMP_MASK, 0x000000FF ); + break; + case DSPF_ARGB1555: + ati128_out32( adrv->mmio_base, SRC_PITCH, + state->src.pitch >> 4); + + ati128_out32( adrv->mmio_base, CLR_CMP_MASK, 0x00007FFF ); + break; + case DSPF_RGB16: + ati128_out32( adrv->mmio_base, SRC_PITCH, + state->src.pitch >> 4); + + ati128_out32( adrv->mmio_base, CLR_CMP_MASK, 0x0000FFFF ); + break; + case DSPF_RGB24: + ati128_out32( adrv->mmio_base, SRC_PITCH, + state->src.pitch >> 3); + + ati128_out32( adrv->mmio_base, CLR_CMP_MASK, 0x00FFFFFF ); + break; + case DSPF_RGB32: + case DSPF_ARGB: + ati128_out32( adrv->mmio_base, SRC_PITCH, + state->src.pitch >> 5); + + ati128_out32( adrv->mmio_base, CLR_CMP_MASK, 0x00FFFFFF ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + ati128_out32( adrv->mmio_base, SRC_OFFSET, + state->src.offset ); + + adev->source = state->source; + adev->src = &state->src; + adev->v_source = 1; +} + +void ati128_set_clip( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + + ati128_waitfifo( adrv, adev, 2 ); + + /* 24bpp needs special treatment */ + if (state->destination->config.format == DSPF_RGB24) { + ati128_out32( adrv->mmio_base, SC_TOP_LEFT, + (state->clip.y1 << 16) | (state->clip.x1*3) ); + + ati128_out32( adrv->mmio_base, SC_BOTTOM_RIGHT, + (state->clip.y2 << 16) | ((state->clip.x2*3) + 3)); + } + else { + ati128_out32( adrv->mmio_base, SC_TOP_LEFT, + (state->clip.y1 << 16) | state->clip.x1 ); + + ati128_out32( adrv->mmio_base, SC_BOTTOM_RIGHT, + (state->clip.y2 << 16) | state->clip.x2 ); + } +} + +void ati128_set_color( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + u32 fill_color = 0; + + if (adev->v_color) + return; + + switch (state->destination->config.format) { + case DSPF_RGB332: + fill_color = PIXEL_RGB332( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_ARGB1555: + fill_color = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB16: + fill_color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB24: + case DSPF_RGB32: + fill_color = PIXEL_RGB32( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_ARGB: + fill_color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + ati128_waitfifo( adrv, adev, 1 ); + ati128_out32( adrv->mmio_base, DP_BRUSH_FRGD_CLR, fill_color); + + + adev->fake_texture_color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + + adev->v_color = 1; +} + +void ati128_set_src_colorkey( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + if (adev->v_src_colorkey) + return; + + ati128_waitfifo( adrv, adev, 1 ); + ati128_out32( adrv->mmio_base, CLR_CMP_CLR_SRC, state->src_colorkey ); + + adev->v_src_colorkey = 1; +} + +void ati128_set_blittingflags( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + if (adev->v_blittingflags) + return; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + adev->ATI_color_compare = (1 << 24) | 5; + } + else { + adev->ATI_color_compare = 0; + } + + adev->blittingflags = state->blittingflags; + adev->v_blittingflags = 1; +} + +void ati128_set_blending_function( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ) +{ + if (adev->v_blending_function) + return; + + adev->ATI_blend_function = SCALE_3D_CNTL_SCALE_3D_FN_SCALE | + ati128SourceBlend[state->src_blend - 1] | + ati128DestBlend [state->dst_blend - 1] | + SCALE_3D_CNTL_TEX_MAP_AEN_ON; + + adev->v_blending_function = 1; +} diff --git a/Source/DirectFB/gfxdrivers/ati128/ati128_state.h b/Source/DirectFB/gfxdrivers/ati128/ati128_state.h new file mode 100755 index 0000000..4cee1cf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/ati128_state.h @@ -0,0 +1,62 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___ATI128_STATE_H__ +#define ___ATI128_STATE_H__ + +#include "ati128.h" + +void ati128_set_destination( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); +void ati128_set_source( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + +void ati128_set_blittingflags( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + +void ati128_set_clip( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + +void ati128_set_color( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + +void ati128_set_src_colorkey( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + +void ati128_set_blending_function( ATI128DriverData *adrv, + ATI128DeviceData *adev, + CardState *state ); + + +#endif diff --git a/Source/DirectFB/gfxdrivers/ati128/mmio.h b/Source/DirectFB/gfxdrivers/ati128/mmio.h new file mode 100755 index 0000000..d2df943 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/mmio.h @@ -0,0 +1,121 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + + +#ifndef ___ATI128_MMIO_H__ +#define ___ATI128_MMIO_H__ + +#include + +#include "ati128.h" + +static inline void +ati128_out32(volatile u8 *mmioaddr, u32 reg, u32 value) +{ +#ifdef __powerpc__ + asm volatile("stwbrx %0,%1,%2;eieio" : : "r"(value), "b"(reg), + "r"(mmioaddr) : "memory"); + +#else + *((volatile u32*)(mmioaddr+reg)) = value; +#endif +} + +static inline u32 +ati128_in32(volatile u8 *mmioaddr, u32 reg) +{ +#ifdef __powerpc__ + u32 value; + + asm volatile("lwbrx %0,%1,%2;eieio" : "=r"(value) : "b"(reg), "r"(mmioaddr)); + + return value; +#else + return *((volatile u32*)(mmioaddr+reg)); +#endif +} + +static inline void ati128_waitidle( ATI128DriverData *adrv, + ATI128DeviceData *adev ) +{ + int timeout = 1000000; + + while (timeout--) { + if ((ati128_in32( adrv->mmio_base, GUI_STAT) & 0x00000FFF) == 64) + break; + + adev->idle_waitcycles++; + } + + timeout = 1000000; + + while (timeout--) { + if ((ati128_in32( adrv->mmio_base, GUI_STAT) & (GUI_ACTIVE | ENG_3D_BUSY)) == ENGINE_IDLE) + break; + + adev->idle_waitcycles++; + } + + ati128_out32( adrv->mmio_base, PC_NGUI_CTLSTAT, + ati128_in32( adrv->mmio_base, PC_NGUI_CTLSTAT) | 0x000000ff); + + timeout = 1000000; + while (timeout--) { + if ((ati128_in32( adrv->mmio_base, PC_NGUI_CTLSTAT) & PC_BUSY) != PC_BUSY) + break; + + adev->idle_waitcycles++; + } + adev->fifo_space = 60; +} + +static inline void ati128_waitfifo( ATI128DriverData *adrv, + ATI128DeviceData *adev, + unsigned int requested_fifo_space) +{ + int timeout = 1000000; + + adev->waitfifo_sum += requested_fifo_space; + adev->waitfifo_calls++; + + if (adev->fifo_space < requested_fifo_space) { + while (timeout--) { + adev->fifo_waitcycles++; + + adev->fifo_space = ati128_in32( adrv->mmio_base, GUI_STAT) & 0x00000FFF; + if (adev->fifo_space >= requested_fifo_space) + break; + } + } + else { + adev->fifo_cache_hits++; + } + adev->fifo_space -= requested_fifo_space; +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/ati128/regs.h b/Source/DirectFB/gfxdrivers/ati128/regs.h new file mode 100755 index 0000000..168eeb0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ati128/regs.h @@ -0,0 +1,919 @@ +#ifndef REG_RAGE128_H +#define REG_RAGE128_H + +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000c +#define BIOS_0_SCRATCH 0x0010 +#define BUS_CNTL 0x0030 +#define GEN_INT_CNTL 0x0040 +#define CRTC_GEN_CNTL 0x0050 +#define CRTC_EXT_CNTL 0x0054 +#define DAC_CNTL 0x0058 +#define I2C_CNTL_1 0x0094 +#define PALETTE_INDEX 0x00b0 +#define PALETTE_DATA 0x00b4 +#define CONFIG_CNTL 0x00e0 +#define GEN_RESET_CNTL 0x00f0 +#define CONFIG_MEMSIZE 0x00f8 +#define MEM_CNTL 0x0140 +#define AGP_BASE 0x0170 +#define AGP_CNTL 0x0174 +#define AGP_APER_OFFSET 0x0178 +#define PCI_GART_PAGE 0x017c +#define PC_NGUI_MODE 0x0180 +#define PC_NGUI_CTLSTAT 0x0184 +#define MPP_TB_CONFIG 0x01C0 +#define MPP_GP_CONFIG 0x01C8 +#define VIPH_CONTROL 0x01D0 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020c +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022c +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define LVDS_GEN_CNTL 0x02d0 +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 +#define VGA_DDA_CONFIG 0x02e8 +#define VGA_DDA_ON_OFF 0x02ec +#define OV0_SCALE_CNTL 0x0420 +#define SUBPIC_CNTL 0x0540 +#define PM4_BUFFER_OFFSET 0x0700 +#define PM4_BUFFER_CNTL 0x0704 +#define PM4_BUFFER_WM_CNTL 0x0708 +#define PM4_BUFFER_DL_RPTR_ADDR 0x070c +#define PM4_BUFFER_DL_RPTR 0x0710 +#define PM4_BUFFER_DL_WPTR 0x0714 +#define PM4_VC_FPU_SETUP 0x071c +#define PM4_FPU_CNTL 0x0720 +#define PM4_VC_FORMAT 0x0724 +#define PM4_VC_CNTL 0x0728 +#define PM4_VC_I01 0x072c +#define PM4_VC_VLOFF 0x0730 +#define PM4_VC_VLSIZE 0x0734 +#define PM4_IW_INDOFF 0x0738 +#define PM4_IW_INDSIZE 0x073c +#define PM4_FPU_FPX0 0x0740 +#define PM4_FPU_FPY0 0x0744 +#define PM4_FPU_FPX1 0x0748 +#define PM4_FPU_FPY1 0x074c +#define PM4_FPU_FPX2 0x0750 +#define PM4_FPU_FPY2 0x0754 +#define PM4_FPU_FPY3 0x0758 +#define PM4_FPU_FPY4 0x075c +#define PM4_FPU_FPY5 0x0760 +#define PM4_FPU_FPY6 0x0764 +#define PM4_FPU_FPR 0x0768 +#define PM4_FPU_FPG 0x076c +#define PM4_FPU_FPB 0x0770 +#define PM4_FPU_FPA 0x0774 +#define PM4_FPU_INTXY0 0x0780 +#define PM4_FPU_INTXY1 0x0784 +#define PM4_FPU_INTXY2 0x0788 +#define PM4_FPU_INTARGB 0x078c +#define PM4_FPU_FPTWICEAREA 0x0790 +#define PM4_FPU_DMAJOR01 0x0794 +#define PM4_FPU_DMAJOR12 0x0798 +#define PM4_FPU_DMAJOR02 0x079c +#define PM4_FPU_STAT 0x07a0 +#define PM4_STAT 0x07b8 +#define PM4_TEST_CNTL 0x07d0 +#define PM4_MICROCODE_ADDR 0x07d4 +#define PM4_MICROCODE_RADDR 0x07d8 +#define PM4_MICROCODE_DATAH 0x07dc +#define PM4_MICROCODE_DATAL 0x07e0 +#define PM4_CMDFIFO_ADDR 0x07e4 +#define PM4_CMDFIFO_DATAH 0x07e8 +#define PM4_CMDFIFO_DATAL 0x07ec +#define PM4_BUFFER_ADDR 0x07f0 +#define PM4_BUFFER_DATAH 0x07f4 +#define PM4_BUFFER_DATAL 0x07f8 +#define PM4_MICRO_CNTL 0x07fc +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 + +/****************************************************************************** + * GUI Block Memory Mapped Registers * + * These registers are FIFOed. * + *****************************************************************************/ +#define PM4_FIFO_DATA_EVEN 0x1000 +#define PM4_FIFO_DATA_ODD 0x1004 + +#define DST_OFFSET 0x1404 +#define DST_PITCH 0x1408 +#define DST_WIDTH 0x140c +#define DST_HEIGHT 0x1410 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_X 0x141c +#define DST_Y 0x1420 +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142c +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_HEIGHT_WIDTH 0x143c +#define DP_GUI_MASTER_CNTL 0x146c +#define BRUSH_SCALE 0x1470 +#define BRUSH_Y_X 0x1474 +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DP_BRUSH_FRGD_CLR 0x147c +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158c +#define SRC_X_Y 0x1590 +#define DST_X_Y 0x1594 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_WIDTH_X_INCY 0x159c +#define DST_HEIGHT_Y 0x15a0 +#define DST_X_SUB 0x15a4 +#define DST_Y_SUB 0x15a8 +#define SRC_OFFSET 0x15ac +#define SRC_PITCH 0x15b0 +#define DST_HEIGHT_WIDTH_BW 0x15b4 +#define CLR_CMP_CNTL 0x15c0 +#define CLR_CMP_CLR_SRC 0x15c4 +#define CLR_CMP_CLR_DST 0x15c8 +#define CLR_CMP_MASK 0x15cc +#define DP_SRC_FRGD_CLR 0x15d8 +#define DP_SRC_BKGD_CLR 0x15dc +#define DST_BRES_ERR 0x1628 +#define DST_BRES_INC 0x162c +#define DST_BRES_DEC 0x1630 +#define DST_BRES_LNTH 0x1634 +#define DST_BRES_LNTH_SUB 0x1638 +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164c +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165c +#define GUI_DEBUG0 0x16a0 +#define GUI_DEBUG1 0x16a4 +#define GUI_TIMEOUT 0x16b0 +#define GUI_TIMEOUT0 0x16b4 +#define GUI_TIMEOUT1 0x16b8 +#define GUI_PROBE 0x16bc +#define DP_CNTL 0x16c0 +#define DP_DATATYPE 0x16c4 +#define DP_MIX 0x16c8 +#define DP_WRITE_MASK 0x16cc +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH 0x16e4 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +#define SC_TOP_LEFT 0x16ec +#define SC_BOTTOM_RIGHT 0x16f0 +#define SRC_SC_BOTTOM_RIGHT 0x16f4 +#define WAIT_UNTIL 0x1720 +#define CACHE_CNTL 0x1724 +#define GUI_STAT 0x1740 +#define PC_GUI_MODE 0x1744 +#define PC_GUI_CTLSTAT 0x1748 +#define PC_DEBUG_MODE 0x1760 +#define BRES_DST_ERR_DEC 0x1780 +#define TRAIL_BRES_T12_ERR_DEC 0x1784 +#define TRAIL_BRES_T12_INC 0x1788 +#define DP_T12_CNTL 0x178c +#define DST_BRES_T1_LNTH 0x1790 +#define DST_BRES_T2_LNTH 0x1794 +#define SCALE_SRC_HEIGHT_WIDTH 0x1994 +#define SCALE_OFFSET_0 0x1998 +#define SCALE_PITCH 0x199c +#define SCALE_X_INC 0x19a0 +#define SCALE_Y_INC 0x19a4 +#define SCALE_HACC 0x19a8 +#define SCALE_VACC 0x19ac +#define SCALE_DST_X_Y 0x19b0 +#define SCALE_DST_HEIGHT_WIDTH 0x19b4 +#define SCALE_3D_CNTL 0x1a00 +#define SCALE_3D_DATATYPE 0x1a20 +#define SETUP_CNTL 0x1bc4 +#define SOLID_COLOR 0x1bc8 +#define WINDOW_XY_OFFSET 0x1bcc +#define DRAW_LINE_POINT 0x1bd0 +#define SETUP_CNTL_PM4 0x1bd4 +#define DST_PITCH_OFFSET_C 0x1c80 +#define DP_GUI_MASTER_CNTL_C 0x1c84 +#define SC_TOP_LEFT_C 0x1c88 +#define SC_BOTTOM_RIGHT_C 0x1c8c + +#define CLR_CMP_MASK_3D 0x1A28 +#define MISC_3D_STATE_CNTL_REG 0x1CA0 +#define MC_SRC1_CNTL 0x19D8 +#define TEX_CNTL 0x1800 + +/* CONSTANTS */ +#define ENG_3D_BUSY 0x02000000 +#define GUI_ACTIVE 0x80000000 + + +#define ENGINE_IDLE 0x0 + +#define PLL_WR_EN 0x00000080 + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define X_MPLL_REF_FB_DIV 0x000a +#define XPLL_CNTL 0x000b +#define XDLL_CNTL 0x000c +#define XCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MCLK_CNTL 0x000f +#define AGP_PLL_CNTL 0x0010 +#define FCP_CNTL 0x0012 +#define PLL_TEST_CNTL 0x0013 + +#define PPLL_RESET 0x01 +#define PPLL_ATOMIC_UPDATE_EN 0x10000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000 +#define PPLL_REF_DIV_MASK 0x3FF +#define PPLL_FB3_DIV_MASK 0x7FF +#define PPLL_POST3_DIV_MASK 0x70000 +#define PPLL_ATOMIC_UPDATE_R 0x8000 +#define PPLL_ATOMIC_UPDATE_W 0x8000 +#define MEM_CFG_TYPE_MASK 0x3 +#define XCLK_SRC_SEL_MASK 0x7 +#define XPLL_FB_DIV_MASK 0xFF00 +#define X_MPLL_REF_DIV_MASK 0xFF + +/* CRTC control values (CRTC_GEN_CNTL) */ +#define CRTC_CSYNC_EN 0x00000010 + +#define CRTC_PIX_WIDTH_MASK 0x00000700 +#define CRTC_PIX_WIDTH_4BPP 0x00000100 +#define CRTC_PIX_WIDTH_8BPP 0x00000200 +#define CRTC_PIX_WIDTH_15BPP 0x00000300 +#define CRTC_PIX_WIDTH_16BPP 0x00000400 +#define CRTC_PIX_WIDTH_24BPP 0x00000500 +#define CRTC_PIX_WIDTH_32BPP 0x00000600 + +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_MASK 0xFF000000 +#define DAC_BLANKING 0x00000004 +#define DAC_RANGE_CNTL 0x00000003 +#define DAC_RANGE_CNTL 0x00000003 +#define DAC_PALETTE_ACCESS_CNTL 0x00000020 +#define DAC_PDWN 0x00008000 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* PC_GUI_CTLSTAT bit constants */ +#define PC_BUSY_INIT 0x10000000 +#define PC_BUSY_GUI 0x20000000 +#define PC_BUSY_NGUI 0x40000000 +#define PC_BUSY 0x80000000 + +#define BUS_MASTER_DIS 0x00000040 +#define PM4_BUFFER_CNTL_NONPM4 0x00000000 + +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_8x8MONO 0x00000000 +#define BRUSH_8x8MONO_LBKGD 0x00000100 +#define BRUSH_8x1MONO 0x00000200 +#define BRUSH_8x1MONO_LBKGD 0x00000300 +#define BRUSH_1x8MONO 0x00000400 +#define BRUSH_1x8MONO_LBKGD 0x00000500 +#define BRUSH_32x1MONO 0x00000600 +#define BRUSH_32x1MONO_LBKGD 0x00000700 +#define BRUSH_32x32MONO 0x00000800 +#define BRUSH_32x32MONO_LBKGD 0x00000900 +#define BRUSH_8x8COLOR 0x00000a00 +#define BRUSH_8x1COLOR 0x00000b00 +#define BRUSH_1x8COLOR 0x00000c00 +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 + +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 + +/* DP_GUI_MASTER_CNTL ROP3 named constants */ +#define ROP3_PATCOPY 0x00f00000 +#define ROP3_SRCCOPY 0x00cc0000 + +#define SRC_DSTCOLOR 0x00030000 + +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 + +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 + +/* LVDS_GEN_CNTL constants */ +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 0x8 +#define LVDS_BL_MOD_EN 0x00010000 +#define LVDS_DIGION 0x00040000 +#define LVDS_BLON 0x00080000 + + +/* from the ati128ddk */ + +#define FOG_3D_TABLE_START 0x1810 +#define FOG_3D_TABLE_END 0x1814 +#define FOG_3D_TABLE_DENSITY 0x181c + +#define FOG_TABLE_INDEX 0x1a14 +#define FOG_TABLE_DATA 0x1a18 + +/* MISC_3D_STATE */ +#define MISC_3D_STATE_SCALE_3D_FN_NOP (0x00000000 << 8) +#define MISC_3D_STATE_SCALE_3D_FN_SCALE (0x00000001 << 8) +#define MISC_3D_STATE_SCALE_3D_FN_TMAP_SHADE (0x00000002 << 8) +#define MISC_3D_STATE_SCALE_PIX_REP_BLEND (0x00000000 << 10) +#define MISC_3D_STATE_SCALE_PIX_REP_REPLICATE (0x00000001 << 10) +#define MISC_3D_STATE_ALPHA_COMB_FNC_ADD_CLAMP (0x00000000 << 12) +#define MISC_3D_STATE_ALPHA_COMB_FNC_ADD_NO_CLAMP (0x00000001 << 12) +#define MISC_3D_STATE_ALPHA_COMB_FNC_SUB_SRC_DST_CLAMP (0x00000002 << 12) +#define MISC_3D_STATE_ALPHA_COMB_FNC_SUB_SRC_DST_NO_CLAMP (0x00000003 << 12) +#define MISC_3D_STATE_FOG_TABLE_EN_VERTEX_FOG (0x00000000 << 14) +#define MISC_3D_STATE_FOG_TABLE_EN_TABLE_FOG (0x00000001 << 14) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_ZERO (0x00000000 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_ONE (0x00000001 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_SRCCOLOR (0x00000002 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_INVSRCCOLOR (0x00000003 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_SRCALPHA (0x00000004 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_INVSRCALPHA (0x00000005 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_DESTALPHA (0x00000006 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_INVDESTALPHA (0x00000007 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_DESTCOLOR (0x00000008 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_INVDESTCOLOR (0x00000009 << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_SRCALPHASAT (0x0000000a << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_BOTHSRCALPHA (0x0000000b << 16) +#define MISC_3D_STATE_ALPHA_BLEND_SRC_BOTHINVSRCALPHA (0x0000000c << 16) +#define MISC_3D_STATE_ALPHA_BLEND_DST_ZERO (0x00000000 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_ONE (0x00000001 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_SRCCOLOR (0x00000002 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_INVSRCCOLOR (0x00000003 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_SRCALPHA (0x00000004 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_INVSRCALPHA (0x00000005 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_DESTALPHA (0x00000006 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_INVDESTALPHA (0x00000007 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_DESTCOLOR (0x00000008 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_INVDESTCOLOR (0x00000009 << 20) +#define MISC_3D_STATE_ALPHA_BLEND_DST_SRCALPHASAT (0x0000000a << 20) +#define MISC_3D_STATE_ALPHA_TEST_OP_NEVER (0x00000000 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_LESS (0x00000001 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_LESSEQUAL (0x00000002 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_EQUAL (0x00000003 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_GREATEREQUAL (0x00000004 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_GREATER (0x00000005 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_NEQUAL (0x00000006 << 24) +#define MISC_3D_STATE_ALPHA_TEST_OP_ALWAYS (0x00000007 << 24) + + + +/* Z_STEN_CNTL */ +#define Z_STEN_CNTL_Z_PIX_WIDTH_16 (0x00000000 << 1) +#define Z_STEN_CNTL_Z_PIX_WIDTH_24 (0x00000001 << 1) +#define Z_STEN_CNTL_Z_PIX_WIDTH_32 (0x00000002 << 1) +#define Z_STEN_CNTL_Z_TEST_NEVER (0x00000000 << 4) +#define Z_STEN_CNTL_Z_TEST_LESS (0x00000001 << 4) +#define Z_STEN_CNTL_Z_TEST_LESSEQUAL (0x00000002 << 4) +#define Z_STEN_CNTL_Z_TEST_EQUAL (0x00000003 << 4) +#define Z_STEN_CNTL_Z_TEST_GREATEREQUAL (0x00000004 << 4) +#define Z_STEN_CNTL_Z_TEST_GREATER (0x00000005 << 4) +#define Z_STEN_CNTL_Z_TEST_NEQUAL (0x00000006 << 4) +#define Z_STEN_CNTL_Z_TEST_ALWAYS (0x00000007 << 4) +#define Z_STEN_CNTL_STENCIL_TEST_NEVER (0x00000000 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_LESS (0x00000001 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_LESSEQUAL (0x00000002 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_EQUAL (0x00000003 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_GREATEREQUAL (0x00000004 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_GREATER (0x00000005 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_NEQUAL (0x00000006 << 12) +#define Z_STEN_CNTL_STENCIL_TEST_ALWAYS (0x00000007 << 12) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_KEEP (0x00000000 << 16) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_ZERO (0x00000001 << 16) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_REPLACE (0x00000002 << 16) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_INC (0x00000003 << 16) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_DEC (0x00000004 << 16) +#define Z_STEN_CNTL_STENCIL_S_FAIL_OP_INV (0x00000005 << 16) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_KEEP (0x00000000 << 20) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_ZERO (0x00000001 << 20) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_REPLACE (0x00000002 << 20) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_INC (0x00000003 << 20) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_DEC (0x00000004 << 20) +#define Z_STEN_CNTL_STENCIL_ZPASS_OP_INV (0x00000005 << 20) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_KEEP (0x00000000 << 24) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_ZERO (0x00000001 << 24) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_REPLACE (0x00000002 << 24) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_INC (0x00000003 << 24) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_DEC (0x00000004 << 24) +#define Z_STEN_CNTL_STENCIL_ZFAIL_OP_INV (0x00000005 << 24) + +/* TEX_CNTL */ +#define TEX_CNTL_Z_EN_OFF (0x00000000 << 0) +#define TEX_CNTL_Z_EN_ON (0x00000001 << 0) +#define TEX_CNTL_Z_MASK_DIS (0x00000000 << 1) +#define TEX_CNTL_Z_MASK_EN (0x00000001 << 1) +#define TEX_CNTL_STENCIL_EN_OFF (0x00000000 << 3) +#define TEX_CNTL_STENCIL_EN_ON (0x00000001 << 3) +#define TEX_CNTL_TEX_EN_SHADE (0x00000000 << 4) +#define TEX_CNTL_TEX_EN_TMAP (0x00000001 << 4) +#define TEX_CNTL_SECONDARY_TEX_EN_OFF (0x00000000 << 5) +#define TEX_CNTL_SECONDARY_TEX_EN_ON (0x00000001 << 5) +#define TEX_CNTL_FOG_EN_OFF (0x00000000 << 7) +#define TEX_CNTL_FOG_EN_ON (0x00000001 << 7) +#define TEX_CNTL_DITHRE_EN_OFF (0x00000000 << 8) +#define TEX_CNTL_DITHRE_EN_ON (0x00000001 << 8) +#define TEX_CNTL_ALPHA_EN_OFF (0x00000000 << 9) +#define TEX_CNTL_ALPHA_EN_ON (0x00000001 << 9) +#define TEX_CNTL_ALPHA_TEST_EN_OFF (0x00000000 << 10) +#define TEX_CNTL_ALPHA_TEST_EN_ON (0x00000001 << 10) +#define TEX_CNTL_SPEC_LIGHT_EN_OFF (0x00000000 << 11) +#define TEX_CNTL_SPEC_LIGHT_EN_ON (0x00000001 << 11) +#define TEX_CNTL_TEX_CHROMA_KEY_EN_OFF (0x00000000 << 12) +#define TEX_CNTL_TEX_CHROMA_KEY_EN_ON (0x00000001 << 12) +#define TEX_CNTL_AMASK_EN_OFF (0x00000000 << 13) +#define TEX_CNTL_AMASK_EN_ON (0x00000001 << 13) +#define TEX_CNTL_LIGHT_FN_DIS (0x00000000 << 14) +#define TEX_CNTL_LIGHT_FN_COPY (0x00000001 << 14) +#define TEX_CNTL_LIGHT_FN_MODULATE (0x00000002 << 14) +#define TEX_CNTL_LIGHT_FN_ADD (0x00000003 << 14) +#define TEX_CNTL_LIGHT_FN_BLEND_CONSTANT (0x00000004 << 14) +#define TEX_CNTL_LIGHT_FN_BLEND_TEXTURE (0x00000005 << 14) +#define TEX_CNTL_LIGHT_FN_BLEND_VERTEX (0x00000006 << 14) +#define TEX_CNTL_LIGHT_FN_BLEND_CONST_COLOR (0x00000007 << 14) +#define TEX_CNTL_ALPHA_LIGHT_FN_DIS (0x00000000 << 18) +#define TEX_CNTL_ALPHA_LIGHT_FN_COPY (0x00000001 << 18) +#define TEX_CNTL_ALPHA_LIGHT_FN_MODULATE (0x00000002 << 18) +#define TEX_CNTL_ALPHA_LIGHT_FN_ADD (0x00000003 << 18) +//#define TEX_CNTL_ANTI_ALIAS_FN +#define TEX_CNTL_TEX_CACHE_FLUSH_OFF (0x00000000 << 23) +#define TEX_CNTL_TEX_CACHE_FLUSH_ON (0x00000001 << 23) +//#define TEX_CNTL_LOD_BIAS + + +/* PRIM_TEX_CNTL */ +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_NEAREST (0x00000000 << 0) +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_LINEAR (0x00000001 << 0) +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_MIPNEAREST (0x00000002 << 0) +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_MIPLINEAR (0x00000003 << 0) +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_LINEARMIPNEAREST (0x00000004 << 0) +#define PRIM_TEX_CNTL_PRIM_MIN_BLEND_FN_LINEARMIPLINEAR (0x00000005 << 0) +#define PRIM_TEX_CNTL_PRIM_MAG_BLEND_FN_NEAREST (0x00000000 << 4) +#define PRIM_TEX_CNTL_PRIM_MAG_BLEND_FN_LINEAR (0x00000001 << 4) +#define PRIM_TEX_CNTL_MIP_MAP_DIS_OFF (0x00000000 << 7) +#define PRIM_TEX_CNTL_MIP_MAP_DIS_ON (0x00000001 << 7) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_S_WRAP (0x00000000 << 8) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_S_MIRROR (0x00000001 << 8) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_S_CLAMP (0x00000002 << 8) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_S_BORDER_COLOR (0x00000003 << 8) +#define PRIM_TEX_CNTL_PRIM_TEX_WRAP_S_OFF (0x00000000 << 10) +#define PRIM_TEX_CNTL_PRIM_TEX_WRAP_S_ON (0x00000001 << 10) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_T_WRAP (0x00000000 << 11) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_T_MIRROR (0x00000001 << 11) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_T_CLAMP (0x00000002 << 11) +#define PRIM_TEX_CNTL_PRIM_TEX_CLAMP_MODE_T_BORDER_COLOR (0x00000003 << 11) +#define PRIM_TEX_CNTL_PRIM_TEX_WRAP_T_OFF (0x00000000 << 13) +#define PRIM_TEX_CNTL_PRIM_TEX_WRAP_T_ON (0x00000001 << 13) +#define PRIM_TEX_CNTL_PRIM_TEX_PERSPECTIVE_DIS_OFF (0x00000000 << 14) +#define PRIM_TEX_CNTL_PRIM_TEX_PERSPECTIVE_DIS_ON (0x00000001 << 14) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_VQ (0x00000000 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_CI4 (0x00000001 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_CI8 (0x00000002 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_ARGB1555 (0x00000003 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_RGB565 (0x00000004 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_RGB888 (0x00000005 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_ARGB8888 (0x00000006 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_RGB332 (0x00000007 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_Y8 (0x00000008 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_RGB8 (0x00000009 << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_CI16 (0x0000000a << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_YUV422 (0x0000000b << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_YUV422_2 (0x0000000c << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_AYUV444 (0x0000000d << 16) +#define PRIM_TEX_CNTL_PRIM_DATATYPE_ARGB4444 (0x0000000e << 16) +//#define PRIM_TEX_CNTL_PRIM_PALETTE_OFF_ +//#define PRIM_TEX_CNTL_PRIM_PSEUDOCOLOR_DATATYPE_ + + +/* SETP_CNTL */ +#define SETUP_CNTL_DONT_START_TRI_OFF (0x00000000 << 0) +#define SETUP_CNTL_DONT_START_TRI_ON (0x00000001 << 0) +#define SETUP_CNTL_Z_BIAS (0x00000000 << 1) +#define SETUP_CNTL_DONT_START_ANY_OFF (0x00000000 << 2) +#define SETUP_CNTL_DONT_START_ANY_ON (0x00000001 << 2) +#define SETUP_CNTL_COLOR_FNC_SOLID_COLOR (0x00000000 << 3) +#define SETUP_CNTL_COLOR_FNC_FLAT_VERT_1 (0x00000001 << 3) +#define SETUP_CNTL_COLOR_FNC_FLAT_VERT_2 (0x00000002 << 3) +#define SETUP_CNTL_COLOR_FNC_FLAT_VERT_3 (0x00000003 << 3) +#define SETUP_CNTL_COLOR_FNC_GOURAUD (0x00000004 << 3) +#define SETUP_CNTL_PRIM_TYPE_SELECT_TRI (0x00000000 << 7) +#define SETUP_CNTL_PRIM_TYPE_SELECT_LINE (0x00000001 << 7) +#define SETUP_CNTL_PRIM_TYPE_SELECT_POINT (0x00000002 << 7) +#define SETUP_CNTL_PRIM_TYPE_SELECT_POLY_EDGE (0x00000003 << 7) +#define SETUP_CNTL_TEXTURE_ST_FORMAT_MULT_W (0x00000000 << 9) +#define SETUP_CNTL_TEXTURE_ST_FORMAT_DIRECT (0x00000001 << 9) +#define SETUP_CNTL_STARTING_VERTEX_SELECT_1 (0x00000001 << 14) +#define SETUP_CNTL_STARTING_VERTEX_SELECT_2 (0x00000002 << 14) +#define SETUP_CNTL_STARTING_VERTEX_SELECT_3 (0x00000003 << 14) +#define SETUP_CNTL_ENDING_VERTEX_SELECT_1 (0x00000001 << 16) +#define SETUP_CNTL_ENDING_VERTEX_SELECT_2 (0x00000002 << 16) +#define SETUP_CNTL_ENDING_VERTEX_SELECT_3 (0x00000003 << 16) +#define SETUP_CNTL_SU_POLY_LINE_LAST (0x00000000 << 18) +#define SETUP_CNTL_SU_POLY_LINE_NOT_LAST (0x00000001 << 18) +#define SETUP_CNTL_SUB_PIX_AMOUNT_2BITS (0x00000000 << 19) +#define SETUP_CNTL_SUB_PIX_AMOUNT_4BITS (0x00000001 << 19) +//#define SETUP_CNTL_SU_POLY_EDGE +//#define SETUP_CNTL_SU_EDGE_DST_Y_MAJOR +//#define SETUP_CNTL_SU_STATE +#define SETUP_CNTL_SET_UP_CONTINUE (0x00000001 << 31) + +/* PM4_VC_FPU_SETUP */ +#define PM4_VC_FPU_SETUP_FRONT_DIR_CW (0x00000000 << 0) +#define PM4_VC_FPU_SETUP_FRONT_DIR_CCW (0x00000001 << 0) +#define PM4_VC_FPU_SETUP_BACKFACE_CULLING_FN_CULL (0x00000000 << 1) +#define PM4_VC_FPU_SETUP_BACKFACE_CULLING_FN_POINT (0x00000001 << 1) +#define PM4_VC_FPU_SETUP_BACKFACE_CULLING_FN_LINE (0x00000002 << 1) +#define PM4_VC_FPU_SETUP_BACKFACE_CULLING_FN_REV_SOLID (0x00000003 << 1) +#define PM4_VC_FPU_SETUP_FRONTFACE_CULLING_FN_CULL (0x00000000 << 3) +#define PM4_VC_FPU_SETUP_FRONTFACE_CULLING_FN_POINT (0x00000001 << 3) +#define PM4_VC_FPU_SETUP_FRONTFACE_CULLING_FN_LINE (0x00000002 << 3) +#define PM4_VC_FPU_SETUP_FRONTFACE_CULLING_FN_REV_SOLID (0x00000003 << 3) +#define PM4_VC_FPU_SETUP_PM4_COLOR_FCN_SOLID (0x00000000 << 5) +#define PM4_VC_FPU_SETUP_PM4_COLOR_FCN_FLAT (0x00000001 << 5) +#define PM4_VC_FPU_SETUP_PM4_COLOR_FCN_GOURAUD (0x00000002 << 5) +#define PM4_VC_FPU_SETUP_PM4_COLOR_FCN_GOURAUD2 (0x00000003 << 5) +#define PM4_VC_FPU_SETUP_PM4_SUB_PIX_AMOUNT_2BITS (0x00000000 << 7) +#define PM4_VC_FPU_SETUP_PM4_SUB_PIX_AMOUNT_4BITS (0x00000001 << 7) +#define PM4_VC_FPU_SETUP_FPU_MODE_2D (0x00000000 << 8) +#define PM4_VC_FPU_SETUP_FPU_MODE_3D (0x00000001 << 8) +#define PM4_VC_FPU_SETUP_TRAP_DISABLE_OFF (0x00000000 << 9) +#define PM4_VC_FPU_SETUP_TRAP_DISABLE_ON (0x00000001 << 9) +#define PM4_VC_FPU_SETUP_EDGE_ANTIALIAS_OFF (0x00000000 << 10) +#define PM4_VC_FPU_SETUP_EDGE_ANTIALIAS_ON (0x00000001 << 10) +#define PM4_VC_FPU_SETUP_SUPERSAMPLE_OFF (0x00000000 << 11) +#define PM4_VC_FPU_SETUP_SUPERSAMPLE_ON (0x00000001 << 11) +#define PM4_VC_FPU_SETUP_XFACTOR_2 (0x00000000 << 12) +#define PM4_VC_FPU_SETUP_XFACTOR_4 (0x00000001 << 12) +#define PM4_VC_FPU_SETUP_YFACTOR_2 (0x00000000 << 13) +#define PM4_VC_FPU_SETUP_YFACTOR_4 (0x00000001 << 13) +#define PM4_VC_FPU_SETUP_FLAT_SHADE_VERTEX_D3D (0x00000000 << 14) +#define PM4_VC_FPU_SETUP_FLAT_SHADE_VERTEX_OPENGL (0x00000001 << 14) +#define PM4_VC_FPU_SETUP_FPU_ROUND_EN_OFF (0x00000000 << 15) +#define PM4_VC_FPU_SETUP_FPU_ROUND_EN_ON (0x00000001 << 15) +#define PM4_VC_FPU_SETUP_VC_WM_SEL_8DW (0x00000000 << 16) +#define PM4_VC_FPU_SETUP_VC_WM_SEL_16DW (0x00000001 << 16) +#define PM4_VC_FPU_SETUP_VC_WM_SEL_32DW (0x00000002 << 16) + +/* SEC_TEX_CNTL */ +#define SEC_TEX_CNTL_SEC_SRC_SEL_ST_0 (0x00000000 << 0) +#define SEC_TEX_CNTL_SEC_SRC_SEL_ST_1 (0x00000001 << 0) + +/* [PRIM_ | SEC_] SEC_TEX_COMBINE_CNTL */ +#define TEX_COMBINE_CNTL_COMB_FNC_DIS (0x00000000 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_COPY (0x00000001 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_COPY_INP (0x00000002 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_MODULATE (0x00000003 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_MODULATE2X (0x00000004 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_MODULATE4X (0x00000005 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_ADD (0x00000006 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_ADD_SIGNED (0x00000007 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_VERTEX (0x00000008 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_TEXTURE (0x00000009 << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_CONST (0x0000000a << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_PREMULT (0x0000000b << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_PREV (0x0000000c << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_PREMULT_INV (0x0000000d << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_ADD_SIGNED2X (0x0000000e << 0) +#define TEX_COMBINE_CNTL_COMB_FNC_BLEND_CONST_COLOR (0x0000000f << 0) +#define TEX_COMBINE_CNTL_COLOR_FACTOR_TEX (0x00000004 << 4) +#define TEX_COMBINE_CNTL_COLOR_FACTOR_NTEX (0x00000005 << 4) +#define TEX_COMBINE_CNTL_COLOR_FACTOR_ALPHA (0x00000006 << 4) +#define TEX_COMBINE_CNTL_COLOR_FACTOR_NALPHA (0x00000007 << 4) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_CONST_COLOR (0x00000002 << 10) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_CONST_ALPHA (0x00000003 << 10) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_INT_COLOR (0x00000004 << 10) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_INT_ALPHA (0x00000005 << 10) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_PREV_COLOR (0x00000008 << 10) +#define TEX_COMBINE_CNTL_INPUT_FACTOR_PREV_ALPHA (0x00000009 << 10) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_DIS (0x00000000 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_COPY (0x00000001 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_COPY_INP (0x00000002 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_MODULATE (0x00000003 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_MODULATE2X (0x00000004 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_MODULATE4X (0x00000005 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_ADD (0x00000006 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_ADD_SIGNED (0x00000007 << 14) +#define TEX_COMBINE_CNTL_COMB_FNC_ALPHA_ADD_SIGNED2X (0x0000000e << 14) +#define TEX_COMBINE_CNTL_ALPHA_FACTOR_TEX_ALPHA (0x00000006 << 18) +#define TEX_COMBINE_CNTL_ALPHA_FACTOR_NTEX_ALPHA (0x00000007 << 18) +#define TEX_COMBINE_CNTL_INP_FACTOR_ALPHA_CONST_ALPHA (0x00000001 << 25) +#define TEX_COMBINE_CNTL_INP_FACTOR_ALPHA_INT_ALPHA (0x00000002 << 25) +#define TEX_COMBINE_CNTL_INP_FACTOR_ALPHA_PREV_ALPHA (0x00000004 << 25) + + +/* SCALE_3D_CNTL */ +#define SCALE_3D_CNTL_SCALE_DITHER_ERR_DIFF (0x00000000 << 1) +#define SCALE_3D_CNTL_SCALE_DITHER_TABLE (0x00000001 << 1) +#define SCALE_3D_CNTL_TEX_CACHE_SIZE_FULL (0x00000000 << 2) +#define SCALE_3D_CNTL_TEX_CACHE_SIZE_HALF (0x00000001 << 2) +#define SCALE_3D_CNTL_DITHER_INIT_CURR (0x00000000 << 3) +#define SCALE_3D_CNTL_DITHER_INIT_RESET (0x00000001 << 3) +#define SCALE_3D_CNTL_ROUND_EN_OFF (0x00000000 << 4) +#define SCALE_3D_CNTL_ROUND_EN_ON (0x00000001 << 4) +#define SCALE_3D_CNTL_TEX_CACHE_DIS_OFF (0x00000000 << 5) +#define SCALE_3D_CNTL_TEX_CACHE_DIS_ON (0x00000001 << 5) +#define SCALE_3D_CNTL_SCALE_3D_FN_NONE (0x00000000 << 6) +#define SCALE_3D_CNTL_SCALE_3D_FN_SCALE (0x00000001 << 6) +#define SCALE_3D_CNTL_SCALE_3D_FN_TMAP_SHADE (0x00000002 << 6) +#define SCALE_3D_CNTL_SCALE_PIX_REP_BLEND (0x00000000 << 8) +#define SCALE_3D_CNTL_SCALE_PIX_REP_REP (0x00000001 << 8) +#define SCALE_3D_CNTL_TEX_CACHE_SPLIT_OFF (0x00000000 << 9) +#define SCALE_3D_CNTL_TEX_CACHE_SPLIT_ON (0x00000001 << 9) +#define SCALE_3D_CNTL_APPLE_YUV_MODE_OFF (0x00000000 << 10) +#define SCALE_3D_CNTL_APPLE_YUV_MODE_ON (0x00000001 << 10) +#define SCALE_3D_CNTL_TEX_CACHE_PAL_MODE_OFF (0x00000000 << 11) +#define SCALE_3D_CNTL_TEX_CACHE_PAL_MODE_ON (0x00000001 << 11) +#define SCALE_3D_CNTL_ALPHA_COMB_FNC_ADD_CLAMP (0x00000000 << 12) +#define SCALE_3D_CNTL_ALPHA_COMB_FNC_ADD_NCLAMP (0x00000001 << 12) +#define SCALE_3D_CNTL_ALPHA_COMB_FNC_SUB_DST_SRC_CLAMP (0x00000002 << 12) +#define SCALE_3D_CNTL_ALPHA_COMB_FNC_SUB_DST_SRC_NCLAMP (0x00000003 << 12) +#define SCALE_3D_CNTL_FOG_TABLE_EN_OFF (0x00000000 << 14) +#define SCALE_3D_CNTL_FOG_TABLE_EN_ON (0x00000001 << 14) +#define SCALE_3D_CNTL_SIGNED_DST_CLAMP_OFF (0x00000000 << 15) +#define SCALE_3D_CNTL_SIGNED_DST_CLAMP_ON (0x00000001 << 15) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_ZERO (0x00000000 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_ONE (0x00000001 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_SRCCOLOR (0x00000002 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVSRCCOLOR (0x00000003 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_SRCALPHA (0x00000004 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVSRCALPHA (0x00000005 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_DSTALPHA (0x00000006 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVDSTALPHA (0x00000007 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_DSTCOLOR (0x00000008 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVDSTCOLOR (0x00000009 << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_SAT (0x0000000a << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_BLEND (0x0000000b << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_SRC_INVBLEND (0x0000000c << 16) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_ZERO (0x00000000 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_ONE (0x00000001 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_SRCCOLOR (0x00000002 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_INVSRCCOLOR (0x00000003 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_SRCALPHA (0x00000004 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_INVSRCALPHA (0x00000005 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_DSTALPHA (0x00000006 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_INVDSTALPHA (0x00000007 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_DSTCOLOR (0x00000008 << 20) +#define SCALE_3D_CNTL_ALPHA_BLEND_DST_INVDSTCOLOR (0x00000009 << 20) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_NEVER (0x00000000 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_LESS (0x00000001 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_LESSEQUAL (0x00000002 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_EQUAL (0x00000003 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_GREATEREQUAL (0x00000004 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_GREATER (0x00000005 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_NEQUAL (0x00000006 << 24) +#define SCALE_3D_CNTL_ALPHA_TEST_OP_ALWAYS (0x00000007 << 24) +#define SCALE_3D_CNTL_COMPOSITE_SHADOW_CMP_EQUAL (0x00000000 << 28) +#define SCALE_3D_CNTL_COMPOSITE_SHADOW_CMP_NEQUAL (0x00000001 << 28) +#define SCALE_3D_CNTL_COMPOSITE_SHADOW_EN_OFF (0x00000000 << 29) +#define SCALE_3D_CNTL_COMPOSITE_SHADOW_EN_ON (0x00000001 << 29) +#define SCALE_3D_CNTL_TEX_MAP_AEN_OFF (0x00000000 << 30) +#define SCALE_3D_CNTL_TEX_MAP_AEN_ON (0x00000001 << 30) +#define SCALE_3D_CNTL_TEX_CACHE_LINE_SIZE_8QW (0x00000000 << 31) +#define SCALE_3D_CNTL_TEX_CACHE_LINE_SIZE_4QW (0x00000001 << 31) + + + + +#define SCALE_3D_DATATYPE 0x1a20 +#define SETUP_CNTL 0x1bc4 +#define SOLID_COLOR 0x1bc8 +#define WINDOW_XY_OFFSET 0x1bcc +#define DRAW_LINE_POINT 0x1bd0 +#define SETUP_CNTL_PM4 0x1bd4 +#define DST_PITCH_OFFSET_C 0x1c80 +#define DP_GUI_MASTER_CNTL_C 0x1c84 +#define SC_TOP_LEFT_C 0x1c88 +#define SC_BOTTOM_RIGHT_C 0x1c8c + +#define Z_OFFSET_C 0x1c90 +#define Z_PITCH_C 0x1c94 +#define Z_STEN_CNTL_C 0x1c98 +#define TEX_CNTL_C 0x1c9c +#define TEXTURE_CLR_CMP_CLR_C 0x1CA4 +#define TEXTURE_CLR_CMP_MSK_C 0x1CA8 +#define FOG_COLOR_C 0x1CAC +#define PRIM_TEX_CNTL_C 0x1CB0 +#define PRIM_TEX_COMBINE_CNTL_C 0x1CB4 +#define TEX_SIZE_PITCH_C 0x1CB8 +#define PRIM_TEX_0_OFFSET_C 0x1CBC +#define PRIM_TEX_1_OFFSET_C 0x1CC0 +#define PRIM_TEX_2_OFFSET_C 0x1CC4 +#define PRIM_TEX_3_OFFSET_C 0x1CC8 +#define PRIM_TEX_4_OFFSET_C 0x1CCC +#define PRIM_TEX_5_OFFSET_C 0x1CD0 +#define PRIM_TEX_6_OFFSET_C 0x1CD4 +#define PRIM_TEX_7_OFFSET_C 0x1CD8 +#define PRIM_TEX_8_OFFSET_C 0x1CDC +#define PRIM_TEX_9_OFFSET_C 0x1CE0 +#define PRIM_TEX_10_OFFSET_C 0x1CE4 +#define SEC_TEX_CNTL_C 0x1D00 +#define SEC_TEX_COMBINE_CNTL_C 0x1D04 +#define SEC_TEX_0_OFFSET_C 0x1D08 +#define SEC_TEX_1_OFFSET_C 0x1D0C +#define SEC_TEX_2_OFFSET_C 0x1D10 +#define SEC_TEX_3_OFFSET_C 0x1D14 +#define SEC_TEX_4_OFFSET_C 0x1D18 +#define SEC_TEX_5_OFFSET_C 0x1D1C +#define SEC_TEX_6_OFFSET_C 0x1D20 +#define SEC_TEX_7_OFFSET_C 0x1D24 +#define SEC_TEX_8_OFFSET_C 0x1D28 +#define SEC_TEX_9_OFFSET_C 0x1D2C +#define SEC_TEX_10_OFFSET_C 0x1D30 +#define CONSTANT_COLOR_C 0x1D34 +#define PRIM_TEXTURE_BORDER_COLOR_C 0x1D38 +#define SEC_TEXTURE_BORDER_COLOR_C 0x1D3C +#define STEN_REF_MASK_C 0x1D40 +#define PLANE_3D_MASK_C 0x1D44 + +#define CLR_CMP_MASK_3D 0x1A28 +#define MC_SRC1_CNTL 0x19D8 +#define TEX_CNTL 0x1800 +#define CLR_CMP_CLR_3D 0x1A24 + + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define R128_EXCL_HORZ_START_MASK 0x000000ff +# define R128_EXCL_HORZ_END_MASK 0x0000ff00 +# define R128_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define R128_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define R128_EXCL_VERT_START_MASK 0x000003ff +# define R128_EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define R128_REG_LD_CTL_LOCK 0x00000001L +# define R128_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define R128_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define R128_REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define R128_SCALER_PIX_EXPAND 0x00000001L +# define R128_SCALER_Y2R_TEMP 0x00000002L +# define R128_SCALER_HORZ_PICK_NEAREST 0x00000003L +# define R128_SCALER_VERT_PICK_NEAREST 0x00000004L +# define R128_SCALER_SIGNED_UV 0x00000010L +# define R128_SCALER_GAMMA_SEL_MASK 0x00000060L +# define R128_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define R128_SCALER_GAMMA_SEL_G22 0x00000020L +# define R128_SCALER_GAMMA_SEL_G18 0x00000040L +# define R128_SCALER_GAMMA_SEL_G14 0x00000060L +# define R128_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define R128_SCALER_SURFAC_FORMAT 0x00000f00L +# define R128_SCALER_SOURCE_15BPP 0x00000300L +# define R128_SCALER_SOURCE_16BPP 0x00000400L +# define R128_SCALER_SOURCE_32BPP 0x00000600L +# define R128_SCALER_SOURCE_YUV9 0x00000900L +# define R128_SCALER_SOURCE_YUV12 0x00000A00L +# define R128_SCALER_SOURCE_VYUY422 0x00000B00L +# define R128_SCALER_SOURCE_YVYU422 0x00000C00L +# define R128_SCALER_SMART_SWITCH 0x00008000L +# define R128_SCALER_BURST_PER_PLANE 0x00ff0000L +# define R128_SCALER_DOUBLE_BUFFER 0x01000000L +# define R128_SCALER_DIS_LIMIT 0x08000000L +# define R128_SCALER_PRG_LOAD_START 0x10000000L +# define R128_SCALER_INT_EMU 0x20000000L +# define R128_SCALER_ENABLE 0x40000000L +# define R128_SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define R128_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define R128_P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define R128_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define R128_P23_ACTIVE_LINES_M1 0x07ff0000L +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define R128_VIF_BUF0_PITCH_SEL 0x00000001L +# define R128_VIF_BUF0_TILE_ADRS 0x00000002L +# define R128_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define R128_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define R128_VIF_BUF1_PITCH_SEL 0x00000001L +# define R128_VIF_BUF1_TILE_ADRS 0x00000002L +# define R128_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define R128_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define R128_VIF_BUF2_PITCH_SEL 0x00000001L +# define R128_VIF_BUF2_TILE_ADRS 0x00000002L +# define R128_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define R128_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_COLOR_CNTL 0x04E0 +#define OV0_VIDEO_KEY_CLR 0x04E4 +#define OV0_VIDEO_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +# define R128_VIDEO_KEY_FN_MASK 0x00000007L +# define R128_VIDEO_KEY_FN_FALSE 0x00000000L +# define R128_VIDEO_KEY_FN_TRUE 0x00000001L +# define R128_VIDEO_KEY_FN_EQ 0x00000004L +# define R128_VIDEO_KEY_FN_NE 0x00000005L +# define R128_GRAPHIC_KEY_FN_MASK 0x00000070L +# define R128_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define R128_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define R128_GRAPHIC_KEY_FN_EQ 0x00000040L +# define R128_GRAPHIC_KEY_FN_NE 0x00000050L +# define R128_CMP_MIX_MASK 0x00000100L +# define R128_CMP_MIX_OR 0x00000000L +# define R128_CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 + + +/* added by DirectFB programmers */ +#define CRTC_OFFSET_FLIP_CNTL 0x00010000 +#define MEM_ADDR_CONFIG 0x0148 + +#endif + diff --git a/Source/DirectFB/gfxdrivers/cle266/Makefile.am b/Source/DirectFB/gfxdrivers/cle266/Makefile.am new file mode 100755 index 0000000..fff4976 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/Makefile.am @@ -0,0 +1,47 @@ +## Makefile.am for DirectFB/gfxdrivers/cle266 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +AM_CFLAGS = $(DFB_CFLAGS) + +cle266_LTLIBRARIES = libdirectfb_cle266.la + +if BUILD_STATIC +cle266_DATA = $(cle266_LTLIBRARIES:.la=.o) +endif + +cle266dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_cle266_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_cle266_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_cle266_la_LIBADD = \ + -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/cle266/Makefile.in b/Source/DirectFB/gfxdrivers/cle266/Makefile.in new file mode 100755 index 0000000..0c7ee2b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/Makefile.in @@ -0,0 +1,619 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/cle266 +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(cle266dir)" "$(DESTDIR)$(cle266dir)" +cle266LTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(cle266_LTLIBRARIES) +libdirectfb_cle266_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_cle266_la_OBJECTS = unichrome.lo uc_accel.lo \ + uc_hwset.lo uc_hwmap.lo uc_state.lo uc_fifo.lo uc_overlay.lo \ + uc_ovl_hwmap.lo uc_ovl_hwset.lo uc_primary.lo +libdirectfb_cle266_la_OBJECTS = $(am_libdirectfb_cle266_la_OBJECTS) +libdirectfb_cle266_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_cle266_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_cle266_la_SOURCES) +DIST_SOURCES = $(libdirectfb_cle266_la_SOURCES) +cle266DATA_INSTALL = $(INSTALL_DATA) +DATA = $(cle266_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +AM_CFLAGS = $(DFB_CFLAGS) +cle266_LTLIBRARIES = libdirectfb_cle266.la +@BUILD_STATIC_TRUE@cle266_DATA = $(cle266_LTLIBRARIES:.la=.o) +cle266dir = $(MODULEDIR)/gfxdrivers +libdirectfb_cle266_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_cle266_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_cle266_la_LIBADD = \ + -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do 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SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/cle266/mmio.h b/Source/DirectFB/gfxdrivers/cle266/mmio.h new file mode 100755 index 0000000..757445a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/mmio.h @@ -0,0 +1,43 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef _VIA_MMIO_H +#define _VIA_MMIO_H + +#define TRACE_ENTER() printf("Entering %s\n", __PRETTY_FUNCTION__) +#define TRACE_LEAVE() printf("Leaving %s\n", __PRETTY_FUNCTION__) + +#ifdef KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + + +#else // !KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) + +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + +#endif // KERNEL + +#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) +#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) + +#define MAXLOOP 0xffffff + +#endif /* _VIA_MMIO_H */ diff --git a/Source/DirectFB/gfxdrivers/cle266/regs2d.h b/Source/DirectFB/gfxdrivers/cle266/regs2d.h new file mode 100755 index 0000000..33c7951 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/regs2d.h @@ -0,0 +1,197 @@ +// Note: This is a modified version of via_regs.h from the XFree86 CVS tree. + +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_2D_H__ +#define __VIA_REGS_2D_H__ + +/* Selected 2D engine raster operations. + * See xc/programs/Xserver/hw/xfree86/xaa/xaarop.h + * in the XFree86 project for the full list. + */ +#define VIA_ROP_DPx (0x5A << 24) +#define VIA_ROP_DSx (0x66 << 24) +#define VIA_ROP_S (0xCC << 24) +#define VIA_ROP_P (0xF0 << 24) + +/* My own reverse-engineered bit definitions */ + +// Use the following definitions with VIA_KEY_CONTROL + +/// When set, red channel is not drawn +#define VIA_KEY_MASK_RED 0x40000000 +/// When set, green channel is not drawn +#define VIA_KEY_MASK_GREEN 0x20000000 +/// When set, blue channel is not drawn +#define VIA_KEY_MASK_BLUE 0x10000000 + +/** When set, destination keying is enabled. + * Caveat: VIA's destination key is the opposite of DirectFB's: + * It draws where there is no match in the destination surface. + */ +#define VIA_KEY_ENABLE_DSTKEY 0x8000 +/** When set, source keying is enabled + * It draws the pixels in the source that do not match the color key. + */ +#define VIA_KEY_ENABLE_SRCKEY 0x4000 +/** Inverts the behaviour of the color keys: + * Dst key: draw where the destination matches the key + * Src key: draw where the source matches the key + * Problem: Since this bit affects both keys, you can not do + * combined source and destination keying with DirectFB. + * The inverted source key is all but useless since it will + * only draw the source pixels that match the key! + * It must be a design error... + */ +#define VIA_KEY_INVERT_KEY 0x2000 + +/* 2D engine registers and bit definitions */ + +#define VIA_MMIO_REGSIZE 0x9000 +#define VIA_MMIO_REGBASE 0x0 +#define VIA_MMIO_VGABASE 0x8000 +#define VIA_MMIO_BLTBASE 0x200000 +#define VIA_MMIO_BLTSIZE 0x10000 + +#define VIA_VQ_SIZE (256*1024) + +/* defines for VIA 2D registers */ +#define VIA_REG_GECMD 0x000 +#define VIA_REG_GEMODE 0x004 +#define VIA_REG_GESTATUS 0x004 /* as same as VIA_REG_GEMODE */ +#define VIA_REG_SRCPOS 0x008 +#define VIA_REG_DSTPOS 0x00C +#define VIA_REG_LINE_K1K2 0x008 +#define VIA_REG_LINE_XY 0x00C +#define VIA_REG_DIMENSION 0x010 /* width and height */ +#define VIA_REG_PATADDR 0x014 +#define VIA_REG_FGCOLOR 0x018 +#define VIA_REG_DSTCOLORKEY 0x018 /* as same as VIA_REG_FG */ +#define VIA_REG_BGCOLOR 0x01C +#define VIA_REG_SRCCOLORKEY 0x01C /* as same as VIA_REG_BG */ +#define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ +#define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ +#define VIA_REG_OFFSET 0x028 +#define VIA_REG_LINE_ERROR 0x028 +#define VIA_REG_KEYCONTROL 0x02C /* color key control */ +#define VIA_REG_SRCBASE 0x030 +#define VIA_REG_DSTBASE 0x034 +#define VIA_REG_PITCH 0x038 /* pitch of src and dst */ +#define VIA_REG_MONOPAT0 0x03C +#define VIA_REG_MONOPAT1 0x040 +#define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ + + +/* defines for VIA video registers */ +#define VIA_REG_INTERRUPT 0x200 +#define VIA_REG_CRTCSTART 0x214 + + +/* defines for VIA HW cursor registers */ +#define VIA_REG_CURSOR_MODE 0x2D0 +#define VIA_REG_CURSOR_POS 0x2D4 +#define VIA_REG_CURSOR_ORG 0x2D8 +#define VIA_REG_CURSOR_BG 0x2DC +#define VIA_REG_CURSOR_FG 0x2E0 + + +/* defines for VIA 3D registers */ +#define VIA_REG_STATUS 0x400 +#define VIA_REG_TRANSET 0x43C +#define VIA_REG_TRANSPACE 0x440 + +/* VIA_REG_STATUS(0x400): Engine Status */ +#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ + + +/* VIA_REG_GECMD(0x00): 2D Engine Command */ +#define VIA_GEC_NOOP 0x00000000 +#define VIA_GEC_BLT 0x00000001 +#define VIA_GEC_LINE 0x00000005 + +#define VIA_GEC_SRC_XY 0x00000000 +#define VIA_GEC_SRC_LINEAR 0x00000010 +#define VIA_GEC_DST_XY 0x00000000 +#define VIA_GEC_DST_LINRAT 0x00000020 + +#define VIA_GEC_SRC_FB 0x00000000 +#define VIA_GEC_SRC_SYS 0x00000040 +#define VIA_GEC_DST_FB 0x00000000 +#define VIA_GEC_DST_SYS 0x00000080 + +#define VIA_GEC_SRC_MONO 0x00000100 /* source is mono */ +#define VIA_GEC_PAT_MONO 0x00000200 /* pattern is mono */ + +#define VIA_GEC_MSRC_OPAQUE 0x00000000 /* mono src is opaque */ +#define VIA_GEC_MSRC_TRANS 0x00000400 /* mono src is transparent */ + +#define VIA_GEC_PAT_FB 0x00000000 /* pattern is in frame buffer */ +#define VIA_GEC_PAT_REG 0x00000800 /* pattern is from reg setting */ + +#define VIA_GEC_CLIP_DISABLE 0x00000000 +#define VIA_GEC_CLIP_ENABLE 0x00001000 + +#define VIA_GEC_FIXCOLOR_PAT 0x00002000 + +#define VIA_GEC_INCX 0x00000000 +#define VIA_GEC_DECY 0x00004000 +#define VIA_GEC_INCY 0x00000000 +#define VIA_GEC_DECX 0x00008000 + +#define VIA_GEC_MPAT_OPAQUE 0x00000000 /* mono pattern is opaque */ +#define VIA_GEC_MPAT_TRANS 0x00010000 /* mono pattern is transparent */ + +#define VIA_GEC_MONO_UNPACK 0x00000000 +#define VIA_GEC_MONO_PACK 0x00020000 +#define VIA_GEC_MONO_DWORD 0x00000000 +#define VIA_GEC_MONO_WORD 0x00040000 +#define VIA_GEC_MONO_BYTE 0x00080000 + +#define VIA_GEC_LASTPIXEL_ON 0x00000000 +#define VIA_GEC_LASTPIXEL_OFF 0x00100000 +#define VIA_GEC_X_MAJOR 0x00000000 +#define VIA_GEC_Y_MAJOR 0x00200000 +#define VIA_GEC_QUICK_START 0x00800000 + + +/* VIA_REG_GEMODE(0x04): GE mode */ +#define VIA_GEM_8bpp 0x00000000 +#define VIA_GEM_16bpp 0x00000100 +#define VIA_GEM_32bpp 0x00000300 + +#define VIA_GEM_640 0x00000000 /* 640*480 */ +#define VIA_GEM_800 0x00000400 /* 800*600 */ +#define VIA_GEM_1024 0x00000800 /* 1024*768 */ +#define VIA_GEM_1280 0x00000C00 /* 1280*1024 */ +#define VIA_GEM_1600 0x00001000 /* 1600*1200 */ +#define VIA_GEM_2048 0x00001400 /* 2048*1536 */ + +/* VIA_REG_PITCH(0x38): Pitch Setting */ +#define VIA_PITCH_ENABLE 0x80000000 + +#endif // __VIA_REGS_2D_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/regs3d.h b/Source/DirectFB/gfxdrivers/cle266/regs3d.h new file mode 100755 index 0000000..ebc6a0d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/regs3d.h @@ -0,0 +1,1641 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_3D_H__ +#define __VIA_REGS_3D_H__ + +#define HC_REG_BASE 0x0400 + +#define HC_ParaN_MASK 0xffffffff +#define HC_Para_MASK 0x00ffffff +#define HC_SubA_MASK 0xff000000 +#define HC_SubA_SHIFT 24 +/* Transmission Setting + */ +#define HC_REG_TRANS_SET 0x003c +#define HC_ParaSubType_MASK 0xff000000 +#define HC_ParaType_MASK 0x00ff0000 +#define HC_ParaOS_MASK 0x0000ff00 +#define HC_ParaAdr_MASK 0x000000ff +#define HC_ParaSubType_SHIFT 24 +#define HC_ParaType_SHIFT 16 +#define HC_ParaOS_SHIFT 8 +#define HC_ParaAdr_SHIFT 0 + +#define HC_ParaType_CmdVdata 0x0000 +#define HC_ParaType_NotTex 0x0001 +#define HC_ParaType_Tex 0x0002 +#define HC_ParaType_Palette 0x0003 +#define HC_ParaType_PreCR 0x0010 +#define HC_ParaType_Auto 0x00fe + +/* Transmission Space + */ +#define HC_REG_Hpara0 0x0040 +#define HC_REG_HpataAF 0x02fc + +/* Read + */ +#define HC_REG_HREngSt 0x0000 +#define HC_REG_HRFIFOempty 0x0004 +#define HC_REG_HRFIFOfull 0x0008 +#define HC_REG_HRErr 0x000c +#define HC_REG_FIFOstatus 0x0010 +/* HC_REG_HREngSt 0x0000 + */ +#define HC_HDASZC_MASK 0x00010000 +#define HC_HSGEMI_MASK 0x0000f000 +#define HC_HLGEMISt_MASK 0x00000f00 +#define HC_HCRSt_MASK 0x00000080 +#define HC_HSE0St_MASK 0x00000040 +#define HC_HSE1St_MASK 0x00000020 +#define HC_HPESt_MASK 0x00000010 +#define HC_HXESt_MASK 0x00000008 +#define HC_HBESt_MASK 0x00000004 +#define HC_HE2St_MASK 0x00000002 +#define HC_HE3St_MASK 0x00000001 +/* HC_REG_HRFIFOempty 0x0004 + */ +#define HC_HRZDempty_MASK 0x00000010 +#define HC_HRTXAempty_MASK 0x00000008 +#define HC_HRTXDempty_MASK 0x00000004 +#define HC_HWZDempty_MASK 0x00000002 +#define HC_HWCDempty_MASK 0x00000001 +/* HC_REG_HRFIFOfull 0x0008 + */ +#define HC_HRZDfull_MASK 0x00000010 +#define HC_HRTXAfull_MASK 0x00000008 +#define HC_HRTXDfull_MASK 0x00000004 +#define HC_HWZDfull_MASK 0x00000002 +#define HC_HWCDfull_MASK 0x00000001 +/* HC_REG_HRErr 0x000c + */ +#define HC_HAGPCMErr_MASK 0x80000000 +#define HC_HAGPCMErrC_MASK 0x70000000 +/* HC_REG_FIFOstatus 0x0010 + */ +#define HC_HRFIFOATall_MASK 0x80000000 +#define HC_HRFIFOATbusy_MASK 0x40000000 +#define HC_HRATFGMDo_MASK 0x00000100 +#define HC_HRATFGMDi_MASK 0x00000080 +#define HC_HRATFRZD_MASK 0x00000040 +#define HC_HRATFRTXA_MASK 0x00000020 +#define HC_HRATFRTXD_MASK 0x00000010 +#define HC_HRATFWZD_MASK 0x00000008 +#define HC_HRATFWCD_MASK 0x00000004 +#define HC_HRATTXTAG_MASK 0x00000002 +#define HC_HRATTXCH_MASK 0x00000001 + +/* AGP Command Setting + */ +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +/* HC_SubA_HAGPCMNT 0x0062 + */ +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +/* HC_SubA_HAGPBpL 0x0063 + */ +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +/* HC_SubA_HAGPBpH 0x0064 + */ +#define HC_HAGPBpH_MASK 0x00ffffff + +/* Miscellaneous Settings + */ +#define HC_SubA_HClipTB 0x0070 +#define HC_SubA_HClipLR 0x0071 +#define HC_SubA_HFPClipTL 0x0072 +#define HC_SubA_HFPClipBL 0x0073 +#define HC_SubA_HFPClipLL 0x0074 +#define HC_SubA_HFPClipRL 0x0075 +#define HC_SubA_HFPClipTBH 0x0076 +#define HC_SubA_HFPClipLRH 0x0077 +#define HC_SubA_HLP 0x0078 +#define HC_SubA_HLPRF 0x0079 +#define HC_SubA_HSolidCL 0x007a +#define HC_SubA_HPixGC 0x007b +#define HC_SubA_HSPXYOS 0x007c +#define HC_SubA_HVertexCNT 0x007d + +#define HC_HClipT_MASK 0x00fff000 +#define HC_HClipT_SHIFT 12 +#define HC_HClipB_MASK 0x00000fff +#define HC_HClipB_SHIFT 0 +#define HC_HClipL_MASK 0x00fff000 +#define HC_HClipL_SHIFT 12 +#define HC_HClipR_MASK 0x00000fff +#define HC_HClipR_SHIFT 0 +#define HC_HFPClipBH_MASK 0x0000ff00 +#define HC_HFPClipBH_SHIFT 8 +#define HC_HFPClipTH_MASK 0x000000ff +#define HC_HFPClipTH_SHIFT 0 +#define HC_HFPClipRH_MASK 0x0000ff00 +#define HC_HFPClipRH_SHIFT 8 +#define HC_HFPClipLH_MASK 0x000000ff +#define HC_HFPClipLH_SHIFT 0 +#define HC_HSolidCH_MASK 0x000000ff +#define HC_HPixGC_MASK 0x00800000 +#define HC_HSPXOS_MASK 0x00fff000 +#define HC_HSPXOS_SHIFT 12 +#define HC_HSPYOS_MASK 0x00000fff + +/* Command + * Command A + */ +#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000*/ +#define HC_HE3Fire_MASK 0x00100000 +#define HC_HPMType_MASK 0x000f0000 +#define HC_HEFlag_MASK 0x0000e000 +#define HC_HShading_MASK 0x00001c00 +#define HC_HPMValidN_MASK 0x00000200 +#define HC_HPLEND_MASK 0x00000100 +#define HC_HVCycle_MASK 0x000000ff +#define HC_HVCycle_Style_MASK 0x000000c0 +#define HC_HVCycle_ChgA_MASK 0x00000030 +#define HC_HVCycle_ChgB_MASK 0x0000000c +#define HC_HVCycle_ChgC_MASK 0x00000003 +#define HC_HPMType_Point 0x00000000 +#define HC_HPMType_Line 0x00010000 +#define HC_HPMType_Tri 0x00020000 +#define HC_HPMType_TriWF 0x00040000 +#define HC_HEFlag_NoAA 0x00000000 +#define HC_HEFlag_ab 0x00008000 +#define HC_HEFlag_bc 0x00004000 +#define HC_HEFlag_ca 0x00002000 +#define HC_HShading_Solid 0x00000000 +#define HC_HShading_FlatA 0x00000400 +#define HC_HShading_FlatB 0x00000800 +#define HC_HShading_FlatC 0x00000c00 +#define HC_HShading_Gouraud 0x00001000 +#define HC_HVCycle_Full 0x00000000 +#define HC_HVCycle_AFP 0x00000040 +#define HC_HVCycle_One 0x000000c0 +#define HC_HVCycle_NewA 0x00000000 +#define HC_HVCycle_AA 0x00000010 +#define HC_HVCycle_AB 0x00000020 +#define HC_HVCycle_AC 0x00000030 +#define HC_HVCycle_NewB 0x00000000 +#define HC_HVCycle_BA 0x00000004 +#define HC_HVCycle_BB 0x00000008 +#define HC_HVCycle_BC 0x0000000c +#define HC_HVCycle_NewC 0x00000000 +#define HC_HVCycle_CA 0x00000001 +#define HC_HVCycle_CB 0x00000002 +#define HC_HVCycle_CC 0x00000003 + +/* Command B + */ +#define HC_HLPrst_MASK 0x00010000 +#define HC_HLLastP_MASK 0x00008000 +#define HC_HVPMSK_MASK 0x00007f80 +#define HC_HBFace_MASK 0x00000040 +#define HC_H2nd1VT_MASK 0x0000003f +#define HC_HVPMSK_X 0x00004000 +#define HC_HVPMSK_Y 0x00002000 +#define HC_HVPMSK_Z 0x00001000 +#define HC_HVPMSK_W 0x00000800 +#define HC_HVPMSK_Cd 0x00000400 +#define HC_HVPMSK_Cs 0x00000200 +#define HC_HVPMSK_S 0x00000100 +#define HC_HVPMSK_T 0x00000080 + +/* Enable Setting + */ +#define HC_SubA_HEnable 0x0000 +#define HC_HenTXEnvMap_MASK 0x00200000 /* environment mapping?? */ +#define HC_HenVertexCNT_MASK 0x00100000 /* vertex counter?? */ +#define HC_HenCPUDAZ_MASK 0x00080000 /* ???? */ +#define HC_HenDASZWC_MASK 0x00040000 /* ???? */ +#define HC_HenFBCull_MASK 0x00020000 /* culling? */ +#define HC_HenCW_MASK 0x00010000 /* color write? */ +#define HC_HenAA_MASK 0x00008000 /* anti aliasing??? */ +#define HC_HenST_MASK 0x00004000 /* stencil?? */ +#define HC_HenZT_MASK 0x00002000 /* z test?? */ +#define HC_HenZW_MASK 0x00001000 /* z write?? */ +#define HC_HenAT_MASK 0x00000800 /* alpha test?? */ +#define HC_HenAW_MASK 0x00000400 /* alpha write?? */ +#define HC_HenSP_MASK 0x00000200 /* specular?? */ +#define HC_HenLP_MASK 0x00000100 /* ???? */ +#define HC_HenTXCH_MASK 0x00000080 /* cache? half speed, right fonts */ +#define HC_HenTXMP_MASK 0x00000040 /* texture mapping */ +#define HC_HenTXPP_MASK 0x00000020 /* perspective correction?? */ +#define HC_HenTXTR_MASK 0x00000010 /* ???? */ +#define HC_HenCS_MASK 0x00000008 /* color space?? looks weird */ +#define HC_HenFOG_MASK 0x00000004 /* obviously fogging */ +#define HC_HenABL_MASK 0x00000002 /* alpha blending */ +#define HC_HenDT_MASK 0x00000001 /* dithering */ + +/* Z Setting + */ +#define HC_SubA_HZWBBasL 0x0010 +#define HC_SubA_HZWBBasH 0x0011 +#define HC_SubA_HZWBType 0x0012 +#define HC_SubA_HZBiasL 0x0013 +#define HC_SubA_HZWBend 0x0014 +#define HC_SubA_HZWTMD 0x0015 +#define HC_SubA_HZWCDL 0x0016 +#define HC_SubA_HZWCTAGnum 0x0017 +#define HC_SubA_HZCYNum 0x0018 +#define HC_SubA_HZWCFire 0x0019 +/* HC_SubA_HZWBType + */ +#define HC_HZWBType_MASK 0x00800000 +#define HC_HZBiasedWB_MASK 0x00400000 +#define HC_HZONEasFF_MASK 0x00200000 +#define HC_HZOONEasFF_MASK 0x00100000 +#define HC_HZWBFM_MASK 0x00030000 +#define HC_HZWBLoc_MASK 0x0000c000 +#define HC_HZWBPit_MASK 0x00003fff +#define HC_HZWBFM_16 0x00000000 +#define HC_HZWBFM_32 0x00020000 +#define HC_HZWBFM_24 0x00030000 +#define HC_HZWBLoc_Local 0x00000000 +#define HC_HZWBLoc_SyS 0x00004000 +/* HC_SubA_HZWBend + */ +#define HC_HZWBend_MASK 0x00ffe000 +#define HC_HZBiasH_MASK 0x000000ff +#define HC_HZWBend_SHIFT 10 +/* HC_SubA_HZWTMD + */ +#define HC_HZWTMD_MASK 0x00070000 +#define HC_HEBEBias_MASK 0x00007f00 +#define HC_HZNF_MASK 0x000000ff +#define HC_HZWTMD_NeverPass 0x00000000 +#define HC_HZWTMD_LT 0x00010000 +#define HC_HZWTMD_EQ 0x00020000 +#define HC_HZWTMD_LE 0x00030000 +#define HC_HZWTMD_GT 0x00040000 +#define HC_HZWTMD_NE 0x00050000 +#define HC_HZWTMD_GE 0x00060000 +#define HC_HZWTMD_AllPass 0x00070000 +#define HC_HEBEBias_SHIFT 8 +/* HC_SubA_HZWCDL 0x0016 + */ +#define HC_HZWCDL_MASK 0x00ffffff +/* HC_SubA_HZWCTAGnum 0x0017 + */ +#define HC_HZWCTAGnum_MASK 0x00ff0000 +#define HC_HZWCTAGnum_SHIFT 16 +#define HC_HZWCDH_MASK 0x000000ff +#define HC_HZWCDH_SHIFT 0 +/* HC_SubA_HZCYNum 0x0018 + */ +#define HC_HZCYNum_MASK 0x00030000 +#define HC_HZCYNum_SHIFT 16 +#define HC_HZWCQWnum_MASK 0x00003fff +#define HC_HZWCQWnum_SHIFT 0 +/* HC_SubA_HZWCFire 0x0019 + */ +#define HC_ZWCFire_MASK 0x00010000 +#define HC_HZWCQWnumLast_MASK 0x00003fff +#define HC_HZWCQWnumLast_SHIFT 0 + +/* Stencil Setting + */ +#define HC_SubA_HSTREF 0x0023 +#define HC_SubA_HSTMD 0x0024 +/* HC_SubA_HSBFM + */ +#define HC_HSBFM_MASK 0x00030000 +#define HC_HSBLoc_MASK 0x0000c000 +#define HC_HSBPit_MASK 0x00003fff +/* HC_SubA_HSTREF + */ +#define HC_HSTREF_MASK 0x00ff0000 +#define HC_HSTOPMSK_MASK 0x0000ff00 +#define HC_HSTBMSK_MASK 0x000000ff +#define HC_HSTREF_SHIFT 16 +#define HC_HSTOPMSK_SHIFT 8 +/* HC_SubA_HSTMD + */ +#define HC_HSTMD_MASK 0x00070000 +#define HC_HSTOPSF_MASK 0x000001c0 +#define HC_HSTOPSPZF_MASK 0x00000038 +#define HC_HSTOPSPZP_MASK 0x00000007 +#define HC_HSTMD_NeverPass 0x00000000 +#define HC_HSTMD_LT 0x00010000 +#define HC_HSTMD_EQ 0x00020000 +#define HC_HSTMD_LE 0x00030000 +#define HC_HSTMD_GT 0x00040000 +#define HC_HSTMD_NE 0x00050000 +#define HC_HSTMD_GE 0x00060000 +#define HC_HSTMD_AllPass 0x00070000 +#define HC_HSTOPSF_KEEP 0x00000000 +#define HC_HSTOPSF_ZERO 0x00000040 +#define HC_HSTOPSF_REPLACE 0x00000080 +#define HC_HSTOPSF_INCRSAT 0x000000c0 +#define HC_HSTOPSF_DECRSAT 0x00000100 +#define HC_HSTOPSF_INVERT 0x00000140 +#define HC_HSTOPSF_INCR 0x00000180 +#define HC_HSTOPSF_DECR 0x000001c0 +#define HC_HSTOPSPZF_KEEP 0x00000000 +#define HC_HSTOPSPZF_ZERO 0x00000008 +#define HC_HSTOPSPZF_REPLACE 0x00000010 +#define HC_HSTOPSPZF_INCRSAT 0x00000018 +#define HC_HSTOPSPZF_DECRSAT 0x00000020 +#define HC_HSTOPSPZF_INVERT 0x00000028 +#define HC_HSTOPSPZF_INCR 0x00000030 +#define HC_HSTOPSPZF_DECR 0x00000038 +#define HC_HSTOPSPZP_KEEP 0x00000000 +#define HC_HSTOPSPZP_ZERO 0x00000001 +#define HC_HSTOPSPZP_REPLACE 0x00000002 +#define HC_HSTOPSPZP_INCRSAT 0x00000003 +#define HC_HSTOPSPZP_DECRSAT 0x00000004 +#define HC_HSTOPSPZP_INVERT 0x00000005 +#define HC_HSTOPSPZP_INCR 0x00000006 +#define HC_HSTOPSPZP_DECR 0x00000007 + +/* Alpha Setting + */ +#define HC_SubA_HABBasL 0x0030 +#define HC_SubA_HABBasH 0x0031 +#define HC_SubA_HABFM 0x0032 +#define HC_SubA_HATMD 0x0033 +#define HC_SubA_HABLCsat 0x0034 +#define HC_SubA_HABLCop 0x0035 +#define HC_SubA_HABLAsat 0x0036 +#define HC_SubA_HABLAop 0x0037 +#define HC_SubA_HABLRCa 0x0038 +#define HC_SubA_HABLRFCa 0x0039 +#define HC_SubA_HABLRCbias 0x003a +#define HC_SubA_HABLRCb 0x003b +#define HC_SubA_HABLRFCb 0x003c +#define HC_SubA_HABLRAa 0x003d +#define HC_SubA_HABLRAb 0x003e +/* HC_SubA_HABFM + */ +#define HC_HABFM_MASK 0x00030000 +#define HC_HABLoc_MASK 0x0000c000 +#define HC_HABPit_MASK 0x000007ff +/* HC_SubA_HATMD + */ +#define HC_HATMD_MASK 0x00000700 +#define HC_HATREF_MASK 0x000000ff +#define HC_HATMD_NeverPass 0x00000000 +#define HC_HATMD_LT 0x00000100 +#define HC_HATMD_EQ 0x00000200 +#define HC_HATMD_LE 0x00000300 +#define HC_HATMD_GT 0x00000400 +#define HC_HATMD_NE 0x00000500 +#define HC_HATMD_GE 0x00000600 +#define HC_HATMD_AllPass 0x00000700 +/* HC_SubA_HABLCsat + */ +#define HC_HABLCsat_MASK 0x00010000 +#define HC_HABLCa_MASK 0x0000fc00 +#define HC_HABLCa_C_MASK 0x0000c000 +#define HC_HABLCa_OPC_MASK 0x00003c00 +#define HC_HABLFCa_MASK 0x000003f0 +#define HC_HABLFCa_C_MASK 0x00000300 +#define HC_HABLFCa_OPC_MASK 0x000000f0 +#define HC_HABLCbias_MASK 0x0000000f +#define HC_HABLCbias_C_MASK 0x00000008 +#define HC_HABLCbias_OPC_MASK 0x00000007 +/*-- Define the input color. + */ +#define HC_XC_Csrc 0x00000000 +#define HC_XC_Cdst 0x00000001 +#define HC_XC_Asrc 0x00000002 +#define HC_XC_Adst 0x00000003 +#define HC_XC_Fog 0x00000004 +#define HC_XC_HABLRC 0x00000005 +#define HC_XC_minSrcDst 0x00000006 +#define HC_XC_maxSrcDst 0x00000007 +#define HC_XC_mimAsrcInvAdst 0x00000008 +#define HC_XC_OPC 0x00000000 +#define HC_XC_InvOPC 0x00000010 +#define HC_XC_OPCp5 0x00000020 +/*-- Define the input Alpha + */ +#define HC_XA_OPA 0x00000000 +#define HC_XA_InvOPA 0x00000010 +#define HC_XA_OPAp5 0x00000020 +#define HC_XA_0 0x00000000 +#define HC_XA_Asrc 0x00000001 +#define HC_XA_Adst 0x00000002 +#define HC_XA_Fog 0x00000003 +#define HC_XA_minAsrcFog 0x00000004 +#define HC_XA_minAsrcAdst 0x00000005 +#define HC_XA_maxAsrcFog 0x00000006 +#define HC_XA_maxAsrcAdst 0x00000007 +#define HC_XA_HABLRA 0x00000008 +#define HC_XA_minAsrcInvAdst 0x00000008 +#define HC_XA_HABLFRA 0x00000009 +/*-- + */ +#define HC_HABLCa_OPC (HC_XC_OPC << 10) +#define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10) +#define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10) +#define HC_HABLCa_Csrc (HC_XC_Csrc << 10) +#define HC_HABLCa_Cdst (HC_XC_Cdst << 10) +#define HC_HABLCa_Asrc (HC_XC_Asrc << 10) +#define HC_HABLCa_Adst (HC_XC_Adst << 10) +#define HC_HABLCa_Fog (HC_XC_Fog << 10) +#define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10) +#define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10) +#define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10) +#define HC_HABLFCa_OPC (HC_XC_OPC << 4) +#define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4) +#define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4) +#define HC_HABLFCa_Csrc (HC_XC_Csrc << 4) +#define HC_HABLFCa_Cdst (HC_XC_Cdst << 4) +#define HC_HABLFCa_Asrc (HC_XC_Asrc << 4) +#define HC_HABLFCa_Adst (HC_XC_Adst << 4) +#define HC_HABLFCa_Fog (HC_XC_Fog << 4) +#define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4) +#define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4) +#define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4) +#define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4) +#define HC_HABLCbias_HABLRCbias 0x00000000 +#define HC_HABLCbias_Asrc 0x00000001 +#define HC_HABLCbias_Adst 0x00000002 +#define HC_HABLCbias_Fog 0x00000003 +#define HC_HABLCbias_Cin 0x00000004 +/* HC_SubA_HABLCop 0x0035 + */ +#define HC_HABLdot_MASK 0x00010000 +#define HC_HABLCop_MASK 0x00004000 +#define HC_HABLCb_MASK 0x00003f00 +#define HC_HABLCb_C_MASK 0x00003000 +#define HC_HABLCb_OPC_MASK 0x00000f00 +#define HC_HABLFCb_MASK 0x000000fc +#define HC_HABLFCb_C_MASK 0x000000c0 +#define HC_HABLFCb_OPC_MASK 0x0000003c +#define HC_HABLCshift_MASK 0x00000003 +#define HC_HABLCb_OPC (HC_XC_OPC << 8) +#define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8) +#define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8) +#define HC_HABLCb_Csrc (HC_XC_Csrc << 8) +#define HC_HABLCb_Cdst (HC_XC_Cdst << 8) +#define HC_HABLCb_Asrc (HC_XC_Asrc << 8) +#define HC_HABLCb_Adst (HC_XC_Adst << 8) +#define HC_HABLCb_Fog (HC_XC_Fog << 8) +#define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8) +#define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8) +#define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8) +#define HC_HABLFCb_OPC (HC_XC_OPC << 2) +#define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2) +#define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2) +#define HC_HABLFCb_Csrc (HC_XC_Csrc << 2) +#define HC_HABLFCb_Cdst (HC_XC_Cdst << 2) +#define HC_HABLFCb_Asrc (HC_XC_Asrc << 2) +#define HC_HABLFCb_Adst (HC_XC_Adst << 2) +#define HC_HABLFCb_Fog (HC_XC_Fog << 2) +#define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2) +#define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2) +#define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2) +#define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2) +/* HC_SubA_HABLAsat 0x0036 + */ +#define HC_HABLAsat_MASK 0x00010000 +#define HC_HABLAa_MASK 0x0000fc00 +#define HC_HABLAa_A_MASK 0x0000c000 +#define HC_HABLAa_OPA_MASK 0x00003c00 +#define HC_HABLFAa_MASK 0x000003f0 +#define HC_HABLFAa_A_MASK 0x00000300 +#define HC_HABLFAa_OPA_MASK 0x000000f0 +#define HC_HABLAbias_MASK 0x0000000f +#define HC_HABLAbias_A_MASK 0x00000008 +#define HC_HABLAbias_OPA_MASK 0x00000007 +#define HC_HABLAa_OPA (HC_XA_OPA << 10) +#define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10) +#define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10) +#define HC_HABLAa_0 (HC_XA_0 << 10) +#define HC_HABLAa_Asrc (HC_XA_Asrc << 10) +#define HC_HABLAa_Adst (HC_XA_Adst << 10) +#define HC_HABLAa_Fog (HC_XA_Fog << 10) +#define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10) +#define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10) +#define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10) +#define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10) +#define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10) +#define HC_HABLFAa_OPA (HC_XA_OPA << 4) +#define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4) +#define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4) +#define HC_HABLFAa_0 (HC_XA_0 << 4) +#define HC_HABLFAa_Asrc (HC_XA_Asrc << 4) +#define HC_HABLFAa_Adst (HC_XA_Adst << 4) +#define HC_HABLFAa_Fog (HC_XA_Fog << 4) +#define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4) +#define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4) +#define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4) +#define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4) +#define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4) +#define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4) +#define HC_HABLAbias_HABLRAbias 0x00000000 +#define HC_HABLAbias_Asrc 0x00000001 +#define HC_HABLAbias_Adst 0x00000002 +#define HC_HABLAbias_Fog 0x00000003 +#define HC_HABLAbias_Aaa 0x00000004 +/* HC_SubA_HABLAop 0x0037 + */ +#define HC_HABLAop_MASK 0x00004000 +#define HC_HABLAb_MASK 0x00003f00 +#define HC_HABLAb_OPA_MASK 0x00000f00 +#define HC_HABLFAb_MASK 0x000000fc +#define HC_HABLFAb_OPA_MASK 0x0000003c +#define HC_HABLAshift_MASK 0x00000003 +#define HC_HABLAb_OPA (HC_XA_OPA << 8) +#define HC_HABLAb_InvOPA (HC_XA_InvOPA << 8) +#define HC_HABLAb_OPAp5 (HC_XA_OPAp5 << 8) +#define HC_HABLAb_0 (HC_XA_0 << 8) +#define HC_HABLAb_Asrc (HC_XA_Asrc << 8) +#define HC_HABLAb_Adst (HC_XA_Adst << 8) +#define HC_HABLAb_Fog (HC_XA_Fog << 8) +#define HC_HABLAb_minAsrcFog (HC_XA_minAsrcFog << 8) +#define HC_HABLAb_minAsrcAdst (HC_XA_minAsrcAdst << 8) +#define HC_HABLAb_maxAsrcFog (HC_XA_maxAsrcFog << 8) +#define HC_HABLAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 8) +#define HC_HABLAb_HABLRA (HC_XA_HABLRA << 8) +#define HC_HABLFAb_OPA (HC_XA_OPA << 2) +#define HC_HABLFAb_InvOPA (HC_XA_InvOPA << 2) +#define HC_HABLFAb_OPAp5 (HC_XA_OPAp5 << 2) +#define HC_HABLFAb_0 (HC_XA_0 << 2) +#define HC_HABLFAb_Asrc (HC_XA_Asrc << 2) +#define HC_HABLFAb_Adst (HC_XA_Adst << 2) +#define HC_HABLFAb_Fog (HC_XA_Fog << 2) +#define HC_HABLFAb_minAsrcFog (HC_XA_minAsrcFog << 2) +#define HC_HABLFAb_minAsrcAdst (HC_XA_minAsrcAdst << 2) +#define HC_HABLFAb_maxAsrcFog (HC_XA_maxAsrcFog << 2) +#define HC_HABLFAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 2) +#define HC_HABLFAb_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 2) +#define HC_HABLFAb_HABLFRA (HC_XA_HABLFRA << 2) +/* HC_SubA_HABLRAa 0x003d + */ +#define HC_HABLRAa_MASK 0x00ff0000 +#define HC_HABLRFAa_MASK 0x0000ff00 +#define HC_HABLRAbias_MASK 0x000000ff +#define HC_HABLRAa_SHIFT 16 +#define HC_HABLRFAa_SHIFT 8 +/* HC_SubA_HABLRAb 0x003e + */ +#define HC_HABLRAb_MASK 0x0000ff00 +#define HC_HABLRFAb_MASK 0x000000ff +#define HC_HABLRAb_SHIFT 8 + +/* Destination Setting + */ +#define HC_SubA_HDBBasL 0x0040 +#define HC_SubA_HDBBasH 0x0041 +#define HC_SubA_HDBFM 0x0042 +#define HC_SubA_HFBBMSKL 0x0043 +#define HC_SubA_HROP 0x0044 +/* HC_SubA_HDBFM 0x0042 + */ +#define HC_HDBFM_MASK 0x001f0000 +#define HC_HDBLoc_MASK 0x0000c000 +#define HC_HDBPit_MASK 0x00003fff +#define HC_HDBFM_RGB555 0x00000000 +#define HC_HDBFM_RGB565 0x00010000 +#define HC_HDBFM_ARGB4444 0x00020000 +#define HC_HDBFM_ARGB1555 0x00030000 +#define HC_HDBFM_BGR555 0x00040000 +#define HC_HDBFM_BGR565 0x00050000 +#define HC_HDBFM_ABGR4444 0x00060000 +#define HC_HDBFM_ABGR1555 0x00070000 +#define HC_HDBFM_ARGB0888 0x00080000 +#define HC_HDBFM_ARGB8888 0x00090000 +#define HC_HDBFM_ABGR0888 0x000a0000 +#define HC_HDBFM_ABGR8888 0x000b0000 +#define HC_HDBLoc_Local 0x00000000 +#define HC_HDBLoc_Sys 0x00004000 +/* HC_SubA_HROP 0x0044 + */ +#define HC_HROP_MASK 0x00000f00 +#define HC_HFBBMSKH_MASK 0x000000ff +#define HC_HROP_BLACK 0x00000000 +#define HC_HROP_DPon 0x00000100 +#define HC_HROP_DPna 0x00000200 +#define HC_HROP_Pn 0x00000300 +#define HC_HROP_PDna 0x00000400 +#define HC_HROP_Dn 0x00000500 +#define HC_HROP_DPx 0x00000600 +#define HC_HROP_DPan 0x00000700 +#define HC_HROP_DPa 0x00000800 +#define HC_HROP_DPxn 0x00000900 +#define HC_HROP_D 0x00000a00 +#define HC_HROP_DPno 0x00000b00 +#define HC_HROP_P 0x00000c00 +#define HC_HROP_PDno 0x00000d00 +#define HC_HROP_DPo 0x00000e00 +#define HC_HROP_WHITE 0x00000f00 + +/* Fog Setting + */ +#define HC_SubA_HFogLF 0x0050 +#define HC_SubA_HFogCL 0x0051 +#define HC_SubA_HFogCH 0x0052 +#define HC_SubA_HFogStL 0x0053 +#define HC_SubA_HFogStH 0x0054 +#define HC_SubA_HFogOOdMF 0x0055 +#define HC_SubA_HFogOOdEF 0x0056 +#define HC_SubA_HFogEndL 0x0057 +#define HC_SubA_HFogDenst 0x0058 +/* HC_SubA_FogLF 0x0050 + */ +#define HC_FogLF_MASK 0x00000010 +#define HC_FogEq_MASK 0x00000008 +#define HC_FogMD_MASK 0x00000007 +#define HC_FogMD_LocalFog 0x00000000 +#define HC_FogMD_LinearFog 0x00000002 +#define HC_FogMD_ExponentialFog 0x00000004 +#define HC_FogMD_Exponential2Fog 0x00000005 +/* #define HC_FogMD_FogTable 0x00000003 */ + +/* HC_SubA_HFogDenst 0x0058 + */ +#define HC_FogDenst_MASK 0x001fff00 +#define HC_FogEndL_MASK 0x000000ff + +/* Texture subtype definitions + */ +#define HC_SubType_Tex0 0x00000000 +#define HC_SubType_Tex1 0x00000001 +#define HC_SubType_TexGeneral 0x000000fe + +/* Attribute of texture n + */ +#define HC_SubA_HTXnL0BasL 0x0000 +#define HC_SubA_HTXnL1BasL 0x0001 +#define HC_SubA_HTXnL2BasL 0x0002 +#define HC_SubA_HTXnL3BasL 0x0003 +#define HC_SubA_HTXnL4BasL 0x0004 +#define HC_SubA_HTXnL5BasL 0x0005 +#define HC_SubA_HTXnL6BasL 0x0006 +#define HC_SubA_HTXnL7BasL 0x0007 +#define HC_SubA_HTXnL8BasL 0x0008 +#define HC_SubA_HTXnL9BasL 0x0009 +#define HC_SubA_HTXnLaBasL 0x000a +#define HC_SubA_HTXnLbBasL 0x000b +#define HC_SubA_HTXnLcBasL 0x000c +#define HC_SubA_HTXnLdBasL 0x000d +#define HC_SubA_HTXnLeBasL 0x000e +#define HC_SubA_HTXnLfBasL 0x000f +#define HC_SubA_HTXnL10BasL 0x0010 +#define HC_SubA_HTXnL11BasL 0x0011 +#define HC_SubA_HTXnL012BasH 0x0020 +#define HC_SubA_HTXnL345BasH 0x0021 +#define HC_SubA_HTXnL678BasH 0x0022 +#define HC_SubA_HTXnL9abBasH 0x0023 +#define HC_SubA_HTXnLcdeBasH 0x0024 +#define HC_SubA_HTXnLf1011BasH 0x0025 +#define HC_SubA_HTXnL0Pit 0x002b +#define HC_SubA_HTXnL1Pit 0x002c +#define HC_SubA_HTXnL2Pit 0x002d +#define HC_SubA_HTXnL3Pit 0x002e +#define HC_SubA_HTXnL4Pit 0x002f +#define HC_SubA_HTXnL5Pit 0x0030 +#define HC_SubA_HTXnL6Pit 0x0031 +#define HC_SubA_HTXnL7Pit 0x0032 +#define HC_SubA_HTXnL8Pit 0x0033 +#define HC_SubA_HTXnL9Pit 0x0034 +#define HC_SubA_HTXnLaPit 0x0035 +#define HC_SubA_HTXnLbPit 0x0036 +#define HC_SubA_HTXnLcPit 0x0037 +#define HC_SubA_HTXnLdPit 0x0038 +#define HC_SubA_HTXnLePit 0x0039 +#define HC_SubA_HTXnLfPit 0x003a +#define HC_SubA_HTXnL10Pit 0x003b +#define HC_SubA_HTXnL11Pit 0x003c +#define HC_SubA_HTXnL0_5WE 0x004b +#define HC_SubA_HTXnL6_bWE 0x004c +#define HC_SubA_HTXnLc_11WE 0x004d +#define HC_SubA_HTXnL0_5HE 0x0051 +#define HC_SubA_HTXnL6_bHE 0x0052 +#define HC_SubA_HTXnLc_11HE 0x0053 +#define HC_SubA_HTXnL0OS 0x0077 +#define HC_SubA_HTXnTB 0x0078 +#define HC_SubA_HTXnMPMD 0x0079 +#define HC_SubA_HTXnCLODu 0x007a +#define HC_SubA_HTXnFM 0x007b +#define HC_SubA_HTXnTRCH 0x007c +#define HC_SubA_HTXnTRCL 0x007d +#define HC_SubA_HTXnTBC 0x007e +#define HC_SubA_HTXnTRAH 0x007f +#define HC_SubA_HTXnTBLCsat 0x0080 +#define HC_SubA_HTXnTBLCop 0x0081 +#define HC_SubA_HTXnTBLMPfog 0x0082 +#define HC_SubA_HTXnTBLAsat 0x0083 +#define HC_SubA_HTXnTBLRCa 0x0085 +#define HC_SubA_HTXnTBLRCb 0x0086 +#define HC_SubA_HTXnTBLRCc 0x0087 +#define HC_SubA_HTXnTBLRCbias 0x0088 +#define HC_SubA_HTXnTBLRAa 0x0089 +#define HC_SubA_HTXnTBLRFog 0x008a +#define HC_SubA_HTXnBumpM00 0x0090 +#define HC_SubA_HTXnBumpM01 0x0091 +#define HC_SubA_HTXnBumpM10 0x0092 +#define HC_SubA_HTXnBumpM11 0x0093 +#define HC_SubA_HTXnLScale 0x0094 +#define HC_SubA_HTXSMD 0x0000 +/* HC_SubA_HTXnL012BasH 0x0020 + */ +#define HC_HTXnL0BasH_MASK 0x000000ff +#define HC_HTXnL1BasH_MASK 0x0000ff00 +#define HC_HTXnL2BasH_MASK 0x00ff0000 +#define HC_HTXnL1BasH_SHIFT 8 +#define HC_HTXnL2BasH_SHIFT 16 +/* HC_SubA_HTXnL345BasH 0x0021 + */ +#define HC_HTXnL3BasH_MASK 0x000000ff +#define HC_HTXnL4BasH_MASK 0x0000ff00 +#define HC_HTXnL5BasH_MASK 0x00ff0000 +#define HC_HTXnL4BasH_SHIFT 8 +#define HC_HTXnL5BasH_SHIFT 16 +/* HC_SubA_HTXnL678BasH 0x0022 + */ +#define HC_HTXnL6BasH_MASK 0x000000ff +#define HC_HTXnL7BasH_MASK 0x0000ff00 +#define HC_HTXnL8BasH_MASK 0x00ff0000 +#define HC_HTXnL7BasH_SHIFT 8 +#define HC_HTXnL8BasH_SHIFT 16 +/* HC_SubA_HTXnL9abBasH 0x0023 + */ +#define HC_HTXnL9BasH_MASK 0x000000ff +#define HC_HTXnLaBasH_MASK 0x0000ff00 +#define HC_HTXnLbBasH_MASK 0x00ff0000 +#define HC_HTXnLaBasH_SHIFT 8 +#define HC_HTXnLbBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0024 + */ +#define HC_HTXnLcBasH_MASK 0x000000ff +#define HC_HTXnLdBasH_MASK 0x0000ff00 +#define HC_HTXnLeBasH_MASK 0x00ff0000 +#define HC_HTXnLdBasH_SHIFT 8 +#define HC_HTXnLeBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0025 + */ +#define HC_HTXnLfBasH_MASK 0x000000ff +#define HC_HTXnL10BasH_MASK 0x0000ff00 +#define HC_HTXnL11BasH_MASK 0x00ff0000 +#define HC_HTXnL10BasH_SHIFT 8 +#define HC_HTXnL11BasH_SHIFT 16 +/* HC_SubA_HTXnL0Pit 0x002b + */ +#define HC_HTXnLnPit_MASK 0x00003fff +#define HC_HTXnEnPit_MASK 0x00080000 +#define HC_HTXnLnPitE_MASK 0x00f00000 +#define HC_HTXnLnPitE_SHIFT 20 +/* HC_SubA_HTXnL0_5WE 0x004b + */ +#define HC_HTXnL0WE_MASK 0x0000000f +#define HC_HTXnL1WE_MASK 0x000000f0 +#define HC_HTXnL2WE_MASK 0x00000f00 +#define HC_HTXnL3WE_MASK 0x0000f000 +#define HC_HTXnL4WE_MASK 0x000f0000 +#define HC_HTXnL5WE_MASK 0x00f00000 +#define HC_HTXnL1WE_SHIFT 4 +#define HC_HTXnL2WE_SHIFT 8 +#define HC_HTXnL3WE_SHIFT 12 +#define HC_HTXnL4WE_SHIFT 16 +#define HC_HTXnL5WE_SHIFT 20 +/* HC_SubA_HTXnL6_bWE 0x004c + */ +#define HC_HTXnL6WE_MASK 0x0000000f +#define HC_HTXnL7WE_MASK 0x000000f0 +#define HC_HTXnL8WE_MASK 0x00000f00 +#define HC_HTXnL9WE_MASK 0x0000f000 +#define HC_HTXnLaWE_MASK 0x000f0000 +#define HC_HTXnLbWE_MASK 0x00f00000 +#define HC_HTXnL7WE_SHIFT 4 +#define HC_HTXnL8WE_SHIFT 8 +#define HC_HTXnL9WE_SHIFT 12 +#define HC_HTXnLaWE_SHIFT 16 +#define HC_HTXnLbWE_SHIFT 20 +/* HC_SubA_HTXnLc_11WE 0x004d + */ +#define HC_HTXnLcWE_MASK 0x0000000f +#define HC_HTXnLdWE_MASK 0x000000f0 +#define HC_HTXnLeWE_MASK 0x00000f00 +#define HC_HTXnLfWE_MASK 0x0000f000 +#define HC_HTXnL10WE_MASK 0x000f0000 +#define HC_HTXnL11WE_MASK 0x00f00000 +#define HC_HTXnLdWE_SHIFT 4 +#define HC_HTXnLeWE_SHIFT 8 +#define HC_HTXnLfWE_SHIFT 12 +#define HC_HTXnL10WE_SHIFT 16 +#define HC_HTXnL11WE_SHIFT 20 +/* HC_SubA_HTXnL0_5HE 0x0051 + */ +#define HC_HTXnL0HE_MASK 0x0000000f +#define HC_HTXnL1HE_MASK 0x000000f0 +#define HC_HTXnL2HE_MASK 0x00000f00 +#define HC_HTXnL3HE_MASK 0x0000f000 +#define HC_HTXnL4HE_MASK 0x000f0000 +#define HC_HTXnL5HE_MASK 0x00f00000 +#define HC_HTXnL1HE_SHIFT 4 +#define HC_HTXnL2HE_SHIFT 8 +#define HC_HTXnL3HE_SHIFT 12 +#define HC_HTXnL4HE_SHIFT 16 +#define HC_HTXnL5HE_SHIFT 20 +/* HC_SubA_HTXnL6_bHE 0x0052 + */ +#define HC_HTXnL6HE_MASK 0x0000000f +#define HC_HTXnL7HE_MASK 0x000000f0 +#define HC_HTXnL8HE_MASK 0x00000f00 +#define HC_HTXnL9HE_MASK 0x0000f000 +#define HC_HTXnLaHE_MASK 0x000f0000 +#define HC_HTXnLbHE_MASK 0x00f00000 +#define HC_HTXnL7HE_SHIFT 4 +#define HC_HTXnL8HE_SHIFT 8 +#define HC_HTXnL9HE_SHIFT 12 +#define HC_HTXnLaHE_SHIFT 16 +#define HC_HTXnLbHE_SHIFT 20 +/* HC_SubA_HTXnLc_11HE 0x0053 + */ +#define HC_HTXnLcHE_MASK 0x0000000f +#define HC_HTXnLdHE_MASK 0x000000f0 +#define HC_HTXnLeHE_MASK 0x00000f00 +#define HC_HTXnLfHE_MASK 0x0000f000 +#define HC_HTXnL10HE_MASK 0x000f0000 +#define HC_HTXnL11HE_MASK 0x00f00000 +#define HC_HTXnLdHE_SHIFT 4 +#define HC_HTXnLeHE_SHIFT 8 +#define HC_HTXnLfHE_SHIFT 12 +#define HC_HTXnL10HE_SHIFT 16 +#define HC_HTXnL11HE_SHIFT 20 +/* HC_SubA_HTXnL0OS 0x0077 + */ +#define HC_HTXnL0OS_MASK 0x003ff000 +#define HC_HTXnLVmax_MASK 0x00000fc0 +#define HC_HTXnLVmin_MASK 0x0000003f +#define HC_HTXnL0OS_SHIFT 12 +#define HC_HTXnLVmax_SHIFT 6 +/* HC_SubA_HTXnTB 0x0078 + */ +#define HC_HTXnTB_MASK 0x00f00000 +#define HC_HTXnFLSe_MASK 0x0000e000 +#define HC_HTXnFLSs_MASK 0x00001c00 +#define HC_HTXnFLTe_MASK 0x00000380 +#define HC_HTXnFLTs_MASK 0x00000070 +#define HC_HTXnFLDs_MASK 0x0000000f +#define HC_HTXnTB_NoTB 0x00000000 +#define HC_HTXnTB_TBC_S 0x00100000 +#define HC_HTXnTB_TBC_T 0x00200000 +#define HC_HTXnTB_TB_S 0x00400000 +#define HC_HTXnTB_TB_T 0x00800000 +#define HC_HTXnFLSe_Nearest 0x00000000 +#define HC_HTXnFLSe_Linear 0x00002000 +#define HC_HTXnFLSe_NonLinear 0x00004000 +#define HC_HTXnFLSe_Sharp 0x00008000 +#define HC_HTXnFLSe_Flat_Gaussian_Cubic 0x0000c000 +#define HC_HTXnFLSs_Nearest 0x00000000 +#define HC_HTXnFLSs_Linear 0x00000400 +#define HC_HTXnFLSs_NonLinear 0x00000800 +#define HC_HTXnFLSs_Flat_Gaussian_Cubic 0x00001800 +#define HC_HTXnFLTe_Nearest 0x00000000 +#define HC_HTXnFLTe_Linear 0x00000080 +#define HC_HTXnFLTe_NonLinear 0x00000100 +#define HC_HTXnFLTe_Sharp 0x00000180 +#define HC_HTXnFLTe_Flat_Gaussian_Cubic 0x00000300 +#define HC_HTXnFLTs_Nearest 0x00000000 +#define HC_HTXnFLTs_Linear 0x00000010 +#define HC_HTXnFLTs_NonLinear 0x00000020 +#define HC_HTXnFLTs_Flat_Gaussian_Cubic 0x00000060 +#define HC_HTXnFLDs_Tex0 0x00000000 +#define HC_HTXnFLDs_Nearest 0x00000001 +#define HC_HTXnFLDs_Linear 0x00000002 +#define HC_HTXnFLDs_NonLinear 0x00000003 +#define HC_HTXnFLDs_Dither 0x00000004 +#define HC_HTXnFLDs_ConstLOD 0x00000005 +#define HC_HTXnFLDs_Ani 0x00000006 +#define HC_HTXnFLDs_AniDither 0x00000007 +/* HC_SubA_HTXnMPMD 0x0079 + */ +#define HC_HTXnMPMD_SMASK 0x00070000 +#define HC_HTXnMPMD_TMASK 0x00380000 +#define HC_HTXnLODDTf_MASK 0x00000007 +#define HC_HTXnXY2ST_MASK 0x00000008 +#define HC_HTXnMPMD_Tsingle 0x00000000 +#define HC_HTXnMPMD_Tclamp 0x00080000 +#define HC_HTXnMPMD_Trepeat 0x00100000 +#define HC_HTXnMPMD_Tmirror 0x00180000 +#define HC_HTXnMPMD_Twrap 0x00200000 +#define HC_HTXnMPMD_Ssingle 0x00000000 +#define HC_HTXnMPMD_Sclamp 0x00010000 +#define HC_HTXnMPMD_Srepeat 0x00020000 +#define HC_HTXnMPMD_Smirror 0x00030000 +#define HC_HTXnMPMD_Swrap 0x00040000 +/* HC_SubA_HTXnCLODu 0x007a + */ +#define HC_HTXnCLODu_MASK 0x000ffc00 +#define HC_HTXnCLODd_MASK 0x000003ff +#define HC_HTXnCLODu_SHIFT 10 +/* HC_SubA_HTXnFM 0x007b + */ +#define HC_HTXnFM_MASK 0x00ff0000 +#define HC_HTXnLoc_MASK 0x00000003 +#define HC_HTXnFM_INDEX 0x00000000 +#define HC_HTXnFM_Intensity 0x00080000 +#define HC_HTXnFM_Lum 0x00100000 +#define HC_HTXnFM_Alpha 0x00180000 +#define HC_HTXnFM_DX 0x00280000 +#define HC_HTXnFM_ARGB16 0x00880000 +#define HC_HTXnFM_ARGB32 0x00980000 +#define HC_HTXnFM_ABGR16 0x00a80000 +#define HC_HTXnFM_ABGR32 0x00b80000 +#define HC_HTXnFM_RGBA16 0x00c80000 +#define HC_HTXnFM_RGBA32 0x00d80000 +#define HC_HTXnFM_BGRA16 0x00e80000 +#define HC_HTXnFM_BGRA32 0x00f80000 +#define HC_HTXnFM_BUMPMAP 0x00380000 +#define HC_HTXnFM_Index1 (HC_HTXnFM_INDEX | 0x00000000) +#define HC_HTXnFM_Index2 (HC_HTXnFM_INDEX | 0x00010000) +#define HC_HTXnFM_Index4 (HC_HTXnFM_INDEX | 0x00020000) +#define HC_HTXnFM_Index8 (HC_HTXnFM_INDEX | 0x00030000) +#define HC_HTXnFM_T1 (HC_HTXnFM_Intensity | 0x00000000) +#define HC_HTXnFM_T2 (HC_HTXnFM_Intensity | 0x00010000) +#define HC_HTXnFM_T4 (HC_HTXnFM_Intensity | 0x00020000) +#define HC_HTXnFM_T8 (HC_HTXnFM_Intensity | 0x00030000) +#define HC_HTXnFM_L1 (HC_HTXnFM_Lum | 0x00000000) +#define HC_HTXnFM_L2 (HC_HTXnFM_Lum | 0x00010000) +#define HC_HTXnFM_L4 (HC_HTXnFM_Lum | 0x00020000) +#define HC_HTXnFM_L8 (HC_HTXnFM_Lum | 0x00030000) +#define HC_HTXnFM_AL44 (HC_HTXnFM_Lum | 0x00040000) +#define HC_HTXnFM_AL88 (HC_HTXnFM_Lum | 0x00050000) +#define HC_HTXnFM_A1 (HC_HTXnFM_Alpha | 0x00000000) +#define HC_HTXnFM_A2 (HC_HTXnFM_Alpha | 0x00010000) +#define HC_HTXnFM_A4 (HC_HTXnFM_Alpha | 0x00020000) +#define HC_HTXnFM_A8 (HC_HTXnFM_Alpha | 0x00030000) +#define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000) +#define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000) +#define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000) +#define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000) +#define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000) +#define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000) +#define HC_HTXnFM_ARGB4444 (HC_HTXnFM_ARGB16 | 0x00030000) +#define HC_HTXnFM_ARGB0888 (HC_HTXnFM_ARGB32 | 0x00000000) +#define HC_HTXnFM_ARGB8888 (HC_HTXnFM_ARGB32 | 0x00010000) +#define HC_HTXnFM_BGR555 (HC_HTXnFM_ABGR16 | 0x00000000) +#define HC_HTXnFM_BGR565 (HC_HTXnFM_ABGR16 | 0x00010000) +#define HC_HTXnFM_ABGR1555 (HC_HTXnFM_ABGR16 | 0x00020000) +#define HC_HTXnFM_ABGR4444 (HC_HTXnFM_ABGR16 | 0x00030000) +#define HC_HTXnFM_ABGR0888 (HC_HTXnFM_ABGR32 | 0x00000000) +#define HC_HTXnFM_ABGR8888 (HC_HTXnFM_ABGR32 | 0x00010000) +#define HC_HTXnFM_RGBA5550 (HC_HTXnFM_RGBA16 | 0x00000000) +#define HC_HTXnFM_RGBA5551 (HC_HTXnFM_RGBA16 | 0x00020000) +#define HC_HTXnFM_RGBA4444 (HC_HTXnFM_RGBA16 | 0x00030000) +#define HC_HTXnFM_RGBA8880 (HC_HTXnFM_RGBA32 | 0x00000000) +#define HC_HTXnFM_RGBA8888 (HC_HTXnFM_RGBA32 | 0x00010000) +#define HC_HTXnFM_BGRA5550 (HC_HTXnFM_BGRA16 | 0x00000000) +#define HC_HTXnFM_BGRA5551 (HC_HTXnFM_BGRA16 | 0x00020000) +#define HC_HTXnFM_BGRA4444 (HC_HTXnFM_BGRA16 | 0x00030000) +#define HC_HTXnFM_BGRA8880 (HC_HTXnFM_BGRA32 | 0x00000000) +#define HC_HTXnFM_BGRA8888 (HC_HTXnFM_BGRA32 | 0x00010000) +#define HC_HTXnFM_VU88 (HC_HTXnFM_BUMPMAP | 0x00000000) +#define HC_HTXnFM_LVU655 (HC_HTXnFM_BUMPMAP | 0x00010000) +#define HC_HTXnFM_LVU888 (HC_HTXnFM_BUMPMAP | 0x00020000) +#define HC_HTXnLoc_Local 0x00000000 +#define HC_HTXnLoc_Sys 0x00000002 +#define HC_HTXnLoc_AGP 0x00000003 +/* HC_SubA_HTXnTRAH 0x007f + */ +#define HC_HTXnTRAH_MASK 0x00ff0000 +#define HC_HTXnTRAL_MASK 0x0000ff00 +#define HC_HTXnTBA_MASK 0x000000ff +#define HC_HTXnTRAH_SHIFT 16 +#define HC_HTXnTRAL_SHIFT 8 +/* HC_SubA_HTXnTBLCsat 0x0080 + *-- Define the input texture. + */ +#define HC_XTC_TOPC 0x00000000 +#define HC_XTC_InvTOPC 0x00000010 +#define HC_XTC_TOPCp5 0x00000020 +#define HC_XTC_Cbias 0x00000000 +#define HC_XTC_InvCbias 0x00000010 +#define HC_XTC_0 0x00000000 +#define HC_XTC_Dif 0x00000001 +#define HC_XTC_Spec 0x00000002 +#define HC_XTC_Tex 0x00000003 +#define HC_XTC_Cur 0x00000004 +#define HC_XTC_Adif 0x00000005 +#define HC_XTC_Fog 0x00000006 +#define HC_XTC_Atex 0x00000007 +#define HC_XTC_Acur 0x00000008 +#define HC_XTC_HTXnTBLRC 0x00000009 +#define HC_XTC_Ctexnext 0x0000000a +/*-- + */ +#define HC_HTXnTBLCsat_MASK 0x00800000 +#define HC_HTXnTBLCa_MASK 0x000fc000 +#define HC_HTXnTBLCb_MASK 0x00001f80 +#define HC_HTXnTBLCc_MASK 0x0000003f +#define HC_HTXnTBLCa_TOPC (HC_XTC_TOPC << 14) +#define HC_HTXnTBLCa_InvTOPC (HC_XTC_InvTOPC << 14) +#define HC_HTXnTBLCa_TOPCp5 (HC_XTC_TOPCp5 << 14) +#define HC_HTXnTBLCa_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCa_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCa_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCa_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCa_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCa_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCa_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCa_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCa_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCa_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCa_Ctexnext (HC_XTC_Ctexnext << 14) +#define HC_HTXnTBLCb_TOPC (HC_XTC_TOPC << 7) +#define HC_HTXnTBLCb_InvTOPC (HC_XTC_InvTOPC << 7) +#define HC_HTXnTBLCb_TOPCp5 (HC_XTC_TOPCp5 << 7) +#define HC_HTXnTBLCb_0 (HC_XTC_0 << 7) +#define HC_HTXnTBLCb_Dif (HC_XTC_Dif << 7) +#define HC_HTXnTBLCb_Spec (HC_XTC_Spec << 7) +#define HC_HTXnTBLCb_Tex (HC_XTC_Tex << 7) +#define HC_HTXnTBLCb_Cur (HC_XTC_Cur << 7) +#define HC_HTXnTBLCb_Adif (HC_XTC_Adif << 7) +#define HC_HTXnTBLCb_Fog (HC_XTC_Fog << 7) +#define HC_HTXnTBLCb_Atex (HC_XTC_Atex << 7) +#define HC_HTXnTBLCb_Acur (HC_XTC_Acur << 7) +#define HC_HTXnTBLCb_HTXnTBLRC (HC_XTC_HTXnTBLRC << 7) +#define HC_HTXnTBLCb_Ctexnext (HC_XTC_Ctexnext << 7) +#define HC_HTXnTBLCc_TOPC (HC_XTC_TOPC << 0) +#define HC_HTXnTBLCc_InvTOPC (HC_XTC_InvTOPC << 0) +#define HC_HTXnTBLCc_TOPCp5 (HC_XTC_TOPCp5 << 0) +#define HC_HTXnTBLCc_0 (HC_XTC_0 << 0) +#define HC_HTXnTBLCc_Dif (HC_XTC_Dif << 0) +#define HC_HTXnTBLCc_Spec (HC_XTC_Spec << 0) +#define HC_HTXnTBLCc_Tex (HC_XTC_Tex << 0) +#define HC_HTXnTBLCc_Cur (HC_XTC_Cur << 0) +#define HC_HTXnTBLCc_Adif (HC_XTC_Adif << 0) +#define HC_HTXnTBLCc_Fog (HC_XTC_Fog << 0) +#define HC_HTXnTBLCc_Atex (HC_XTC_Atex << 0) +#define HC_HTXnTBLCc_Acur (HC_XTC_Acur << 0) +#define HC_HTXnTBLCc_HTXnTBLRC (HC_XTC_HTXnTBLRC << 0) +#define HC_HTXnTBLCc_Ctexnext (HC_XTC_Ctexnext << 0) +/* HC_SubA_HTXnTBLCop 0x0081 + */ +#define HC_HTXnTBLdot_MASK 0x00c00000 +#define HC_HTXnTBLCop_MASK 0x00380000 +#define HC_HTXnTBLCbias_MASK 0x0007c000 +#define HC_HTXnTBLCshift_MASK 0x00001800 +#define HC_HTXnTBLAop_MASK 0x00000380 +#define HC_HTXnTBLAbias_MASK 0x00000078 +#define HC_HTXnTBLAshift_MASK 0x00000003 +#define HC_HTXnTBLCop_Add 0x00000000 +#define HC_HTXnTBLCop_Sub 0x00080000 +#define HC_HTXnTBLCop_Min 0x00100000 +#define HC_HTXnTBLCop_Max 0x00180000 +#define HC_HTXnTBLCop_Mask 0x00200000 +#define HC_HTXnTBLCbias_Cbias (HC_XTC_Cbias << 14) +#define HC_HTXnTBLCbias_InvCbias (HC_XTC_InvCbias << 14) +#define HC_HTXnTBLCbias_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCbias_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCbias_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCbias_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCbias_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCbias_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCbias_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCbias_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCbias_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCbias_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCshift_1 0x00000000 +#define HC_HTXnTBLCshift_2 0x00000800 +#define HC_HTXnTBLCshift_No 0x00001000 +#define HC_HTXnTBLCshift_DotP 0x00001800 +#define HC_HTXnTBLAop_Add 0x00000000 +#define HC_HTXnTBLAop_Sub 0x00000080 +#define HC_HTXnTBLAop_Min 0x00000100 +#define HC_HTXnTBLAop_Max 0x00000180 +#define HC_HTXnTBLAop_Mask 0x00000200 +#define HC_HTXnTBLAbias_Inv 0x00000040 +#define HC_HTXnTBLAbias_Adif 0x00000000 +#define HC_HTXnTBLAbias_Fog 0x00000008 +#define HC_HTXnTBLAbias_Acur 0x00000010 +#define HC_HTXnTBLAbias_HTXnTBLRAbias 0x00000018 +#define HC_HTXnTBLAbias_Atex 0x00000020 +#define HC_HTXnTBLAshift_1 0x00000000 +#define HC_HTXnTBLAshift_2 0x00000001 +#define HC_HTXnTBLAshift_No 0x00000002 +/* #define HC_HTXnTBLAshift_DotP 0x00000003 */ +/* HC_SubA_HTXnTBLMPFog 0x0082 + */ +#define HC_HTXnTBLMPfog_MASK 0x00e00000 +#define HC_HTXnTBLMPfog_0 0x00000000 +#define HC_HTXnTBLMPfog_Adif 0x00200000 +#define HC_HTXnTBLMPfog_Fog 0x00400000 +#define HC_HTXnTBLMPfog_Atex 0x00600000 +#define HC_HTXnTBLMPfog_Acur 0x00800000 +#define HC_HTXnTBLMPfog_GHTXnTBLRFog 0x00a00000 +/* HC_SubA_HTXnTBLAsat 0x0083 + *-- Define the texture alpha input. + */ +#define HC_XTA_TOPA 0x00000000 +#define HC_XTA_InvTOPA 0x00000008 +#define HC_XTA_TOPAp5 0x00000010 +#define HC_XTA_Adif 0x00000000 +#define HC_XTA_Fog 0x00000001 +#define HC_XTA_Acur 0x00000002 +#define HC_XTA_HTXnTBLRA 0x00000003 +#define HC_XTA_Atex 0x00000004 +#define HC_XTA_Atexnext 0x00000005 +/*-- + */ +#define HC_HTXnTBLAsat_MASK 0x00800000 +#define HC_HTXnTBLAMB_MASK 0x00700000 +#define HC_HTXnTBLAa_MASK 0x0007c000 +#define HC_HTXnTBLAb_MASK 0x00000f80 +#define HC_HTXnTBLAc_MASK 0x0000001f +#define HC_HTXnTBLAMB_SHIFT 20 +#define HC_HTXnTBLAa_TOPA (HC_XTA_TOPA << 14) +#define HC_HTXnTBLAa_InvTOPA (HC_XTA_InvTOPA << 14) +#define HC_HTXnTBLAa_TOPAp5 (HC_XTA_TOPAp5 << 14) +#define HC_HTXnTBLAa_Adif (HC_XTA_Adif << 14) +#define HC_HTXnTBLAa_Fog (HC_XTA_Fog << 14) +#define HC_HTXnTBLAa_Acur (HC_XTA_Acur << 14) +#define HC_HTXnTBLAa_HTXnTBLRA (HC_XTA_HTXnTBLRA << 14) +#define HC_HTXnTBLAa_Atex (HC_XTA_Atex << 14) +#define HC_HTXnTBLAa_Atexnext (HC_XTA_Atexnext << 14) +#define HC_HTXnTBLAb_TOPA (HC_XTA_TOPA << 7) +#define HC_HTXnTBLAb_InvTOPA (HC_XTA_InvTOPA << 7) +#define HC_HTXnTBLAb_TOPAp5 (HC_XTA_TOPAp5 << 7) +#define HC_HTXnTBLAb_Adif (HC_XTA_Adif << 7) +#define HC_HTXnTBLAb_Fog (HC_XTA_Fog << 7) +#define HC_HTXnTBLAb_Acur (HC_XTA_Acur << 7) +#define HC_HTXnTBLAb_HTXnTBLRA (HC_XTA_HTXnTBLRA << 7) +#define HC_HTXnTBLAb_Atex (HC_XTA_Atex << 7) +#define HC_HTXnTBLAb_Atexnext (HC_XTA_Atexnext << 7) +#define HC_HTXnTBLAc_TOPA (HC_XTA_TOPA << 0) +#define HC_HTXnTBLAc_InvTOPA (HC_XTA_InvTOPA << 0) +#define HC_HTXnTBLAc_TOPAp5 (HC_XTA_TOPAp5 << 0) +#define HC_HTXnTBLAc_Adif (HC_XTA_Adif << 0) +#define HC_HTXnTBLAc_Fog (HC_XTA_Fog << 0) +#define HC_HTXnTBLAc_Acur (HC_XTA_Acur << 0) +#define HC_HTXnTBLAc_HTXnTBLRA (HC_XTA_HTXnTBLRA << 0) +#define HC_HTXnTBLAc_Atex (HC_XTA_Atex << 0) +#define HC_HTXnTBLAc_Atexnext (HC_XTA_Atexnext << 0) +/* HC_SubA_HTXnTBLRAa 0x0089 + */ +#define HC_HTXnTBLRAa_MASK 0x00ff0000 +#define HC_HTXnTBLRAb_MASK 0x0000ff00 +#define HC_HTXnTBLRAc_MASK 0x000000ff +#define HC_HTXnTBLRAa_SHIFT 16 +#define HC_HTXnTBLRAb_SHIFT 8 +#define HC_HTXnTBLRAc_SHIFT 0 +/* HC_SubA_HTXnTBLRFog 0x008a + */ +#define HC_HTXnTBLRFog_MASK 0x0000ff00 +#define HC_HTXnTBLRAbias_MASK 0x000000ff +#define HC_HTXnTBLRFog_SHIFT 8 +#define HC_HTXnTBLRAbias_SHIFT 0 +/* HC_SubA_HTXnLScale 0x0094 + */ +#define HC_HTXnLScale_MASK 0x0007fc00 +#define HC_HTXnLOff_MASK 0x000001ff +#define HC_HTXnLScale_SHIFT 10 +/* HC_SubA_HTXSMD 0x0000 + */ +#define HC_HTXSMD_MASK 0x00000080 +#define HC_HTXTMD_MASK 0x00000040 +#define HC_HTXNum_MASK 0x00000038 +#define HC_HTXTRMD_MASK 0x00000006 +#define HC_HTXCHCLR_MASK 0x00000001 +#define HC_HTXNum_SHIFT 3 + +/* Texture Palette n + */ +#define HC_SubType_TexPalette0 0x00000000 +#define HC_SubType_TexPalette1 0x00000001 +#define HC_SubType_FogTable 0x00000010 +#define HC_SubType_Stipple 0x00000014 +/* HC_SubA_TexPalette0 0x0000 + */ +#define HC_HTPnA_MASK 0xff000000 +#define HC_HTPnR_MASK 0x00ff0000 +#define HC_HTPnG_MASK 0x0000ff00 +#define HC_HTPnB_MASK 0x000000ff +/* HC_SubA_FogTable 0x0010 + */ +#define HC_HFPn3_MASK 0xff000000 +#define HC_HFPn2_MASK 0x00ff0000 +#define HC_HFPn1_MASK 0x0000ff00 +#define HC_HFPn_MASK 0x000000ff +#define HC_HFPn3_SHIFT 24 +#define HC_HFPn2_SHIFT 16 +#define HC_HFPn1_SHIFT 8 + +/* Auto Testing & Security + */ +#define HC_SubA_HenFIFOAT 0x0000 +#define HC_SubA_HFBDrawFirst 0x0004 +#define HC_SubA_HFBBasL 0x0005 +#define HC_SubA_HFBDst 0x0006 +/* HC_SubA_HenFIFOAT 0x0000 + */ +#define HC_HenFIFOAT_MASK 0x00000020 +#define HC_HenGEMILock_MASK 0x00000010 +#define HC_HenFBASwap_MASK 0x00000008 +#define HC_HenOT_MASK 0x00000004 +#define HC_HenCMDQ_MASK 0x00000002 +#define HC_HenTXCTSU_MASK 0x00000001 +/* HC_SubA_HFBDrawFirst 0x0004 + */ +#define HC_HFBDrawFirst_MASK 0x00000800 +#define HC_HFBQueue_MASK 0x00000400 +#define HC_HFBLock_MASK 0x00000200 +#define HC_HEOF_MASK 0x00000100 +#define HC_HFBBasH_MASK 0x000000ff + +/* GEMI Setting + */ +#define HC_SubA_HTArbRCM 0x0008 +#define HC_SubA_HTArbRZ 0x000a +#define HC_SubA_HTArbWZ 0x000b +#define HC_SubA_HTArbRTX 0x000c +#define HC_SubA_HTArbRCW 0x000d +#define HC_SubA_HTArbE2 0x000e +#define HC_SubA_HArbRQCM 0x0010 +#define HC_SubA_HArbWQCM 0x0011 +#define HC_SubA_HGEMITout 0x0020 +#define HC_SubA_HFthRTXD 0x0040 +#define HC_SubA_HFthRTXA 0x0044 +#define HC_SubA_HCMDQstL 0x0050 +#define HC_SubA_HCMDQendL 0x0051 +#define HC_SubA_HCMDQLen 0x0052 +/* HC_SubA_HTArbRCM 0x0008 + */ +#define HC_HTArbRCM_MASK 0x0000ffff +/* HC_SubA_HTArbRZ 0x000a + */ +#define HC_HTArbRZ_MASK 0x0000ffff +/* HC_SubA_HTArbWZ 0x000b + */ +#define HC_HTArbWZ_MASK 0x0000ffff +/* HC_SubA_HTArbRTX 0x000c + */ +#define HC_HTArbRTX_MASK 0x0000ffff +/* HC_SubA_HTArbRCW 0x000d + */ +#define HC_HTArbRCW_MASK 0x0000ffff +/* HC_SubA_HTArbE2 0x000e + */ +#define HC_HTArbE2_MASK 0x0000ffff +/* HC_SubA_HArbRQCM 0x0010 + */ +#define HC_HTArbRQCM_MASK 0x0000ffff +/* HC_SubA_HArbWQCM 0x0011 + */ +#define HC_HArbWQCM_MASK 0x0000ffff +/* HC_SubA_HGEMITout 0x0020 + */ +#define HC_HGEMITout_MASK 0x000f0000 +#define HC_HNPArbZC_MASK 0x0000ffff +#define HC_HGEMITout_SHIFT 16 +/* HC_SubA_HFthRTXD 0x0040 + */ +#define HC_HFthRTXD_MASK 0x00ff0000 +#define HC_HFthRZD_MASK 0x0000ff00 +#define HC_HFthWZD_MASK 0x000000ff +#define HC_HFthRTXD_SHIFT 16 +#define HC_HFthRZD_SHIFT 8 +/* HC_SubA_HFthRTXA 0x0044 + */ +#define HC_HFthRTXA_MASK 0x000000ff + +/****************************************************************************** +** Define the Halcyon Internal register access constants. For simulator only. +******************************************************************************/ +#define HC_SIMA_HAGPBstL 0x0000 +#define HC_SIMA_HAGPBendL 0x0001 +#define HC_SIMA_HAGPCMNT 0x0002 +#define HC_SIMA_HAGPBpL 0x0003 +#define HC_SIMA_HAGPBpH 0x0004 +#define HC_SIMA_HClipTB 0x0005 +#define HC_SIMA_HClipLR 0x0006 +#define HC_SIMA_HFPClipTL 0x0007 +#define HC_SIMA_HFPClipBL 0x0008 +#define HC_SIMA_HFPClipLL 0x0009 +#define HC_SIMA_HFPClipRL 0x000a +#define HC_SIMA_HFPClipTBH 0x000b +#define HC_SIMA_HFPClipLRH 0x000c +#define HC_SIMA_HLP 0x000d +#define HC_SIMA_HLPRF 0x000e +#define HC_SIMA_HSolidCL 0x000f +#define HC_SIMA_HPixGC 0x0010 +#define HC_SIMA_HSPXYOS 0x0011 +#define HC_SIMA_HCmdA 0x0012 +#define HC_SIMA_HCmdB 0x0013 +#define HC_SIMA_HEnable 0x0014 +#define HC_SIMA_HZWBBasL 0x0015 +#define HC_SIMA_HZWBBasH 0x0016 +#define HC_SIMA_HZWBType 0x0017 +#define HC_SIMA_HZBiasL 0x0018 +#define HC_SIMA_HZWBend 0x0019 +#define HC_SIMA_HZWTMD 0x001a +#define HC_SIMA_HZWCDL 0x001b +#define HC_SIMA_HZWCTAGnum 0x001c +#define HC_SIMA_HZCYNum 0x001d +#define HC_SIMA_HZWCFire 0x001e +/* #define HC_SIMA_HSBBasL 0x001d */ +/* #define HC_SIMA_HSBBasH 0x001e */ +/* #define HC_SIMA_HSBFM 0x001f */ +#define HC_SIMA_HSTREF 0x0020 +#define HC_SIMA_HSTMD 0x0021 +#define HC_SIMA_HABBasL 0x0022 +#define HC_SIMA_HABBasH 0x0023 +#define HC_SIMA_HABFM 0x0024 +#define HC_SIMA_HATMD 0x0025 +#define HC_SIMA_HABLCsat 0x0026 +#define HC_SIMA_HABLCop 0x0027 +#define HC_SIMA_HABLAsat 0x0028 +#define HC_SIMA_HABLAop 0x0029 +#define HC_SIMA_HABLRCa 0x002a +#define HC_SIMA_HABLRFCa 0x002b +#define HC_SIMA_HABLRCbias 0x002c +#define HC_SIMA_HABLRCb 0x002d +#define HC_SIMA_HABLRFCb 0x002e +#define HC_SIMA_HABLRAa 0x002f +#define HC_SIMA_HABLRAb 0x0030 +#define HC_SIMA_HDBBasL 0x0031 +#define HC_SIMA_HDBBasH 0x0032 +#define HC_SIMA_HDBFM 0x0033 +#define HC_SIMA_HFBBMSKL 0x0034 +#define HC_SIMA_HROP 0x0035 +#define HC_SIMA_HFogLF 0x0036 +#define HC_SIMA_HFogCL 0x0037 +#define HC_SIMA_HFogCH 0x0038 +#define HC_SIMA_HFogStL 0x0039 +#define HC_SIMA_HFogStH 0x003a +#define HC_SIMA_HFogOOdMF 0x003b +#define HC_SIMA_HFogOOdEF 0x003c +#define HC_SIMA_HFogEndL 0x003d +#define HC_SIMA_HFogDenst 0x003e +/*---- start of texture 0 setting ---- + */ +#define HC_SIMA_HTX0L0BasL 0x0040 +#define HC_SIMA_HTX0L1BasL 0x0041 +#define HC_SIMA_HTX0L2BasL 0x0042 +#define HC_SIMA_HTX0L3BasL 0x0043 +#define HC_SIMA_HTX0L4BasL 0x0044 +#define HC_SIMA_HTX0L5BasL 0x0045 +#define HC_SIMA_HTX0L6BasL 0x0046 +#define HC_SIMA_HTX0L7BasL 0x0047 +#define HC_SIMA_HTX0L8BasL 0x0048 +#define HC_SIMA_HTX0L9BasL 0x0049 +#define HC_SIMA_HTX0LaBasL 0x004a +#define HC_SIMA_HTX0LbBasL 0x004b +#define HC_SIMA_HTX0LcBasL 0x004c +#define HC_SIMA_HTX0LdBasL 0x004d +#define HC_SIMA_HTX0LeBasL 0x004e +#define HC_SIMA_HTX0LfBasL 0x004f +#define HC_SIMA_HTX0L10BasL 0x0050 +#define HC_SIMA_HTX0L11BasL 0x0051 +#define HC_SIMA_HTX0L012BasH 0x0052 +#define HC_SIMA_HTX0L345BasH 0x0053 +#define HC_SIMA_HTX0L678BasH 0x0054 +#define HC_SIMA_HTX0L9abBasH 0x0055 +#define HC_SIMA_HTX0LcdeBasH 0x0056 +#define HC_SIMA_HTX0Lf1011BasH 0x0057 +#define HC_SIMA_HTX0L0Pit 0x0058 +#define HC_SIMA_HTX0L1Pit 0x0059 +#define HC_SIMA_HTX0L2Pit 0x005a +#define HC_SIMA_HTX0L3Pit 0x005b +#define HC_SIMA_HTX0L4Pit 0x005c +#define HC_SIMA_HTX0L5Pit 0x005d +#define HC_SIMA_HTX0L6Pit 0x005e +#define HC_SIMA_HTX0L7Pit 0x005f +#define HC_SIMA_HTX0L8Pit 0x0060 +#define HC_SIMA_HTX0L9Pit 0x0061 +#define HC_SIMA_HTX0LaPit 0x0062 +#define HC_SIMA_HTX0LbPit 0x0063 +#define HC_SIMA_HTX0LcPit 0x0064 +#define HC_SIMA_HTX0LdPit 0x0065 +#define HC_SIMA_HTX0LePit 0x0066 +#define HC_SIMA_HTX0LfPit 0x0067 +#define HC_SIMA_HTX0L10Pit 0x0068 +#define HC_SIMA_HTX0L11Pit 0x0069 +#define HC_SIMA_HTX0L0_5WE 0x006a +#define HC_SIMA_HTX0L6_bWE 0x006b +#define HC_SIMA_HTX0Lc_11WE 0x006c +#define HC_SIMA_HTX0L0_5HE 0x006d +#define HC_SIMA_HTX0L6_bHE 0x006e +#define HC_SIMA_HTX0Lc_11HE 0x006f +#define HC_SIMA_HTX0L0OS 0x0070 +#define HC_SIMA_HTX0TB 0x0071 +#define HC_SIMA_HTX0MPMD 0x0072 +#define HC_SIMA_HTX0CLODu 0x0073 +#define HC_SIMA_HTX0FM 0x0074 +#define HC_SIMA_HTX0TRCH 0x0075 +#define HC_SIMA_HTX0TRCL 0x0076 +#define HC_SIMA_HTX0TBC 0x0077 +#define HC_SIMA_HTX0TRAH 0x0078 +#define HC_SIMA_HTX0TBLCsat 0x0079 +#define HC_SIMA_HTX0TBLCop 0x007a +#define HC_SIMA_HTX0TBLMPfog 0x007b +#define HC_SIMA_HTX0TBLAsat 0x007c +#define HC_SIMA_HTX0TBLRCa 0x007d +#define HC_SIMA_HTX0TBLRCb 0x007e +#define HC_SIMA_HTX0TBLRCc 0x007f +#define HC_SIMA_HTX0TBLRCbias 0x0080 +#define HC_SIMA_HTX0TBLRAa 0x0081 +#define HC_SIMA_HTX0TBLRFog 0x0082 +#define HC_SIMA_HTX0BumpM00 0x0083 +#define HC_SIMA_HTX0BumpM01 0x0084 +#define HC_SIMA_HTX0BumpM10 0x0085 +#define HC_SIMA_HTX0BumpM11 0x0086 +#define HC_SIMA_HTX0LScale 0x0087 +/*---- end of texture 0 setting ---- 0x008f + */ +#define HC_SIMA_TX0TX1_OFF 0x0050 +/*---- start of texture 1 setting ---- + */ +#define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) +/*---- end of texture 1 setting ---- 0xaf + */ +#define HC_SIMA_HTXSMD 0x00b0 +#define HC_SIMA_HenFIFOAT 0x00b1 +#define HC_SIMA_HFBDrawFirst 0x00b2 +#define HC_SIMA_HFBBasL 0x00b3 +#define HC_SIMA_HTArbRCM 0x00b4 +#define HC_SIMA_HTArbRZ 0x00b5 +#define HC_SIMA_HTArbWZ 0x00b6 +#define HC_SIMA_HTArbRTX 0x00b7 +#define HC_SIMA_HTArbRCW 0x00b8 +#define HC_SIMA_HTArbE2 0x00b9 +#define HC_SIMA_HGEMITout 0x00ba +#define HC_SIMA_HFthRTXD 0x00bb +#define HC_SIMA_HFthRTXA 0x00bc +/* Define the texture palette 0 + */ +#define HC_SIMA_HTP0 0x0100 +#define HC_SIMA_HTP1 0x0200 +#define HC_SIMA_FOGTABLE 0x0300 +#define HC_SIMA_STIPPLE 0x0400 +#define HC_SIMA_HE3Fire 0x0440 +#define HC_SIMA_TRANS_SET 0x0441 +#define HC_SIMA_HREngSt 0x0442 +#define HC_SIMA_HRFIFOempty 0x0443 +#define HC_SIMA_HRFIFOfull 0x0444 +#define HC_SIMA_HRErr 0x0445 +#define HC_SIMA_FIFOstatus 0x0446 + +/****************************************************************************** +** Define the AGP command header. +******************************************************************************/ +#define HC_ACMD_MASK 0xfe000000 +#define HC_ACMD_SUB_MASK 0x0c000000 +#define HC_ACMD_HCmdA 0xee000000 +#define HC_ACMD_HCmdB 0xec000000 +#define HC_ACMD_HCmdC 0xea000000 +#define HC_ACMD_H1 0xf0000000 +#define HC_ACMD_H2 0xf2000000 +#define HC_ACMD_H3 0xf4000000 +#define HC_ACMD_H4 0xf6000000 + +#define HC_ACMD_H1IO_MASK 0x000001ff +#define HC_ACMD_H2IO1_MASK 0x001ff000 +#define HC_ACMD_H2IO2_MASK 0x000001ff +#define HC_ACMD_H2IO1_SHIFT 12 +#define HC_ACMD_H2IO2_SHIFT 0 +#define HC_ACMD_H3IO_MASK 0x000001ff +#define HC_ACMD_H3COUNT_MASK 0x01fff000 +#define HC_ACMD_H3COUNT_SHIFT 12 +#define HC_ACMD_H4ID_MASK 0x000001ff +#define HC_ACMD_H4COUNT_MASK 0x01fffe00 +#define HC_ACMD_H4COUNT_SHIFT 9 + +/******************************************************************************** +** Define Header +********************************************************************************/ +#define HC_HEADER2 0xF210F110 + +/******************************************************************************** +** Define Dummy Value +********************************************************************************/ +#define HC_DUMMY 0xCCCCCCCC +/******************************************************************************** +** Define for DMA use +********************************************************************************/ +#define HALCYON_HEADER2 0XF210F110 +#define HALCYON_FIRECMD 0XEE100000 +#define HALCYON_FIREMASK 0XFFF00000 +#define HALCYON_CMDB 0XEC000000 +#define HALCYON_CMDBMASK 0XFFFE0000 +#define HALCYON_SUB_ADDR0 0X00000000 +#define HALCYON_HEADER1MASK 0XFFFFFF00 +#define HALCYON_HEADER1 0XF0000000 +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +#define HC_HAGPBpH_MASK 0x00ffffff + +#endif // __VIA_REGS_3D_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_accel.c b/Source/DirectFB/gfxdrivers/cle266/uc_accel.c new file mode 100755 index 0000000..caad848 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_accel.c @@ -0,0 +1,504 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include + +#include "unichrome.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "mmio.h" + +#define UC_ACCEL_BEGIN() \ + UcDriverData *ucdrv = (UcDriverData*) drv; \ + UcDeviceData *ucdev = (UcDeviceData*) dev; \ + struct uc_fifo *fifo = ucdrv->fifo; \ + /*printf("entering %s\n", __PRETTY_FUNCTION__)*/ + +#define UC_ACCEL_END() \ + UC_FIFO_CHECK(fifo); \ + /*printf("leaving %s\n", __PRETTY_FUNCTION__)*/ + +// Private functions --------------------------------------------------------- + +/** Wait until a new command can be set up. */ + +static inline void uc_waitcmd(UcDriverData* ucdrv, UcDeviceData* ucdev) +{ + int loop = 0; + + if (!ucdev->must_wait) + return; + + //printf("waitcmd "); + + while (VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/VIA: Timeout waiting for idle command regulator!\n"); + break; + } + } + + //printf("waited for %d (0x%x) cycles.\n", loop, loop); + + ucdev->cmd_waitcycles += loop; + ucdev->must_wait = 0; +} + +/** Send commands to 2D/3D engine. */ + +void uc_emit_commands(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + uc_waitcmd(ucdrv, ucdev); + + UC_FIFO_FLUSH(fifo); + + ucdev->must_wait = 1; +} + +void uc_flush_texture_cache(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + (void) ucdev; + + UC_FIFO_PREPARE(fifo, 4); + + UC_FIFO_ADD_HDR(fifo, (HC_ParaType_Tex << 16) | (HC_SubType_TexGeneral << 24)); + UC_FIFO_ADD_3D(fifo, HC_SubA_HTXSMD, HC_HTXCHCLR_MASK); + UC_FIFO_ADD_3D(fifo, HC_SubA_HTXSMD, 0); + + UC_FIFO_CHECK(fifo); +} + +/** + * Draw a horizontal or vertical line. + * + * @param fifo command FIFO + * + * @param x start x position + * @param y start y position + * @param len length + * @param hv if zero: draw from left to right + * if nonzero: draw from top to bottom. + * + * @note This is actually a 1-pixel high or wide rectangular color fill. + */ + +static inline void uc_draw_hv_line(struct uc_fifo* fifo, + int x, int y, int len, int hv, int rop) +{ + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(y) << 16) | RS16(x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, len << (hv ? 16 : 0)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | rop | VIA_GEC_CLIP_ENABLE); +} + +// DirectFB interfacing functions -------------------------------------------- + +// Functions using the 2D engine --- + +bool uc_fill_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 8); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(r->y) << 16) | RS16(r->x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, + (((RS16(r->h - 1)) << 16) | RS16((r->w - 1)))); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | ucdev->draw_rop2d | VIA_GEC_CLIP_ENABLE); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + int rop = ucdev->draw_rop2d; + + // Draw lines, in this order: top, bottom, left, right + + UC_FIFO_PREPARE(fifo, 26); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + uc_draw_hv_line(fifo, r->x, r->y, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y + r->h - 1, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y, r->h - 1, 1, rop); + uc_draw_hv_line(fifo, r->x + r->w - 1, r->y, r->h - 1, 1, rop); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + //printf("%s: l = (%d, %d) - (%d, %d), c = 0x%08x\n", __PRETTY_FUNCTION__, + // line->x1, line->y1, line->x2, line->y2, ucdev->color); + + int cmd; + int dx, dy, tmp, error; + + error = 1; + + cmd = VIA_GEC_LINE | VIA_GEC_FIXCOLOR_PAT | ucdev->draw_rop2d + | VIA_GEC_CLIP_ENABLE; + + dx = line->x2 - line->x1; + if (dx < 0) + { + dx = -dx; + cmd |= VIA_GEC_DECX; // line will be drawn from right + error = 0; + } + + dy = line->y2 - line->y1; + if (dy < 0) + { + dy = -dy; + cmd |= VIA_GEC_DECY; // line will be drawn from bottom + } + + if (dy > dx) + { + tmp = dy; + dy = dx; + dx = tmp; // Swap 'dx' and 'dy' + cmd |= VIA_GEC_Y_MAJOR; // Y major line + } + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_K1K2, + ((((dy << 1) & 0x3fff) << 16)| (((dy - dx) << 1) & 0x3fff))); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_XY, + ((RS16(line->y1) << 16) | RS16(line->x1))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, dx); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_ERROR, + (((dy << 1) - dx - error) & 0x3fff)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit(void* drv, void* dev, DFBRectangle* rect, int dx, int dy) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = (%d, %d, %d, %d) -> (%d, %d)\n", __PRETTY_FUNCTION__, + // rect->x, rect->y, rect->h, rect->w, dx, dy); + + int cmd = VIA_GEC_BLT | VIA_ROP_S | VIA_GEC_CLIP_ENABLE; + + int sx = rect->x; + int sy = rect->y; + int w = rect->w; + int h = rect->h; + + if (!w || !h) return true; + + (void) ucdev; // Kill 'unused variable' compiler warning. + + if (sx < dx) { + cmd |= VIA_GEC_DECX; + sx += w - 1; + dx += w - 1; + } + + if (sy < dy) { + cmd |= VIA_GEC_DECY; + sy += h - 1; + dy += h - 1; + } + + UC_FIFO_PREPARE(fifo, 10); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_SRCPOS, (RS16(sy) << 16) | RS16(sx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, (RS16(dy) << 16) | RS16(dx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, (RS16(h - 1) << 16) | RS16(w - 1)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +// Functions using the 3D engine --- + +bool uc_fill_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color3d); + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_AFP | + HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC | HC_HShading_FlatC; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 18); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y + r->h, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_AFP | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 20); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line_3d(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, line->x1, line->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, line->x2, line->y2, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_fill_triangle(void* drv, void* dev, DFBTriangle* tri) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 14); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, tri->x1, tri->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, tri->x2, tri->y2, 0); + UC_FIFO_ADD_XYC(fifo, tri->x3, tri->y3, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit_3d(void* drv, void* dev, + DFBRectangle* rect, int dx, int dy) +{ + // TODO: Write separate blit function to save some overhead. + + // Hmm, I don't think we can save anything beyond a few CPU cycles. -- dok + + DFBRectangle dest = {dx, dy, rect->w, rect->h}; + return uc_stretch_blit(drv, dev, rect, &dest); +} + +bool uc_stretch_blit(void* drv, void* dev, + DFBRectangle* sr, DFBRectangle* dr) +{ + UC_ACCEL_BEGIN() + + float w = ucdev->hwtex.l2w; + float h = ucdev->hwtex.l2h; + + float dy = dr->y; + + float s1 = (sr->x ) / w; + float t1 = (sr->y ) / h; + float s2 = (sr->x + sr->w) / w; + float t2 = (sr->y + sr->h) / h; + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_FlatC | + HC_HVCycle_AFP | HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (ucdev->bflags & DSBLIT_DEINTERLACE) { + t1 *= 0.5f; + t2 *= 0.5f; + + if (ucdev->field) + dy += 0.5f; + else + dy -= 0.5f; + } + + UC_FIFO_PREPARE(fifo, 30); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy, 1, 0, s2, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy+dr->h, 1, 0, s1, t2); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy, 1, ucdev->color3d, s1, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy+dr->h, 1, ucdev->color3d, s2, t2); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + +#define DFBCOLOR_TO_ARGB(c) PIXEL_ARGB( (c).a, (c).r, (c).g, (c).b ) + +bool uc_texture_triangles( void *drv, void *dev, + DFBVertex *vertices, int num, + DFBTriangleFormation formation ) +{ + UC_ACCEL_BEGIN() + + int i; + + int cmdB = HC_ACMD_HCmdB | + HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Z | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_Gouraud | + HC_HVCycle_Full; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + + switch (formation) { + case DTTF_LIST: + cmdA |= HC_HVCycle_NewA | HC_HVCycle_NewB | HC_HVCycle_NewC; + break; + case DTTF_STRIP: + cmdA |= HC_HVCycle_AB | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + case DTTF_FAN: + cmdA |= HC_HVCycle_AA | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + default: + D_ONCE( "unknown triangle formation" ); + return false; + } + + UC_FIFO_PREPARE(fifo, 6 + num * 7); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + for (i=0; icolor3d, + vertices[i].s, vertices[i].t); + } + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + + // Blit profiling + + //struct timeval tv_start, tv_stop; + //gettimeofday(&tv_start, NULL); + + // Run test here + + //gettimeofday(&tv_stop, NULL); + + //tv_stop.tv_sec -= tv_start.tv_sec; + //tv_stop.tv_usec -= tv_start.tv_usec; + //if (tv_stop.tv_usec < 0) { + // tv_stop.tv_sec--; + // tv_stop.tv_usec += 1000000; + //} + + //printf("elapsed time: %d us\n", tv_stop.tv_usec); diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_accel.h b/Source/DirectFB/gfxdrivers/cle266/uc_accel.h new file mode 100755 index 0000000..fb6e111 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_accel.h @@ -0,0 +1,119 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_ACCEL_H__ +#define __UC_ACCEL_H__ + +#include "unichrome.h" + + +// 2D accelerator capabilites + +#define UC_DRAWING_FLAGS_2D (DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_2D (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY) + +#define UC_DRAWING_FUNCTIONS_2D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE) + +#define UC_BLITTING_FUNCTIONS_2D (DFXL_BLIT) + + +// 3D accelerator capabilites + +#ifdef UC_ENABLE_3D + +#define UC_DRAWING_FLAGS_3D (DSDRAW_BLEND | DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_3D (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE) + +#define UC_DRAWING_FUNCTIONS_3D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE | \ + DFXL_FILLTRIANGLE) + +#define UC_BLITTING_FUNCTIONS_3D (DFXL_BLIT | \ + DFXL_STRETCHBLIT | \ + DFXL_TEXTRIANGLES) + +#else + +#define UC_DRAWING_FLAGS_3D 0 +#define UC_BLITTING_FLAGS_3D 0 +#define UC_DRAWING_FUNCTIONS_3D 0 +#define UC_BLITTING_FUNCTIONS_3D 0 + +#endif // UC_ENABLE_3D + + +// Functions + +void uc_emit_commands ( void *drv, + void *dev ); + +void uc_flush_texture_cache( void *drv, + void *dev ); + +bool uc_fill_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_blit ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_fill_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line_3d ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_fill_triangle ( void *drv, + void *dev, + DFBTriangle *tri ); + +bool uc_blit_3d ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_stretch_blit ( void *drv, + void *dev, + DFBRectangle *srect, + DFBRectangle *drect ); + +bool uc_texture_triangles ( void *drv, + void *dev, + DFBVertex *vertices, + int num, + DFBTriangleFormation formation ); + +#endif // __UC_ACCEL_H__ + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c new file mode 100755 index 0000000..cc13433 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c @@ -0,0 +1,198 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include +#include + +#include + +#include "uc_fifo.h" + +//#define UC_FIFO_DUMP_DATA + +// Private functions --------------------------------------------------------- + +/** + * Pad the FIFO buffer to a 32 byte boundary. Used by uc_flush_agp(). + * @note Equivalent DRI code is in via_ioctl::viaFlushPrimsLocked() + */ + +static void uc_fifo_pad(struct uc_fifo* fifo) +{ + switch (fifo->used & 0x7) + { + case 0: + break; + case 2: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 4: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 6: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + default: + break; + } +} + +/** + * Manually write the FIFO buffer to the hardware. + * @note Equivalent DRI code is in via_ioctl::flush_sys() + */ + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs) +{ + u32* p; + u32* q; + + volatile u32* hwregs = regs; + volatile u32* reg_tset = regs + VIA_REG_TRANSET; + volatile u32* reg_tspace = regs + VIA_REG_TRANSPACE; + + int check2Dcmd; + u32 addr; + + p = fifo->buf; + q = fifo->head; + check2Dcmd = 0; + + uc_fifo_pad(fifo); + +#ifdef UC_FIFO_DUMP_DATA + printf("Flushing FIFO ... \n"); +#endif + + while (p != q) { + + if (*p == HALCYON_HEADER2) { + p++; + check2Dcmd = !(*p == HALCYON_SUB_ADDR0); +#ifdef UC_FIFO_DUMP_DATA + printf("tset = 0x%08x\n", *p); +#endif + *reg_tset = *p; + p++; + } + else if (check2Dcmd && ((*p & HALCYON_HEADER1MASK) == HALCYON_HEADER1)) { + addr = (*p) & 0x0000001f; + p++; +#ifdef UC_FIFO_DUMP_DATA + printf("2D (0x%02x) = 0x%x\n", addr << 2, *p); +#endif + *(hwregs + addr) = *p; + p++; + } + else if ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD) { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + + if ((p != q) && ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD)) + p++; + + if ((*p & HALCYON_CMDBMASK) != HC_ACMD_HCmdB) + check2Dcmd = 1; + } + else { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + } + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} + +/** Use an AGP transfer to write the FIFO buffer to the hardware. Not implemented. */ +#if 0 +static void uc_fifo_flush_agp(struct uc_fifo* fifo) +{ + // TODO - however, there is no point in doing this, because + // an AGP transfer can require more register writes than + // needed for drawing a single primitive. DirectFB needs to + // adopt a begin/end architecture first, like OpenGL has. + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} +#endif + +// Public functions ---------------------------------------------------------- + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create(FusionSHMPoolShared *pool, size_t size) +{ + struct uc_fifo* fifo; + + size += 32; // Needed for padding. + + fifo = SHCALLOC(pool, 1, sizeof(struct uc_fifo)); + if (!fifo) return NULL; + + // Note: malloc won't work for DMA buffers... + + fifo->buf = SHMALLOC(pool, sizeof(u32) * size); + if (!(fifo->buf)) { + SHFREE(pool, fifo); + return NULL; + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->size = (unsigned int) size; + fifo->prep = 0; + + //fifo->flush_sys = uc_fifo_flush_sys; + + //fifo->flush = uc_fifo_flush_sys; + + return fifo; +} + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo) +{ + if (fifo) { + if (fifo->buf) { + SHFREE(pool, fifo->buf); + fifo->buf = NULL; + } + SHFREE(pool, fifo); + } +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h new file mode 100755 index 0000000..c7e2fe3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h @@ -0,0 +1,268 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_FIFO_H__ +#define __UC_FIFO_H__ + +// Note to self: remove when added to makefile as -DUC_DEBUG. +#define UC_DEBUG 1 + +#include + +#include "regs2d.h" +#include "regs3d.h" +#include "mmio.h" + +/** + * uc_fifo - GPU data queue. + * + * buf: buffer start (userspace address) + * head: pointer to first unused entry. + * + * size: maximum number of entries in the fifo. + * prep: number of entries allocated to be used. + * used: number of entries currently in use. + * + * hwregs: GPU register base address + * reg_tset: address to GPU TRANSET register + * reg_tspace: address to GPU TRANSPACE register + * + * flush: function pointer to flush function (DMA or CPU) + * flush_sys: function pointer to flush_sys (non-DMA) function + */ + +struct uc_fifo +{ + u32* buf; + u32* head; + + unsigned int size; + unsigned int prep; + unsigned int used; + + //void (*flush)(struct uc_fifo* fifo, volatile void *hwregs); + //void (*flush_sys)(struct uc_fifo* fifo, volatile void *hwregs); +}; + +// Help macros --------------------------------------------------------------- + +// For the record: Macros suck maintenance- and debugging-wise, +// but provide guaranteed inlining of the code. + +/** + * Send the contents of the FIFO buffer to the hardware, and clear + * the buffer. The transfer may be performed by the CPU or by DMA. + */ + +//#define UC_FIFO_FLUSH(fifo) (fifo)->flush(fifo,ucdrv->hwregs) + +/** + * Same as UC_FIFO_FLUSH(), but always uses the CPU to transfer data. + */ + +//#define UC_FIFO_FLUSH_SYS(fifo) (fifo)->flush_sys(fifo,ucdrv->hwregs) + +#define UC_FIFO_FLUSH(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) +#define UC_FIFO_FLUSH_SYS(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) + +/** + * Make sure there is room for dwsize double words in the FIFO. + * If necessary, the FIFO is flushed first. + * + * @param fifo the fifo + * @param dwsize number of double words to allocate + * + * @note It is ok to request more space than you will actually + * be using. This is useful when you don't know exactly beforehand + * how many entries you need. + * + * @note equivalent DRI code is in via_ioctl.c::viaCheckDma() + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + D_DEBUG("CLE266: FIFO full - flushing it."); \ + UC_FIFO_FLUSH(fifo); \ + } \ + if (dwsize + (fifo)->prep + 32 > (fifo)->size) { \ + D_BUG("CLE266: FIFO too small for allocation."); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#else + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + UC_FIFO_FLUSH(fifo); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#endif // UC_FIFO_DEBUG + +/** + * Add a 32-bit data word to the FIFO. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD(fifo, data) \ + do { \ + *((fifo)->head) = (data); \ + (fifo)->head++; \ + (fifo)->used++; \ + } while(0) + +/** + * Add a command header. (HC_HEADER2 + parameter selection) + * Takes two entries in the fifo. + */ + +#define UC_FIFO_ADD_HDR(fifo, param) \ + do { \ + UC_FIFO_ADD(fifo, HC_HEADER2); \ + UC_FIFO_ADD(fifo, param); \ + } while(0); + +/** + * Add a floating point value to the FIFO. + * Non-floats (e.g integers) are converted first. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD_FLOAT(fifo, val) \ + do { \ + union {float f; u32 i;} v; \ + v.f = (float) (val); \ + UC_FIFO_ADD(fifo, v.i); \ + } while(0) + +/** + * Add a vertex on the form (x, y, color) to the FIFO. + * Takes three entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYC(fifo, x, y, color) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + } while(0) + +/** + * Add a vertex on the form (x, y, w, color, s, t) to the FIFO. + * Takes six entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYWCST(fifo, x, y, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYZWCST(fifo, x, y, z, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, z); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYCST(fifo, x, y, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + + +/** + * Add data specifically for the 2D controller, to the fifo. + * Takes two entries in the FIFO. + * + * @param reg 2D register index + * @param data 32-bit data to add + */ + +#define UC_FIFO_ADD_2D(fifo, reg, data) \ + do { \ + UC_FIFO_ADD(fifo, ((reg) >> 2) | HALCYON_HEADER1); \ + UC_FIFO_ADD(fifo, (data)); \ + } while (0) + +/** + * Add data specifically for a 3D controller register, to the fifo. + * Takes one entry in the FIFO. + * + * @param reg 3D register index (8 bit) + * @param data 24-bit data to add (make sure bits 24 - 31 are cleared!) + */ + +#define UC_FIFO_ADD_3D(fifo, reg, data) \ + UC_FIFO_ADD(fifo, ((reg) << 24) | (data)) + +/** + * Pad the FIFO to an even number of entries. + * Takes zero or one entries in the FIFO. + */ +#define UC_FIFO_PAD_EVEN(fifo) \ + if (fifo->used & 1) UC_FIFO_ADD(fifo, HC_DUMMY) + +/** + * Check for buffer overruns. + * Can be redefined to nothing in release builds. + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_CHECK(fifo) \ + do { \ + if ((fifo)->used > ((fifo)->size) - 32) { \ + D_BUG("CLE266: FIFO overrun."); \ + } \ + if ((fifo)->used > (fifo)->prep) { \ + D_BUG("CLE266: FIFO allocation error."); \ + } \ + } while(0) + +#else + +#define UC_FIFO_CHECK(fifo) do { } while(0) + +#endif // UC_DEBUG + + +// FIFO functions ------------------------------------------------------------ + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create(FusionSHMPoolShared *pool, size_t size); + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo); + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs); + +#endif // __UC_FIFO_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hw.h b/Source/DirectFB/gfxdrivers/cle266/uc_hw.h new file mode 100755 index 0000000..83e3085 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hw.h @@ -0,0 +1,93 @@ +// Shared header file for uc_hwmap.c and uc_hwset.c. + +#ifndef __UC_HW_H__ +#define __UC_HW_H__ + +#include + +#include + +#include "unichrome.h" +#include "uc_fifo.h" + +// GPU - mapping functions (uc_hwmap.c) + +/// Map a DirectFB destination surface pixel format to the hw. (3D) +static inline int uc_map_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HDBFM_ARGB1555; + case DSPF_RGB16: return HC_HDBFM_RGB565; + case DSPF_RGB32: return HC_HDBFM_ARGB0888; + case DSPF_ARGB: return HC_HDBFM_ARGB8888; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +/// Map a DirectFB source surface pixel format to the hw. (3D) +static inline int uc_map_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HTXnFM_ARGB1555; + case DSPF_RGB16: return HC_HTXnFM_RGB565; + case DSPF_RGB32: return HC_HTXnFM_ARGB0888; + case DSPF_ARGB: return HC_HTXnFM_ARGB8888; + case DSPF_A8: return HC_HTXnFM_A8; + case DSPF_LUT8: return HC_HTXnFM_Index8; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +void uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dformat ); + +void uc_map_blitflags ( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat ); + +// GPU - setting functions (uc_hwset.c) + +void uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_texenv ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_clip ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_3d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_color_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +#endif // __UC_HW_H__ + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c b/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c new file mode 100755 index 0000000..4c2d8a0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c @@ -0,0 +1,357 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware mapping functions ------------------------------------------------ + +#include + +#include "uc_hw.h" +#include + +/// Map DirectFB blending functions to hardware +void +uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dst_format ) +{ + bool dst_alpha = DFB_PIXELFORMAT_HAS_ALPHA(dst_format); + + // The HW's blending equation is: + // (Ca * FCa + Cbias + Cb * FCb) << Cshift + + // Set source blending function + + // Ca -- always from source color. + hwalpha->regHABLCsat = HC_HABLCsat_MASK | HC_HABLCa_OPC | HC_HABLCa_Csrc; + // Aa -- always from source alpha. + hwalpha->regHABLAsat = HC_HABLAsat_MASK | HC_HABLAa_OPA | HC_HABLAa_Asrc; + + // FCa and FAa depend on the following condition. + switch (sblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + break; + + case DSBF_SRCALPHASAT: + // GL_SRC_ALPHA_SATURATE + if (!dst_alpha) { + // (f, f, f, 1), f = min(As, 1 - Ad) = min(As, 1 - 1) = 0 + // So (f, f, f, 1) = (0, 0, 0, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { + // (f, f, f, 1), f = min(As, 1 - Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_mimAsrcInvAdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + break; + default: + D_BUG("Unsupported blending function!"); + break; + } + + // Set destination blending function + + // Op is add. + // bias is 0. + + hwalpha->regHABLCsat |= HC_HABLCbias_HABLRCbias; + hwalpha->regHABLAsat |= HC_HABLAbias_HABLRAbias; + + // Cb -- always from destination color. + hwalpha->regHABLCop = HC_HABLCb_OPC | HC_HABLCb_Cdst; + // Ab -- always from destination alpha. + hwalpha->regHABLAop = HC_HABLAb_OPA | HC_HABLAb_Adst; + + // FCb -- depends on the following condition. + switch (dblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_0; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + break; + + case DSBF_SRCALPHASAT: + // Unsupported? + + default: + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + } +} + +/// Map DFBSurfaceBlittingFlags to the hardware +void +uc_map_blitflags( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat ) +{ + bool gotalpha = DFB_PIXELFORMAT_HAS_ALPHA(sformat); + + if (bflags & DSBLIT_COLORIZE) { + // Cv0 = Ct*Cf + + // Hw setting: + // Ca = Ct, Cb = Cf, Cop = +, Cc = 0, Cbias = 0, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_Tex | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_Dif | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_0 | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + else { + // Cv0 = Ct + + // Hw setting: + // Ca = 0, Cb = 0, Cop = +, Cc = 0, Cbias = Ct, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_0 | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_0 | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_Tex | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + + if (bflags & DSBLIT_BLEND_COLORALPHA) { + if ((bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) { + // Av0 = At*Af + + // Hw setting: + // Aa = At, Ab = Af, Cop = +, Ac = 0, Abias = 0, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_Atex | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_Adif | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { + // (!(bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) || !gotalpha + // Av0 = Af + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = Af, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Adif | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } + else { // !(bflags & DSBLIT_BLEND_COLORALPHA) + if ((bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) { + // Av0 = At + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = At, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Atex | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { // !gotalpha + // Av0 = 1.0 + + // D_BUG warning: I'm guessing where values should go, + // and how big (0xff = 1.0 ?) it should be. + + // Hw setting: + // Aa = 1.0, Ab = 1.0, Cop = -, Ac = 1.0, Abias = 1.0, Ashift = No. + // => Av = Aa*(Ab-Ac) + Abias = 1*(1-1)+1 = 1 + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Inv | HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c b/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c new file mode 100755 index 0000000..8ba9d09 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c @@ -0,0 +1,419 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware setting functions ------------------------------------------------ + +#include + +#include "uc_hw.h" +#include +#include +#include + +/// Integer 2-logarithm, y = log2(x), where x and y are integers. +#define ILOG2(x,y) ILOG2_PORTABLE(x,y) + +#define ILOG2_PORTABLE(x,y) \ + do { \ + unsigned int i = 0; \ + y = x; \ + while (y != 0) { \ + i++; \ + y = y >> 1; \ + } \ + y = i-1; \ + } while (0) + +#define ILOG2_X86(x,y) // TODO - use BSR (bit scan reverse) instruction + +/// Set alpha blending function (3D) +void +uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_alpha *hwalpha = &ucdev->hwalpha; + + if (UC_IS_VALID( uc_blending_fn )) + return; + + uc_map_blending_fn( hwalpha, state->src_blend, state->dst_blend, + state->destination->config.format ); + + UC_FIFO_PREPARE( fifo, 14 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCsat, hwalpha->regHABLCsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCop, hwalpha->regHABLCop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAsat, hwalpha->regHABLAsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAop, hwalpha->regHABLAop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCa, hwalpha->regHABLRCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCa, hwalpha->regHABLRFCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCbias, hwalpha->regHABLRCbias ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCb, hwalpha->regHABLRCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCb, hwalpha->regHABLRFCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAa, hwalpha->regHABLRAa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAb, hwalpha->regHABLRAb ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_blending_fn ); +} + +/// Set texture environment (3D) +void +uc_set_texenv( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + if (UC_IS_VALID( uc_texenv )) + return; + + uc_map_blitflags( hwtex, state->blittingflags, state->source->config.format ); + + // Texture mapping method + hwtex->regHTXnTB = HC_HTXnFLSs_Linear | HC_HTXnFLTs_Linear | + HC_HTXnFLSe_Linear | HC_HTXnFLTe_Linear; + + hwtex->regHTXnMPMD = HC_HTXnMPMD_Sclamp | HC_HTXnMPMD_Tclamp; + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24) ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTB, hwtex->regHTXnTB ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnMPMD, hwtex->regHTXnMPMD ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCsat, hwtex->regHTXnTBLCsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCop, hwtex->regHTXnTBLCop_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLMPfog, hwtex->regHTXnTBLMPfog_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLAsat, hwtex->regHTXnTBLAsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRCb, hwtex->regHTXnTBLRCb_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRAa, hwtex->regHTXnTBLRAa_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRFog, hwtex->regHTXnTBLRFog_0 ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_texenv ); +} + +/// Set clipping rectangle (2D and 3D) +void +uc_set_clip( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (DFB_REGION_EQUAL( ucdev->clip, state->clip )) + return; + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + +#ifdef UC_ENABLE_3D + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipTB, + (RS12(state->clip.y1) << 12) | RS12(state->clip.y2+1) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipLR, + (RS12(state->clip.x1) << 12) | RS12(state->clip.x2+1) ); + +#endif + + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPTL, + (RS16(state->clip.y1) << 16) | RS16(state->clip.x1) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPBR, + (RS16(state->clip.y2) << 16) | RS16(state->clip.x2) ); + + UC_FIFO_CHECK( fifo ); + + ucdev->clip = state->clip; +} + +/// Set destination (2D and 3D) +void +uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + CoreSurface *destination = state->destination; + + DFBSurfacePixelFormat dst_format = destination->config.format; + int dst_offset = state->dst.offset; + int dst_pitch = state->dst.pitch; + int dst_bpp = DFB_BYTES_PER_PIXEL( dst_format ); + + + /* Save FIFO space and CPU cycles. */ + if (ucdev->dst_format == dst_format && + ucdev->dst_offset == dst_offset && + ucdev->dst_pitch == dst_pitch) + return; + + // 2D engine setting + + ucdev->pitch = (ucdev->pitch & 0x7fff) | (((dst_pitch >> 3) & 0x7fff) << 16); + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, (VIA_PITCH_ENABLE | ucdev->pitch) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, (dst_offset >> 3) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_GEMODE, (dst_bpp - 1) << 8 ); + +#ifdef UC_ENABLE_3D + // 3D engine setting + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasL, dst_offset & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasH, dst_offset >> 24 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBFM, (uc_map_dst_format( dst_format ) | + (dst_pitch & HC_HDBPit_MASK) | + HC_HDBLoc_Local) ); + + UC_FIFO_PAD_EVEN(fifo); +#endif + + UC_FIFO_CHECK( fifo ); + + ucdev->dst_format = dst_format; + ucdev->dst_offset = dst_offset; + ucdev->dst_pitch = dst_pitch; +} + +/// Set new source (2D) +void +uc_set_source_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_source2d )) + return; + + ucdev->pitch &= 0x7fff0000; + ucdev->pitch |= (state->src.pitch >> 3) & 0x7fff; + + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, state->src.offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, VIA_PITCH_ENABLE | ucdev->pitch ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_source2d ); +} + +/// Set new source (3D) +void +uc_set_source_3d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + CoreSurface *source = state->source; + + int src_height, src_offset, src_pitch; + + if (UC_IS_VALID( uc_source3d )) + return; + + src_height = source->config.size.h; + src_offset = state->src.offset; + src_pitch = state->src.pitch; + + /* + * TODO: Check if we can set the odd/even field as L1/L2 texture and select + * between L0/L1/L2 upon blit. Otherwise we depend on SMF_BLITTINGFLAGS ;( + */ + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + if (source->field) + src_offset += src_pitch; + + src_height >>= 1; + src_pitch <<= 1; + } + + ucdev->field = source->field; + + // Round texture size up to nearest + // value evenly divisible by 2^n + + ILOG2(source->config.size.w, hwtex->we); + hwtex->l2w = 1 << hwtex->we; + if (hwtex->l2w < source->config.size.w) { + hwtex->we++; + hwtex->l2w <<= 1; + } + + ILOG2(src_height, hwtex->he); + hwtex->l2h = 1 << hwtex->he; + if (hwtex->l2h < src_height) { + hwtex->he++; + hwtex->l2h <<= 1; + } + + hwtex->format = uc_map_src_format_3d( source->config.format ); + + UC_FIFO_PREPARE( fifo, 10); + + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24)); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnFM, HC_HTXnLoc_Local | hwtex->format ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0OS, (0 << HC_HTXnLVmax_SHIFT) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5WE, hwtex->we ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5HE, hwtex->he ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL012BasH, (src_offset >> 24) & 0xff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0BasL, (src_offset ) & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0Pit, (HC_HTXnEnPit_MASK | src_pitch) ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + // Upload the palette of a 256 color texture. + + if (hwtex->format == HC_HTXnFM_Index8) { + int i, num; + DFBColor *colors; + + UC_FIFO_PREPARE( fifo, 258 ); + + UC_FIFO_ADD_HDR( fifo, ((HC_ParaType_Palette << 16) | + (HC_SubType_TexPalette0 << 24)) ); + + colors = source->palette->entries; + num = source->palette->num_entries; + + if (num > 256) + num = 256; + + /* What about the last entry? -- dok */ + for (i = 0; i < num; i++) + UC_FIFO_ADD( fifo, PIXEL_ARGB(colors[i].a, colors[i].r, + colors[i].g, colors[i].b) ); + + for (; i < 256; i++) + UC_FIFO_ADD( fifo, 0 ); + + UC_FIFO_CHECK( fifo ); + } + + UC_VALIDATE( uc_source3d ); +} + +/// Set either destination color key, or fill color, as needed. (2D) +void +uc_set_color_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + u32 color = 0; + + if (UC_IS_VALID( uc_color2d )) + return; + + switch (state->destination->config.format) { + case DSPF_ARGB1555: + color = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + color |= color << 16; + break; + + case DSPF_RGB16: + color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b); + color |= color << 16; + break; + + case DSPF_RGB32: + case DSPF_ARGB: + color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + + default: + D_BUG( "unexpected pixel format" ); + } + + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + // Opaque line drawing needs this + UC_FIFO_ADD_2D( fifo, VIA_REG_MONOPAT0, 0xff ); + + UC_FIFO_ADD_2D( fifo, VIA_REG_KEYCONTROL, 0 ); + UC_FIFO_ADD_2D( fifo, VIA_REG_FGCOLOR, color ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_color2d ); + UC_INVALIDATE( uc_colorkey2d ); +} + +void +uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_colorkey2d )) + return; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, VIA_KEY_ENABLE_SRCKEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_BGCOLOR, state->src_colorkey ); + } + else if (state->blittingflags & DSBLIT_DST_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, + VIA_KEY_ENABLE_DSTKEY | VIA_KEY_INVERT_KEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_FGCOLOR, state->dst_colorkey ); + } + else { + UC_FIFO_PREPARE( fifo, 4 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, 0 ); + } + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_colorkey2d ); + UC_INVALIDATE( uc_color2d ); +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c new file mode 100755 index 0000000..2c50476 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c @@ -0,0 +1,320 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +#include + +#include + +#include + +// Forward declaration +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data); + + +static int uc_ovl_datasize( void ) +{ + return sizeof(UcOverlayData); +} + + +static DFBResult +uc_ovl_init_layer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + + // Set layer type, capabilities and name + + description->caps = UC_OVL_CAPS; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA CLE266 Video"); + + adjustment->flags = DCAF_NONE; + + // Fill out the default configuration + + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + + ucovl->v1.win.w = 720; + ucovl->v1.win.h = 576; + ucovl->v1.win.x = 0; + ucovl->v1.win.y = 0; + + config->width = 720; + config->height = 576; + + config->pixelformat = DSPF_YV12; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + // Reset overlay + + ucovl->extfifo_on = false; + ucovl->hwrev = ucdrv->hwrev; + ucovl->scrwidth = ucovl->v1.win.w; + + ucovl->v1.isenabled = false; + ucovl->v1.cfg = *config; + ucovl->v1.ox = 0; + ucovl->v1.oy = 0; + +// adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | +// DCAF_HUE | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + ucovl->v1.adj = *adjustment; + + uc_ovl_remove(layer, driver_data, layer_data, NULL); + + return DFB_OK; +} + + +static DFBResult +uc_ovl_set_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + + /* get new destination rectangle */ + DFBRectangle win = config->dest;; + + // Bounds checking + if ((win.x < -8192) || (win.x > 8192) || + (win.y < -8192) || (win.y > 8192) || + (win.w < 32) || (win.w > 4096) || + (win.h < 32) || (win.h > 4096)) + { + D_DEBUG("Layer size or position is out of bounds."); + return DFB_INVAREA; + } + + ucovl->v1.isenabled = true; + ucovl->v1.win = win; + + ucovl->deinterlace = config->options & DLOP_DEINTERLACING; + ucovl->surface = surface; + ucovl->lock = lock; + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_CHANGE, surface, lock); +} + + +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + volatile u8* vio = ucdrv->hwregs; + + ucovl->v1.isenabled = false; + + uc_ovl_vcmd_wait(vio); + + VIDEO_OUT(vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL(16,12,8)); + // VIDEO_OUT(vio, ALPHA_V3_FIFO_CONTROL, 0x0407181f); + + if (ucovl->hwrev == 0x10) { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0); + } + else { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); + } + + VIDEO_OUT(vio, HQV_CONTROL, VIDEO_IN(vio, HQV_CONTROL) & ~HQV_ENABLE); + VIDEO_OUT(vio, V1_CONTROL, VIDEO_IN(vio, V1_CONTROL) & ~V1_ENABLE); + // VIDEO_OUT(vio, V3_CONTROL, VIDEO_IN(vio, V3_CONTROL) & ~V3_ENABLE); + + VIDEO_OUT(vio, V_COMPOSE_MODE, + VIDEO_IN(vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + ucovl->surface = NULL; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_test_region(CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed) +{ + CoreLayerRegionConfigFlags fail = 0; + + // Check layer options + + if (config->options & ~UC_OVL_OPTIONS) + fail |= CLRCF_OPTIONS; + + // Check pixelformats + + switch (config->format) { + case DSPF_YUY2: + break; + case DSPF_UYVY: + fail |= CLRCF_FORMAT; // Nope... doesn't work. + break; + case DSPF_I420: + case DSPF_YV12: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + fail |= CLRCF_FORMAT; + } + + // Check width and height + + if (config->width > 4096 || config->width < 32) + fail |= CLRCF_WIDTH; + + if (config->height > 4096 || config->height < 32) + fail |= CLRCF_HEIGHT; + + if (failed) *failed = fail; + if (fail) return DFB_UNSUPPORTED; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_flip_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock) +{ + //printf("Entering %s ... \n", __PRETTY_FUNCTION__); + + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + DFBResult ret; + + if (((flags & DSFLIP_WAITFORSYNC) == DSFLIP_WAITFORSYNC) && + !dfb_config->pollvsync_after) + dfb_layer_wait_vsync( layer ); + + dfb_surface_flip(surface, false); + + ucovl->field = 0; + ucovl->lock = lock; + + ret = uc_ovl_update(ucdrv, ucovl, UC_OVL_FLIP, surface, lock); + if (ret) + return ret; + + if ((flags & DSFLIP_WAIT) && + (dfb_config->pollvsync_after || !(flags & DSFLIP_ONSYNC))) + dfb_layer_wait_vsync(layer); + + return DFB_OK; +} + +static DFBResult +uc_ovl_get_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int *level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + *level = ucovl->v1.level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (level == 0) return DFB_INVARG; + if (level > 0) { + // Enable underlay mode. + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(-1)); + } + else { + // Enable overlay mode (default) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, + uc_ovl_map_alpha(ucovl->v1.opacity)); + } + + ucovl->v1.level = level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_input_field( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + ucovl->field = field; + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_FIELD, ucovl->surface, ucovl->lock); +} + +DisplayLayerFuncs ucOverlayFuncs = { + .LayerDataSize = uc_ovl_datasize, + .InitLayer = uc_ovl_init_layer, + .SetRegion = uc_ovl_set_region, + .RemoveRegion = uc_ovl_remove, + .TestRegion = uc_ovl_test_region, + .FlipRegion = uc_ovl_flip_region, + .GetLevel = uc_ovl_get_level, + .SetLevel = uc_ovl_set_level, + .SetInputField = uc_ovl_set_input_field, + .SetColorAdjustment = uc_ovl_set_adjustment, +}; diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h new file mode 100755 index 0000000..e687980 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h @@ -0,0 +1,85 @@ +#ifndef __UC_OVERLAY_H__ +#define __UC_OVERLAY_H__ + +#define UC_OVL_CAPS (DLCAPS_SURFACE | DLCAPS_OPACITY | DLCAPS_SCREEN_LOCATION \ + | DLCAPS_DEINTERLACING | DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST \ + | DLCAPS_SATURATION | DLCAPS_HUE) +#define UC_OVL_OPTIONS (DLOP_DEINTERLACING) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) +#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ + (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) + +// Actions for uc_ovl_update() + +#define UC_OVL_FLIP 1 +#define UC_OVL_CHANGE 2 +#define UC_OVL_FIELD 4 + +/** Overlay layer data. */ +struct uc_ovl_vinfo { + bool isenabled; // True when visible + DFBRectangle win; // Layer screen rectangle. + DFBDisplayLayerConfig cfg; // Layer configuration + int ox, oy; // Top-left visible corner (the offset) + // in the source surface + u8 opacity; // Layer opacity + int level; // Position in the DirectFB layer stack + // < 0 = underlay mode, > 0 = overlay mode + DFBColorAdjustment adj; // Color adjustment (brightness etc) +}; + +typedef struct _UcOverlayData { + + // TODO: initialize the variables!!! + + u8 hwrev; // CLE266 revision + int scrwidth; // Current screen width + + bool extfifo_on; // True when we're using the extended fifo. + u8 mclk_save[3]; + + struct uc_ovl_vinfo v1; // Video overlay V1 + + bool deinterlace; + int field; + + CoreSurface *surface; + + CoreSurfaceBufferLock *lock; +} UcOverlayData; + + +// Video engine - mapping functions (uc_ovl_hwmap.c) + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini); +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount); +u32 uc_ovl_map_qwpitch(int falign, DFBSurfacePixelFormat format, int sw); +u32 uc_ovl_map_format(DFBSurfacePixelFormat format); +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, int* ox, int* oy); +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int x, int y, int w, int h, int pitch, int field, + u32* y_start, u32* u_start, u32* v_start); +u32 uc_ovl_map_alpha(int opacity); +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo); +u32 uc_ovl_map_fifo(u8 depth, u8 pre_thr, u8 thr); +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2); + +// Video engine - setting functions (uc_ovl_hwset.c) + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth); +void uc_ovl_vcmd_wait(volatile u8* vio); +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock); +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj); + +#endif // __UC_OVERLAY_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c new file mode 100755 index 0000000..890b9bc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c @@ -0,0 +1,560 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" +#include + +/** + * Map hw settings for vertical scaling. + * + * @param sh source height + * @param dh destination height + * @param zoom will hold vertical setting of zoom register. + * @param mini will hold vertical setting of mini register. + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomHeight() + */ + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini) +{ + u32 sh1, tmp, d; + bool zoom_ok = true; + + if (sh == dh) { // No zoom + // Do nothing + } + else if (sh < dh) { // Zoom in + + tmp = (sh * 0x0400) / dh; + zoom_ok = !(tmp > 0x3ff); + + *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + else { // sw > dh - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sh1 = sh; + for (d = 1; d < 5; d++) { + sh1 >>= 1; + if (sh1 <= dh) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + *mini |= ((d<<1)-1) << 16; // <= {1,3,5,7} << 16 + + // Add scaling + + if (sh1 < dh) { + tmp = (sh1 * 0x400) / dh; + *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + } + + return zoom_ok; +} + + +/** + * Map hw settings for horizontal scaling. + * + * @param sw source width + * @param dw destination width + * + * @param zoom will hold horizontal setting of zoom register. + * @param mini will hold horizontal setting of mini register. + * @param falign will hold fetch aligment + * @param dcount will hold display count + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() + */ +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount) +{ + u32 tmp, sw1, d; + int md; // Minify-divider + bool zoom_ok = true; + + md = 1; + *falign = 0; + + if (sw == dw) { // No zoom + // Do nothing + } + else if (sw < dw) { // Zoom in + + tmp = (sw * 0x0800) / dw; + zoom_ok = !(tmp > 0x7ff); + + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + *mini |= V1_X_INTERPOLY; + } + else { // sw > dw - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sw1 = sw; + for (d = 1; d < 5; d++) { + sw1 >>= 1; + if (sw1 <= dw) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + md = 1 << d; // <= {2,4,8,16} + *falign = ((md<<1)-1) & 0xf; // <= {3,7,15,15} + *mini |= V1_X_INTERPOLY; + *mini |= ((d<<1)-1) << 24; // <= {1,3,5,7} << 24 + + // Add scaling + + if (sw1 < dw) { + //CLE bug + //tmp = sw1*0x0800 / dw; + tmp = (sw1 - 2) * 0x0800 / dw; + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + } + } + + *dcount = sw - md; + + return zoom_ok; +} + + +/** + * @param falign fetch alignment + * @param format overlay pixel format + * @param sw source width + * + * @returns qword pitch register setting + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() + * @note Only call after uc_ovl_map_hzoom() + */ +u32 uc_ovl_map_qwpitch(int falign, DFBSurfacePixelFormat format, int sw) +{ + int fetch = 0; + + switch (format) { + case DSPF_YV12: + fetch = ALIGN_TO(sw, 32) >> 4; + break; + case DSPF_I420: + fetch = (ALIGN_TO(sw, 16) >> 4) + 1; + break; + case DSPF_UYVY: + case DSPF_YUY2: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case DSPF_RGB32: + case DSPF_ARGB: + fetch = (ALIGN_TO(sw << 2, 16) >> 4) + 1; + break; + default: + D_BUG("Unexpected pixelformat!"); + break; + } + + if (fetch < 4) fetch = 4; + + // Note: Unsure if alignment is needed or is in the way. + fetch = ALIGN_TO(fetch, falign + 1); + return fetch << 20; // V12_QWORD_PER_LINE +} + + +/** + * Map pixel format. + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() + */ +u32 uc_ovl_map_format(DFBSurfacePixelFormat format) +{ + switch (format) { + case DSPF_YV12: + case DSPF_I420: + return V1_COLORSPACE_SIGN | V1_YUV420; + case DSPF_UYVY: + case DSPF_YUY2: + return V1_COLORSPACE_SIGN | V1_YUV422; + case DSPF_ARGB1555: + return V1_RGB15; + case DSPF_RGB16: + return V1_RGB16; + case DSPF_RGB32: + case DSPF_ARGB: + return V1_RGB32; + default : + D_BUG("Unexpected pixelformat!"); + return V1_YUV422; + } +} + + +/** + * Map overlay window. + * + * @param scrw screen width (eg. 800) + * @param scrh screen height (eg. 600) + * @param win destination window + * @param sw source surface width + * @param sh source surface height + * + * @param win_start will hold window start register setting + * @param win_end will hold window end register setting + * + * @parm ox will hold new leftmost coordinate in source surface + * @parm oy will hold new topmost coordinate in source surface + */ +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, int* ox, int* oy) +{ + int x1, y1, x2, y2; + int x,y,dw,dh; // These help making the code readable... + + *ox = 0; + *oy = 0; + *win_start = 0; + *win_end = 0; + + x = win->x; + y = win->y; + dw = win->w; + dh = win->h; + + // For testing the clipping + //scrw -= 100; + //scrh -= 100; + + // Handle invisible case. + if ((x > scrw) || (y > scrh) || (x+dw < 0) || (y+dh < 0)) return; + + // Vertical clipping + + if ((y >= 0) && (y+dh < scrh)) { + // No clipping + y1 = y; + y2 = y+dh-1; + } + else if ((y < 0) && (y+dh < scrh)) { + // Top clip + y1 = 0; + y2 = y+dh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + } + else if ((y >= 0) && (y+dh >= scrh)) { + // Bottom clip + y1 = y; + y2 = scrh-1; + } + else { // if (y < 0) && (y+dh >= scrh) + // Top and bottom clip + y1 = 0; + y2 = scrh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + } + + // Horizontal clipping + + if ((x >= 0) && (x+dw < scrw)) { + // No clipping + x1 = x; + x2 = x+dw-1; + } + else if ((x < 0) && (x+dw < scrw)) { + // Left clip + x1 = 0; + x2 = x+dw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + } + else if ((x >= 0) && (x+dw >= scrw)) { + // Right clip + x1 = x; + x2 = scrw-1; + } + else { // if (x < 0) && (x+dw >= scrw) + // Left and right clip + x1 = 0; + x2 = scrw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + } + + *win_start = (x1 << 16) | y1; + *win_end = (x2 << 16) | y2; + + // For testing the clipping + //*win_start = ((x1+50) << 16) | (y1+50); + //*win_end = ((x2+50) << 16) | (y2+50); +} + + +/** + * Map overlay buffer address. + * + * @param format pixel format + * @param buf Framebuffer address of surface (0 = start of framebuffer) + * @param ox leftmost pixel to show (used when clipping, else set to zero) + * @param oy topmost pixel to show (used when clipping, else set to zero) + * @param w total surface width (does *not* depend on the x parameter) + * @param h total surface height (does *not* depend on the y parameter) + * @param pitch source surface pitch (bytes per pixel) + * + * @param y_start will hold start address of Y(UV) or RGB buffer + * @param u_start will hold start address of Cb buffer (planar modes only) + * @param v_start will hold start address of Cr buffer (planar modes only) + * + * @note Derived from VIA's V4L driver. See ddover.c, + * DDOver_GetSrcStartAddress() and DDOVer_GetYCbCrStartAddress() + */ +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int ox, int oy, int sw, int sh, int sp, int field, + u32* y_start, u32* u_start, u32* v_start) +{ + int swap_cb_cr = 0; + + u32 tmp; + u32 y_offset, uv_offset = 0; + + switch (format) { + + case DSPF_YUY2: + case DSPF_UYVY: + y_offset = ((oy * sp) + ((ox << 1) & ~15)); + break; + + case DSPF_YV12: + swap_cb_cr = 1; + case DSPF_I420: + y_offset = ((((oy & ~3) * sp) + ox) & ~31) ; + if (oy > 0) + uv_offset = (((((oy & ~3) >> 1) * sp) + ox) & ~31) >> 1; + else + uv_offset = y_offset >> 1; + break; + + case DSPF_ARGB1555: + case DSPF_RGB16: + y_offset = (oy * sp) + ((ox * 16) >> 3); + break; + + case DSPF_RGB32: + case DSPF_ARGB: + y_offset = (oy * sp) + ((ox * 32) >> 3); + break; + + default: + y_offset = 0; + uv_offset = 0; + D_BUG("Unexpected pixelformat!"); + } + + if (field) { + y_offset += sp; + uv_offset += sp >> 1; + } + + *y_start = buf + y_offset; + + if (u_start && v_start) { + *u_start = buf + sp * sh + uv_offset; + *v_start = buf + sp * sh + sp * (sh >> 2) + uv_offset; + + if (swap_cb_cr) { + tmp = *u_start; + *u_start = *v_start; + *v_start = tmp; + } + } +} + + +/** + * Map alpha mode and opacity. + * + * @param opacity Alpha opacity: 0 = transparent, 255 = opaque. + * -1 = Use alpha from underlying graphics. + * + * @returns alpha control register setting. + * + * @note: Unfortunately, if using alpha from underlying graphics, + * the video is opaque if alpha = 255 and transparent if = 0. + * The inverse would have made more sense ... + * + * @note: The hardware supports a separate alpha plane as well, + * but it is not implemented here. + * + * @note: Derived from ddmpeg.c, VIAAlphaWin() + */ + +u32 uc_ovl_map_alpha(int opacity) +{ + u32 ctrl = 0x00080000; // Not sure what this number is, supposedly + // it is the "expire number divided by 4". + + if (opacity > 255) opacity = 255; + + if (opacity < 0) { + ctrl |= ALPHA_WIN_BLENDING_GRAPHIC; + } + else { + opacity = opacity >> 4; // Throw away bits 0 - 3 + ctrl |= (opacity << 12) | ALPHA_WIN_BLENDING_CONSTANT; + } + + return ctrl; // V_ALPHA_CONTROL +} + +/** + * Calculate V1 control and fifo-control register values + * @param format pixel format + * @param sw source width + * @param hwrev CLE266 hardware revision + * @param extfifo_on set this true if the extended FIFO is enabled + * @param control will hold value for V1_CONTROL + * @param fifo will hold value for V1_FIFO_CONTROL + */ +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo) +{ + *control = V1_BOB_ENABLE | V1_ENABLE | uc_ovl_map_format(format); + + if (hwrev == 0x10) { + *control |= V1_EXPIRE_NUM_F; + } + else { + if (extfifo_on) { + *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; + } + else { + *control |= V1_EXPIRE_NUM; + } + } + + if ((format == DSPF_YV12) || (format == DSPF_I420)) { + //Minified video will be skewed without this workaround. + if (sw <= 80) { //Fetch count <= 5 + *fifo = UC_MAP_V1_FIFO_CONTROL(16,0,0); + } + else { + if (hwrev == 0x10) + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(16,12,8); + } + } + else { + if (hwrev == 0x10) { + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); // Default rev 0x10 + } + else { + if (extfifo_on) + *fifo = UC_MAP_V1_FIFO_CONTROL(48,40,40); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(32,29,16); // Default + } + } +} + +/** uc_ovl_map_adjustment() helper - clamp x to [lo, hi] */ +static float clamp(float x, float lo, float hi) +{ + return (x < lo) ? lo : ((x > hi) ? hi : x); /* 2 nested if's. */ +} + +/** + * uc_ovl_map_adjustment() helper - format x for the hardware. + * + * @param x The value to format. + * @param ndec Number of binary decimals. + * @param sbit sign bit position. + * =0: use two's complement representation + * >0: use a sign bit + positive value. + * @param mask Bitmask + * @param shift Position in hardware register. + */ +static int fmt(float x, int ndec, int sbit, u32 mask, int shift) +{ + int y = (x * (1 << ndec)); + if (sbit && (y < 0)) y = -y | (1 << sbit); + return (((u32) y) & mask) << shift; +} + +/** + * Map color adjustment to CLE266 hardware. + * + * @param adj DirectFB color adjustment. All fields are assumed valid. + * @param a1 Will hold value for V1_ColorSpaceReg_1 + * @param a2 Will hold value for V1_ColorSpaceReg_2 + */ +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2) +{ + float con, sat, bri, hue; + float c, s; + float A, B1, C1, D, B2, C2, B3, C3; + + // Map contrast to [0, 2.0] (preferred: [0, 1.66]), default: 1.0. + con = (float) adj->contrast / 32768.0; + // Map saturation to [0, 2.0], default: 1.0. + sat = (float) adj->saturation / 32768.0; + // Map brightness to [-121, 125], (preferred: [-94, 125.1]), default: 3.97. + bri = (float) (adj->brightness - 31696) / 270.48; + // Map hue to [-pi, pi], default is 0.0. + hue = (float) (adj->hue - 32768) / 10430.378; + // Note: The limits are estimates that need testing. + + // Map parameters to hw registers. + + s = sin(hue) * con * sat; + c = cos(hue) * con * sat; + + A = clamp(1.164*con, 0, 1.9375); + B1 = clamp(-1.596*s, -0.75, 0.75); + C1 = clamp(1.596*c, 1, 2.875); + B2 = clamp( (0.813*s - 0.391*c), 0, -0.875); + C2 = clamp(-(0.813*c + 0.391*s), 0, -1.875); + B3 = clamp(2.018*c, 0, 3.75); + C3 = clamp(2.018*s, -1.25, 1.25); + D = clamp(1.164*(bri-16), -128, 127); + + *a1 = + fmt(A, 4, 0, 0x1f, 24) | fmt(B1, 2, 2, 0x07, 18) | + fmt(C1, 3, 0, 0x1f, 9) | fmt(D, 0, 0, 0xff, 0); + + *a2 = + fmt(B2, 3, 4, 0x7, 25) | fmt(C2, 3, 4, 0xf, 17) | + fmt(B3, 2, 0, 0xf, 10) | fmt(C3, 2, 3, 0xf, 2); +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c new file mode 100755 index 0000000..e8ba755 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c @@ -0,0 +1,266 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +#include + +#include + +/** + * Set up the extended video FIFO. + * @note It will be turned on if ucovl->scrwidth > 1024. + */ + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth) +{ + u8* mclk_save = ucovl->mclk_save; + + if (!iopl(3)) { + if (scrwidth <= 1024) { // Disable + if (ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + outb(0x16, 0x3c4); outb(mclk_save[0], 0x3c5); + outb(0x17, 0x3c4); outb(mclk_save[1], 0x3c5); + outb(0x18, 0x3c4); outb(mclk_save[2], 0x3c5); + ucovl->extfifo_on = false; + } + } + else { // Enable + if (!ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + // Save current setting + outb(0x16, 0x3c4); mclk_save[0] = inb(0x3c5); + outb(0x17, 0x3c4); mclk_save[1] = inb(0x3c5); + outb(0x18, 0x3c4); mclk_save[2] = inb(0x3c5); + // Enable extended FIFO + outb(0x17, 0x3c4); outb(0x2f, 0x3c5); + outb(0x16, 0x3c4); outb((mclk_save[0] & 0xf0) | 0x14, 0x3c5); + outb(0x18, 0x3c4); outb(0x56, 0x3c5); + ucovl->extfifo_on = true; + } + } + } + else { + printf("cle266: could set io perissons\n"); + } + ucovl->scrwidth = scrwidth; +} + +void uc_ovl_vcmd_wait(volatile u8* vio) +{ + while ((VIDEO_IN(vio, V_COMPOSE_MODE) + & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); +} + +/** + * Update the video overlay. + * + * @param action = UC_OVL_CHANGE: update everything + * = UC_OVL_FLIP: only flip to the front surface buffer. + * @param surface source surface + * + * @note: Derived from ddmpeg.c, Upd_Video() + */ + +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, + int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock) +{ + int sw, sh, sp, sfmt; // Source width, height, pitch and format + int dx, dy; // Destination position + int dw, dh; // Destination width and height + VideoMode *videomode; + DFBRectangle scr; // Screen size + + bool write_buffers = false; + bool write_settings = false; + + volatile u8* vio = ucdrv->hwregs; + + u32 win_start, win_end; // Overlay register settings + u32 zoom, mini; + u32 dcount, falign, qwpitch; + u32 y_start, u_start, v_start; + u32 v_ctrl, fifo_ctrl; + + int offset = lock->offset; + + + if (!ucovl->v1.isenabled) return DFB_OK; + + qwpitch = 0; + + // Get screen size + videomode = dfb_system_current_mode(); + scr.w = videomode ? videomode->xres : 720; + scr.h = videomode ? videomode->yres : 576; + scr.x = 0; + scr.y = 0; + + if (ucovl->scrwidth != scr.w) { + // FIXME: fix uc_ovl_setup_fifo() + // uc_ovl_setup_fifo(ucovl, scr.w); + action |= UC_OVL_CHANGE; + } + + D_ASSERT(surface); + + sw = surface->config.size.w; + sh = surface->config.size.h; + sp = lock->pitch; + sfmt = surface->config.format; + + if (ucovl->deinterlace) { + /*if (ucovl->field) + offset += sp;*/ + + sh /= 2; + //sp *= 2; + } + + if (action & UC_OVL_CHANGE) { + + if ((sw > 4096) || (sh > 4096) || + (sw < 32) || (sh < 1) || (sp > 0x1fff)) { + D_DEBUG("Layer surface size is out of bounds."); + return DFB_INVAREA; + } + + dx = ucovl->v1.win.x; + dy = ucovl->v1.win.y; + dw = ucovl->v1.win.w; + dh = ucovl->v1.win.h; + + // Get image format, FIFO size, etc. + + uc_ovl_map_v1_control(sfmt, sw, ucovl->hwrev, ucovl->extfifo_on, + &v_ctrl, &fifo_ctrl); + + if (ucovl->deinterlace) { + v_ctrl |= /*V1_BOB_ENABLE |*/ V1_FRAME_BASE; + } + + // Get layer window. + // The parts that fall outside the screen are clipped. + + uc_ovl_map_window(scr.w, scr.h, &(ucovl->v1.win), sw, sh, + &win_start, &win_end, &ucovl->v1.ox, &ucovl->v1.oy); + + // Get scaling and data-fetch parameters + + // Note: the *_map_?zoom() functions return false if the scaling + // is out of bounds. We don't act on it for now, because it only + // makes the display look strange. + + zoom = 0; + mini = 0; + + uc_ovl_map_vzoom(sh, dh, &zoom, &mini); + uc_ovl_map_hzoom(sw, dw, &zoom, &mini, &falign, &dcount); + qwpitch = uc_ovl_map_qwpitch(falign, sfmt, sw); + + write_settings = true; + } + + if (action & (UC_OVL_FIELD | UC_OVL_FLIP | UC_OVL_CHANGE)) { + int field = 0; + // Update the buffer pointers + + if (ucovl->deinterlace) { + field = ucovl->field; + } + + uc_ovl_map_buffer(sfmt, offset, + ucovl->v1.ox, ucovl->v1.oy, sw, surface->config.size.h, sp, 0/*field*/, &y_start, + &u_start, &v_start); + + if (field) { + y_start |= 0x08000000; + } + + write_buffers = true; + } + + // Write to the hardware + +/* if (write_settings || write_buffers) + uc_ovl_vcmd_wait(vio);*/ + + if (write_settings) { + + VIDEO_OUT(vio, V1_CONTROL, v_ctrl); + VIDEO_OUT(vio, V_FIFO_CONTROL, fifo_ctrl); + + VIDEO_OUT(vio, V1_WIN_START_Y, win_start); + VIDEO_OUT(vio, V1_WIN_END_Y, win_end); + + VIDEO_OUT(vio, V1_SOURCE_HEIGHT, (sh << 16) | dcount); + VIDEO_OUT(vio, V12_QWORD_PER_LINE, qwpitch); + VIDEO_OUT(vio, V1_STRIDE, sp | ((sp >> 1) << 16)); + + VIDEO_OUT(vio, V1_MINI_CONTROL, mini); + VIDEO_OUT(vio, V1_ZOOM_CONTROL, zoom); + } + + if (write_buffers) { + + VIDEO_OUT(vio, V1_STARTADDR_0, y_start); + VIDEO_OUT(vio, V1_STARTADDR_CB0, u_start); + VIDEO_OUT(vio, V1_STARTADDR_CR0, v_start); + } + + if (write_settings || write_buffers) { + VIDEO_OUT(vio, V_COMPOSE_MODE, V1_COMMAND_FIRE); + } + + return DFB_OK; +} + +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + DFBColorAdjustment* ucadj; + u32 a1, a2; + + ucadj = &ucovl->v1.adj; + + if (adj->flags & DCAF_BRIGHTNESS) + ucadj->brightness = adj->brightness; + if (adj->flags & DCAF_CONTRAST) + ucadj->contrast = adj->contrast; + if (adj->flags & DCAF_HUE) + ucadj->hue = adj->hue; + if (adj->flags & DCAF_SATURATION) + ucadj->saturation = adj->saturation; + + uc_ovl_map_adjustment(ucadj, &a1, &a2); + + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_1, a1); + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_2, a2); + + return DFB_OK; +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_primary.c b/Source/DirectFB/gfxdrivers/cle266/uc_primary.c new file mode 100755 index 0000000..d0d0fe9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_primary.c @@ -0,0 +1,176 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include + +#include + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +/* primary layer hooks */ + +#define OSD_OPTIONS (DLOP_ALPHACHANNEL | DLOP_SRC_COLORKEY | DLOP_OPACITY) + +DisplayLayerFuncs ucOldPrimaryFuncs; +void *ucOldPrimaryDriverData; + +static DFBResult +osdInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + DFBResult ret; + + /* call the original initialization function first */ + ret = ucOldPrimaryFuncs.InitLayer( layer, + ucOldPrimaryDriverData, + layer_data, description, + config, adjustment ); + if (ret) + return ret; + + /* set name */ + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA CLE266 Graphics"); + + /* add support for options */ + config->flags |= DLCONF_OPTIONS; + + config->pixelformat = dfb_config->mode.format ? + dfb_config->mode.format : DSPF_ARGB; + config->options = DLOP_ALPHACHANNEL; + + /* add some capabilities */ + description->caps |= DLCAPS_ALPHACHANNEL | + DLCAPS_OPACITY | DLCAPS_SRC_COLORKEY; + + return DFB_OK; +} + +static DFBResult +osdTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + DFBResult ret; + CoreLayerRegionConfigFlags fail = 0; + DFBDisplayLayerOptions options = config->options; + + /* remove options before calling the original function */ + config->options = DLOP_NONE; + + /* call the original function */ + ret = ucOldPrimaryFuncs.TestRegion( layer, ucOldPrimaryDriverData, + layer_data, config, &fail ); + + /* check options if specified */ + if (options) { + /* any unsupported option wanted? */ + if (options & ~OSD_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* opacity and alpha channel cannot be used at once */ + if ((options & (DLOP_OPACITY | DLOP_ALPHACHANNEL)) == + (DLOP_OPACITY | DLOP_ALPHACHANNEL)) + { + fail |= CLRCF_OPTIONS; + } + } + + /* restore options */ + config->options = options; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return ret; +} + +static DFBResult +osdSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + /* call the original function */ + ret = ucOldPrimaryFuncs.SetRegion( layer, ucOldPrimaryDriverData, + layer_data, region_data, + config, updated, surface, + palette, lock ); + if (ret) + return ret; + + uc_ovl_vcmd_wait(ucdrv->hwregs); + + /* select pixel based or global alpha */ + + if (config->options & DLOP_ALPHACHANNEL) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(-1)); + else if (config->options & DLOP_OPACITY) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(config->opacity)); + else + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(0xff)); + + VIDEO_OUT(ucdrv->hwregs, V_COMPOSE_MODE, V1_COMMAND_FIRE); + + return DFB_OK; +} + +DisplayLayerFuncs ucPrimaryFuncs = { + .InitLayer = osdInitLayer, + + .TestRegion = osdTestRegion, + .SetRegion = osdSetRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_state.c b/Source/DirectFB/gfxdrivers/cle266/uc_state.c new file mode 100755 index 0000000..7ac74e9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_state.c @@ -0,0 +1,269 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_hw.h" + +enum uc_state_type { + UC_TYPE_UNSUPPORTED, + UC_TYPE_2D, + UC_TYPE_3D +}; + +/// GPU selecting functions -------------------------------------------------- + +static inline bool +uc_has_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_has_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + case DSPF_LUT8: + return true; + + default: + break; + } + + return false; +} + +static inline enum uc_state_type +uc_select_drawtype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_2D) && + !(accel & DFXL_FILLTRIANGLE)) + return UC_TYPE_2D; + + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_3D)) + return UC_TYPE_3D; + + return UC_TYPE_UNSUPPORTED; +} + +static inline enum uc_state_type +uc_select_blittype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_2D)) { + if ((state->source->config.format == state->destination->config.format) && + !((state->blittingflags & DSBLIT_SRC_COLORKEY) && + (state->blittingflags & DSBLIT_DST_COLORKEY)) && + !(accel & (DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES))) + return UC_TYPE_2D; + } + + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_3D)) { + if (uc_has_src_format_3d( state->source->config.format )) + return UC_TYPE_3D; + } + + return UC_TYPE_UNSUPPORTED; +} + +// DirectFB interfacing functions -------------------------------------------- + +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel) +{ + /* Check destination format. */ + if (!uc_has_dst_format( state->destination->config.format )) + return; + + if (DFB_DRAWING_FUNCTION(accel)) { + /* Check drawing parameters. */ + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + state->accel |= UC_DRAWING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + state->accel |= UC_DRAWING_FUNCTIONS_3D; + break; + default: + return; + } + } + else { + /* Check blitting parameters. */ + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + state->accel |= UC_BLITTING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + state->accel |= UC_BLITTING_FUNCTIONS_3D; + break; + default: + return; + } + } +} + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel) +{ + UcDriverData *ucdrv = (UcDriverData*) drv; + UcDeviceData *ucdev = (UcDeviceData*) dev; + struct uc_fifo *fifo = ucdrv->fifo; + + u32 rop3d = HC_HROP_P; + u32 regEnable = HC_HenCW_MASK | HC_HenAW_MASK; + + StateModificationFlags modified = state->mod_hw; + + // Check modified states and update hw + + if (modified & SMF_SOURCE) + UC_INVALIDATE( uc_source2d ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SOURCE)) + UC_INVALIDATE( uc_source3d | uc_texenv ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SRC_COLORKEY | SMF_DST_COLORKEY)) + UC_INVALIDATE( uc_colorkey2d ); + + if (modified & (SMF_COLOR | SMF_DESTINATION | SMF_DRAWING_FLAGS)) + UC_INVALIDATE( uc_color2d ); + + if (modified & (SMF_SRC_BLEND | SMF_DST_BLEND)) + UC_INVALIDATE( uc_blending_fn ); + + + if (modified & SMF_COLOR) + ucdev->color3d = PIXEL_ARGB( state->color.a, state->color.r, + state->color.g, state->color.b ); + + if (modified & SMF_DRAWING_FLAGS) { + if (state->drawingflags & DSDRAW_XOR) { + ucdev->draw_rop3d = HC_HROP_DPx; + ucdev->draw_rop2d = VIA_ROP_DPx; + } + else { + ucdev->draw_rop3d = HC_HROP_P; + ucdev->draw_rop2d = VIA_ROP_P; + } + } + + ucdev->bflags = state->blittingflags; + + if (modified & SMF_DESTINATION) + uc_set_destination(ucdrv, ucdev, state); + + if (modified & SMF_CLIP) + uc_set_clip(ucdrv, ucdev, state); + + + // Select GPU and check remaining states + + if (DFB_DRAWING_FUNCTION(accel)) { + + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + + uc_set_color_2d(ucdrv, ucdev, state); + + state->set = UC_DRAWING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->FillRectangle = uc_fill_rectangle_3d; + funcs->DrawRectangle = uc_draw_rectangle_3d; + funcs->DrawLine = uc_draw_line_3d; + + if (state->drawingflags & DSDRAW_BLEND) { + uc_set_blending_fn(ucdrv, ucdev, state); + regEnable |= HC_HenABL_MASK; + } + + rop3d = ucdev->draw_rop3d; + + state->set = UC_DRAWING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported drawing function!"); + break; + } + } + else { // DFB_BLITTING_FUNCTION(accel) + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + uc_set_source_2d(ucdrv, ucdev, state); + funcs->Blit = uc_blit; + + uc_set_colorkey_2d(ucdrv, ucdev, state); + state->set = UC_BLITTING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->Blit = uc_blit_3d; + uc_set_source_3d(ucdrv, ucdev, state); + uc_set_texenv(ucdrv, ucdev, state); + uc_set_blending_fn(ucdrv, ucdev, state); + + regEnable |= HC_HenTXMP_MASK | HC_HenTXCH_MASK | HC_HenTXPP_MASK | HC_HenDT_MASK; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_BLEND_COLORALPHA)) + regEnable |= HC_HenABL_MASK; + + state->set = UC_BLITTING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported drawing function!"); + break; + } + } + +#ifdef UC_ENABLE_3D + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + /* Don't know what this does. DRI code always clears it. */ + UC_FIFO_ADD_3D ( fifo, HC_SubA_HPixGC, 0 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HEnable, regEnable ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HFBBMSKL, 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HROP, rop3d | 0xff ); +#endif + + UC_FIFO_CHECK(fifo); + + state->mod_hw = 0; +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_state.h b/Source/DirectFB/gfxdrivers/cle266/uc_state.h new file mode 100755 index 0000000..a3e7484 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_state.h @@ -0,0 +1,68 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_STATE__ +#define __UC_STATE__ + +#include +#include +#include + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel); +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel); + + + +/* +struct uc_hw_misc +{ + // These control clipping... + + u32 regHClipTB; + u32 regHClipLR; + u32 regHFPClipTL; + u32 regHFPClipBL; + u32 regHFPClipLL; + u32 regHFPClipRL; + u32 regHFPClipTBH; + u32 regHFPClipLRH; + + // Other functions + + u32 regHLP; // Line stipple pattern + u32 regHLPRF; // Line stipple factor + u32 regHSolidCL; // --- Don't know. Unused in DRI. + u32 regHPixGC; // Don't know. Is kept cleared in DRI. + //u32 regHSPXYOS; // Polygon stipple x and y offsets. Unused here. + u32 regHVertexCNT; // --- Don't know. Unused in DRI. + + u8 ps_xos; // Polygon stipple x-offset. => regHSPXYOS + u8 ps_yos; // Polygon stipple y-offset. => regHSPXYOS + u32 ps_pat[32]; // Polygon stipple pattern buffer. + // These are not registers... +}; + + +/// Stencil control. + +struct uc_hw_stencil +{ + //u32 regHSBBasL; // These aren't in regs3d.h, but they should exist... + //u32 regHSBBasH; + //u32 regHSBFM; + + u32 regHSTREF; // Stencil reference value and plane mask + u32 regHSTMD; // Stencil test function and fail operation and + // zpass/zfail operations. +}; +*/ + +#endif // __UC_STATE__ diff --git a/Source/DirectFB/gfxdrivers/cle266/unichrome.c b/Source/DirectFB/gfxdrivers/cle266/unichrome.c new file mode 100755 index 0000000..7dbb8bc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/unichrome.c @@ -0,0 +1,548 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + + +/* + +EPIA-M benchmarks (df_dok) + + SW v0.0.1 v0.1.0 v0.2.0 v0.3 + +Anti-aliased Text 98.97 - - - 280.80 KChars/sec +Anti-aliased Text (blend) 28.85 - - - 280.61 KChars/sec +Fill Rectangles 25.21 443.46 437.05 432.39 435.60 Mpixel/sec +Fill Rectangles (blend) 5.54 - 130.12 128.42 127.82 MPixel/sec +Fill Triangles 24.84 173.44 129.76 127.86 128.63 MPixel/sec +Fill Triangles (blend) 5.46 - 129.81 127.86 128.67 MPixel/sec +Draw Rectangles 11.82 58.98 59.07 52.48 55.10 KRects/sec +Draw Rectangles (blend) 1.98 - 32.13 22.76 23.50 KRects/sec +Draw Lines 42.67 283.81 292.33 193.87 203.20 KLines/sec +Draw Lines (blend) 8.54 - 142.62 101.23 102.80 KLines/sec +Blit 21.48 - 117.38 114.26 114.41 MPixel/sec +Blit colorkeyed 22.54 - 117.34 114.26 114.41 MPixel/sec +Blit w/ format conversion 16.22 - - 103.41 103.00 MPixel/sec +Blit from 32bit (blend) 4.19 - - 87.72 87.32 MPixel/sec +Blit from 8bit palette 11.02 - - 110.13 113.37 MPixel/sec +Blit from 8bit pal. (blend) 3.78 - - 110.20 113.40 MPixel/sec +Stretch Blit 23.19 - - 99.53 99.32 MPixel/sec +Stretch Blit colorkeyed 25.04 - - 5.00 38.00 MPixel/sec + + +Comparing M9000 and M10000 + +v0.2.0 M9000 M10000 + +Anti-aliased Text - - KChars/sec +Anti-aliased Text (blend) - - KChars/sec +Fill Rectangles 401.82 432.39 Mpixel/sec +Fill Rectangles (blend) 129.05 128.42 MPixel/sec +Fill Triangles 128.46 127.86 MPixel/sec +Fill Triangles (blend) 128.46 127.86 MPixel/sec +Draw Rectangles 55.51 52.48 KRects/sec +Draw Rectangles (blend) 26.90 22.76 KRects/sec +Draw Lines 225.00 193.87 KLines/sec +Draw Lines (blend) 121.29 101.23 KLines/sec +Blit 112.36 114.26 MPixel/sec +Blit colorkeyed 112.28 114.26 MPixel/sec +Blit w/ format conversion 103.92 103.41 MPixel/sec +Blit from 32bit (blend) 87.89 87.72 MPixel/sec +Blit from 8bit palette 110.56 110.13 MPixel/sec +Blit from 8bit pal. (blend) 110.56 110.20 MPixel/sec +Stretch Blit 108.67 99.53 MPixel/sec +Stretch Blit colorkeyed 4.79 5.00 MPixel/sec + + +v0.0.1 and v0.1.0 are tested on an EPIA-M9000, +later versions on an EPIA-M10000. + +*/ + +// DirectFB headers + +#include + +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +// System headers + +#include +#include +#include +#include +#include +#include +#include + +#include + +// Driver headers + +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "mmio.h" + +#ifndef FB_ACCEL_VIA_UNICHROME +#define FB_ACCEL_VIA_UNICHROME 77 +#endif + +extern DisplayLayerFuncs ucOverlayFuncs; +extern DisplayLayerFuncs ucPrimaryFuncs; + +extern DisplayLayerFuncs ucOldPrimaryFuncs; +extern void *ucOldPrimaryDriverData; + +DFB_GRAPHICS_DRIVER(cle266) + +//---------- + + +/** + * Dump beginning of virtual queue. + * Use it to check that the VQ actually is in use. */ +#if 0 +static void uc_dump_vq(UcDeviceData *ucdev) +{ + int i; + u8* vq; + + if (!ucdev->vq_start) return; + vq = dfb_system_video_memory_virtual(ucdev->vq_start); + + for (i = 0; i < 128; i++) { + printf("%02x ", *(vq+i)); + if ((i+1) % 16 == 0) printf("\n"); + } +} +#endif + +/** Allocate memory for the virtual queue. */ + +static DFBResult uc_alloc_vq(CoreGraphicsDevice *device, UcDeviceData *ucdev) +{ + if (ucdev->vq_start) return DFB_OK; + + ucdev->vq_size = 256*1024; // 256kb + ucdev->vq_start = dfb_gfxcard_reserve_memory( device, ucdev->vq_size ); + + if (!ucdev->vq_start) + return DFB_INIT; + + ucdev->vq_end = ucdev->vq_start + ucdev->vq_size - 1; + + // Debug: clear buffer + memset((void *) dfb_system_video_memory_virtual(ucdev->vq_start), + 0xcc, ucdev->vq_size); + + // uc_dump_vq(ucdev); + + return DFB_OK; +} + +/** + * Initialize the hardware. + * @param enable enable VQ if true (else disable it.) + */ + +static DFBResult uc_init_2d_engine(CoreGraphicsDevice *device, UcDeviceData *ucdev, UcDriverData *ucdrv, bool enable) +{ + DFBResult result = DFB_OK; + volatile u8* hwregs = ucdrv->hwregs; + + // Init 2D engine registers to reset 2D engine + + VIA_OUT(hwregs, 0x04, 0x0); + VIA_OUT(hwregs, 0x08, 0x0); + VIA_OUT(hwregs, 0x0c, 0x0); + VIA_OUT(hwregs, 0x10, 0x0); + VIA_OUT(hwregs, 0x14, 0x0); + VIA_OUT(hwregs, 0x18, 0x0); + VIA_OUT(hwregs, 0x1c, 0x0); + VIA_OUT(hwregs, 0x20, 0x0); + VIA_OUT(hwregs, 0x24, 0x0); + VIA_OUT(hwregs, 0x28, 0x0); + VIA_OUT(hwregs, 0x2c, 0x0); + VIA_OUT(hwregs, 0x30, 0x0); + VIA_OUT(hwregs, 0x34, 0x0); + VIA_OUT(hwregs, 0x38, 0x0); + VIA_OUT(hwregs, 0x3c, 0x0); + VIA_OUT(hwregs, 0x40, 0x0); + + // Init AGP and VQ registers + + VIA_OUT(hwregs, 0x43c, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00000000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + VIA_OUT(hwregs, 0x440, 0x7D000000); + + VIA_OUT(hwregs, 0x43c, 0xfe020000); + VIA_OUT(hwregs, 0x440, 0x00000000); + + if (enable) { + result = uc_alloc_vq(device,ucdev); + enable = (result == DFB_OK); + } + + if (enable) { // Enable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x080003fe); + VIA_OUT(hwregs, 0x440, 0x0a00027c); + VIA_OUT(hwregs, 0x440, 0x0b000260); + VIA_OUT(hwregs, 0x440, 0x0c000274); + VIA_OUT(hwregs, 0x440, 0x0d000264); + VIA_OUT(hwregs, 0x440, 0x0e000000); + VIA_OUT(hwregs, 0x440, 0x0f000020); + VIA_OUT(hwregs, 0x440, 0x1000027e); + VIA_OUT(hwregs, 0x440, 0x110002fe); + VIA_OUT(hwregs, 0x440, 0x200f0060); + + VIA_OUT(hwregs, 0x440, 0x00000006); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + + VIA_OUT(hwregs, 0x440, 0x52000000 | + ((ucdev->vq_start & 0xFF000000) >> 24) | + ((ucdev->vq_end & 0xFF000000) >> 16)); + VIA_OUT(hwregs, 0x440, 0x50000000 | (ucdev->vq_start & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x51000000 | (ucdev->vq_end & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x53000000 | (ucdev->vq_size >> 3)); + } + else { // Disable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x00000004); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + } + + return result; +} + +static void uc_init_3d_engine(volatile u8* hwregs, int hwrev, bool init_all) +{ + u32 i; + + if (init_all) { + + // Clear NotTex registers (?) + + VIA_OUT(hwregs, 0x43C, 0x00010000); + for (i = 0; i <= 0x7d; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear texture unit 0 (?) + + VIA_OUT(hwregs, 0x43C, 0x00020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear texture unit 1 (?) + + VIA_OUT(hwregs, 0x43C, 0x01020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear general texture settings (?) + + VIA_OUT(hwregs, 0x43C, 0xfe020000); + for (i = 0; i <= 0x03; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear palette settings (?) + + VIA_OUT(hwregs, 0x43C, 0x00030000); + for (i = 0; i <= 0xff; i++) + VIA_OUT(hwregs, 0x440, 0); + + VIA_OUT(hwregs, 0x43C, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x10000002); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + + VIA_OUT(hwregs, 0x43C, 0x00fe0000); + + if (hwrev >= 3) + VIA_OUT(hwregs, 0x440,0x40008c0f); + else + VIA_OUT(hwregs, 0x440,0x4000800f); + + VIA_OUT(hwregs, 0x440,0x44000000); + VIA_OUT(hwregs, 0x440,0x45080C04); + VIA_OUT(hwregs, 0x440,0x46800408); + VIA_OUT(hwregs, 0x440,0x50000000); + VIA_OUT(hwregs, 0x440,0x51000000); + VIA_OUT(hwregs, 0x440,0x52000000); + VIA_OUT(hwregs, 0x440,0x53000000); + + } + + VIA_OUT(hwregs, 0x43C,0x00fe0000); + VIA_OUT(hwregs, 0x440,0x08000001); + VIA_OUT(hwregs, 0x440,0x0A000183); + VIA_OUT(hwregs, 0x440,0x0B00019F); + VIA_OUT(hwregs, 0x440,0x0C00018B); + VIA_OUT(hwregs, 0x440,0x0D00019B); + VIA_OUT(hwregs, 0x440,0x0E000000); + VIA_OUT(hwregs, 0x440,0x0F000000); + VIA_OUT(hwregs, 0x440,0x10000000); + VIA_OUT(hwregs, 0x440,0x11000000); + VIA_OUT(hwregs, 0x440,0x20000000); +} + +/** */ + +static void uc_after_set_var(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + + VGA_OUT8(ucdrv->hwregs, 0x3c4, 0x1a); + // Clear bit 6 in extended VGA register 0x1a to prevent system lockup. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) & 0xbf); + // Set bit 2, it might make a difference. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) | 0x4); +} + +/** Wait until the engine is idle. */ + +static DFBResult uc_engine_sync(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + UcDeviceData* ucdev = (UcDeviceData*) dev; + + int loop = 0; + +/* printf("Entering uc_engine_sync(), status is 0x%08x\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS)); +*/ + + while ((VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & 0xfffeffff) != 0x00020000) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/VIA: Timeout waiting for idle engine!\n"); + break; + } + } + + /* printf("Leaving uc_engine_sync(), status is 0x%08x, " + "waiting for %d (0x%x) cycles.\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS), loop, loop); + */ + + ucdev->idle_waitcycles += loop; + ucdev->must_wait = 0; + + return DFB_OK; +} + + +// DirectFB interfacing functions -------------------------------------------- + +static int driver_probe(CoreGraphicsDevice *device) +{ + struct stat s; + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_VIA_UNICHROME: + return 1; + } + + return stat(UNICHROME_DEVICE, &s) + 1; +} + +static void driver_get_info(CoreGraphicsDevice* device, + GraphicsDriverInfo* info) +{ + // Fill in driver info structure. + + snprintf(info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "VIA UniChrome Driver"); + + snprintf(info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "-"); + + snprintf(info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org"); + + snprintf(info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL"); + + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (UcDriverData); + info->device_data_size = sizeof (UcDeviceData); +} + + +static DFBResult driver_init_driver(CoreGraphicsDevice* device, + GraphicsDeviceFuncs* funcs, + void* driver_data, + void* device_data, + CoreDFB *core) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + ucdrv->file = -1; + ucdrv->pool = dfb_core_shmpool( core ); + + ucdrv->hwregs = dfb_gfxcard_map_mmio( device, 0, 0 ); + if (!ucdrv->hwregs) { + int fd; + + fd = open(UNICHROME_DEVICE, O_RDWR | O_SYNC, 0); + if (fd < 0) { + D_ERROR("Could not access %s. " + "Is the cle266vgaio module installed?\n", UNICHROME_DEVICE); + return DFB_IO; + } + + ucdrv->file = fd; + + ucdrv->hwregs = mmap(NULL, 0x1000000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (ucdrv->hwregs == MAP_FAILED) + return DFB_IO; + } + + /* FIXME: this belongs to device_data! */ + ucdrv->fifo = uc_fifo_create(ucdrv->pool, UC_FIFO_SIZE); + if (!ucdrv->fifo) + return D_OOSHM(); + + uc_after_set_var(driver_data, device_data); + + ucdrv->hwrev = 3; // FIXME: Get the real hardware revision number!!! + + // Driver specific initialization + + funcs->CheckState = uc_check_state; + funcs->SetState = uc_set_state; + funcs->EngineSync = uc_engine_sync; + funcs->EmitCommands = uc_emit_commands; + funcs->FlushTextureCache = uc_flush_texture_cache; + funcs->AfterSetVar = uc_after_set_var; + + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + funcs->FillTriangle = uc_fill_triangle; + funcs->Blit = uc_blit; + funcs->StretchBlit = uc_stretch_blit; + funcs->TextureTriangles = uc_texture_triangles; + + + /* install primary layer hooks */ + if ( getenv("DFB_CLE266_UNDERLAY")) + dfb_layers_hook_primary( device, driver_data, &ucPrimaryFuncs, + &ucOldPrimaryFuncs, &ucOldPrimaryDriverData ); + + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &ucOverlayFuncs ); + + return DFB_OK; +} + +static DFBResult driver_init_device(CoreGraphicsDevice* device, + GraphicsDeviceInfo* device_info, + void* driver_data, + void* device_data) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + UcDeviceData *ucdev = (UcDeviceData*) device_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "UniChrome"); + snprintf(device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "VIA/S3G"); + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = + UC_DRAWING_FUNCTIONS_2D | UC_DRAWING_FUNCTIONS_3D | + UC_BLITTING_FUNCTIONS_2D | UC_BLITTING_FUNCTIONS_3D; + + device_info->caps.drawing = UC_DRAWING_FLAGS_2D | UC_DRAWING_FLAGS_3D; + device_info->caps.blitting = UC_BLITTING_FLAGS_2D | UC_BLITTING_FLAGS_3D; + + device_info->limits.surface_byteoffset_alignment = 32; + device_info->limits.surface_pixelpitch_alignment = 32; + + ucdev->pitch = 0; + ucdev->draw_rop2d = VIA_ROP_P; + ucdev->draw_rop3d = HC_HROP_P; + ucdev->color = 0; + ucdev->bflags = 0; + + ucdev->must_wait = 0; + ucdev->cmd_waitcycles = 0; + ucdev->idle_waitcycles = 0; + + uc_init_2d_engine(device, ucdev, ucdrv, false); // VQ disabled - can't make it work. + uc_init_3d_engine(ucdrv->hwregs, ucdrv->hwrev, 1); + + return DFB_OK; +} + +static void driver_close_device(CoreGraphicsDevice *device, + void *driver_data, void *device_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcDeviceData* ucdev = (UcDeviceData*) device_data; + + // uc_dump_vq(ucdev); + + uc_engine_sync(driver_data, device_data); + uc_init_2d_engine(device, ucdev, ucdrv, false); +} + +static void driver_close_driver(CoreGraphicsDevice* device, void* driver_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (ucdrv->fifo) + uc_fifo_destroy( ucdrv->pool, ucdrv->fifo ); + + if (ucdrv->file != -1) + close( ucdrv->file ); +} diff --git a/Source/DirectFB/gfxdrivers/cle266/unichrome.h b/Source/DirectFB/gfxdrivers/cle266/unichrome.h new file mode 100755 index 0000000..801216b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/unichrome.h @@ -0,0 +1,140 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UNICHROME_H__ +#define __UNICHROME_H__ + +#include +#include +#include +#include + +#include + +#define UNICHROME_DEVICE "/dev/cle266vgaio" +#define UC_FIFO_SIZE 4096 + +/** If defined - the driver will use the 3D engine. */ +#define UC_ENABLE_3D +//#undef UC_ENABLE_3D + + +/** Register settings for the current source surface. (3D) */ +struct uc_hw_texture { + DFBSurfaceBlittingFlags bltflags; + + u32 l2w; //width, rounded up to nearest 2^m, eg 600 => 1024 + u32 l2h; //height, rounded up, e.g 480 => 512 + u32 we; //width exponent, i.e m in the number 2^m + u32 he; //height exponent + + u32 format; // HW pixel format + + // 3d engine texture environment, texture unit 0 + + // Used for the DSBLIT_BLEND_ALPHACHANNEL, DSBLIT_BLEND_COLORALPHA + // and DSBLIT_COLORIZE blitting flags. + + u32 regHTXnTB; + u32 regHTXnMPMD; + + u32 regHTXnTBLCsat_0; + u32 regHTXnTBLCop_0; + u32 regHTXnTBLMPfog_0; + u32 regHTXnTBLAsat_0; + u32 regHTXnTBLRCb_0; + u32 regHTXnTBLRAa_0; + u32 regHTXnTBLRFog_0; +}; + + +/** Hardware source-destination blending registers. */ +struct uc_hw_alpha { +/* + u32 regHABBasL; // Alpha buffer, low 24 bits. + u32 regHABBasH; // Alpha buffer, high 8 bits. + u32 regHABFM; // Alpha pixel format, memory type and pitch. + u32 regHATMD; // Alpha test function and reference value. + + // Blending function +*/ + u32 regHABLCsat; + u32 regHABLCop; + u32 regHABLAsat; + u32 regHABLAop; + u32 regHABLRCa; + u32 regHABLRFCa; + u32 regHABLRCbias; + u32 regHABLRCb; + u32 regHABLRFCb; + u32 regHABLRAa; + u32 regHABLRAb; +}; + +typedef enum { + uc_source2d = 0x00000001, + uc_source3d = 0x00000002, + uc_texenv = 0x00000004, + uc_blending_fn = 0x00000008, + uc_color2d = 0x00000010, + uc_colorkey2d = 0x00000020 +} UcStateBits; + +#define UC_VALIDATE(b) (ucdev->valid |= (b)) +#define UC_INVALIDATE(b) (ucdev->valid &= ~(b)) +#define UC_IS_VALID(b) (ucdev->valid & (b)) + +typedef struct _UcDeviceData { + + /* State validation */ + UcStateBits valid; + + /* Current state settings */ + u32 pitch; // combined src/dst pitch (2D) + u32 color; // 2D fill color + u32 color3d; // color for 3D operations + u32 draw_rop2d; // logical drawing ROP (2D) + u32 draw_rop3d; // logical drawing ROP (3D) + + DFBSurfaceBlittingFlags bflags; // blitting flags + DFBRegion clip; // clipping region + + DFBSurfacePixelFormat dst_format; // destination pixel format + int dst_offset; // destination buffer byte offset + int dst_pitch; // destination buffer byte pitch + + int field; // source field + + /* Hardware settings */ + struct uc_hw_alpha hwalpha; // alpha blending setting (3D) + struct uc_hw_texture hwtex; // hardware settings for blitting (3D) + + + /// Set directly after a 2D/3D engine command is sent. + int must_wait; + unsigned int cmd_waitcycles; + unsigned int idle_waitcycles; + + u32 vq_start; // VQ related + u32 vq_size; + u32 vq_end; + +} UcDeviceData; + + +typedef struct _UcDriverData { + int file; // File handle to mmapped IO region. + int hwrev; // Hardware revision + volatile void* hwregs; // Hardware register base + struct uc_fifo* fifo; // Data FIFO. + FusionSHMPoolShared *pool; +} UcDriverData; + + +#endif // __UNICHROME_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/vidregs.h b/Source/DirectFB/gfxdrivers/cle266/vidregs.h new file mode 100755 index 0000000..5331fc1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/vidregs.h @@ -0,0 +1,498 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIDREGS_H__ +#define __VIDREGS_H__ + + +/* Video registers */ +#define V_FLAGS 0x00 +#define V_CAP_STATUS 0x04 +#define V_FLIP_STATUS 0x04 +#define V_ALPHA_WIN_START 0x08 +#define V_ALPHA_WIN_END 0x0C +#define V_ALPHA_CONTROL 0x10 +#define V_CRT_STARTADDR 0x14 +#define V_CRT_STARTADDR_2 0x18 +#define V_ALPHA_STRIDE 0x1C +#define V_COLOR_KEY 0x20 +#define V_ALPHA_STARTADDR 0x24 +#define V_CHROMAKEY_LOW 0x28 +#define V_CHROMAKEY_HIGH 0x2C + +#define V1_CONTROL 0x30 +#define V12_QWORD_PER_LINE 0x34 +#define V1_STARTADDR_1 0x38 +#define V1_STARTADDR_Y1 V1_STARTADDR_1 /* added by Kevin 3/30/2002 */ +#define V1_STRIDE 0x3C +#define V1_WIN_START_Y 0x40 +#define V1_WIN_START_X 0x42 +#define V1_WIN_END_Y 0x44 +#define V1_WIN_END_X 0x46 +#define V1_STARTADDR_2 0x48 +#define V1_STARTADDR_Y2 V1_STARTADDR_2 /* added by Kevin 3/30/2002 */ +#define V1_ZOOM_CONTROL 0x4C +#define V1_MINI_CONTROL 0x50 +#define V1_STARTADDR_0 0x54 +#define V1_STARTADDR_Y0 V1_STARTADDR_0 /* added by Kevin 3/30/2002 */ +#define V_FIFO_CONTROL 0x58 +#define V1_STARTADDR_3 0x5C +#define V1_STARTADDR_Y3 V1_STARTADDR_3 /* added by Kevin 3/30/2002 */ + +#define HI_CONTROL 0x60 +#define SND_COLOR_KEY 0x64 +#define ALPHA_V3_PREFIFO_CONTROL 0x68 +#define V1_SOURCE_HEIGHT 0x6C +#define HI_TRANSPARENT_COLOR 0x70 +#define V_DISPLAY_TEMP 0x74 /* No use */ +#define ALPHA_V3_FIFO_CONTROL 0x78 +#define V3_SOURCE_WIDTH 0x7C +#define V3_COLOR_KEY 0x80 +#define V1_ColorSpaceReg_1 0x84 +#define V1_ColorSpaceReg_2 0x88 +#define V1_STARTADDR_CB0 0x8C +#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ +#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ +#define V_COMPOSE_MODE 0x98 + +#define V3_STARTADDR_2 0x9C +#define V3_CONTROL 0xA0 +#define V3_STARTADDR_0 0xA4 +#define V3_STARTADDR_1 0xA8 +#define V3_STRIDE 0xAC +#define V3_WIN_START_Y 0xB0 +#define V3_WIN_START_X 0xB2 +#define V3_WIN_END_Y 0xB4 +#define V3_WIN_END_X 0xB6 +#define V3_ALPHA_QWORD_PER_LINE 0xB8 +#define V3_ZOOM_CONTROL 0xBC +#define V3_MINI_CONTROL 0xC0 +#define V3_ColorSpaceReg_1 0xC4 +#define V3_ColorSpaceReg_2 0xC8 +#define V3_DISPLAY_TEMP 0xCC /* No use */ + +#define V1_STARTADDR_CB1 0xE4 +#define V1_STARTADDR_CB2 0xE8 +#define V1_STARTADDR_CB3 0xEC +#define V1_STARTADDR_CR0 0xF0 +#define V1_STARTADDR_CR1 0xF4 +#define V1_STARTADDR_CR2 0xF8 +#define V1_STARTADDR_CR3 0xFC + +/* Video Capture Engine Registers - port 1 */ +#define CAP0_MASKS 0x100 +#define CAP1_MASKS 0x104 +#define CAP0_CONTROL 0x110 +#define CAP0_H_RANGE 0x114 +#define CAP0_V_RANGE 0x118 +#define CAP0_SCAL_CONTROL 0x11C +#define CAP0_VBI_H_RANGE 0x120 +#define CAP0_VBI_V_RANGE 0x124 +#define CAP0_VBI_STARTADDR 0x128 +#define CAP0_VBI_STRIDE 0x12C +#define CAP0_ANCIL_COUNT 0x130 +#define CAP0_MAXCOUNT 0x134 +#define CAP0_VBIMAX_COUNT 0x138 +#define CAP0_DATA_COUNT 0x13C +#define CAP0_FB_STARTADDR0 0x140 +#define CAP0_FB_STARTADDR1 0x144 +#define CAP0_FB_STARTADDR2 0x148 +#define CAP0_STRIDE 0x150 + +/* Video Capture Engine Registers - port 2 */ +#define CAP1_CONTROL 0x154 +#define CAP1_SCAL_CONTROL 0x160 +#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ +#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ +#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ +#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ +#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ +#define CAP1_MAXCOUNT 0x178 +#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ +#define CAP1_DATA_COUNT 0x180 +#define CAP1_FB_STARTADDR0 0x184 +#define CAP1_FB_STARTADDR1 0x188 +#define CAP1_STRIDE 0x18C + +/* SUBPICTURE Registers */ +#define SUBP_CONTROL_STRIDE 0x1C0 +#define SUBP_STARTADDR 0x1C4 +#define RAM_TABLE_CONTROL 0x1C8 +#define RAM_TABLE_READ 0x1CC + +/* HQV Registers */ +#define HQV_CONTROL 0x1D0 +#define HQV_SRC_STARTADDR_Y 0x1D4 +#define HQV_SRC_STARTADDR_U 0x1D8 +#define HQV_SRC_STARTADDR_V 0x1DC +#define HQV_SRC_FETCH_LINE 0x1E0 +#define HQV_FILTER_CONTROL 0x1E4 +#define HQV_MINIFY_CONTROL 0x1E8 +#define HQV_DST_STARTADDR0 0x1EC +#define HQV_DST_STARTADDR1 0x1F0 +#define HQV_DST_STARTADDR2 0x1FC +#define HQV_DST_STRIDE 0x1F4 +#define HQV_SRC_STRIDE 0x1F8 + + + +/* Video command definitions */ + +/* #define V_ALPHA_CONTROL - 0x210 */ +#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 +#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 +#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 +#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 +#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 +#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 +#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 +#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 +#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 + +/* V_CHROMAKEY_LOW - 0x228 */ +#define V_CHROMAKEY_V3 0x80000000 + +/* V1_CONTROL - 0x230 */ +#define V1_ENABLE 0x00000001 +#define V1_FULL_SCREEN 0x00000002 +#define V1_YUV422 0x00000000 +#define V1_RGB32 0x00000004 +#define V1_RGB15 0x00000008 +#define V1_RGB16 0x0000000C +#define V1_YUV420 0x00000010 +#define V1_COLORSPACE_SIGN 0x00000080 +#define V1_SRC_IS_FRAME_PIC 0x00000200 +#define V1_SRC_IS_FIELD_PIC 0x00000000 +#define V1_BOB_ENABLE 0x00400000 +#define V1_FIELD_BASE 0x00000000 +#define V1_FRAME_BASE 0x01000000 +#define V1_SWAP_SW 0x00000000 +#define V1_SWAP_HW_HQV 0x02000000 +#define V1_SWAP_HW_CAPTURE 0x04000000 +#define V1_SWAP_HW_MC 0x06000000 +/* #define V1_DOUBLE_BUFFERS 0x00000000 */ +/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ +#define V1_EXPIRE_NUM 0x00050000 +#define V1_EXPIRE_NUM_A 0x000a0000 +#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ +#define V1_FIFO_EXTENDED 0x00200000 +#define V1_ON_CRT 0x00000000 +#define V1_ON_SND_DISPLAY 0x80000000 +#define V1_FIFO_32V1_32V2 0x00000000 +#define V1_FIFO_48V1_32V2 0x00200000 + +/* V12_QWORD_PER_LINE - 0x234 */ +#define V1_FETCH_COUNT 0x3ff00000 +#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f +#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ + +/* V1_STRIDE */ +#define V1_STRIDE_YMASK 0x00001fff +#define V1_STRIDE_UVMASK 0x1ff00000 + +/* V1_ZOOM_CONTROL - 0x24C */ +#define V1_X_ZOOM_ENABLE 0x80000000 +#define V1_Y_ZOOM_ENABLE 0x00008000 + +/* V1_MINI_CONTROL - 0x250 */ +#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V1_X_DIV_2 0x01000000 +#define V1_X_DIV_4 0x03000000 +#define V1_X_DIV_8 0x05000000 +#define V1_X_DIV_16 0x07000000 +#define V1_Y_DIV_2 0x00010000 +#define V1_Y_DIV_4 0x00030000 +#define V1_Y_DIV_8 0x00050000 +#define V1_Y_DIV_16 0x00070000 + +/* V1_STARTADDR0 - 0x254 */ +#define SW_FLIP_ODD 0x08000000 + +/* V_FIFO_CONTROL - 0x258 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V1_FIFO_DEPTH12 0x0000000B +#define V1_FIFO_DEPTH16 0x0000000F +#define V1_FIFO_DEPTH32 0x0000001F +#define V1_FIFO_DEPTH48 0x0000002F +#define V1_FIFO_DEPTH64 0x0000003F +#define V1_FIFO_THRESHOLD6 0x00000600 +#define V1_FIFO_THRESHOLD8 0x00000800 +#define V1_FIFO_THRESHOLD12 0x00000C00 +#define V1_FIFO_THRESHOLD16 0x00001000 +#define V1_FIFO_THRESHOLD24 0x00001800 +#define V1_FIFO_THRESHOLD32 0x00002000 +#define V1_FIFO_THRESHOLD40 0x00002800 +#define V1_FIFO_THRESHOLD48 0x00003000 +#define V1_FIFO_THRESHOLD56 0x00003800 +#define V1_FIFO_THRESHOLD61 0x00003D00 +#define V1_FIFO_PRETHRESHOLD10 0x0A000000 +#define V1_FIFO_PRETHRESHOLD12 0x0C000000 +#define V1_FIFO_PRETHRESHOLD29 0x1d000000 +#define V1_FIFO_PRETHRESHOLD40 0x28000000 +#define V1_FIFO_PRETHRESHOLD44 0x2c000000 +#define V1_FIFO_PRETHRESHOLD56 0x38000000 +#define V1_FIFO_PRETHRESHOLD61 0x3D000000 + +/* ALPHA_V3_FIFO_CONTROL - 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * 8 level FIFO for ALPHA + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V3_FIFO_DEPTH16 0x0000000F +#define V3_FIFO_DEPTH24 0x00000017 +#define V3_FIFO_DEPTH32 0x0000001F +#define V3_FIFO_DEPTH48 0x0000002F +#define V3_FIFO_DEPTH64 0x0000003F +#define V3_FIFO_THRESHOLD8 0x00000800 +#define V3_FIFO_THRESHOLD12 0x00000C00 +#define V3_FIFO_THRESHOLD16 0x00001000 +#define V3_FIFO_THRESHOLD24 0x00001800 +#define V3_FIFO_THRESHOLD32 0x00002000 +#define V3_FIFO_THRESHOLD40 0x00002800 +#define V3_FIFO_THRESHOLD48 0x00003000 +#define V3_FIFO_THRESHOLD61 0x00003D00 +#define V3_FIFO_PRETHRESHOLD10 0x0000000A +#define V3_FIFO_PRETHRESHOLD12 0x0000000C +#define V3_FIFO_PRETHRESHOLD29 0x0000001d +#define V3_FIFO_PRETHRESHOLD40 0x00000028 +#define V3_FIFO_PRETHRESHOLD44 0x0000002c +#define V3_FIFO_PRETHRESHOLD56 0x00000038 +#define V3_FIFO_PRETHRESHOLD61 0x0000003D +#define V3_FIFO_MASK 0x0000007F +#define ALPHA_FIFO_DEPTH8 0x00070000 +#define ALPHA_FIFO_THRESHOLD4 0x04000000 +#define ALPHA_FIFO_MASK 0xffff0000 +#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 + +/* IA2 */ +#define ColorSpaceValue_1 0x140020f2 +#define ColorSpaceValue_2 0x0a0a2c00 + +#define ColorSpaceValue_1_3123C0 0x13000DED +#define ColorSpaceValue_2_3123C0 0x13171000 + +/* For TV setting */ +#define ColorSpaceValue_1TV 0x140020f2 +#define ColorSpaceValue_2TV 0x0a0a2c00 + +/* V_COMPOSE_MODE - 0x298 */ +#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ +#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ +#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ +#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ +#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ +#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ +#define COMPOSE_V1_TOP 0x00000000 +#define COMPOSE_V3_TOP 0x00100000 +#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ +#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ +#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ +#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ +#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ +#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ +#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 + +/* V3_ZOOM_CONTROL - 0x2bc */ +#define V3_X_ZOOM_ENABLE 0x80000000 +#define V3_Y_ZOOM_ENABLE 0x00008000 + +/* V3_MINI_CONTROL - 0x2c0 */ +#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V3_X_DIV_2 0x01000000 +#define V3_X_DIV_4 0x03000000 +#define V3_X_DIV_8 0x05000000 +#define V3_X_DIV_16 0x07000000 +#define V3_Y_DIV_2 0x00010000 +#define V3_Y_DIV_4 0x00030000 +#define V3_Y_DIV_8 0x00050000 +#define V3_Y_DIV_16 0x00070000 + +/* SUBP_CONTROL_STRIDE - 0x3c0 */ +#define SUBP_HQV_ENABLE 0x00010000 +#define SUBP_IA44 0x00020000 +#define SUBP_AI44 0x00000000 +#define SUBP_STRIDE_MASK 0x00001fff +#define SUBP_CONTROL_MASK 0x00070000 + +/* RAM_TABLE_CONTROL - 0x3c8 */ +#define RAM_TABLE_RGB_ENABLE 0x00000007 + +/* CAPTURE0_CONTROL - 0x310 */ +#define C0_ENABLE 0x00000001 +#define BUFFER_2_MODE 0x00000000 +#define BUFFER_3_MODE 0x00000004 +#define BUFFER_4_MODE 0x00000006 +#define SWAP_YUYV 0x00000000 +#define SWAP_UYVY 0x00000100 +#define SWAP_YVYU 0x00000200 +#define SWAP_VYUY 0x00000300 +#define IN_601_8 0x00000000 +#define IN_656_8 0x00000010 +#define IN_601_16 0x00000020 +#define IN_656_16 0x00000030 +#define DEINTER_ODD 0x00000000 +#define DEINTER_EVEN 0x00001000 +#define DEINTER_ODD_EVEN 0x00002000 +#define DEINTER_FRAME 0x00003000 +#define VIP_1 0x00000000 +#define VIP_2 0x00000400 +#define H_FILTER_2 0x00010000 +#define H_FILTER_4 0x00020000 +#define H_FILTER_8_1331 0x00030000 +#define H_FILTER_8_12221 0x00040000 +#define VIP_ENABLE 0x00000008 +#define EN_FIELD_SIG 0x00000800 +#define VREF_INVERT 0x00100000 +#define FIELD_INPUT_INVERSE 0x00400000 +#define FIELD_INVERSE 0x40000000 + +#define C1_H_MINI_EN 0x00000800 +#define C0_H_MINI_EN 0x00000800 +#define C1_V_MINI_EN 0x04000000 +#define C0_V_MINI_EN 0x04000000 +#define C1_H_MINI_2 0x00000400 + +/* CAPTURE1_CONTROL - 0x354 */ +#define C1_ENABLE 0x00000001 + +/* V3_CONTROL - 0x2A0 */ +#define V3_ENABLE 0x00000001 +#define V3_FULL_SCREEN 0x00000002 +#define V3_YUV422 0x00000000 +#define V3_RGB32 0x00000004 +#define V3_RGB15 0x00000008 +#define V3_RGB16 0x0000000C +#define V3_COLORSPACE_SIGN 0x00000080 +#define V3_EXPIRE_NUM 0x00040000 +#define V3_EXPIRE_NUM_F 0x000f0000 +#define V3_BOB_ENABLE 0x00400000 +#define V3_FIELD_BASE 0x00000000 +#define V3_FRAME_BASE 0x01000000 +#define V3_SWAP_SW 0x00000000 +#define V3_SWAP_HW_HQV 0x02000000 +#define V3_FLIP_HW_CAPTURE0 0x04000000 +#define V3_FLIP_HW_CAPTURE1 0x06000000 + +/* V3_ALPHA_FETCH_COUNT - 0x2B8 */ +#define V3_FETCH_COUNT 0x3ff00000 +#define ALPHA_FETCH_COUNT 0x000003ff + +/* HQV_CONTROL - 0x3D0 */ +#define HQV_RGB32 0x00000000 +#define HQV_RGB16 0x20000000 +#define HQV_RGB15 0x30000000 +#define HQV_YUV422 0x80000000 +#define HQV_YUV420 0xC0000000 +#define HQV_ENABLE 0x08000000 +#define HQV_SRC_SW 0x00000000 +#define HQV_SRC_MC 0x01000000 +#define HQV_SRC_CAPTURE0 0x02000000 +#define HQV_SRC_CAPTURE1 0x03000000 +#define HQV_FLIP_EVEN 0x00000000 +#define HQV_FLIP_ODD 0x00000020 +#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ +#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ +#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ +#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ +#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ +#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ +#define HQV_IDLE 0x00000008 +#define HQV_FLIP_STATUS 0x00000001 +#define HQV_DOUBLE_BUFF 0x00000000 +#define HQV_TRIPLE_BUFF 0x04000000 +#define HQV_SUBPIC_FLIP 0x00008000 +#define HQV_FIFO_STATUS 0x00001000 + +/* HQV_FILTER_CONTROL - 0x3E4 */ +#define HQV_H_LOWPASS_2TAP 0x00000001 +#define HQV_H_LOWPASS_4TAP 0x00000002 +#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ +#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ +#define HQV_H_HIGH_PASS 0x00000008 +#define HQV_H_LOW_PASS 0x00000000 +#define HQV_V_LOWPASS_2TAP 0x00010000 +#define HQV_V_LOWPASS_4TAP 0x00020000 +#define HQV_V_LOWPASS_8TAP1 0x00030000 +#define HQV_V_LOWPASS_8TAP2 0x00040000 +#define HQV_V_HIGH_PASS 0x00080000 +#define HQV_V_LOW_PASS 0x00000000 +#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 +#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 +#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_H_HIPASS_F1_2TAP 0x00000050 +#define HQV_H_HIPASS_F2_2TAP 0x00000100 +#define HQV_V_HIPASS_F1_2TAP 0x00500000 +#define HQV_V_HIPASS_F2_2TAP 0x01000000 +#define HQV_H_HIPASS_F1_4TAP 0x00000060 +#define HQV_H_HIPASS_F2_4TAP 0x00000200 +#define HQV_V_HIPASS_F1_4TAP 0x00600000 +#define HQV_V_HIPASS_F2_4TAP 0x02000000 +#define HQV_H_HIPASS_F1_8TAP 0x00000080 +#define HQV_H_HIPASS_F2_8TAP 0x00000400 +#define HQV_V_HIPASS_F1_8TAP 0x00800000 +#define HQV_V_HIPASS_F2_8TAP 0x04000000 +/* IA2 NEW */ +#define HQV_V_FILTER2 0x00080000 +#define HQV_H_FILTER2 0x00000008 +#define HQV_H_TAP2_11 0x00000041 +#define HQV_H_TAP4_121 0x00000042 +#define HQV_H_TAP4_1111 0x00000401 +#define HQV_H_TAP8_1331 0x00000221 +#define HQV_H_TAP8_12221 0x00000402 +#define HQV_H_TAP16_1991 0x00000159 +#define HQV_H_TAP16_141041 0x0000026A +#define HQV_H_TAP32 0x0000015A +#define HQV_V_TAP2_11 0x00410000 +#define HQV_V_TAP4_121 0x00420000 +#define HQV_V_TAP4_1111 0x04010000 +#define HQV_V_TAP8_1331 0x02210000 +#define HQV_V_TAP8_12221 0x04020000 +#define HQV_V_TAP16_1991 0x01590000 +#define HQV_V_TAP16_141041 0x026A0000 +#define HQV_V_TAP32 0x015A0000 +#define HQV_V_FILTER_DEFAULT 0x00420000 +#define HQV_H_FILTER_DEFAULT 0x00000040 + +/* HQV_MINI_CONTROL - 0x3E8 */ +#define HQV_H_MINIFY_ENABLE 0x00000800 +#define HQV_V_MINIFY_ENABLE 0x08000000 +#define HQV_VDEBLOCK_FILTER 0x80000000 +#define HQV_HDEBLOCK_FILTER 0x00008000 + +#endif // __VIDREGS_H__ diff --git a/Source/DirectFB/gfxdrivers/cyber5k/Makefile.am b/Source/DirectFB/gfxdrivers/cyber5k/Makefile.am new file mode 100755 index 0000000..6112a8d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/Makefile.am @@ -0,0 +1,41 @@ +## Makefile.am for DirectFB/gfxdrivers/cyber5k + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +cyber5k_LTLIBRARIES = libdirectfb_cyber5k.la + +if BUILD_STATIC +cyber5k_DATA = $(cyber5k_LTLIBRARIES:.la=.o) +endif + +cyber5kdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_cyber5k_la_SOURCES = \ + cyber5k.c \ + cyber5k.h \ + cyber5k_overlay.h \ + cyber5k_overlay.c \ + cyber5k_underlay.c \ + cyber5k_alpha.c \ + cyber5k_alpha.h \ + regs.h \ + mmio.h + +libdirectfb_cyber5k_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_cyber5k_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/cyber5k/Makefile.in b/Source/DirectFB/gfxdrivers/cyber5k/Makefile.in new file mode 100755 index 0000000..9861ceb --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/Makefile.in @@ -0,0 +1,607 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/cyber5k +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(cyber5kdir)" "$(DESTDIR)$(cyber5kdir)" +cyber5kLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(cyber5k_LTLIBRARIES) +libdirectfb_cyber5k_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_cyber5k_la_OBJECTS = cyber5k.lo cyber5k_overlay.lo \ + cyber5k_underlay.lo cyber5k_alpha.lo +libdirectfb_cyber5k_la_OBJECTS = $(am_libdirectfb_cyber5k_la_OBJECTS) +libdirectfb_cyber5k_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_cyber5k_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_cyber5k_la_SOURCES) +DIST_SOURCES = $(libdirectfb_cyber5k_la_SOURCES) +cyber5kDATA_INSTALL = $(INSTALL_DATA) +DATA = $(cyber5k_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = 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2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +DFB_GRAPHICS_DRIVER( cyber5k ) + +#include "regs.h" +#include "mmio.h" +#include "cyber5k.h" +#include "cyber5k_alpha.h" + + +/* HACK */ +volatile u8 *cyber_mmio = NULL; + + +/* FIXME: support for destination color keying */ + +#define CYBER5K_DRAWING_FLAGS \ + (DSDRAW_NOFX) + +#define CYBER5K_DRAWING_FUNCTIONS \ + (DFXL_DRAWLINE | DFXL_DRAWRECTANGLE | DFXL_FILLRECTANGLE) + +#define CYBER5K_BLITTING_FLAGS \ + (DSBLIT_SRC_COLORKEY) + +#define CYBER5K_BLITTING_FUNCTIONS \ + (DFXL_BLIT) + +static bool cyber5kFillRectangle( void *drv, void *dev, DFBRectangle *rect ); +static bool cyber5kFillRectangle24( void *drv, void *dev, DFBRectangle *rect ); +static bool cyber5kDrawRectangle( void *drv, void *dev, DFBRectangle *rect ); +static bool cyber5kDrawRectangle24( void *drv, void *dev, DFBRectangle *rect ); +static bool cyber5kBlit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool cyber5kBlit24( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); + +static DFBResult cyber5kEngineSync( void *drv, void *dev ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + + cyber_waitidle( cdrv, cdev ); + + return DFB_OK; +} + +static void cyber5kCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + /* check destination format first */ + switch (state->destination->config.format) { + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + /* if there are no other drawing flags than the supported */ + if (state->drawingflags & ~CYBER5K_DRAWING_FLAGS) + return; + + state->accel |= CYBER5K_DRAWING_FUNCTIONS; + + /* no line drawing in 24bit mode */ + if (state->destination->config.format == DSPF_RGB24) + state->accel &= ~DFXL_DRAWLINE; + } + else { + /* if there are no other blitting flags than the supported + and the source and destination formats are the same */ + if (state->blittingflags & ~CYBER5K_BLITTING_FLAGS) + return; + if (state->source->config.format != state->destination->config.format) + return; + + state->accel |= CYBER5K_BLITTING_FUNCTIONS; + } +} + +static inline void +cyber5k_validate_dst( CyberDriverData *cdrv, CyberDeviceData *cdev, + CardState *state, GraphicsDeviceFuncs *funcs ) +{ + CoreSurface *dest = state->destination; + + if (cdev->v_dst) + return; + + cdev->dst_pixeloffset = state->dst.offset / + DFB_BYTES_PER_PIXEL(dest->config.format); + cdev->dst_pixelpitch = state->dst.pitch / + DFB_BYTES_PER_PIXEL(dest->config.format); + + switch (dest->config.format) { + case DSPF_RGB16: + funcs->FillRectangle = cyber5kFillRectangle; + funcs->DrawRectangle = cyber5kDrawRectangle; + funcs->Blit = cyber5kBlit; + cyber_out16( cdrv->mmio_base, DSTWIDTH, cdev->dst_pixelpitch - 1 ); + cyber_out8( cdrv->mmio_base, COPFMT, 1 ); + break; + case DSPF_RGB24: + funcs->FillRectangle = cyber5kFillRectangle24; + funcs->DrawRectangle = cyber5kDrawRectangle24; + funcs->Blit = cyber5kBlit24; + cyber_out16( cdrv->mmio_base, DSTWIDTH, cdev->dst_pixelpitch*3 -1); + cyber_out8( cdrv->mmio_base, COPFMT, 2 ); + break; + case DSPF_RGB32: + case DSPF_ARGB: + funcs->FillRectangle = cyber5kFillRectangle; + funcs->DrawRectangle = cyber5kDrawRectangle; + funcs->Blit = cyber5kBlit; + cyber_out16( cdrv->mmio_base, DSTWIDTH, cdev->dst_pixelpitch - 1 ); + cyber_out8( cdrv->mmio_base, COPFMT, 3 ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + cdev->v_dst = 1; +} + +static inline void +cyber5k_validate_src( CyberDriverData *cdrv, + CyberDeviceData *cdev, CardState *state ) +{ + CoreSurface *source = state->source; + + if (cdev->v_src) + return; + + cdev->src_pixeloffset = state->src.offset / + DFB_BYTES_PER_PIXEL(source->config.format); + cdev->src_pixelpitch = state->src.pitch / + DFB_BYTES_PER_PIXEL(source->config.format); + + cyber_out16( cdrv->mmio_base, SRC1WIDTH, + state->src.pitch /DFB_BYTES_PER_PIXEL(source->config.format) - 1); + + cdev->v_src = 1; +} + +static inline void +cyber5k_validate_color( CyberDriverData *cdrv, + CyberDeviceData *cdev, CardState *state ) +{ + u32 fill_color = 0; + + if (cdev->v_color) + return; + + switch (state->destination->config.format) { + case DSPF_RGB16: + fill_color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB24: + case DSPF_RGB32: + fill_color = PIXEL_RGB32( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_ARGB: + fill_color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + cyber_out32( cdrv->mmio_base, FCOLOR, fill_color ); + + cdev->v_src_colorkey = 0; + + cdev->v_color = 1; +} + +static inline void +cyber5k_validate_src_colorkey( CyberDriverData *cdrv, + CyberDeviceData *cdev, CardState *state ) +{ + if (cdev->v_src_colorkey) + return; + + cyber_out32( cdrv->mmio_base, FCOLOR, state->src_colorkey ); + cyber_out32( cdrv->mmio_base, BCOLOR, state->src_colorkey ); + + cdev->v_color = 0; + + cdev->v_src_colorkey = 1; +} + +static inline void +cyber5k_validate_blitting_cmd( CyberDriverData *cdrv, + CyberDeviceData *cdev, CardState *state ) +{ + if (cdev->v_blitting_cmd) + return; + + cdev->blitting_cmd = COP_PXBLT | PAT_FIXFGD | FGD_IS_SRC1; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + cdev->blitting_cmd |= TRANS_ENABLE | TRANS_IS_SRC1 | TRANS_INVERT; + + cdev->v_blitting_cmd = 1; +} + +static void cyber5kSetState( void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + + if (state->mod_hw) { + if (state->mod_hw & SMF_DESTINATION) + cdev->v_dst = cdev->v_color = 0; + else if (state->mod_hw & SMF_COLOR) + cdev->v_color = 0; + + if (state->mod_hw & SMF_SOURCE) + cdev->v_src = cdev->v_src_colorkey = 0; + else if (state->mod_hw & SMF_SRC_COLORKEY) + cdev->v_src_colorkey = 0; + + if (state->mod_hw & SMF_BLITTING_FLAGS) + cdev->v_blitting_cmd = 0; + } + + cyber5k_validate_dst( cdrv, cdev, state, funcs ); + + switch (accel) { + case DFXL_DRAWLINE: + case DFXL_DRAWRECTANGLE: + case DFXL_FILLRECTANGLE: + cyber5k_validate_color( cdrv, cdev, state ); + + state->set = CYBER5K_DRAWING_FUNCTIONS; + break; + + case DFXL_BLIT: + cyber5k_validate_src( cdrv, cdev, state ); + cyber5k_validate_blitting_cmd( cdrv, cdev, state ); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + cyber5k_validate_src_colorkey( cdrv, cdev, state ); + + state->set = CYBER5K_BLITTING_FUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function!" ); + break; + } + + state->mod_hw = 0; +} + +static bool cyber5kFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + cyber_waitidle( cdrv, cdev ); + + cyber_out32( mmio, DSTPTR, cdev->dst_pixeloffset + + rect->y * cdev->dst_pixelpitch + + rect->x ); + + cyber_out32( mmio, HEIGHTWIDTH, ((rect->h-1) << 16) | (rect->w-1) ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + return true; +} + +static bool cyber5kFillRectangle24( void *drv, void *dev, DFBRectangle *rect ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + cyber_waitidle( cdrv, cdev ); + + cyber_out32( mmio, DSTPTR, (cdev->dst_pixeloffset + + rect->y * cdev->dst_pixelpitch + + rect->x) * 3 ); + cyber_out8( mmio, DSTXROT, rect->x & 7 ); + + cyber_out32( mmio, HEIGHTWIDTH, ((rect->h-1) << 16) | (rect->w-1) ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + return true; +} + +static bool cyber5kDrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + u32 dst = cdev->dst_pixeloffset + + rect->y * cdev->dst_pixelpitch + rect->x; + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst ); + cyber_out32( mmio, DIMW, 0 ); + cyber_out32( mmio, DIMH, rect->h - 1 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst + rect->w - 1); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst ); + cyber_out32( mmio, DIMW, rect->w - 1 ); + cyber_out32( mmio, DIMH, 0 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst + cdev->dst_pixelpitch * (rect->h - 1) ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + return true; +} + +static bool cyber5kDrawRectangle24( void *drv, void *dev, DFBRectangle *rect ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + u32 dst = cdev->dst_pixeloffset + + (rect->y * cdev->dst_pixelpitch + rect->x) * 3; + + cyber_waitidle( cdrv, cdev ); + cyber_out8( mmio, DSTXROT, rect->x & 7 ); + cyber_out32( mmio, DSTPTR, dst ); + cyber_out32( mmio, DIMW, rect->w - 1 ); + cyber_out32( mmio, DIMH, 0 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst + cdev->dst_pixelpitch * (rect->h-1) * 3 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, dst ); + cyber_out32( mmio, DIMW, 0 ); + cyber_out32( mmio, DIMH, rect->h - 1 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + cyber_waitidle( cdrv, cdev ); + cyber_out8( mmio, DSTXROT, (rect->x + rect->w - 1) & 7 ); + cyber_out32( mmio, DSTPTR, dst + (rect->w-1) * 3 ); + cyber_out32( mmio, PIXOP, COP_PXBLT | PAT_FIXFGD ); + + return true; +} + +static bool cyber5kDrawLine( void *drv, void *dev, DFBRegion *line ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + u32 cmd = COP_LINE_DRAW | PAT_FIXFGD; + + int dx; + int dy; + + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + if (dx < 0) { + dx = -dx; + cmd |= DX_NEG; + } + if (dy < 0) { + dy = -dy; + cmd |= DY_NEG; + } + if (dx < dy) { + int tmp; + cmd |= YMAJOR; + tmp = dx; + dx = dy; + dy = tmp; + } + + cyber_waitidle( cdrv, cdev ); + cyber_out32( mmio, DSTPTR, + cdev->dst_pixeloffset + + line->y1 * cdev->dst_pixelpitch + line->x1); + + cyber_out16( mmio, DIMW , dx); + cyber_out16( mmio, K1 , 2*dy); + cyber_out16( mmio, ERRORTERM, 2*dy-dx); + cyber_out32( mmio, K2 ,2*(dy-dx)); + cyber_out32( mmio, PIXOP , cmd); + + return true; +} + +static bool cyber5kBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + u32 cmd = cdev->blitting_cmd; + + cyber_waitidle( cdrv, cdev ); + + if (rect->x < dx) { + cmd |= DEC_X; + + rect->x += rect->w - 1; + dx += rect->w - 1; + } + + if (rect->y < dy) { + cmd |= DEC_Y; + + rect->y += rect->h - 1; + dy += rect->h - 1; + } + + cyber_out32( mmio, DSTPTR, + cdev->dst_pixeloffset + dy * cdev->dst_pixelpitch + dx ); + cyber_out32( mmio, SRC1PTR, + cdev->src_pixeloffset + + rect->y * cdev->src_pixelpitch + rect->x ); + cyber_out32( mmio, HEIGHTWIDTH, ((rect->h-1) << 16) | (rect->w-1) ); + cyber_out32( mmio, PIXOP , cmd); + + return true; +} + +static bool cyber5kBlit24( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + CyberDriverData *cdrv = (CyberDriverData*) drv; + CyberDeviceData *cdev = (CyberDeviceData*) dev; + volatile u8 *mmio = cdrv->mmio_base; + + u32 cmd = cdev->blitting_cmd; + u32 src = 0; + u32 dst = 0; + + cyber_waitidle( cdrv, cdev ); + + if (rect->x < dx) { + cmd |= DEC_X; + + rect->x += rect->w - 1; + dx += rect->w - 1; + + src += 2; + dst += 2; + } + + if (rect->y < dy) { + cmd |= DEC_Y; + + rect->y += rect->h - 1; + dy += rect->h - 1; + } + + src += cdev->src_pixeloffset + rect->y * cdev->dst_pixelpitch + rect->x; + dst += cdev->dst_pixeloffset + dy * cdev->dst_pixelpitch + dx; + + cyber_out32( mmio, DSTPTR , src ); + cyber_out32( mmio, SRC1PTR , dst ); + cyber_out32( mmio, HEIGHTWIDTH, ((rect->h-1) << 16) | (rect->w-1) ); + cyber_out32( mmio, PIXOP , cmd ); + + return true; +} + +/* primary layer hooks */ + +#define OSD_OPTIONS (DLOP_ALPHACHANNEL | DLOP_SRC_COLORKEY | DLOP_OPACITY) + +DisplayLayerFuncs oldPrimaryFuncs; +void *oldPrimaryDriverData; + +static DFBResult +osdInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + DFBResult ret; + + /* call the original initialization function first */ + ret = oldPrimaryFuncs.InitLayer( layer, + oldPrimaryDriverData, + layer_data, description, + config, adjustment ); + if (ret) + return ret; + + /* set name */ + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "CyberPro OSD"); + + /* add support for options */ + config->flags |= DLCONF_OPTIONS; + + /* add some capabilities */ + description->caps |= DLCAPS_ALPHACHANNEL | + DLCAPS_OPACITY | DLCAPS_SRC_COLORKEY; + + return DFB_OK; +} + +static DFBResult +osdTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + DFBResult ret; + CoreLayerRegionConfigFlags fail = 0; + DFBDisplayLayerOptions options = config->options; + + /* remove options before calling the original function */ + config->options = DLOP_NONE; + + /* call the original function */ + ret = oldPrimaryFuncs.TestRegion( layer, oldPrimaryDriverData, + layer_data, config, &fail ); + + /* check options if specified */ + if (options) { + /* any unsupported option wanted? */ + if (options & ~OSD_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* opacity and alpha channel cannot be used at once */ + if ((options & (DLOP_OPACITY | DLOP_ALPHACHANNEL)) == + (DLOP_OPACITY | DLOP_ALPHACHANNEL)) + { + fail |= CLRCF_OPTIONS; + } + } + + /* restore options */ + config->options = options; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return ret; +} + +static DFBResult +osdSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + + /* call the original function */ + ret = oldPrimaryFuncs.SetRegion( layer, oldPrimaryDriverData, + layer_data, region_data, + config, updated, surface, + palette, lock ); + if (ret) + return ret; + + /* select pixel based or global alpha */ + if (config->options & DLOP_ALPHACHANNEL) + cyber_select_alpha_src( ALPHA_GRAPHICS ); + else + cyber_select_alpha_src( ALPHA_REGISTER ); + + cyber_set_alpha_reg( config->opacity, + config->opacity, + config->opacity ); + + /* source color keying */ + cyber_select_RAM_addr( RAM_CPU ); + cyber_set_alpha_RAM_reg( 0, 0x00, 0x00, 0x00 ); + cyber_select_magic_alpha_src( ALPHA_LOOKUP ); + cyber_enable_magic_alpha_blend( config->options & DLOP_SRC_COLORKEY ); + + /* FIXME: hardcoded black color key */ + cyber_set_magic_match_reg( 0, 0, 0 ); + + return DFB_OK; +} + +DisplayLayerFuncs newPrimaryFuncs = { + .InitLayer = osdInitLayer, + + .TestRegion = osdTestRegion, + .SetRegion = osdSetRegion, +}; + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_IGS_CYBER2000: + case FB_ACCEL_IGS_CYBER2010: + case FB_ACCEL_IGS_CYBER5000: +#ifdef FB_ACCEL_IGS_CYBER5K + case FB_ACCEL_IGS_CYBER5K: /* CyberPro 5xxx */ +#endif + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Cyber Pro Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + info->version.major = 0; + info->version.minor = 4; + + info->driver_data_size = sizeof (CyberDriverData); + info->device_data_size = sizeof (CyberDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + CyberDriverData *cdrv = (CyberDriverData*) driver_data; + + /* gain access to memory mapped registers */ + cdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!cdrv->mmio_base) + return DFB_IO; + + /* HACK */ + cyber_mmio = cdrv->mmio_base; + + /* fill acceleration function table */ + funcs->EngineSync = cyber5kEngineSync; + funcs->CheckState = cyber5kCheckState; + funcs->SetState = cyber5kSetState; + + funcs->FillRectangle = cyber5kFillRectangle; + funcs->DrawRectangle = cyber5kDrawRectangle; + funcs->DrawLine = cyber5kDrawLine; + funcs->Blit = cyber5kBlit; + + /* install primary layer hooks */ + dfb_layers_hook_primary( device, driver_data, &newPrimaryFuncs, + &oldPrimaryFuncs, &oldPrimaryDriverData ); + + /* add the video underlay */ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_IGS_CYBER5000: +#ifdef FB_ACCEL_IGS_CYBER5K + case FB_ACCEL_IGS_CYBER5K: /* CyberPro 5xxx */ +#endif + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &cyberUnderlayFuncs ); + } + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + CyberDriverData *cdrv = (CyberDriverData*) driver_data; + volatile u8 *mmio = cdrv->mmio_base; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Cyber Pro" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "TVIA" ); + + + device_info->caps.flags = 0; + device_info->caps.accel = CYBER5K_DRAWING_FUNCTIONS | + CYBER5K_BLITTING_FUNCTIONS; + device_info->caps.drawing = CYBER5K_DRAWING_FLAGS; + device_info->caps.blitting = CYBER5K_BLITTING_FLAGS; + + device_info->limits.surface_byteoffset_alignment = 16; + device_info->limits.surface_pixelpitch_alignment = 4; + + + /* set fifo policy at startup */ + cyber_grphw(0x74, 0x1b); + cyber_grphw(0x75, 0x1e); + + cyber_grphw(0xD9, 0x0f); + cyber_grphw(0xDA, 0x1b); + cyber_grphw(0xDD, 0x00); + + cyber_seqw(0xD9, 0x0f); + cyber_seqw(0xDA, 0x1b); + cyber_seqw(0xDD, 0x00); + + + + cyber_out8 (mmio, COPFLAGS, 1); + cyber_out8 (mmio, FMIX , 0x03); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + CyberDriverData *cdrv = (CyberDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, cdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k.h b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k.h new file mode 100755 index 0000000..82aaabf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k.h @@ -0,0 +1,63 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___CYBER5K_H__ +#define ___CYBER5K_H__ + +#include +#include + +/* HACK */ +extern volatile u8 *cyber_mmio; + + +typedef struct { + volatile u8 *mmio_base; +} CyberDriverData; + +typedef struct { + /* state validation */ + int v_dst; + int v_src; + int v_color; + int v_src_colorkey; + int v_blitting_cmd; + + /* stored values */ + u32 dst_pixeloffset; + u32 dst_pixelpitch; + u32 src_pixeloffset; + u32 src_pixelpitch; + + u32 blitting_cmd; +} CyberDeviceData; + + +extern DisplayLayerFuncs cyberUnderlayFuncs; + +#endif diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.c b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.c new file mode 100755 index 0000000..4862293 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.c @@ -0,0 +1,260 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include "cyber5k.h" +#include "cyber5k_alpha.h" +#include "regs.h" + +void cyber_cleanup_alpha(void) +{ + int i; + + cyber_grphw(0xfa, 0); + for (i=0; i<16; i++) { + if (i == 0x0A) {/*Don't clean up SyncLock video path if there is one*/ + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) & 0x08); + } + else { + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + } + } + + cyber_grphw(0xfa, 8); + for (i=0; i<16; i++) { + if(i==0x0F) {/*Just in case there is a SyncLock video*/ + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) | 0xC0); + } + else { + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + } + } + + cyber_grphw(0xfa, 0x10); + for (i=0; i<16; i++) { + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + } + + cyber_grphw(0xfa, 0x18); + for (i=0; i<16; i++) { + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + } + + cyber_grphw(0xfa, 0x20); + for (i=0; i<16; i++) { + cyber_out8(cyber_mmio, SEQINDEX, 0x40 + i); + cyber_out8(cyber_mmio, SEQDATA, 0x00); + } + + cyber_out8(cyber_mmio, SEQINDEX, 0xA6); + /*for video capture*/ + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) & 0xF0); + +#if 0 + /*for 8-bit Index mode*/ + if(bEnabled8Bit) /*if we are in 8-bit alpha-blending mode, remember to disable it*/ + EnablePaletteMode(0); +#endif + + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0x80); + cyber_out8(cyber_mmio, GRAINDEX, 0xe0); + cyber_out8(cyber_mmio, GRADATA, cyber_in8(cyber_mmio, 0x03cf) | 0x04); + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0x00); +} + +void cyber_enable_alpha(int enable) +{ + cyber_grphw(0xfa, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4b); + if (enable) + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) | 0x80)); + else + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & 0x7F)); +} + +void cyber_enable_fullscreen_alpha(int enable) +{ + cyber_grphw(0xfa, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4b); + if (enable) + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) | 0x40)); + else + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & 0xBF)); +} + +void cyber_select_blend_src1(int src) +{ + cyber_grphw(0xfa, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x49); + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & ~0x03) | src); +} + +void cyber_select_blend_src2(int src) +{ + cyber_grphw(0xfa, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4d); + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & ~0x30) | (src << 4)); + if(src == SRC2_OVERLAY1) { /*if source is Overlay one only, disable Overlay 2*/ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0x08); + cyber_out8(cyber_mmio, SEQINDEX, 0x4f); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) | 0x08); + cyber_out8(cyber_mmio, GRADATA, 0x00); + } +} + +void cyber_select_alpha_src(int src) +{ + cyber_grphw(0xfa, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x49); + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & ~0x60) | (src << 5)); + /*if alpha source comes form Overlay2, we need to disable Overlay2 color key function*/ + if(src == ALPHA_OVERLAY2) { + /*Disable Overlay 2 in Source B path*/ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0x08); + cyber_out8(cyber_mmio, SEQINDEX, 0x4f); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) | 0x08); + /*Disable V2 generally */ + cyber_out8(cyber_mmio, GRADATA, 0x20); + cyber_out8(cyber_mmio, SEQINDEX, 0x47); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) | 0x02); + cyber_out8(cyber_mmio, GRADATA, 0x00); + } +} + +void cyber_set_alpha_reg(unsigned char r, unsigned char g, unsigned char b) +{ + cyber_grphw(0xfa, 0); + + cyber_seqw(0x46, r); + cyber_seqw(0x47, g); + cyber_seqw(0x48, b); +} + + +void cyber_set_magic_match_reg( unsigned char bR, unsigned char bG, unsigned char bB ) +{ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 8); + /*Disable range feature first*/ + cyber_out8(cyber_mmio, SEQINDEX, 0x46); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) & 0x7F); + + cyber_out8(cyber_mmio, SEQINDEX, 0x40); + cyber_out8(cyber_mmio, SEQDATA, bR); + cyber_out8(cyber_mmio, SEQINDEX, 0x41); + cyber_out8(cyber_mmio, SEQDATA, bG); + cyber_out8(cyber_mmio, SEQINDEX, 0x42); + cyber_out8(cyber_mmio, SEQDATA, bB); +} + +void cyber_set_alpha_RAM_reg( unsigned char bIndex, unsigned char bR, unsigned char bG, unsigned char bB) +{ + unsigned char bData; + + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x49); + bData = cyber_in8(cyber_mmio, SEQDATA); + cyber_out8(cyber_mmio, SEQDATA, 0x18); /*select CPU to write*/ + + cyber_out8(cyber_mmio, SEQINDEX, 0x4e); /*enable index of alpha RAM R*/ + cyber_out8(cyber_mmio, SEQDATA, 0x20+bIndex); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4f); /*RAM data port*/ + cyber_out8(cyber_mmio, SEQDATA, bR); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4e); /*enable index of alpha RAM G*/ + cyber_out8(cyber_mmio, SEQDATA, 0x40+bIndex); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4f); /*RAM data port*/ + cyber_out8(cyber_mmio, SEQDATA, bG); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4e); /*enable index of alpha RAM B*/ + cyber_out8(cyber_mmio, SEQDATA, 0x80+bIndex); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4f); /*RAM data port*/ + cyber_out8(cyber_mmio, SEQDATA, bB); + + cyber_out8(cyber_mmio, SEQINDEX, 0x49); + cyber_out8(cyber_mmio, SEQDATA, bData); + + cyber_out8(cyber_mmio, SEQINDEX, 0x4e); /*Set index of alpha RAM */ + cyber_out8(cyber_mmio, SEQDATA, bIndex); +} + +void cyber_select_RAM_addr( unsigned char bRAMAddrSel ) +{ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0); + + cyber_out8(cyber_mmio, SEQINDEX, 0x49); + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & ~0x18) | (bRAMAddrSel << 3)); +} + +void cyber_enable_magic_alpha_blend( unsigned char enable ) +{ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 8); + + cyber_out8(cyber_mmio, SEQINDEX, 0x46); + if (enable) + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) | 0x01)); + else + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & 0xFE)); + + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 0x20); + cyber_out8(cyber_mmio, SEQINDEX, 0x47); + cyber_out8(cyber_mmio, SEQDATA, cyber_in8(cyber_mmio, SEQDATA) & 0x7F); + cyber_out8(cyber_mmio, GRADATA, 0x00); +} + +void cyber_select_magic_alpha_src( unsigned char bAlphaSrc ) +{ + cyber_out8(cyber_mmio, GRAINDEX, 0xfa); + cyber_out8(cyber_mmio, GRADATA, 8); + + cyber_out8(cyber_mmio, SEQINDEX, 0x46); + cyber_out8(cyber_mmio, SEQDATA, (cyber_in8(cyber_mmio, SEQDATA) & ~0x0C) | (bAlphaSrc << 2)); +} diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.h b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.h new file mode 100755 index 0000000..f3f635c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_alpha.h @@ -0,0 +1,64 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef CYBER5KFB_ALPHA_H +#define CYBER5KFB_ALPHA_H + +#include "mmio.h" + +#define SRC1_GRAPHICS 0 +#define SRC1_OVERLAY1 1 +#define SRC1_OVERLAY2 2 + +#define SRC2_OVERLAY1 0 +#define SRC2_OVERLAY2 1 +#define SRC2_GRAPHICS 2 + +#define ALPHA_GRAPHICS 0 +#define ALPHA_OVERLAY2 1 +#define ALPHA_LOOKUP 2 +#define ALPHA_REGISTER 3 + +#define RAM_CPU 3 + +void cyber_cleanup_alpha(void); +void cyber_enable_alpha(int enable); +void cyber_enable_fullscreen_alpha(int enable); +void cyber_cleanup_alpha(void); +void cyber_select_blend_src1(int src); +void cyber_select_blend_src2(int src); +void cyber_select_alpha_src(int src); +void cyber_set_alpha_reg(unsigned char r, unsigned char g, unsigned char b); + +void cyber_select_RAM_addr( unsigned char bRAMAddrSel ); +void cyber_set_alpha_RAM_reg( unsigned char bIndex, unsigned char bR, unsigned char bG, unsigned char bB); +void cyber_select_magic_alpha_src( unsigned char bAlphaSrc ); +void cyber_enable_magic_alpha_blend( unsigned char enable ); +void cyber_set_magic_match_reg( unsigned char bR, unsigned char bG, unsigned char bB ); + +#endif /* CYBER5KFB_ALPHA_H */ diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.c b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.c new file mode 100755 index 0000000..b4638df --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.c @@ -0,0 +1,376 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include "cyber5k.h" +#include "cyber5k_overlay.h" +#include "regs.h" +#include "mmio.h" + +static int overlay_byte_per_pixel = 2; +static int overlay_init = 0; + +static unsigned char savedReg74, savedReg75; /*FIFO control registers for 2D Graphics*/ +static unsigned char savedRegD9[2], savedRegDA[2], savedRegDD[2]; /*FIFO control registers for Overlay*/ +/*Following is our FIFO policy number, should be programmed to +0x3CE/0x74, 0x3CE/0x75, 0x3CE(0x3C4)/0xD9, 0x3CE(0x3C4)/0xDA, +0x3CE(0x3c4)/0xDD respectively in order to get a best memory bandwidth. +Current value is a group of experence value based on 70MHZ EDO/SG RAM.*/ +static unsigned char bFIFOPolicyNum[5] = {0x10, 0x10, 0x1C, 0x1C, 0x06}; + + +static void +cyber_videoreg_mask( unsigned char index, unsigned char value, unsigned char mask ) +{ + unsigned char tmp; + + cyber_out8( cyber_mmio, GRAINDEX, index ); + tmp = cyber_in8( cyber_mmio, GRADATA ); + tmp &= mask; + tmp |= value; + cyber_out8( cyber_mmio, GRADATA, tmp ); +} + +static void +cyber_seqreg_mask( unsigned char index, unsigned char value, unsigned char mask ) +{ + unsigned char tmp; + + cyber_out8( cyber_mmio, SEQINDEX, index ); + tmp = cyber_in8( cyber_mmio, SEQDATA ); + + tmp &= mask; + tmp |= value; + cyber_out8( cyber_mmio, SEQDATA, tmp ); +} + +static void +cyber_overlayreg_mask( unsigned char index, unsigned char value, unsigned char mask ) { + unsigned char tmp; + + cyber_out8( cyber_mmio, GRAINDEX, index ); + tmp = cyber_in8( cyber_mmio, GRADATA ); + + tmp &= mask; + tmp |= value; + cyber_out8(cyber_mmio, GRADATA, tmp); +} + +void cyber_cleanup_overlay(void) +{ + /*restore FIFO control regs*/ + cyber_seqreg_mask(0xA7, 0x0, ~0x5); + + + if (!overlay_init) + return; + overlay_init = 0; + + + cyber_grphw(0x74, savedReg74); + cyber_grphw(0x75, savedReg75); + + cyber_grphw(0xD9, savedRegD9[0]); + cyber_grphw(0xDA, savedRegDA[0]); + cyber_grphw(0xDD, savedRegDD[0]); + + cyber_seqw(0xD9, savedRegD9[1]); + cyber_seqw(0xDA, savedRegDA[1]); + cyber_seqw(0xDD, savedRegDD[1]); +} + +void cyber_init_overlay(void) +{ + /*Clear Overlay path first*/ + cyber_grphw(DISP_CTL_I, 0x00); + + /* Video Display Vertical Starting Line (may not need initiate here)*/ + cyber_grphw(DEST_RECT_TOP_L, 0x00); + cyber_grphw(DEST_RECT_TOP_H, 0x00); + + /* Overlay Vertical DDA Increment Value*/ + cyber_grphw(DDA_Y_INC_L, 0x00); + cyber_grphw(DDA_Y_INC_H, 0x10); + + /* Video Memory Starting Address*/ + cyber_grphw(MEMORY_START_L, 0x00); + cyber_grphw(MEMORY_START_M, 0x0f); + cyber_grphw(MEMORY_START_H, 0x03); /* Temporary fixed to 0x30f00 = 0xc3c00 >> 2*/ + /* 0x3c00 = 0x300*0x14 = 768*20*/ + + /* Video Display Horizontal Starting Pixel -- may not need init here*/ + cyber_grphw(DEST_RECT_LEFT_L, 0x20); + cyber_grphw(DEST_RECT_LEFT_H, 0x00); + + /* Video Display Horizontal Ending Pixel -- may not need init here*/ + cyber_grphw(DEST_RECT_RIGHT_L, 0x60); + cyber_grphw(DEST_RECT_RIGHT_H, 0x01); + + /* Video Display Vertical Ending Line -- may not need init here*/ + cyber_grphw(DEST_RECT_BOTTOM_L, 0xe0); + cyber_grphw(DEST_RECT_BOTTOM_H, 0x00); + + /* Video Color Compare Register*/ + cyber_grphw(COLOR_CMP_RED, 0x00); + cyber_grphw(COLOR_CMP_GREEN,0x00); + cyber_grphw(COLOR_CMP_BLUE, 0x00); + + /* Video Horizontal DDA Increment Value*/ + cyber_grphw(DDA_X_INC_L, 0x00); + cyber_grphw(DDA_X_INC_H, 0x10); + + /* Video Format Control*/ + cyber_grphw(VIDEO_FORMAT, 0x00); + + /* Video Misc Control*/ + cyber_grphw(MISC_CTL_I, 0x00); + + cyber_grphw(MISC_CTL_I, 0x01); /* Video Misc Control*/ + + /*default to colorkey*/ + cyber_grphw(DISP_CTL_I, 0x04 ); + +#ifdef NTSCTVOUT /*if your TV output mode is NTSC*/ + cyber_seqreg_mask(0xA6, 0x20, ~0x30); +#else /*if your TV output mode is PAL*/ + cyber_seqreg_mask(0xA6, 0x30, ~0x30); +#endif + + + if (overlay_init) + return; + overlay_init = 1; + + + +/* the following code is commented out, since saved values are not clean if */ +/* DirectFB crashed while underlay was enabled, hardcoded bootup */ +/* values instead (see below) */ + +/* + cyber_out8(cyber_mmio, GRAINDEX, 0x74); + savedReg74 = cyber_in8(cyber_mmio, GRADATA); + cyber_out8(cyber_mmio, GRAINDEX, 0x75); + savedReg75 = cyber_in8(cyber_mmio, GRADATA); + + cyber_out8(cyber_mmio, GRAINDEX, 0xD9); + savedRegD9[0] = cyber_in8(cyber_mmio, GRADATA); + cyber_out8(cyber_mmio, GRAINDEX, 0xDA); + savedRegDA[0] = cyber_in8(cyber_mmio, GRADATA); + cyber_out8(cyber_mmio, GRAINDEX, 0xDD); + savedRegDD[0] = cyber_in8(cyber_mmio, GRADATA); + + cyber_out8(cyber_mmio, SEQINDEX, 0xD9); + savedRegD9[1] = cyber_in8(cyber_mmio, SEQDATA); + cyber_out8(cyber_mmio, SEQINDEX, 0xDA); + savedRegDA[1] = cyber_in8(cyber_mmio, SEQDATA); + cyber_out8(cyber_mmio, SEQINDEX, 0xDD); + savedRegDD[1] = cyber_in8(cyber_mmio, SEQDATA); + */ + + + savedReg74 = 0x1b; + savedReg74 = 0x1e; + + savedRegD9[0] = 0x0f; + savedRegDA[0] = 0x1b; + savedRegDD[0] = 0x00; + + savedRegD9[1] = 0x0f; + savedRegDA[1] = 0x1b; + savedRegDD[1] = 0x00; +} + +void cyber_change_overlay_fifo(void) +{ + cyber_grphw(0x74, bFIFOPolicyNum[0]); + cyber_grphw(0x75, bFIFOPolicyNum[1]); + cyber_grphw(0xD9, bFIFOPolicyNum[2]); + cyber_grphw(0xDA, bFIFOPolicyNum[3]); + + cyber_videoreg_mask(0xA6, 0x08, ~0x08); + cyber_videoreg_mask(0xF1, 0x40, (unsigned char)(~0xC0)); + cyber_overlayreg_mask(FIFO_CTL_I, bFIFOPolicyNum[4] & 0x05, ~0x05); + cyber_overlayreg_mask(FIFO_CTL_I, 0x2, ~0x02); +} + +void cyber_set_overlay_format(int format) { + switch (format) { + case OVERLAY_YUV422: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x00, 0xF8 ); + overlay_byte_per_pixel = 2; + break; + case OVERLAY_RGB555: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x01, 0xF8 ); + overlay_byte_per_pixel = 2; + break; + case OVERLAY_RGB565: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x02, 0xF8 ); + overlay_byte_per_pixel = 2; + break; + case OVERLAY_RGB888: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x03, 0xF8 ); + overlay_byte_per_pixel = 3; + break; + case OVERLAY_RGB8888: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x04, 0xF8 ); + overlay_byte_per_pixel = 4; + break; + case OVERLAY_RGB8: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x05, 0xF8 ); + overlay_byte_per_pixel = 1; + break; + case OVERLAY_RGB4444: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x06, 0xF8 ); + overlay_byte_per_pixel = 2; + break; + case OVERLAY_RGB8T: + cyber_overlayreg_mask( VIDEO_FORMAT, 0x07, 0xF8 ); + overlay_byte_per_pixel = 1; + break; + } +} + +void cyber_set_overlay_mode(int mode) +{ + switch (mode) { + case OVERLAY_COLORKEY: + cyber_overlayreg_mask( DISP_CTL_I, 0x00, 0xFD ); + break; + case OVERLAY_WINDOWKEY: + default: + cyber_overlayreg_mask( DISP_CTL_I, 0x02, 0xFD ); + break; + } +} + +void cyber_set_overlay_srcaddr(int addr, int x, int y, int width, int pitch) +{ + unsigned char bHigh; + int wByteFetch; + + addr += y * pitch + x * overlay_byte_per_pixel; + addr >>= 2; + + /*playback start addr*/ + cyber_grphw( MEMORY_START_L, (unsigned char)( addr & 0x0000FF) ); + cyber_grphw( MEMORY_START_M, (unsigned char)((addr & 0x00FF00) >> 8) ); + cyber_grphw( MEMORY_START_H, (unsigned char)((addr & 0xFF0000) >> 16) ); + + /* pitch is a multiple of 64 bits*/ + pitch >>= 3; /* 64 bit address field*/ + wByteFetch = (width * overlay_byte_per_pixel + 7) >> 3; + + bHigh = (unsigned char)(pitch >> 8) & 0x0F; + bHigh = bHigh | (((unsigned char)(wByteFetch >> 8)) << 4 ); + + cyber_grphw( MEMORY_PITCH_L, (unsigned char)(pitch) ); + cyber_grphw( MEMORY_PITCH_H, bHigh ); + + cyber_grphw( MEMORY_OFFSET_PHASE, (unsigned char)(wByteFetch) ); + + if (width > 720) /*Turn off interpolation*/ + cyber_overlayreg_mask( DISP_CTL_I, 0x20, 0xDF ); + else { /*Turn off interpolation*/ + if (width > 360) { /* Y Only*/ + cyber_seqreg_mask(0xA6, 0x40, ~0x40); + } + else { + cyber_seqreg_mask(0xA6, 0x00, ~0x40); + } + + cyber_overlayreg_mask( DISP_CTL_I, 0x00, 0xDF ); + } +} + +void cyber_set_overlay_window(int left, int top, int right, int bottom) +{ + cyber_grphw( DEST_RECT_LEFT_L, (unsigned char)(left ) ); + cyber_grphw( DEST_RECT_LEFT_H, (unsigned char)(left >> 8) ); + cyber_grphw( DEST_RECT_RIGHT_L, (unsigned char)(right ) ); + cyber_grphw( DEST_RECT_RIGHT_H, (unsigned char)(right >> 8) ); + + cyber_grphw( DEST_RECT_TOP_L, (unsigned char)(top ) ); + cyber_grphw( DEST_RECT_TOP_H, (unsigned char)(top >> 8) ); + cyber_grphw( DEST_RECT_BOTTOM_L, (unsigned char)(bottom ) ); + cyber_grphw( DEST_RECT_BOTTOM_H, (unsigned char)(bottom >> 8) ); +} + +void cyber_set_overlay_scale( unsigned char bEnableBob, int wSrcXExt, int wDstXExt, int wSrcYExt, int wDstYExt ) +{ + int dwScale; + + cyber_grphw( DDA_X_INIT_L, 0x0 ); /* set to 0x800;*/ + cyber_grphw( DDA_X_INIT_H, 0x8 ); + if ( wSrcXExt == wDstXExt ) + dwScale = 0x1000; + else + dwScale = ( wSrcXExt * 0x1000 ) / wDstXExt; + cyber_grphw( DDA_X_INC_L, (unsigned char)( dwScale & 0x00FF) ); + cyber_grphw( DDA_X_INC_H, (unsigned char)((dwScale & 0xFF00) >> 8) ); + + cyber_grphw( DDA_Y_INIT_L, 0x0 ); /* set to 0x800;*/ + cyber_grphw( DDA_Y_INIT_H, 0x8 ); + + if ( wSrcYExt == wDstYExt ) + dwScale = 0x1000; + else + dwScale = ( wSrcYExt * 0x1000 ) / wDstYExt; + + + if (bEnableBob == 0) {/*Disable Bob mode*/ + cyber_seqreg_mask(0xA7, 0x0, ~0x5); /*Bob/Weave disable*/ + } + else {/*Enable Bob mode*/ + wSrcYExt = wSrcYExt / 2; + if (wSrcYExt == wDstYExt) + dwScale = 0x1000; + else + dwScale = ( wSrcYExt * 0x1000 ) / wDstYExt; + if (dwScale <= 0x815 && dwScale >= 0x7eb) { + cyber_seqreg_mask(0xA7, 0x5, ~0x5); /*Bob/Weave enable*/ + } + else { + cyber_seqreg_mask(0xA7, 0x4, ~0x5); /*Bob/Weave enable*/ + } + } + + cyber_grphw( DDA_Y_INC_L, (unsigned char)( dwScale & 0x00FF) ); + cyber_grphw( DDA_Y_INC_H, (unsigned char)((dwScale & 0xFF00) >> 8) ); +} + +void cyber_enable_overlay(int enable) +{ + if (enable) + cyber_overlayreg_mask( DISP_CTL_I, 0x84, (unsigned char)(~0x84) ); + else + cyber_overlayreg_mask( DISP_CTL_I, 0x00, 0x7F ); /* Disable Vafc !!!*/ +} diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.h b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.h new file mode 100755 index 0000000..bb24499 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_overlay.h @@ -0,0 +1,92 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef CYBER5KFB_OVERLAY_H +#define CYBER5KFB_OVERLAY_H + +#include "regs.h" + +#define OVERLAY_YUV422 0 /*captured data is YUV 422 format*/ +#define OVERLAY_RGB555 1 +#define OVERLAY_RGB565 2 +#define OVERLAY_RGB888 3 +#define OVERLAY_RGB8888 4 +#define OVERLAY_RGB8 5 +#define OVERLAY_RGB4444 6 +#define OVERLAY_RGB8T 7 + +#define OVERLAY_COLORKEY 0 /*Overlayed window is of color keying*/ +#define OVERLAY_WINDOWKEY 1 /*Overlayed window is of window keying*/ + +#define OVERLAY_WEAVEMODE 0 +#define OVERLAY_BOBMODE 1 + + +#define MEMORY_START_L 0xC0 +#define MEMORY_START_M 0xC1 +#define MEMORY_START_H 0xC2 +#define MEMORY_PITCH_L 0xC3 +#define MEMORY_PITCH_H 0xC4 +#define DEST_RECT_LEFT_L 0xC5 +#define DEST_RECT_LEFT_H 0xC6 +#define DEST_RECT_RIGHT_L 0xC7 +#define DEST_RECT_RIGHT_H 0xC8 +#define DEST_RECT_TOP_L 0xC9 +#define DEST_RECT_TOP_H 0xCA +#define DEST_RECT_BOTTOM_L 0xCB +#define DEST_RECT_BOTTOM_H 0xCC +#define MEMORY_OFFSET_PHASE 0xCD +#define COLOR_CMP_RED 0xCE +#define COLOR_CMP_GREEN 0xCF +#define COLOR_CMP_BLUE 0xD0 +#define DDA_X_INIT_L 0xD1 +#define DDA_X_INIT_H 0xD2 +#define DDA_X_INC_L 0xD3 +#define DDA_X_INC_H 0xD4 +#define DDA_Y_INIT_L 0xD5 +#define DDA_Y_INIT_H 0xD6 +#define DDA_Y_INC_L 0xD7 +#define DDA_Y_INC_H 0xD8 +#define FIFO_TIMING_CTL_L 0xD9 +#define FIFO_TIMING_CTL_H 0xDA +#define VIDEO_FORMAT 0xDB +#define DISP_CTL_I 0xDC +#define FIFO_CTL_I 0xDD +#define MISC_CTL_I 0xDE + +void cyber_cleanup_overlay(void); +void cyber_init_overlay(void); +void cyber_enable_overlay(int enable); +void cyber_change_overlay_fifo(void); +void cyber_set_overlay_format(int format); +void cyber_set_overlay_mode(int mode); +void cyber_set_overlay_srcaddr(int addr, int x, int y, int width, int pitch); +void cyber_set_overlay_window(int left, int top, int right, int bottom); +void cyber_set_overlay_scale( unsigned char bEnableBob, int wSrcXExt, int wDstXExt, int wSrcYExt, int wDstYExt ); + +#endif /* CYBER5KFB_OVERLAY_H */ diff --git a/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_underlay.c b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_underlay.c new file mode 100755 index 0000000..588f111 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/cyber5k_underlay.c @@ -0,0 +1,301 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include "cyber5k.h" +#include "cyber5k_alpha.h" +#include "cyber5k_overlay.h" + +typedef struct { + CoreLayerRegionConfig config; +} CyberUnderlayLayerData; + +static void udl_set_all ( CyberDriverData *cdrv, + CyberUnderlayLayerData *cudl, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); +static void udl_set_location( CyberDriverData *cdrv, + CyberUnderlayLayerData *cudl, + CoreLayerRegionConfig *config, + CoreSurface *surface ); + +#define CYBER_UNDERLAY_SUPPORTED_OPTIONS (DLOP_NONE) + +/**********************/ + +static int +udlLayerDataSize( void ) +{ + return sizeof(CyberUnderlayLayerData); +} + +static DFBResult +udlInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *default_config, + DFBColorAdjustment *default_adj ) +{ + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_ALPHACHANNEL | + DLCAPS_OPACITY | DLCAPS_SRC_COLORKEY | + DLCAPS_SCREEN_LOCATION; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE | + DLTF_BACKGROUND; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "CyberPro Underlay" ); + + /* fill out the default configuration */ + default_config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + default_config->width = 768; + default_config->height = 576; + default_config->pixelformat = DSPF_RGB16; + default_config->buffermode = DLBM_FRONTONLY; + default_config->options = DLOP_NONE; + + /* initialize registers */ + cyber_init_overlay(); + + /* workaround */ + cyber_change_overlay_fifo(); + cyber_cleanup_overlay(); + cyber_init_overlay(); + + return DFB_OK; +} + +static DFBResult +udlTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + /* check for unsupported options */ + if (config->options & ~CYBER_UNDERLAY_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* check pixel format */ + switch (config->format) { + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_YUY2: + break; + + default: + fail |= CLRCF_FORMAT; + } + + /* check width */ + if (config->width > 1024 || config->width < 4) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 1024 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +udlSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + CyberDriverData *cdrv = (CyberDriverData*) driver_data; + CyberUnderlayLayerData *cudl = (CyberUnderlayLayerData*) layer_data; + + /* remember configuration */ + cudl->config = *config; + + /* set up layer */ + udl_set_all( cdrv, cudl, config, surface, lock ); + + return DFB_OK; +} + +static DFBResult +udlRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + /* disable and clean up */ + cyber_enable_overlay(0); + cyber_cleanup_alpha(); + cyber_cleanup_overlay(); + + return DFB_OK; +} + +static DFBResult +udlFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + CyberDriverData *cdrv = (CyberDriverData*) driver_data; + CyberUnderlayLayerData *cudl = (CyberUnderlayLayerData*) layer_data; + + dfb_surface_flip( surface, false ); + + udl_set_all( cdrv, cudl, &cudl->config, surface, lock ); + + return DFB_OK; +} + + +DisplayLayerFuncs cyberUnderlayFuncs = { + .LayerDataSize = udlLayerDataSize, + .InitLayer = udlInitLayer, + + .TestRegion = udlTestRegion, + .SetRegion = udlSetRegion, + .RemoveRegion = udlRemoveRegion, + .FlipRegion = udlFlipRegion, +}; + + +/* internal */ + +static void udl_set_all( CyberDriverData *cdrv, + CyberUnderlayLayerData *cudl, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + /* set the pixel format */ + switch (surface->config.format) { + case DSPF_RGB332: + cyber_set_overlay_format (OVERLAY_RGB8); + break; + + case DSPF_ARGB1555: + cyber_set_overlay_format (OVERLAY_RGB555); + break; + + case DSPF_RGB16: + cyber_set_overlay_format (OVERLAY_RGB565); + break; + + case DSPF_RGB24: + cyber_set_overlay_format (OVERLAY_RGB888); + break; + + case DSPF_ARGB: + case DSPF_RGB32: + cyber_set_overlay_format (OVERLAY_RGB8888); + break; + + case DSPF_YUY2: + cyber_set_overlay_format (OVERLAY_YUV422); + break; + + default: + D_BUG("unexpected pixelformat"); + break; + } + + cyber_set_overlay_mode( OVERLAY_WINDOWKEY ); + + /* set address */ + cyber_set_overlay_srcaddr( lock->offset, 0, 0, + surface->config.size.w, lock->pitch ); + + /* set location and scaling */ + udl_set_location( cdrv, cudl, config, surface ); + + /* tune fifo */ + cyber_change_overlay_fifo(); + + /* set up alpha blending */ + cyber_enable_alpha( 1 ); + cyber_enable_fullscreen_alpha( 1 ); + cyber_select_blend_src1( SRC1_GRAPHICS ); + cyber_select_blend_src2( SRC2_OVERLAY1 ); + + /* FIXME: find out why the opacity can't be set outside of this function */ + cyber_set_alpha_reg( 0xcc, 0xcc, 0xcc ); + + /* turn it on */ + cyber_enable_overlay(1); +} + +static void udl_set_location( CyberDriverData *cdrv, + CyberUnderlayLayerData *cudl, + CoreLayerRegionConfig *config, + CoreSurface *surface ) +{ + /* set location */ + cyber_set_overlay_window( config->dest.x, config->dest.y, + config->dest.x + config->dest.w - 1, + config->dest.y + config->dest.h - 1 ); + + /* set scaling */ + cyber_set_overlay_scale( surface->config.size.h == 576 ? /* HACK: support interlaced video */ + OVERLAY_BOBMODE : OVERLAY_WEAVEMODE, + surface->config.size.w, config->dest.w, + surface->config.size.h, config->dest.h ); +} + diff --git a/Source/DirectFB/gfxdrivers/cyber5k/mmio.h b/Source/DirectFB/gfxdrivers/cyber5k/mmio.h new file mode 100755 index 0000000..59f9a8d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/mmio.h @@ -0,0 +1,126 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __CYBER5K_MMIO__ +#define __CYBER5K_MMIO__ + +#include +#include "cyber5k.h" +#include "regs.h" + +static inline void +cyber_out8(volatile u8 *mmioaddr, u32 reg, u8 value) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static inline void +cyber_out16(volatile u8 *mmioaddr, u32 reg, u16 value) +{ + *((volatile u16*)(mmioaddr+reg)) = value; +} + +static inline void +cyber_out32(volatile u8 *mmioaddr, u32 reg, u32 value) +{ + *((volatile u32*)(mmioaddr+reg)) = value; +} + +static inline u8 +cyber_in8(volatile u8 *mmioaddr, u32 reg) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static inline u16 +cyber_in16(volatile u8 *mmioaddr, u32 reg) +{ + return *((volatile u16*)(mmioaddr+reg)); +} + +static inline u32 +cyber_in32(volatile u8 *mmioaddr, u32 reg) +{ + return *((volatile u32*)(mmioaddr+reg)); +} + +/* Wait for idle accelerator */ +static inline void +cyber_waitidle( CyberDriverData *cdrv, CyberDeviceData *cdev ) +{ +/* while (cyber_in8(mmioaddr, COP_STAT) & (CMDFF_FULL | HOSTFF_NOTEMPTY)) { + grodis = 0; + }*/ + while ( cyber_in8(cdrv->mmio_base, COP_STAT) & (COP_BUSY|CMDFF_FULL|HOSTFF_NOTEMPTY) ); +} + +/* ------------------------------------------------------------------------ */ + +static inline void cyber_crtcw(int reg, int val) +{ + cyber_out8( cyber_mmio, CRTINDEX, reg ); + cyber_out8( cyber_mmio, CRTDATA, val ); +} + +static inline void cyber_grphw(int reg, int val) +{ + cyber_out8( cyber_mmio, GRAINDEX, reg ); + cyber_out8( cyber_mmio, GRADATA, val ); +} + +static inline unsigned int cyber_grphr(int reg) +{ + cyber_out8( cyber_mmio, GRAINDEX, reg ); + return cyber_in8( cyber_mmio, GRADATA ); +} + +static inline void cyber_attrw(int reg, int val) +{ + cyber_in8( cyber_mmio, ATTRRESET ); + cyber_out8( cyber_mmio, ATTRINDEX, reg ); + cyber_in8( cyber_mmio, ATTRDATAR ); + cyber_out8( cyber_mmio, ATTRDATAW, val ); +} + +static inline void cyber_seqw(int reg, int val) +{ + cyber_out8( cyber_mmio, SEQINDEX, reg ); + cyber_out8( cyber_mmio, SEQDATA, val ); +} + +static inline void cyber_tvw(int reg, int val) +{ + cyber_out8( cyber_mmio, 0xb0000 + reg, val ); +} + +static inline unsigned int cyber_tvr(int reg) +{ + return cyber_in8( cyber_mmio, 0xb0000 + reg ); +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/cyber5k/regs.h b/Source/DirectFB/gfxdrivers/cyber5k/regs.h new file mode 100755 index 0000000..7ae038a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cyber5k/regs.h @@ -0,0 +1,387 @@ +#ifndef REGS_H +#define REGS_H + +/* + * COP MMIO definition + * + */ + +#define OPAQUE 0 +#define TRANSPARENT 1 + +#define TRANSPARENT_SRC 1 +#define TRANSPARENT_DST 2 +#define SRC_FROM_SYS 4 +#define PAT_IS_MONO 8 + +#define R2_ZERO 0x00 +#define R2_S_AND_D 0x01 +#define R2_S_AND_ND 0x02 +#define R2_S 0x03 +#define R2_NS_AND_D 0x04 +#define R2_D 0x05 +#define R2_S_XOR_D 0x06 +#define R2_S_OR_D 0x07 +#define R2_NS_AND_ND 0x08 +#define R2_S_XOR_ND 0x09 +#define R2_ND 0x0A +#define R2_S_OR_ND 0x0B +#define R2_NS 0x0C +#define R2_NS_OR_D 0x0D +#define R2_NS_OR_ND 0x0E +#define R2_ONE 0x0F + +#define R3_S 0xF0 +#define R3_P 0xCC + + +#define COP_BASE 0xBF000 +#define COP_STAT 0x11 + COP_BASE + #define HBLTW_NOTREADY 0x01 + #define HOSTFF_NOTEMPTY 0x02 + #define CMDFF_FULL 0x04 + #define SUSPEND_COP 0x08 + #define COP_STOPPED 0x10 + #define TERMINATE_COP 0x20 + #define HBLT_NOTACKZ 0x40 + #define COP_BUSY 0x80 + +#define SRC1WIDTH 0x18 + COP_BASE +#define COPFMT 0x1C + COP_BASE +#define ERRORTERM 0x20 + COP_BASE +#define K1 0x24 + COP_BASE +#define K2 0x28 + COP_BASE +#define FMIX 0x48 + COP_BASE +#define BMIX 0x49 + COP_BASE +#define FCOLOR 0x58 + COP_BASE +#define BCOLOR 0x5C + COP_BASE +#define HEIGHTWIDTH 0x60 + COP_BASE +#define DIMW 0x60 + COP_BASE +#define DIMH 0x62 + COP_BASE +#define SRC1BASE 0x70 + COP_BASE +#define DSTXROT 0x78 + COP_BASE +#define DSTYROT 0x7A + COP_BASE +#define PATYROT 0x7A + COP_BASE +#define PIXOP 0x7C + COP_BASE +#define PIXOP_LO 0x7C + COP_BASE +#define PIXOP_HI 0x7E + COP_BASE + + /* Direction */ + #define YMAJOR 0x1 + #define DEC_Y 0x2 + #define DY_NEG 0x2 + #define DEC_X 0x4 + #define DX_NEG 0x4 + #define ERRORTERM_POS 0x8 + + /* Draw mode */ + #define DRAW_1ST_PIXEL_NULL 0x10 + #define DRAW_LAST_PIXEL_NULL 0x20 + #define DRAW_AREA_BOUND 0x30 + + /* transparent mode */ + #define TRANS_IS_SRC1 0x0000 + #define TRANS_IS_SRC2 0x0100 + #define TRANS_IS_DST 0x0200 + #define TRANS_INVERT 0x0400 + #define TRANS_ENABLE 0x0800 + + /* Cop Operation */ + #define PAT_OPAQUE_TEXTOUT 0x1000 + #define PAT_OPAQUE_TILE 0x2000 + #define PAT_OPAQUE_LINE 0x3000 + #define PAT_TRANS_TEXTOUT 0x5000 + #define PAT_TRANS_TILE 0x6000 + #define PAT_TRANS_LINE 0x7000 + #define PAT_FIXFGD 0x8000 + #define PAT_COLOR_TILE 0x9000 + + /* Host-Mem Direction */ + #define HOST_READ_SRC1 0x10000 + #define HOST_WRITE_SRC1 0x20000 + #define HOST_WRITE_SRC2 0x30000 + + /* Source2 Select */ + #define SRC2_IS_COLOR 0x000000 + #define SRC2_IS_OPAQUE_MONO 0x100000 + #define SRC2_IS_FGDCOLOR 0x200000 + #define SRC2_IS_TRANS_MONO 0x500000 + + /* Cop Command */ + #define COP_STEP_DRAW 0x4000000 + #define COP_LINE_DRAW 0x5000000 + #define COP_PXBLT 0x8000000 + #define COP_INVERT_PXBLT 0x9000000 + #define COP_PXBLT256 0xB000000 + + /* Fore&Back */ + #define FGD_IS_SRC1 0x20000000 + #define FGD_IS_COLOR 0x00000000 + #define BGD_IS_SRC1 0x80000000 + #define BGD_IS_COLOR 0x00000000 + +#define SRC2WIDTH 0x118 + COP_BASE +#define COPFLAGS 0x130 + COP_BASE + #define FMONO_ENABLE 0x10 + #define FMONO_DISABLE 0xEF + #define COP_1WS 0x4 + +#define FASTMONOSIZE 0x13C + COP_BASE +#define PATXROT 0x150 + COP_BASE +#define SRC1PTR 0x170 + COP_BASE +#define SRC2PTR 0x174 + COP_BASE +#define DSTPTR 0x178 + COP_BASE +#define DSTWIDTH 0x218 + COP_BASE + +/* ---------------------------------------------------------------------- */ + +#define PORT46E8 0x46E8 /* R */ +#define PORT102 0x102 /* R/W */ +#define MISCREAD 0x3CC /* R */ +#define MISCWRITE 0x3C2 /* W */ +#define SEQINDEX 0x3C4 /* R/W */ +#define SEQDATA 0x3C5 /* R/W */ +#define CRTINDEX 0x3D4 /* R/W */ +#define CRTDATA 0x3D5 /* R/W */ +#define ATTRRESET 0x3DA /* R/W */ +#define ATTRINDEX 0x3C0 /* R/W */ +#define ATTRDATAW 0x3C0 /* W, Attrib write data port */ +#define ATTRDATAR 0x3C1 /* R, Attrib read data port */ +#define GRAINDEX 0x3CE /* R/W */ +#define GRADATA 0x3CF /* R/W */ +#define RAMDACMASK 0x3C6 /* R/W, Mask register */ +#define RAMDACINDEXR 0x3C7 /* R/W, RAM read index port */ +#define RAMDACINDEXW 0x3C8 /* R/W, RAM write index port */ +#define RAMDACDATA 0x3C9 /* R/W, RAM Date port */ +#define IGS3CEINDEX 0x3CE /* R/W */ +#define IGS3CFDATA 0x3CF /* R/W */ +#define IGS3D4INDEX 0x3D4 /* R/W */ +#define IGS3D5DATA 0x3D5 /* R/W */ +#define IGS3C4INDEX 0x3C4 /* R/W */ +#define IGS3C5DATA 0x3C5 /* R/W */ + +#define SEQCOUNT 0x05 +#define MISCCOUNT 0x01 +#define CRTCOUNT 0x19 +#define ATTRCOUNT 0x15 +#define GRACOUNT 0x09 +#define EXTPARTIALCOUNT 8 /* define 8 extended regs for color depth change */ + +#define SREGCOUNT SEQCOUNT+MISCCOUNT+CRTCOUNT+ATTRCOUNT+GRACOUNT +#define EREGCOUNT EXTPARTIALCOUNT * 2 + 1 + + +#define PIXFORMAT_8BPP 0 +#define PIXFORMAT_16BPP 1 +#define PIXFORMAT_24BPP 2 + +#define VISUALID_256 1 +#define VISUALID_64K 2 +#define VISUALID_16M 4 +#define VISUALID_32K 6 + +#define FUNC_CTL 0x3c +#define FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */ + +#define BIU_BM_CONTROL 0x3e +#define BIU_BM_CONTROL_ENABLE 0x01 /* enable bus-master */ +#define BIU_BM_CONTROL_BURST 0x02 /* enable burst */ +#define BIU_BM_CONTROL_BACK2BACK 0x04 /* enable back to back */ + +#define X_V2_VID_MEM_START 0x40 +#define X_V2_VID_SRC_WIDTH 0x43 +#define X_V2_X_START 0x45 +#define X_V2_X_END 0x47 +#define X_V2_Y_START 0x49 +#define X_V2_Y_END 0x4b +#define X_V2_VID_SRC_WIN_WIDTH 0x4d + +#define Y_V2_DDA_X_INC 0x43 +#define Y_V2_DDA_Y_INC 0x47 +#define Y_V2_VID_FIFO_CTL 0x49 +#define Y_V2_VID_FMT 0x4b +#define Y_V2_VID_DISP_CTL1 0x4c +#define Y_V2_VID_FIFO_CTL1 0x4d + +#define J_X2_VID_MEM_START 0x40 +#define J_X2_VID_SRC_WIDTH 0x43 +#define J_X2_X_START 0x47 +#define J_X2_X_END 0x49 +#define J_X2_Y_START 0x4b +#define J_X2_Y_END 0x4d +#define J_X2_VID_SRC_WIN_WIDTH 0x4f + +#define K_X2_DDA_X_INIT 0x40 +#define K_X2_DDA_X_INC 0x42 +#define K_X2_DDA_Y_INIT 0x44 +#define K_X2_DDA_Y_INC 0x46 +#define K_X2_VID_FMT 0x48 +#define K_X2_VID_DISP_CTL1 0x49 + +#define K_CAP_X2_CTL1 0x49 + +#define CAP_X_START 0x60 +#define CAP_X_END 0x62 +#define CAP_Y_START 0x64 +#define CAP_Y_END 0x66 +#define CAP_DDA_X_INIT 0x68 +#define CAP_DDA_X_INC 0x6a +#define CAP_DDA_Y_INIT 0x6c +#define CAP_DDA_Y_INC 0x6e + +#define MEM_CTL2 0x72 +#define MEM_CTL2_SIZE_2MB 0x01 +#define MEM_CTL2_SIZE_4MB 0x02 +#define MEM_CTL2_SIZE_MASK 0x03 +#define MEM_CTL2_64BIT 0x04 + +#define EXT_FIFO_CTL 0x74 + +#define CAP_PIP_X_START 0x80 +#define CAP_PIP_X_END 0x82 +#define CAP_PIP_Y_START 0x84 +#define CAP_PIP_Y_END 0x86 + +#define CAP_NEW_CTL1 0x88 + +#define CAP_NEW_CTL2 0x89 + +#define BM_CTRL0 0x9c +#define BM_CTRL1 0x9d + +#define CAP_MODE1 0xa4 +#define CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */ +#define CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */ +#define CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */ +#define CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */ +#define CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */ +#define CAP_MODE1_MIRRORY 0x40 /* mirror vertically */ +#define CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */ + +#define CAP_MODE2 0xa5 + +#define Y_TV_CTL 0xae + +#define EXT_MEM_START 0xc0 /* ext start address 21 bits */ +#define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */ +#define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */ +#define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */ +#define EXT_X_START 0xc5 /* ext->screen, 16 bits */ +#define EXT_X_END 0xc7 /* ext->screen, 16 bits */ +#define EXT_Y_START 0xc9 /* ext->screen, 16 bits */ +#define EXT_Y_END 0xcb /* ext->screen, 16 bits */ +#define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */ +#define EXT_COLOUR_COMPARE 0xce /* 24 bits */ +#define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */ +#define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */ +#define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */ +#define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */ + +#define EXT_VID_FIFO_CTL 0xd9 + +#define EXT_VID_FMT 0xdb +#define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */ +#define EXT_VID_FMT_RGB555 0x01 +#define EXT_VID_FMT_RGB565 0x02 +#define EXT_VID_FMT_RGB888_24 0x03 +#define EXT_VID_FMT_RGB888_32 0x04 +#define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */ +#define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */ +#define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */ +#define EXT_VID_FMT_UV128 0x80 /* UV data offset by 128 */ + +#define EXT_VID_DISP_CTL1 0xdc +#define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */ +#define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */ +#define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */ +#define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */ +#define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 */ +#define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* vertical interpolation off */ +#define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */ +#define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */ + +#define EXT_VID_FIFO_CTL1 0xdd + +#define VFAC_CTL1 0xe8 +#define VFAC_CTL1_CAPTURE 0x01 /* capture enable */ +#define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */ +#define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */ +#define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */ +#define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */ +#define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */ +#define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */ + +#define VFAC_CTL2 0xe9 +#define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */ +#define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */ +#define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */ +#define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */ +#define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */ +#define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */ +#define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */ +#define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */ + +#define VFAC_CTL3 0xea +#define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */ + +#define CAP_MEM_START 0xeb /* 18 bits */ +#define CAP_MAP_WIDTH 0xed /* high 6 bits */ +#define CAP_PITCH 0xee /* 8 bits */ + +#define CAP_CTL_MISC 0xef +#define CAP_CTL_MISC_HDIV 0x01 +#define CAP_CTL_MISC_HDIV4 0x02 +#define CAP_CTL_MISC_ODDEVEN 0x04 +#define CAP_CTL_MISC_HSYNCDIV2 0x08 +#define CAP_CTL_MISC_SYNCTZHIGH 0x10 +#define CAP_CTL_MISC_SYNCTZOR 0x20 +#define CAP_CTL_MISC_DISPUSED 0x80 + +#define REG_BANK 0xfa +#define REG_BANK_X 0x00 +#define REG_BANK_Y 0x01 +#define REG_BANK_W 0x02 +#define REG_BANK_T 0x03 +#define REG_BANK_J 0x04 +#define REG_BANK_K 0x05 + +/* + * Bus-master + */ +#define BM_VID_ADDR_LOW 0xbc040 +#define BM_VID_ADDR_HIGH 0xbc044 +#define BM_ADDRESS_LOW 0xbc080 +#define BM_ADDRESS_HIGH 0xbc084 +#define BM_LENGTH 0xbc088 +#define BM_CONTROL 0xbc08c +#define BM_CONTROL_ENABLE 0x01 /* enable transfer */ +#define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */ +#define BM_CONTROL_INIT 0x04 /* initialise status & count */ +#define BM_COUNT 0xbc090 /* read-only */ + +/* + * Graphics Co-processor + */ +#define CO_CMD_L_PATTERN_FGCOL 0x8000 +#define CO_CMD_L_INC_LEFT 0x0004 +#define CO_CMD_L_INC_UP 0x0002 + +#define CO_CMD_H_SRC_PIXMAP 0x2000 +#define CO_CMD_H_BLITTER 0x0800 + +#define CO_REG_CONTROL 0xbf011 +#define CO_REG_SRC_WIDTH 0xbf018 +#define CO_REG_PIX_FORMAT 0xbf01c +#define CO_REG_FORE_MIX 0xbf048 +#define CO_REG_FOREGROUND 0xbf058 +#define CO_REG_WIDTH 0xbf060 +#define CO_REG_HEIGHT 0xbf062 +#define CO_REG_X_PHASE 0xbf078 +#define CO_REG_CMD_L 0xbf07c +#define CO_REG_CMD_H 0xbf07e +#define CO_REG_SRC_PTR 0xbf170 +#define CO_REG_DEST_PTR 0xbf178 +#define CO_REG_DEST_WIDTH 0xbf218 + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/Makefile.am b/Source/DirectFB/gfxdrivers/davinci/Makefile.am new file mode 100755 index 0000000..d291092 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/Makefile.am @@ -0,0 +1,77 @@ +## Makefile.am for DirectFB/src/core/gfxcards/davinci + +EXTRA_DIST = \ + directfbrc \ + Makefile.kernel \ + kernel-module/c64x/Makefile \ + kernel-module/c64x/c64x.c \ + kernel-module/Makefile \ + kernel-module/include/linux/c64x.h \ + patches/ti-davinci-2.6.10-mvl401-fbio_set_start.patch + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems \ + -I$(srcdir)/kernel-module/include + +bin_PROGRAMS = c64xdump + +lib_LTLIBRARIES = libdavinci_c64x.la + +davinci_LTLIBRARIES = libdirectfb_davinci.la + +if BUILD_STATIC +davinci_DATA = $(davinci_LTLIBRARIES:.la=.o) +endif + +davincidir = $(MODULEDIR)/gfxdrivers +includedir = @INCLUDEDIR@ +includelinuxdir = @INCLUDEDIR@/linux + +include_HEADERS = \ + davincifb.h \ + davinci_c64x.h \ + davinci_gfxdriver.h + +includelinux_HEADERS = \ + kernel-module/include/linux/c64x.h + +libdavinci_c64x_la_SOURCES = \ + davinci_c64x.c + +libdavinci_c64x_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la + +libdirectfb_davinci_la_SOURCES = \ + davinci_2d.c \ + davinci_2d.h \ + davinci_gfxdriver.c \ + davinci_osd.c \ + davinci_osd.h \ + davinci_osd_pool.c \ + davinci_osd_pool.h \ + davinci_screen.c \ + davinci_screen.h \ + davinci_video.c \ + davinci_video.h \ + davinci_video_pool.c \ + davinci_video_pool.h + +libdirectfb_davinci_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_davinci_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la \ + $(builddir)/libdavinci_c64x.la + +c64xdump_SOURCES = c64xdump.c +c64xdump_LDADD = $(top_builddir)/lib/direct/libdirect.la + +include $(top_srcdir)/rules/libobject.make diff --git a/Source/DirectFB/gfxdrivers/davinci/Makefile.in b/Source/DirectFB/gfxdrivers/davinci/Makefile.in new file mode 100755 index 0000000..9e46327 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/Makefile.in @@ -0,0 +1,771 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +bin_PROGRAMS = c64xdump$(EXEEXT) +DIST_COMMON = $(include_HEADERS) $(includelinux_HEADERS) \ + $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/davinci +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(davincidir)" "$(DESTDIR)$(libdir)" \ + "$(DESTDIR)$(bindir)" "$(DESTDIR)$(davincidir)" \ + "$(DESTDIR)$(includedir)" "$(DESTDIR)$(includelinuxdir)" +davinciLTLIBRARIES_INSTALL = $(INSTALL) +libLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(davinci_LTLIBRARIES) $(lib_LTLIBRARIES) +libdavinci_c64x_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la +am_libdavinci_c64x_la_OBJECTS = davinci_c64x.lo +libdavinci_c64x_la_OBJECTS = $(am_libdavinci_c64x_la_OBJECTS) +libdirectfb_davinci_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la \ + $(builddir)/libdavinci_c64x.la +am_libdirectfb_davinci_la_OBJECTS = davinci_2d.lo davinci_gfxdriver.lo \ + davinci_osd.lo davinci_osd_pool.lo davinci_screen.lo \ + davinci_video.lo davinci_video_pool.lo +libdirectfb_davinci_la_OBJECTS = $(am_libdirectfb_davinci_la_OBJECTS) +libdirectfb_davinci_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_davinci_la_LDFLAGS) $(LDFLAGS) -o $@ +binPROGRAMS_INSTALL = $(INSTALL_PROGRAM) +PROGRAMS = $(bin_PROGRAMS) +am_c64xdump_OBJECTS = c64xdump.$(OBJEXT) +c64xdump_OBJECTS = $(am_c64xdump_OBJECTS) +c64xdump_DEPENDENCIES = $(top_builddir)/lib/direct/libdirect.la +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdavinci_c64x_la_SOURCES) \ + $(libdirectfb_davinci_la_SOURCES) $(c64xdump_SOURCES) +DIST_SOURCES = $(libdavinci_c64x_la_SOURCES) \ + $(libdirectfb_davinci_la_SOURCES) $(c64xdump_SOURCES) +davinciDATA_INSTALL = $(INSTALL_DATA) +DATA = $(davinci_DATA) +includeHEADERS_INSTALL = $(INSTALL_HEADER) +includelinuxHEADERS_INSTALL = $(INSTALL_HEADER) +HEADERS = $(include_HEADERS) $(includelinux_HEADERS) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = 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+ mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-binPROGRAMS \ + uninstall-davinciDATA uninstall-davinciLTLIBRARIES \ + uninstall-includeHEADERS uninstall-includelinuxHEADERS \ + uninstall-libLTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/davinci/Makefile.kernel b/Source/DirectFB/gfxdrivers/davinci/Makefile.kernel new file mode 100755 index 0000000..f58d56e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/Makefile.kernel @@ -0,0 +1,6 @@ +CROSS_COMPILE = arm-v4t-linux-gnueabi- +KERNEL_SOURCE = $(shell pwd)/../../../linux-davinci-2.6 +KERNEL_BUILD = $(KERNEL_SOURCE) + +all: + $(MAKE) -C kernel-module KERNEL_SOURCE=$(KERNEL_SOURCE) KERNEL_BUILD=$(KERNEL_BUILD) diff --git a/Source/DirectFB/gfxdrivers/davinci/c64xdump.c b/Source/DirectFB/gfxdrivers/davinci/c64xdump.c new file mode 100755 index 0000000..f70c8e0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/c64xdump.c @@ -0,0 +1,117 @@ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define C64X_DEVICE "/dev/c64x" +#define C64X_DEVICE0 "/dev/c64x0" +#define C64X_QLEN direct_page_align( sizeof(c64xTaskControl) ) +#define C64X_MLEN direct_page_align( 0x2000000 ) + +static const char *state_names[] = { "DONE", "ERROR", "TODO", "RUNNING" }; + +// manual (examples) +//#define DAVINCI_C64X_IDLE_MAX (567087584/10) +//#define DAVINCI_C64X_IDLE_MAX (59457217) + +// auto +#ifndef DAVINCI_C64X_IDLE_MAX +#define DAVINCI_C64X_IDLE_MAX (0) +#endif + +int main (int argc, char *argv[]) +{ + int fd; + void *mem; + c64xTaskControl *ctl; + c64xTask *queue; + int idle_max = DAVINCI_C64X_IDLE_MAX; + uint32_t idle_last = 0; + long long stamp_last = 0; + + fd = direct_try_open( C64X_DEVICE, C64X_DEVICE0, O_RDONLY, true ); + if (fd < 0) + return -1; + + ctl = mmap( NULL, C64X_QLEN, PROT_READ, MAP_SHARED, fd, 0 ); + if (ctl == MAP_FAILED) { + D_PERROR( "C64XDump: Mapping %lu bytes at %lu via '%s' failed!\n", C64X_QLEN, 0UL, C64X_DEVICE ); + close( fd ); + return -2; + } + + mem = mmap( NULL, C64X_MLEN, PROT_READ, MAP_SHARED, fd, C64X_QLEN ); + if (mem == MAP_FAILED) { + D_PERROR( "C64XDump: Mapping %lu bytes at %lu via '%s' failed!\n", C64X_MLEN, C64X_QLEN, C64X_DEVICE ); + munmap( (void*)ctl, C64X_QLEN ); + close( fd ); + return -2; + } + + queue = mem + (0x8fe00000 - 0x8e000000); + + while (1) { + usleep( 250000 ); + + int loadx = 1000; + uint32_t counter = ctl->idlecounter; + long long stamp = direct_clock_get_abs_micros(); + uint32_t ql_dsp = ctl->QL_dsp; + uint32_t ql_arm = ctl->QL_arm; + uint32_t qh_dsp = ctl->QH_dsp; + uint32_t qh_arm = ctl->QH_arm; + uint32_t task = queue[ql_dsp & C64X_QUEUE_MASK].c64x_function; + int dl, dh; + + dl = ql_arm - ql_dsp; + if (dl < 0) + dl += C64X_QUEUE_LENGTH; + + dh = qh_arm - qh_dsp; + if (dh < 0) + dh += C64X_QUEUE_LENGTH; + + printf( "\e[H\e[J" ); + printf( "High Q: arm %5d - dsp %5d = %d\n", qh_arm, qh_dsp, dh ); + printf( "Low Q: arm %5d - dsp %5d = %d\n", ql_arm, ql_dsp, dl ); + + printf( " (%08x: func %d - %s)\n", + task, (task >> 2) & 0x3fff, state_names[task & 3] ); + + printf( "Counter: %u\n", counter ); + + if (counter >= idle_last && idle_last) { + long long int cdiff = counter - idle_last; + long long int tdiff = stamp - stamp_last; + + long long int diff = cdiff * 1200000 / tdiff; + +#if !DAVINCI_C64X_IDLE_MAX + if (diff > idle_max) + idle_max = diff; +#endif + + loadx = (idle_max - diff) * 1000 / idle_max; + } + + if (idle_max) + printf( "Load: %d.%d%% (idle_max %d)\n", loadx / 10, loadx % 10, idle_max ); + + idle_last = counter; + stamp_last = stamp; + } + + + munmap( (void*)mem, C64X_MLEN ); + munmap( (void*)ctl, C64X_QLEN ); + close( fd ); + + return 0; +} diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_2d.c b/Source/DirectFB/gfxdrivers/davinci/davinci_2d.c new file mode 100755 index 0000000..7b97fb7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_2d.c @@ -0,0 +1,1050 @@ +/* + TI Davinci driver - 2D Acceleration + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "davinci_2d.h" +#include "davinci_gfxdriver.h" + + +D_DEBUG_DOMAIN( Davinci_2D, "Davinci/2D", "Davinci 2D Acceleration" ); + +/* + * State validation flags. + * + * There's no prefix because of the macros below. + */ +enum { + DESTINATION = 0x00000001, + FILLCOLOR = 0x00000002, + + SOURCE = 0x00000010, + SOURCE_MULT = 0x00000020, + + BLIT_BLEND_SUB = 0x00010000, + DRAW_BLEND_SUB = 0x00020000, + + ALL = 0x00030033 +}; + +/* + * State handling macros. + */ + +#define DAVINCI_VALIDATE(flags) do { ddev->v_flags |= (flags); } while (0) +#define DAVINCI_INVALIDATE(flags) do { ddev->v_flags &= ~(flags); } while (0) + +#define DAVINCI_CHECK_VALIDATE(flag) do { \ + if (! (ddev->v_flags & flag)) \ + davinci_validate_##flag( ddev, state ); \ + } while (0) + +/**************************************************************************************************/ + +static bool davinciFillRectangle16( void *drv, + void *dev, + DFBRectangle *rect ); + +static bool davinciFillRectangle32( void *drv, + void *dev, + DFBRectangle *rect ); + +static bool davinciFillRectangleBlend32( void *drv, + void *dev, + DFBRectangle *rect ); + +static bool davinciBlit16 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +static bool davinciBlit32to16 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +static bool davinciBlit32 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +static bool davinciBlitKeyed16 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +static bool davinciBlitKeyed32 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +static bool davinciBlitBlend32 ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +/**************************************************************************************************/ + +static inline int +get_blit_blend_sub_function( const CardState *state ) +{ + DFBSurfaceBlittingFlags flags = state->blittingflags & ~DSBLIT_COLORIZE; + + if (state->dst_blend == DSBF_INVSRCALPHA) { + switch (state->src_blend) { + case DSBF_SRCALPHA: + if (flags == DSBLIT_BLEND_ALPHACHANNEL) + return C64X_BLEND_SRC_INVSRC; + break; + + case DSBF_ONE: + switch (flags) { + case DSBLIT_BLEND_ALPHACHANNEL: + return C64X_BLEND_ONE_INVSRC; + + case DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_SRC_PREMULTIPLY: + return C64X_BLEND_ONE_INVSRC_PREMULT_SRC; + + case DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_BLEND_COLORALPHA | + DSBLIT_SRC_PREMULTCOLOR: + return C64X_BLEND_ONE_INVSRC_PREMULT_ALPHA; + + default: + break; + } + break; + + default: + break; + } + } + + return -1; +} + +static inline int +get_draw_blend_sub_function( const CardState *state ) +{ + DFBSurfaceDrawingFlags flags = state->drawingflags; + + if (state->dst_blend == DSBF_INVSRCALPHA) { + switch (state->src_blend) { + case DSBF_SRCALPHA: + if (flags == DSDRAW_BLEND) + return C64X_BLEND_SRC_INVSRC; + break; + + case DSBF_ONE: + switch (flags) { + case DSDRAW_BLEND: + return C64X_BLEND_ONE_INVSRC; + + case DSDRAW_BLEND | + DSDRAW_SRC_PREMULTIPLY: + return C64X_BLEND_ONE_INVSRC_PREMULT_SRC; + + default: + break; + } + break; + + default: + break; + } + } + + return -1; +} + +/**************************************************************************************************/ + +/* + * Called by davinciSetState() to ensure that the destination registers are properly set + * for execution of rendering functions. + */ +static inline void +davinci_validate_DESTINATION( DavinciDeviceData *ddev, + CardState *state ) +{ + /* Remember destination parameters for usage in rendering functions. */ + ddev->dst_addr = state->dst.addr; + ddev->dst_phys = state->dst.phys; + ddev->dst_size = state->dst.allocation->size; + ddev->dst_pitch = state->dst.pitch; + ddev->dst_format = state->dst.buffer->format; + ddev->dst_bpp = DFB_BYTES_PER_PIXEL( ddev->dst_format ); + + D_DEBUG_AT( Davinci_2D, " => DESTINATION: 0x%08lx\n", ddev->dst_phys ); + + /* Set the flag. */ + DAVINCI_VALIDATE( DESTINATION ); +} + +/* + * Called by davinciSetState() to ensure that the color register is properly set + * for execution of rendering functions. + */ +static inline void +davinci_validate_FILLCOLOR( DavinciDeviceData *ddev, + CardState *state ) +{ + switch (ddev->dst_format) { + case DSPF_ARGB: + case DSPF_RGB32: + ddev->fillcolor = ddev->color_argb; + break; + + case DSPF_RGB16: + ddev->fillcolor = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + + ddev->fillcolor |= ddev->fillcolor << 16; + break; + + case DSPF_UYVY: { + int y, u, v; + + RGB_TO_YCBCR( state->color.r, state->color.g, state->color.b, y, u, v ); + + ddev->fillcolor = PIXEL_UYVY( y, u, v ); + break; + } + + default: + D_BUG( "unexpected format %s", dfb_pixelformat_name(ddev->dst_format) ); + return; + } + + D_DEBUG_AT( Davinci_2D, " => FILLCOLOR: 0x%08lx\n", ddev->fillcolor ); + + /* Set the flag. */ + DAVINCI_VALIDATE( FILLCOLOR ); +} + +/* + * Called by davinciSetState() to ensure that the source registers are properly set + * for execution of blitting functions. + */ +static inline void +davinci_validate_SOURCE( DavinciDeviceData *ddev, + CardState *state ) +{ + /* Remember source parameters for usage in rendering functions. */ + ddev->src_addr = state->src.addr; + ddev->src_phys = state->src.phys; + ddev->src_pitch = state->src.pitch; + ddev->src_format = state->src.buffer->format; + ddev->src_bpp = DFB_BYTES_PER_PIXEL( ddev->src_format ); + + D_DEBUG_AT( Davinci_2D, " => SOURCE: 0x%08lx\n", ddev->src_phys ); + + /* Set the flag. */ + DAVINCI_VALIDATE( SOURCE ); +} + +/* + * Called by davinciSetState() to ensure that the source ARGB modulation is properly set + * for execution of blitting functions. + */ +static inline void +davinci_validate_SOURCE_MULT( DavinciDeviceData *ddev, + CardState *state ) +{ + switch (ddev->dst_format) { + case DSPF_ARGB: + if (state->blittingflags & DSBLIT_COLORIZE) + ddev->source_mult = 0xff000000 | ddev->color_argb; + else + ddev->source_mult = 0xffffffff; + break; + + default: + D_BUG( "unexpected format %s", dfb_pixelformat_name(ddev->dst_format) ); + return; + } + + D_DEBUG_AT( Davinci_2D, " => SOURCE_MULT: 0x%08lx\n", ddev->source_mult ); + + /* Set the flag. */ + DAVINCI_VALIDATE( SOURCE_MULT ); +} + +/* + * Called by davinciSetState() to ensure that the blend sub function index is valid + * for execution of blitting functions. + */ +static inline void +davinci_validate_BLIT_BLEND_SUB( DavinciDeviceData *ddev, + CardState *state ) +{ + int index = get_blit_blend_sub_function( state ); + + if (index < 0) { + D_BUG( "unexpected state" ); + return; + } + + /* Set blend sub function index. */ + ddev->blit_blend_sub_function = index; + + D_DEBUG_AT( Davinci_2D, " => BLIT_BLEND_SUB: %d\n", index ); + + /* Set the flag. */ + DAVINCI_VALIDATE( BLIT_BLEND_SUB ); +} + +/* + * Called by davinciSetState() to ensure that the blend sub function index is valid + * for execution of drawing functions. + */ +static inline void +davinci_validate_DRAW_BLEND_SUB( DavinciDeviceData *ddev, + CardState *state ) +{ + int index = get_draw_blend_sub_function( state ); + + if (index < 0) { + D_BUG( "unexpected state" ); + return; + } + + /* Set blend sub function index. */ + ddev->draw_blend_sub_function = index; + + D_DEBUG_AT( Davinci_2D, " => DRAW_BLEND_SUB: %d\n", index ); + + /* Set the flag. */ + DAVINCI_VALIDATE( DRAW_BLEND_SUB ); +} + +/**************************************************************************************************/ + +/* + * Wait for the blitter to be idle. + * + * This function is called before memory that has been written to by the hardware is about to be + * accessed by the CPU (software driver) or another hardware entity like video encoder (by Flip()). + * It can also be called by applications explicitly, e.g. at the end of a benchmark loop to include + * execution time of queued commands in the measurement. + */ +DFBResult +davinciEngineSync( void *drv, void *dev ) +{ + DFBResult ret; + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s()\n", __FUNCTION__ ); + + if (!ddev->synced) { + D_DEBUG_AT( Davinci_2D, " -> syncing...\n" ); + + ret = davinci_c64x_wait_low( &ddrv->c64x ); + if (ret) { + D_DEBUG_AT( Davinci_2D, " -> ERROR (%s)\n", DirectFBErrorString(ret) ); + return ret; + } + + D_DEBUG_AT( Davinci_2D, " => syncing done.\n" ); + + ddev->synced = true; + } + else + D_DEBUG_AT( Davinci_2D, " => already synced!\n" ); + + return DFB_OK; +} + +/* + * Reset the graphics engine. + */ +void +davinciEngineReset( void *drv, void *dev ) +{ + D_DEBUG_AT( Davinci_2D, "%s()\n", __FUNCTION__ ); +} + +/* + * Start processing of queued commands if required. + * + * This function is called before returning from the graphics core to the application. + * Usually that's after each rendering function. The only functions causing multiple commands + * to be queued with a single emition at the end are DrawString(), TileBlit(), BatchBlit(), + * DrawLines() and possibly FillTriangle() which is emulated using multiple FillRectangle() calls. + */ +void +davinciEmitCommands( void *drv, void *dev ) +{ + DFBResult ret; + DavinciDeviceData *ddev = dev; + DavinciDriverData *ddrv = drv; + + D_DEBUG_AT( Davinci_2D, "%s()\n", __FUNCTION__ ); + + ret = davinci_c64x_emit_tasks( &ddrv->c64x, &ddrv->tasks, C64X_TEF_RESET ); + if (ret) + D_DERROR( ret, "Davinci/Driver: Error emitting local task buffer!\n" ); + + ddev->synced = false; +} + +/* + * Invalidate the DSP's read cache. + */ +void +davinciFlushTextureCache( void *drv, void *dev ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s()\n", __FUNCTION__ ); + + /* Bad workaround */ + davinci_c64x_blit_32( &ddrv->c64x, dfb_config->video_phys, 1024, dfb_config->video_phys, 1024, 256, 64 ); + + /* These don't work */ +// davinci_c64x_wb_inv_range( &ddrv->c64x, dfb_config->video_phys, +// dfb_config->video_length, 2 ); + +// davinci_c64x_wb_inv_range( &ddrv->c64x, ddev->fix[OSD0].smem_start, +// ddev->fix[OSD0].smem_len, 2 ); +} + +/* + * Check for acceleration of 'accel' using the given 'state'. + */ +void +davinciCheckState( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ) +{ + D_DEBUG_AT( Davinci_2D, "%s( state %p, accel 0x%08x ) <- dest %p\n", + __FUNCTION__, state, accel, state->destination ); + + /* Return if the desired function is not supported at all. */ + if (accel & ~(DAVINCI_SUPPORTED_DRAWINGFUNCTIONS | DAVINCI_SUPPORTED_BLITTINGFUNCTIONS)) + return; + + /* Return if the destination format is not supported. */ + switch (state->destination->config.format) { + case DSPF_UYVY: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + default: + return; + } + + /* Check if drawing or blitting is requested. */ + if (DFB_DRAWING_FUNCTION( accel )) { + /* Return if unsupported drawing flags are set. */ + if (state->drawingflags & ~DAVINCI_SUPPORTED_DRAWINGFLAGS) + return; + + /* Limited blending support. */ + if (state->drawingflags & (DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY)) { + if (state->destination->config.format != DSPF_ARGB) + return; + + if (get_draw_blend_sub_function( state ) < 0) + return; + } + } + else { + /* Return if unsupported blitting flags are set. */ + if (state->blittingflags & ~DAVINCI_SUPPORTED_BLITTINGFLAGS) + return; + + /* No other flags supported when color keying is used. */ + if ((state->blittingflags & DSBLIT_SRC_COLORKEY) && state->blittingflags != DSBLIT_SRC_COLORKEY) + return; + + /* Return if the source format is not supported. */ + switch (state->source->config.format) { + case DSPF_UYVY: + case DSPF_RGB16: + /* Only color keying for these formats. */ + if (state->blittingflags & ~DSBLIT_SRC_COLORKEY) + return; + /* No format conversion supported. */ + if (state->source->config.format != state->destination->config.format) + return; + break; + + case DSPF_RGB32: + /* Only color keying for these formats. */ + if (state->blittingflags & ~DSBLIT_SRC_COLORKEY) + return; + /* fall through */ + case DSPF_ARGB: + /* Only few blending combinations are valid. */ + if ((state->blittingflags & ~DSBLIT_SRC_COLORKEY) && get_blit_blend_sub_function( state ) < 0) + return; + /* Only ARGB/RGB32 -> RGB16 conversion (without any flag). */ + if (state->source->config.format != state->destination->config.format && + (state->destination->config.format != DSPF_RGB16 || state->blittingflags)) + return; + break; + + default: + return; + } + + /* Checks per function. */ + switch (accel) { + case DFXL_STRETCHBLIT: + /* No flags supported with StretchBlit(). */ + if (state->blittingflags) + return; + + /* Only (A)RGB at 32 bit supported. */ + if (state->source->config.format != DSPF_ARGB && state->source->config.format != DSPF_RGB32) + return; + + break; + + default: + break; + } + } + + /* Enable acceleration of the function. */ + state->accel |= accel; + + D_DEBUG_AT( Davinci_2D, " => accel 0x%08x\n", state->accel ); +} + +/* + * Make sure that the hardware is programmed for execution of 'accel' according to the 'state'. + */ +void +davinciSetState( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ) +{ + DavinciDeviceData *ddev = dev; + StateModificationFlags modified = state->mod_hw; + + D_DEBUG_AT( Davinci_2D, "%s( state %p, accel 0x%08x ) <- dest %p, modified 0x%08x\n", + __FUNCTION__, state, accel, state->destination, modified ); + + /* + * 1) Invalidate hardware states + * + * Each modification to the hw independent state invalidates one or more hardware states. + */ + + /* Simply invalidate all? */ + if (modified == SMF_ALL) { + D_DEBUG_AT( Davinci_2D, " <- ALL\n" ); + + DAVINCI_INVALIDATE( ALL ); + } + else if (modified) { + /* Invalidate destination settings. */ + if (modified & SMF_DESTINATION) { + D_DEBUG_AT( Davinci_2D, " <- DESTINATION | FILLCOLOR\n" ); + + DAVINCI_INVALIDATE( DESTINATION | FILLCOLOR ); + } + else if (modified & SMF_COLOR) { + D_DEBUG_AT( Davinci_2D, " <- FILLCOLOR\n" ); + + DAVINCI_INVALIDATE( FILLCOLOR ); + } + + /* Invalidate source settings. */ + if (modified & SMF_SOURCE) { + D_DEBUG_AT( Davinci_2D, " <- SOURCE\n" ); + + DAVINCI_INVALIDATE( SOURCE ); + } + + /* Invalidate source color(ize) settings. */ + if (modified & (SMF_BLITTING_FLAGS | SMF_COLOR)) { + D_DEBUG_AT( Davinci_2D, " <- SOURCE_MULT\n" ); + + DAVINCI_INVALIDATE( SOURCE_MULT ); + } + + /* Invalidate blend function for blitting. */ + if (modified & (SMF_BLITTING_FLAGS | SMF_SRC_BLEND | SMF_DST_BLEND)) { + D_DEBUG_AT( Davinci_2D, " <- BLIT_BLEND_SUB\n" ); + + DAVINCI_INVALIDATE( BLIT_BLEND_SUB ); + } + + /* Invalidate blend function for drawing. */ + if (modified & (SMF_DRAWING_FLAGS | SMF_SRC_BLEND | SMF_DST_BLEND)) { + D_DEBUG_AT( Davinci_2D, " <- DRAW_BLEND_SUB\n" ); + + DAVINCI_INVALIDATE( DRAW_BLEND_SUB ); + } + } + + /* + * Just keep these values, no computations needed here. + * Values used by state validation or rendering functions. + */ + ddev->blitting_flags = state->blittingflags; + ddev->clip = state->clip; + ddev->color = state->color; + ddev->colorkey = state->src_colorkey; + ddev->color_argb = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + + /* + * 2) Validate hardware states + * + * Each function has its own set of states that need to be validated. + */ + + /* Always requiring valid destination... */ + DAVINCI_CHECK_VALIDATE( DESTINATION ); + + /* Depending on the function... */ + switch (accel) { + case DFXL_FILLRECTANGLE: + D_DEBUG_AT( Davinci_2D, " -> FILLRECTANGLE\n" ); + + /* Validate blend sub function index for drawing... */ + if (state->drawingflags & (DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY)) + DAVINCI_CHECK_VALIDATE( DRAW_BLEND_SUB ); + else + /* ...or just validate fill color. */ + DAVINCI_CHECK_VALIDATE( FILLCOLOR ); + + /* Choose function. */ + switch (DFB_BYTES_PER_PIXEL( state->destination->config.format )) { + case 2: + funcs->FillRectangle = davinciFillRectangle16; + break; + + case 4: + if (state->drawingflags & (DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY)) + funcs->FillRectangle = davinciFillRectangleBlend32; + else + funcs->FillRectangle = davinciFillRectangle32; + break; + + default: + D_BUG( "unexpected destination bpp %d", + DFB_BYTES_PER_PIXEL( state->destination->config.format ) ); + break; + } + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set |= DAVINCI_SUPPORTED_DRAWINGFUNCTIONS; + break; + + case DFXL_BLIT: + D_DEBUG_AT( Davinci_2D, " -> BLIT\n" ); + + /* ...require valid source. */ + DAVINCI_CHECK_VALIDATE( SOURCE ); + + /* Validate blend sub function index for blitting. */ + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + DAVINCI_CHECK_VALIDATE( BLIT_BLEND_SUB ); + + /* Validate ARGB source modulator. */ + DAVINCI_CHECK_VALIDATE( SOURCE_MULT ); + } + + /* Choose function. */ + switch (DFB_BYTES_PER_PIXEL( state->destination->config.format )) { + case 2: + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + funcs->Blit = davinciBlitKeyed16; + else if (state->source->config.format == DSPF_ARGB || + state->source->config.format == DSPF_RGB32) + funcs->Blit = davinciBlit32to16; + else + funcs->Blit = davinciBlit16; + break; + + case 4: + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + funcs->Blit = davinciBlitKeyed32; + else if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + funcs->Blit = davinciBlitBlend32; + else + funcs->Blit = davinciBlit32; + break; + + default: + D_BUG( "unexpected destination bpp %d", + DFB_BYTES_PER_PIXEL( state->destination->config.format ) ); + break; + } + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set |= DFXL_BLIT; + break; + + case DFXL_STRETCHBLIT: + D_DEBUG_AT( Davinci_2D, " -> STRETCHBLIT\n" ); + + /* ...require valid source. */ + DAVINCI_CHECK_VALIDATE( SOURCE ); + + /* Choose function. */ +#if 0 // only 32bit, statically set in driver_init_driver() + switch (state->destination->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + funcs->StretchBlit = davinciStretchBlit32; + break; + + default: + D_BUG( "unexpected destination format %s", + dfb_pixelformat_name( state->destination->config.format ) ); + break; + } +#endif + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set |= DFXL_STRETCHBLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + /* + * 4) Clear modification flags + * + * All flags have been evaluated in 1) and remembered for further validation. + * If the hw independent state is not modified, this function won't get called + * for subsequent rendering functions, unless they aren't defined by 3). + */ + state->mod_hw = 0; +} + +/**********************************************************************************************************************/ +/**********************************************************************************************************************/ + +/* + * Render a filled rectangle using the current hardware state. + */ +static bool +davinciFillRectangle16( void *drv, void *dev, DFBRectangle *rect ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d )\n", __FUNCTION__, DFB_RECTANGLE_VALS(rect) ); + + /* FIXME: Optimize in DSP. */ + if ((rect->x | rect->w) & 1) + davinci_c64x_fill_16__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * rect->y + ddev->dst_bpp * rect->x, + ddev->dst_pitch, + rect->w, rect->h, + ddev->fillcolor ); + else + davinci_c64x_fill_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * rect->y + ddev->dst_bpp * rect->x, + ddev->dst_pitch, + rect->w/2, rect->h, + ddev->fillcolor ); + + return true; +} + +static bool +davinciFillRectangle32( void *drv, void *dev, DFBRectangle *rect ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d )\n", __FUNCTION__, DFB_RECTANGLE_VALS(rect) ); + + if (ddev->dst_format == DSPF_ARGB && ddev->color.a == 0xff) + davinci_c64x_blit_blend_32__L( &ddrv->tasks, + C64X_BLEND_ONE_INVSRC, + ddev->dst_phys + ddev->dst_pitch * rect->y + ddev->dst_bpp * rect->x, + ddev->dst_pitch, + 0, + 0, + rect->w, rect->h, + ddev->color_argb, + 0xff ); + else + davinci_c64x_fill_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * rect->y + ddev->dst_bpp * rect->x, + ddev->dst_pitch, + rect->w, rect->h, + ddev->fillcolor ); + + return true; +} + +/**********************************************************************************************************************/ + +static bool +davinciFillRectangleBlend32( void *drv, void *dev, DFBRectangle *rect ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d )\n", __FUNCTION__, DFB_RECTANGLE_VALS(rect) ); + + davinci_c64x_blit_blend_32__L( &ddrv->tasks, + ddev->draw_blend_sub_function, + ddev->dst_phys + ddev->dst_pitch * rect->y + ddev->dst_bpp * rect->x, + ddev->dst_pitch, + 0, + 0, + rect->w, rect->h, + ddev->color_argb, + 0xff ); + + return true; +} + +/**********************************************************************************************************************/ +/**********************************************************************************************************************/ + +/* + * Blit a rectangle using the current hardware state. + */ +static bool +davinciBlit16( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d )\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y ); + + /* FIXME: Optimize in DSP. */ + if ((dx | rect->x | rect->w) & 1) + davinci_c64x_blit_16__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h ); + else + davinci_c64x_blit_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w/2, rect->h ); + + return true; +} + +static bool +davinciBlit32( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d )\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y ); + + davinci_c64x_blit_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h ); + + return true; +} + +/**********************************************************************************************************************/ + +static bool +davinciBlit32to16( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d )\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y ); + + davinci_c64x_dither_argb__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + DAVINCI_C64X_MEM, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h ); + + return true; +} + +/**********************************************************************************************************************/ + +static bool +davinciBlitKeyed16( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d ) <- key 0x%04lx\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y, ddev->colorkey ); + + davinci_c64x_blit_keyed_16__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h, + ddev->colorkey, + (1 << DFB_COLOR_BITS_PER_PIXEL( ddev->dst_format )) - 1 ); + + return true; +} + +static bool +davinciBlitKeyed32( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d ) <- key 0x%08lx\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y, ddev->colorkey ); + + davinci_c64x_blit_keyed_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h, + ddev->colorkey, + (1 << DFB_COLOR_BITS_PER_PIXEL( ddev->dst_format )) - 1 ); + + return true; +} + +/**********************************************************************************************************************/ + +static bool +davinciBlitBlend32( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d )\n", + __FUNCTION__, dx, dy, rect->w, rect->h, rect->x, rect->y ); + + davinci_c64x_blit_blend_32__L( &ddrv->tasks, + ddev->blit_blend_sub_function, + ddev->dst_phys + ddev->dst_pitch * dy + ddev->dst_bpp * dx, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * rect->y + ddev->src_bpp * rect->x, + ddev->src_pitch, + rect->w, rect->h, + ddev->source_mult, + ddev->color.a ); + + return true; +} + +/**********************************************************************************************************************/ +/**********************************************************************************************************************/ + +bool +davinciStretchBlit32( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ) +{ + DavinciDriverData *ddrv = drv; + DavinciDeviceData *ddev = dev; + + DFBRegion clip = DFB_REGION_INIT_FROM_RECTANGLE( drect ); + + D_DEBUG_AT( Davinci_2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d-%4dx%4d )\n", + __FUNCTION__, DFB_RECTANGLE_VALS(drect), DFB_RECTANGLE_VALS(srect) ); + + if (!dfb_region_region_intersect( &clip, &ddev->clip )) + return true; + + dfb_region_translate( &clip, -drect->x, -drect->y ); + + davinci_c64x_stretch_32__L( &ddrv->tasks, + ddev->dst_phys + ddev->dst_pitch * drect->y + ddev->dst_bpp * drect->x, + ddev->dst_pitch, + ddev->src_phys + ddev->src_pitch * srect->y + ddev->src_bpp * srect->x, + ddev->src_pitch, + drect->w, drect->h, + srect->w, srect->h, + &clip ); + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_2d.h b/Source/DirectFB/gfxdrivers/davinci/davinci_2d.h new file mode 100755 index 0000000..881c179 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_2d.h @@ -0,0 +1,79 @@ +/* + TI Davinci driver - 2D Acceleration + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_2D_H__ +#define __DAVINCI_2D_H__ + + +#define DAVINCI_SUPPORTED_DRAWINGFLAGS (DSDRAW_BLEND |\ + DSDRAW_SRC_PREMULTIPLY) + +#define DAVINCI_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE) + +#define DAVINCI_SUPPORTED_BLITTINGFLAGS (DSBLIT_BLEND_ALPHACHANNEL |\ + DSBLIT_BLEND_COLORALPHA |\ + DSBLIT_COLORIZE |\ + DSBLIT_SRC_COLORKEY |\ + DSBLIT_SRC_PREMULTIPLY |\ + DSBLIT_SRC_PREMULTCOLOR) + +#define DAVINCI_SUPPORTED_BLITTINGFUNCTIONS (DFXL_BLIT | DFXL_STRETCHBLIT) + + +DFBResult davinciEngineSync ( void *drv, + void *dev ); + +void davinciEngineReset ( void *drv, + void *dev ); + +void davinciEmitCommands ( void *drv, + void *dev ); + +void davinciFlushTextureCache( void *drv, + void *dev ); + +void davinciCheckState ( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ); + +void davinciSetState ( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ); + +bool davinciStretchBlit32 ( void *drv, + void *dev, + DFBRectangle *srect, + DFBRectangle *drect ); + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.c b/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.c new file mode 100755 index 0000000..431ffdd --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.c @@ -0,0 +1,2053 @@ +/* + TI Davinci driver - C64X+ DSP Library + + (c) Copyright 2008 directfb.org + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp and + Olaf Dreesen . + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "davinci_c64x.h" + + +/**********************************************************************************************************************/ + +#define C64X_DEVICE "/dev/c64x" +#define C64X_DEVICE0 "/dev/c64x0" +#define C64X_QLEN direct_page_align( sizeof(c64xTaskControl) ) +#define C64X_MLEN direct_page_align( 0x2000000 ) + +__attribute__((noinline)) +static void +davinci_c64x_queue_error( DavinciC64x *c64x, const char *msg ) +{ + c64xTaskControl *ctl = c64x->ctl; + uint32_t dsp = ctl->QL_dsp; + uint32_t arm = ctl->QL_arm; + uint32_t armp = (arm-1) & C64X_QUEUE_MASK; + c64xTask *dsp_task = &c64x->QueueL[dsp]; + c64xTask *arm_task = &c64x->QueueL[arm]; + c64xTask *armp_task = &c64x->QueueL[armp]; + + D_PERROR( "Davinci/C64X+: %s [DSP %d / %d (%s), ARM %d / %d (%s) <- %d / %d (%s)]\n", + msg, + dsp, + (dsp_task->c64x_function >> 2) & 0x3fff, + state_names[dsp_task->c64x_function & 3], + arm, + (arm_task->c64x_function >> 2) & 0x3fff, + state_names[arm_task->c64x_function & 3], + armp, + (armp_task->c64x_function >> 2) & 0x3fff, + state_names[armp_task->c64x_function & 3] ); +} + +/* + +1. Idle Case + + ARM ARM + DSP DSP + | . . . . . . . . | | . . . . . . . . | free = length-1 + + +2. Busy Case (ARM after) + + ARM ARM + DSP DSP + | o . . . . . . . | | . o o . . . . . | free = length-1 - arm + dsp + + +3. Busy Case (ARM before) + + ARM ARM + DSP DSP + | . . . . . o o o | | o o . . . . . o | free = dsp - arm - 1 + + +4. Full Case (ARM after) + + ARM + DSP + | o o o o o o o . | free = 0 + + +5. Full Case (ARM before) + + ARM ARM + DSP DSP + | o o o o o . o o | | . o o o o o o o | free = 0 + +*/ + +DFBResult +davinci_c64x_emit_tasks( DavinciC64x *c64x, + DavinciC64xTasks *tasks, + DavinciC64xEmitFlags flags ) +{ + c64xTaskControl *ctl = c64x->ctl; + uint32_t arm = ctl->QL_arm; + unsigned int emitted = 0; + unsigned int timeout = 23; + + D_MAGIC_ASSERT( tasks, DavinciC64xTasks ); + + while (emitted < tasks->num_tasks) { + uint32_t dsp = ctl->QL_dsp; + int free; + + if (arm == dsp) + free = C64X_QUEUE_LENGTH - 1; + else if (arm > dsp) + free = C64X_QUEUE_LENGTH - 1 - arm + dsp; + else + free = dsp - arm - 1; + + if (free) { + int emit = MIN( free, tasks->num_tasks - emitted ); + int copy = MIN( emit, C64X_QUEUE_LENGTH - arm ); + + memcpy( (void*) &c64x->QueueL[arm], (void*) &tasks->tasks[emitted], sizeof(c64xTask) * copy ); + + if (copy < emit) { + memcpy( (void*) &c64x->QueueL[0], (void*) &tasks->tasks[emitted+copy], sizeof(c64xTask) * (emit - copy) ); + + arm = (emit - copy); + } + else + arm = (arm + copy) & C64X_QUEUE_MASK; + + mb(); + + ctl->QL_arm = arm; + + mb(); + + emitted += emit; + + timeout = 23; + } + else { + if (!timeout--) { + davinci_c64x_queue_error( c64x, "Emit Timeout!" ); + return DFB_TIMEOUT; + } + + usleep( 7000 ); + } + } + + if (flags & C64X_TEF_RESET) + tasks->num_tasks = 0; + + return DFB_OK; +} + +DFBResult +davinci_c64x_tasks_init( DavinciC64xTasks *tasks, + unsigned int size ) +{ + tasks->tasks = D_MALLOC( sizeof(c64xTask) * size ); + if (!tasks->tasks) + return D_OOM(); + + tasks->max_tasks = size; + tasks->num_tasks = 0; + + D_MAGIC_SET( tasks, DavinciC64xTasks ); + + return DFB_OK; +} + +DFBResult +davinci_c64x_tasks_destroy( DavinciC64xTasks *tasks ) +{ + D_MAGIC_ASSERT( tasks, DavinciC64xTasks ); + D_ASSERT( tasks->tasks != NULL ); + + D_FREE( (void*) tasks->tasks ); + + tasks->tasks = NULL; + + D_MAGIC_CLEAR( tasks ); + + return DFB_OK; +} + +DFBResult +davinci_c64x_wait_low( DavinciC64x *c64x ) +{ + DFBResult ret; + c64xTaskControl *ctl = c64x->ctl; + + while (ctl->QL_dsp != ctl->QL_arm) { + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_function = C64X_FLAG_TODO | C64X_FLAG_INTERRUPT; + + c64x_submit_task( c64x, task ); + + if (ioctl( c64x->fd, C64X_IOCTL_WAIT_LOW )) { + c64xTask *dsp_task = &c64x->QueueL[ctl->QL_dsp]; + + ret = errno2result( errno ); + D_PERROR( "Davinci/C64X+: C64X_IOCTL_WAIT_LOW failed! [DSP %d / %d (%s), ARM %d / %d (%s)]\n", + ctl->QL_dsp, + (dsp_task->c64x_function >> 2) & 0x3fff, + state_names[dsp_task->c64x_function & 3], + ctl->QL_arm, + (task->c64x_function >> 2) & 0x3fff, + state_names[task->c64x_function & 3] ); + return ret; + } + } + + return DFB_OK; +} + +/**********************************************************************************************************************/ +/* Benchmarking or Testing */ +/**********************************************************************************************************************/ + +#if 1 +#define BRINTF(x...) do { direct_log_printf( NULL, x ); } while (0) +#else +#define BRINTF(x...) printf( x ) +#endif + +static void +bench_mem( const char *name, + void *ptr, + int length, + bool copy, + bool from ) +{ + int i, num; + long long t1, t2, dt, total; + char buf[0x100]; + + if (length > sizeof(buf)) + length = sizeof(buf); + + num = 0x2000000 / length; + + t1 = direct_clock_get_abs_micros(); + + if (copy) { + if (from) + for (i=0; imem + 0x01000000; + int *src = c64x->mem + 0x01100000; + + +#if 0 + src[num++] = DVA_BLOCK_WORD( 100, 0, 1 ); + src[num++] = DVA_BLOCK_WORD( 200, 0, 0 ); + src[num++] = DVA_BLOCK_WORD( 210, 1, 0 ); + src[num++] = DVA_BLOCK_WORD( 220, 2, 1 ); + src[num++] = DVA_BLOCK_WORD( 300, 0, 1 ); + src[num++] = DVA_BLOCK_WORD( 400, 0, 0 ); + src[num++] = DVA_BLOCK_WORD( 410, 1, 1 ); + src[num++] = DVA_BLOCK_WORD( 500, 0, 0 ); + src[num++] = DVA_BLOCK_WORD( 510, 63, 1 ); + src[num++] = DVA_BLOCK_WORD( 600, 63, 1 ); +#else + src[num++] = DVA_BLOCK_WORD(136, 0, 0); + src[num++] = DVA_BLOCK_WORD(-12, 8, 0); + src[num++] = DVA_BLOCK_WORD(7, 16, 0); + src[num++] = DVA_BLOCK_WORD(-2, 24, 1); + + src[num++] = DVA_BLOCK_WORD(136, 0, 0); + src[num++] = DVA_BLOCK_WORD(-12, 8, 0); + src[num++] = DVA_BLOCK_WORD(7, 16, 0); + src[num++] = DVA_BLOCK_WORD(-2, 24, 1); + + + src[num++] = DVA_BLOCK_WORD(1076, 0, 0); + src[num++] = DVA_BLOCK_WORD(-204, 8, 0); + src[num++] = DVA_BLOCK_WORD(-168, 16, 0); + src[num++] = DVA_BLOCK_WORD(-129, 24, 0); + src[num++] = DVA_BLOCK_WORD(-100, 32, 0); + src[num++] = DVA_BLOCK_WORD(-40, 40, 0); + src[num++] = DVA_BLOCK_WORD(-14, 48, 1); +#if 1 + src[num++] = DVA_BLOCK_WORD(1068, 0, 0); + src[num++] = DVA_BLOCK_WORD(2, 1, 0); + src[num++] = DVA_BLOCK_WORD(-202, 8, 0); + src[num++] = DVA_BLOCK_WORD(-168, 16, 0); + src[num++] = DVA_BLOCK_WORD(-2, 9, 0); + src[num++] = DVA_BLOCK_WORD(-129, 24, 0); + src[num++] = DVA_BLOCK_WORD(-97, 32, 0); + src[num++] = DVA_BLOCK_WORD(-40, 40, 0); + src[num++] = DVA_BLOCK_WORD(-13, 48, 1); +#else + src[num++] = DVA_BLOCK_WORD(1068, 0, 0); +// src[num++] = DVA_BLOCK_WORD(2, 1, 0); + src[num++] = DVA_BLOCK_WORD(-202, 8, 0); + src[num++] = DVA_BLOCK_WORD(-1, 16, 0); +// src[num++] = DVA_BLOCK_WORD(-2, 9, 0); + src[num++] = DVA_BLOCK_WORD(-1, 24, 0); + src[num++] = DVA_BLOCK_WORD(-97, 32, 1); +// src[num++] = DVA_BLOCK_WORD(-40, 40, 0); +// src[num++] = DVA_BLOCK_WORD(-13, 48, 1); +#endif + + src[num++] = DVA_BLOCK_WORD(1048, 0, 0); + src[num++] = DVA_BLOCK_WORD(-26, 8, 0); + src[num++] = DVA_BLOCK_WORD(4, 16, 0); + src[num++] = DVA_BLOCK_WORD(5, 24, 0); + src[num++] = DVA_BLOCK_WORD(-4, 32, 1); + + src[num++] = DVA_BLOCK_WORD(996, 0, 0); + src[num++] = DVA_BLOCK_WORD(24, 8, 0); + src[num++] = DVA_BLOCK_WORD(-2, 24, 0); + src[num++] = DVA_BLOCK_WORD(3, 32, 0); + src[num++] = DVA_BLOCK_WORD(-4, 48, 1); +#endif + + BRINTF("\n"); + BRINTF("\n\n.======================== Testing load_block (dct_type_interlaced: %s) ========================.\n", + dct_type_interlaced ? "yes" : "no"); + BRINTF("\n"); + BRINTF( "SOURCE (DVABlockWords)\n" ); + BRINTF("\n"); + + for (i=0; i> 16, (src[i] >> 1) & 0x3f, src[i] & 1); + + BRINTF("\n\n"); + + + memset( dst, 0x55, 0x100000 ); + + + // test routine + davinci_c64x_load_block( c64x, DAVINCI_C64X_MEM+0x01100000, 10, dct_type_interlaced ? 0x7f : 0x3f ); + + // copy idct buffer to memory where we can read it + davinci_c64x_blit_16( c64x, DAVINCI_C64X_MEM+0x01000000, 0, 0xf065c0, 0, 16 * 24, 1 ); + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + + BRINTF( "-> IDCT BUFFER (16x16 + [ 8x8 8x8 ] shorts)\n" ); + BRINTF("\n"); + + for (i=0; i<16*24; i++) { + BRINTF("%5d ", dst[i] ); + if ((i&15)==15) { + BRINTF("\n"); + } + if ((i&255)==255) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); + +#if 1 + s16 *blocks = c64x->mem + 0x01200000; + int offset = 0; + + memset( blocks, 0, 1024 ); + + for (i=0; i> 1) & 0x3f)] = src[i] >> 16; + + if (src[i] & 1) + offset += 64; + } + + memset( dst, 0x55, 0x100000 ); + + // test routine + for (i=0; i<6; i++) + davinci_c64x_dva_idct( c64x, DAVINCI_C64X_MEM+0x01000000 + i*128, 16, DAVINCI_C64X_MEM+0x01200000 + i*128 ); + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + + BRINTF( "-> SINGLE IDCT (59) BLOCKS (6x 8x8 shorts)\n" ); + BRINTF("\n"); + + for (i=0; i<6*64; i++) { + BRINTF("%5d ", dst[i] ); + if ((i&7)==7) { + BRINTF("\n"); + } + if ((i&63)==63) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); +#endif + +#if 0 +// s16 blocks[384]; +// int offset = 0; + offset = 0; + + memset( blocks, 0, 1024 ); + + for (i=0; i> 1) & 0x3f)] = src[i] >> 16; + + if (src[i] & 1) { + int n; + + for (n = 0; n < 8; n++) + idct_row (blocks + offset + 8 * n); + + for (n = 0; n < 8; n++) + idct_col (blocks + offset + n); + + offset += 64; + } + } + + BRINTF( "-> REFERENCE IDCT BLOCKS (6x 8x8 shorts)\n" ); + BRINTF("\n"); + + for (i=0; i<6*64; i++) { + BRINTF("%5d ", blocks[i] ); + if ((i&7)==7) { + BRINTF("\n"); + } + if ((i&63)==63) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); +#endif +} + +static inline void +bench_dezigzag( DavinciC64x *c64x ) +{ + int i, num; + long long t1, t2, dt, total; + //int length = 0x10000; + + num = 0x200000;// / length; + + short *p = c64x->mem + 0x1000000; + + for (i=0; i<64; i++) { + p[i] = i; + BRINTF("%3d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_DEZIGZAG | C64X_FLAG_TODO; + + task->c64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x200000; + task->c64x_arg[1] = (DAVINCI_C64X_MEM+0x01000000)+0x000000; + //task->c64x_arg[2] = length/4; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + p = c64x->mem + 0x1200000; + for (i=0; i<64; i++) { + BRINTF("%3d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + dt = t2 - t1; + total = num;// * length; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "de_zigzag()", total * 1000000ULL / dt ); +} + +#define DUMP_PIXELS 1 + +static inline void +bench_blend_argb( DavinciC64x *c64x, int sub ) +{ + int i, num; + long long t1, t2, dt, total; + + num = 1;//0x20000; + + u32 *src = c64x->mem + 0x1000000; + u32 *dst = c64x->mem + 0x1200000; + + BRINTF( "\nTESTING BLEND_32 SUB %d\n", sub ); + + BRINTF( "\nSOURCE " ); + + for (i=0; i> 24, (src[i] >> 16) & 0xff, (src[i] >> 8) & 0xff, src[i] & 0xff); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF( "\nDESTINATION " ); + + for (i=0; i> 24, (dst[i] >> 16) & 0xff, (dst[i] >> 8) & 0xff, dst[i] & 0xff); + if (i%8==7) { + BRINTF("\n"); + } + } + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_BLEND_32 | C64X_FLAG_TODO | (sub << 16); + + task->c64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x200000; + task->c64x_arg[1] = 32; + task->c64x_arg[2] = (DAVINCI_C64X_MEM+0x01000000)+0x000000; + task->c64x_arg[3] = 32; + task->c64x_arg[4] = 8; + task->c64x_arg[5] = 8; + task->c64x_arg[6] = 0x80; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + BRINTF( "\n\nDESTINATION (AFTER) " ); + + for (i=0; i> 24, (dst[i] >> 16) & 0xff, (dst[i] >> 8) & 0xff, dst[i] & 0xff); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "blend_32(8x8)", total * 1000000ULL / dt ); +} + +static inline void +bench_fetch_uyvy( DavinciC64x *c64x, bool interleave, int xoff, int yoff ) { + int i, x, y, num=1; + long long t1, t2, dt, total; + u8 *yuv = c64x->mem + 0x1000000; + u8 *src = c64x->mem + 0x1200000; + + BRINTF("\n\n\n.======================== Testing fetch_uyvy (inter %d, xoff %d, yoff %d) ========================.\n\n", + interleave, xoff, yoff); + + for (y=0; y<20; y++) { + for (x=0; x<40; x++) { + int val = (y*40)+x; + src[y*1440 + x] = val; + BRINTF("%02x ", val&0xff); + } + BRINTF("\n"); + } + BRINTF("\n"); + + memset( yuv, 0xAA, 0x100000 ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x000000; + task->c64x_arg[1] = (DAVINCI_C64X_MEM+0x01000000)+0x200000 + yoff*1440 + xoff * 2; + task->c64x_arg[2] = 1440; + + task->c64x_function = (21 << 2) | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + BRINTF( "\n\nDESTINATION\n\nY:\n" ); + for (y=0;y<27;y++) { + if (y==18) BRINTF("\nUV:\n"); + for (x=0;x<32;x++) { + BRINTF("%02x ",yuv[y*32+x]); + } + BRINTF("\n"); + } + + dt = t2 - t1; + total = num; + + D_INFO("\n\nDavinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "blend_fetch_uyvy(16x16)", total * 1000000ULL / dt ); +} +#if 0 +static inline void +bench_fetch_uyvy( DavinciC64x *c64x, bool interleave, int xoff, int yoff ) +{ + int i, x, y, num; + long long t1, t2, dt, total; + + num = 1;//0x20000; + + u8 *yuv = c64x->mem + 0x1000000; + u8 *src = c64x->mem + 0x1200000; + + BRINTF("\n"); + BRINTF("\n\n.======================== Testing fetch_uyvy (inter %d, xoff %d, yoff %d) ========================.\n", + interleave, xoff, yoff); + BRINTF("\n"); + BRINTF( "SOURCE (20x20)\n" ); + + for (y=0; y<20; y++) { + for (x=0; x<40; x++) { + int val = (x & 1) ? (x * 4 + y*0x10) : (x/4 + 0x40 + (x&2) * 0x10 + y*0x08); + + src[y*1440 + x] = val; + + BRINTF("%02x ", val&0xff); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + memset( yuv, 0x55, 0x100000 ); + + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = (19 << 2) | C64X_FLAG_TODO; + + task->c64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x000000; + task->c64x_arg[1] = (DAVINCI_C64X_MEM+0x01000000)+0x200000 + yoff*1440 + xoff * 2; + task->c64x_arg[2] = 1440; + task->c64x_arg[3] = 16; + task->c64x_arg[4] = interleave ? 1 : 0; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + BRINTF( "\n\nDESTINATION (17x18 / [9x9 9x9])\n" ); + + for (y=0; y<18; y++) { + for (x=0; x<17; x++) { + BRINTF("%02x ", yuv[y*32 + x]); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<9; y++) { + for (x=0; x<9; x++) { + BRINTF("%02x ", yuv[y*32 + x + 32*18]); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<9; y++) { + for (x=0; x<9; x++) { + BRINTF("%02x ", yuv[y*32 + x + 32*18+16]); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + BRINTF("\n\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "blend_fetch_uyvy(16x16)", total * 1000000ULL / dt ); +} +#endif + +#if 0 +static inline void +bench_put_idct( DavinciC64x *c64x, int dct_type ) +{ + int i, num; + long long t1, t2, dt, total; + //int length = 0x10000; + + num = 0x10000;// / length; + + u8 *dst = c64x->mem + 0x01000000; + int *src = c64x->mem + 0x01200000; + + src[0] = DVA_BLOCK_WORD( 100, 0, 1 ); + src[1] = DVA_BLOCK_WORD( 200, 0, 0 ); + src[2] = DVA_BLOCK_WORD( 210, 1, 0 ); + src[3] = DVA_BLOCK_WORD( 220, 2, 1 ); + src[4] = DVA_BLOCK_WORD( 300, 0, 1 ); + src[5] = DVA_BLOCK_WORD( 400, 0, 0 ); + src[6] = DVA_BLOCK_WORD( 410, 1, 1 ); + src[7] = DVA_BLOCK_WORD( 500, 0, 0 ); + src[8] = DVA_BLOCK_WORD( 510, 63, 1 ); + src[9] = DVA_BLOCK_WORD( 600, 63, 1 ); + + BRINTF("\n"); + BRINTF("\n\n.======================== Testing put_idct (%d) ========================.\n", dct_type); + BRINTF("\n"); + + memset( dst, 0x55, 0x100000 ); + + for (i=0; i<10; i++) { + BRINTF("0x%08x (%d, %d, %d)\n", (u32)src[i], src[i] >> 16, (src[i] >> 1) & 0x3f, src[i] & 1); + } + + BRINTF("\n"); + + t1 = direct_clock_get_abs_micros(); + + { + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_function = C64X_LOAD_BLOCK | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x1200000; + task->c64x_arg[1] = 10; + task->c64x_arg[2] = 0x3f; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_blit_16( c64x, (DAVINCI_C64X_MEM+0x01000000), 0, 0xf06180, 0, 384, 1 ); + davinci_c64x_blit_16( c64x, (DAVINCI_C64X_MEM+0x01100000), 0, 0xf06480, 0, 384/2, 1 ); + + davinci_c64x_put_uyvy_16x16( c64x, (DAVINCI_C64X_MEM+0x01300000), 32, 0xf06180, 0 ); + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + for (i=0; i<384; i++) { + BRINTF("%5d ", dst[i] ); + if (i%8==7) { + BRINTF("\n"); + } + if (i%64==63) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); + + + for (i=0; i<384; i++) { + BRINTF("%3d ", duv[i] ); + if (i%8==7) { + BRINTF("\n"); + } + if (i%64==63) { + BRINTF("\n"); + } + } + + BRINTF("\n\n"); + + for (i=0; i<16*16*2; i++) { + BRINTF("%02x ", duy[i]); + + if (i%32==31) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + dt = t2 - t1; + total = num;// * length; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "block_load()", total * 1000000ULL / dt ); +} +#endif + +static inline void +bench_put_mc( DavinciC64x *c64x, bool interleave ) +{ + int x, y, i, num; + long long t1, t2, dt, total; + + num = 1;//720/16*576/16; + + u8 *dst = c64x->mem + 0x1000000; + u8 *src = c64x->mem + 0x1200000; + + BRINTF("\n"); + BRINTF("\n\n.======================== Testing put_mc (%d) ========================.\n", interleave); + BRINTF("\n"); + BRINTF("SOURCE (16x16 / [8x8 8x8]\n"); + + for (y=0; y<16; y++) { + for (x=0; x<16; x++) { + u8 val = (x << 4) + y; + src[y*16 + x] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16 + 8] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + memset( dst, 0x55, 0x100000 ); + + davinci_c64x_blit_32( c64x, C64X_MC_BUFFER_Y, 16, DAVINCI_C64X_MEM+0x1200000, 16, 4, 24 ); + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_PUT_MC_UYVY_16x16 | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x1000000; + task->c64x_arg[1] = 1440; + task->c64x_arg[2] = interleave ? 1 : 0; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + BRINTF("\n"); + BRINTF("DESTINATION (16x16 UYVY)\n"); + + for (y=0; y<16; y++) { + for (x=0; x<32; x++) + BRINTF("%02x ", dst[y*1440 + x]); + + BRINTF("\n"); + } + + BRINTF("\n\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "put_mc_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_put_sum( DavinciC64x *c64x, bool interleave ) +{ + int x, y, i, num; + long long t1, t2, dt, total; + + num = 1;//720/16*576/16; + + u8 *dst = c64x->mem + 0x1000000; + u8 *src = c64x->mem + 0x1200000; + u32 *words = c64x->mem + 0x1100000; + + BRINTF("\n"); + BRINTF("\n\n.======================== Testing put_sum (%d) ========================.\n", interleave); + BRINTF("\n"); + BRINTF("WORDS (6x IDCT with one value)\n"); + + words[0] = DVA_BLOCK_WORD( 0, 0, 1 ); + words[1] = DVA_BLOCK_WORD( 50, 0, 1 ); + words[2] = DVA_BLOCK_WORD( 100, 0, 1 ); + words[3] = DVA_BLOCK_WORD( 150, 0, 1 ); + words[4] = DVA_BLOCK_WORD( 200, 0, 1 ); + words[5] = DVA_BLOCK_WORD( 250, 0, 1 ); + + BRINTF("\n"); + BRINTF("\n"); + + memset( dst, 0x55, 0x100000 ); + + for (i=0; i<6; i++) { + BRINTF("0x%08x (%d, %d, %d)\n", (u32)words[i], words[i] >> 16, (words[i] >> 1) & 0x3f, words[i] & 1); + } + + { + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_function = C64X_LOAD_BLOCK | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x1100000; + task->c64x_arg[1] = 6; + task->c64x_arg[2] = 0x3f; + + c64x_submit_task( c64x, task ); + } + + BRINTF("\n"); + BRINTF("SOURCE (16x16 / [8x8 8x8]\n"); + + for (y=0; y<16; y++) { + for (x=0; x<16; x++) { + u8 val = (x << 4) + y; + src[y*16 + x] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16 + 8] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + memset( dst, 0x55, 0x100000 ); + + davinci_c64x_blit_32( c64x, C64X_MC_BUFFER_Y, 16, DAVINCI_C64X_MEM+0x1200000, 16, 4, 24 ); + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_PUT_SUM_UYVY_16x16 | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x1000000; + task->c64x_arg[1] = 1440; + task->c64x_arg[2] = interleave ? 1 : 0; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + BRINTF("\n"); + BRINTF("DESTINATION (16x16 UYVY)\n"); + + for (y=0; y<16; y++) { + for (x=0; x<32; x++) + BRINTF("%02x ", dst[y*1440 + x]); + + BRINTF("\n"); + } + + BRINTF("\n\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "put_sum_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_sat_mc( DavinciC64x *c64x ) +{ + int x, y, i, num; + long long t1, t2, dt, total; + + num = 1;//720/16*576/16; + + u8 *dst = c64x->mem + 0x1000000; + u8 *src = c64x->mem + 0x1200000; + + BRINTF("\n\n.======================== Testing sat_mc ========================.\n"); + BRINTF("\n"); + BRINTF("SOURCE (16x16 / [8x8 8x8]\n"); + + for (y=0; y<16; y++) { + for (x=0; x<16; x++) { + u8 val = (x << 4) + y; + src[y*16 + x] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) { + u8 val = (x << 4) + y*2; + src[y*16 + x + 16*16 + 8] = val; + BRINTF("%02x ", val); + } + + BRINTF("\n"); + } + + BRINTF("\n"); + + memset( dst, 0x55, 0x100000 ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = (57 << 2) | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x1000000; + task->c64x_arg[1] = DAVINCI_C64X_MEM+0x1200000; + task->c64x_arg[2] = 16; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + BRINTF("\n"); + BRINTF("DESTINATION (16x16 / [8x8 8x8]\n"); + + for (y=0; y<16; y++) { + for (x=0; x<16; x++) + BRINTF("%02x ", dst[y*16 + x]); + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) + BRINTF("%02x ", dst[y*16 + x + 16*16]); + + BRINTF("\n"); + } + + BRINTF("\n"); + + for (y=0; y<8; y++) { + for (x=0; x<8; x++) + BRINTF("%02x ", dst[y*16 + x + 16*16 + 8]); + + BRINTF("\n"); + } + + BRINTF("\n\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "sat_mc_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_uyvy_1( DavinciC64x *c64x, bool progressive ) +{ + c64xTask *task; + int i, num; + long long t1, t2, dt, total; + + num = 720/16*576/16; + + u8 *u = c64x->mem + 0x1200000; + u8 *p = c64x->mem + 0x1000000; + + BRINTF("\n\n\n.======================== Testing put_uyvy (%s) ========================.\n\n", + progressive ? "progressive" : "interlaced"); + + for (i=0; i<256; i++) { + p[i] = i - 128; + BRINTF("Y%-3d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[256+i] = i-32; + BRINTF("U%-3d ", p[256+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[320+i] = i-32; + BRINTF("V%-3d ", p[320+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + for (i=0; i<384; i++) { + BRINTF("%4d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + memset( u, 0x55, 720*576*2 ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_PUT_UYVY_16x16 | C64X_FLAG_TODO; + + task->c64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x200000+i*16*16*2; + task->c64x_arg[1] = 720 * 2; + task->c64x_arg[2] = (DAVINCI_C64X_MEM+0x01000000); + task->c64x_arg[3] = 0; + + c64x_submit_task( c64x, task ); + } + + BRINTF("\n"); + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + for (i=0; i<16*16*2; i++) { + BRINTF("%02x ", u[i/32*720*2 + i%32]); + + if (i%32==31) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "put_uyvy_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_uyvy_2( DavinciC64x *c64x, bool progressive ) +{ + c64xTask *task; + int i, num; + long long t1, t2, dt, total; + + num = 1;//720/16*576/16; + + u8 *u = c64x->mem + 0x0200000; + u8 *p = c64x->mem + 0x0000000; + + BRINTF("\n\n\n.======================== Testing put_uyvy (%s) ========================.\n\n", + progressive ? "progressive" : "interlaced"); + + for (i=0; i<256; i++) { + p[i] = i/8; + BRINTF("Y%-3d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[256+i] = i/8 + 128; + BRINTF("U%-3d ", p[256+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[320+i] = i/8 + 240; + BRINTF("V%-3d ", p[320+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + for (i=0; i<384; i++) { + BRINTF("%4d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + memset( u, 0x55, 720*576*2 ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_PUT_UYVY_16x16 | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM+0x200000+i*16*16*2; + task->c64x_arg[1] = 720 * 2; + task->c64x_arg[2] = DAVINCI_C64X_MEM; + task->c64x_arg[3] = 0; + + c64x_submit_task( c64x, task ); + } + + BRINTF("\n"); + + davinci_c64x_write_back_all( c64x ); + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + for (i=0; i<16*16*2; i++) { + BRINTF("%02x ", u[i/32*720*2 + i%32]); + + if (i%32==31) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "put_uyvy_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_uyvy_3( DavinciC64x *c64x, bool progressive ) +{ + c64xTask *task; + int i, num; + long long t1, t2, dt, total; + + num = 1;//720/16*576/16; + + u8 *u = c64x->mem + 0x1200000; + u8 *p = c64x->mem + 0x1000000; + + BRINTF("\n\n\n.======================== Testing put_uyvy (%s) ========================.\n\n", + progressive ? "progressive" : "interlaced"); + + for (i=0; i<256; i++) { + p[i] = i%8; + BRINTF("Y%-3d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[256+i] = i%8 + 128; + BRINTF("U%-3d ", p[256+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + for (i=0; i<64; i++) { + p[320+i] = i%8 + 240; + BRINTF("V%-3d ", p[320+i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + for (i=0; i<384; i++) { + BRINTF("%4d ", p[i]); + if (i%8==7) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + memset( u, 0x55, 720*576*2 ); + + t1 = direct_clock_get_abs_micros(); + + for (i=0; ic64x_function = C64X_PUT_UYVY_16x16 | C64X_FLAG_TODO; + + task->c64x_arg[0] = (DAVINCI_C64X_MEM+0x01000000)+0x200000+i*16*16*2; + task->c64x_arg[1] = 720 * 2; + task->c64x_arg[2] = (DAVINCI_C64X_MEM+0x01000000); + task->c64x_arg[3] = 0; + + c64x_submit_task( c64x, task ); + } + + BRINTF("\n"); + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + for (i=0; i<16*16*2; i++) { + BRINTF("%02x ", u[i/32*720*2 + i%32]); + + if (i%32==31) { + BRINTF("\n"); + } + } + + BRINTF("\n"); + + dt = t2 - t1; + total = num; + + D_INFO( "Davinci/C64X: BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "put_uyvy_16x16()", total * 1000000ULL / dt ); +} + +static inline void +bench_mc( DavinciC64x *c64x, int func, int w, int h, bool avg, const char *name ) +{ + int i, x, y, num; + long long t1, t2, dt, total; + + num = 0x1;//0000; + + u8 *dst = c64x->mem + 0x1200000; + u8 *dsr = c64x->mem + 0x1100000; + u8 *src = c64x->mem + 0x1000000; + + BRINTF("\n\n.============ Testing %s ============.\n", name); + BRINTF("\n"); + BRINTF("SRC REF\n"); + + for (y=0; yc64x_function = (func << 2) | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM + 0x01200000; + task->c64x_arg[1] = 32; + task->c64x_arg[2] = DAVINCI_C64X_MEM + 0x01000000; + task->c64x_arg[3] = DAVINCI_C64X_MEM + 0x01100000; + task->c64x_arg[4] = 32; + task->c64x_arg[5] = h; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + BRINTF("-> DST\n"); + + for (y=0; yc64x_function = (63 << 2) | C64X_FLAG_TODO; + + task->c64x_arg[0] = nom; + task->c64x_arg[1] = den; + + c64x_submit_task( c64x, task ); + + davinci_c64x_wait_low( c64x ); + + BRINTF("%x / %x = %x\n\n\n", nom, den, task->c64x_return); +} + +static inline void +bench_dither_argb( DavinciC64x *c64x ) +{ + int i, x, y, num, w = 8, h = 17; + long long t1, t2, dt, total; + + num = 0x10000; + + u16 *dr = c64x->mem + 0x1200000; + u8 *da = c64x->mem + 0x1100000; + u32 *src = c64x->mem + 0x1000000; + + BRINTF("\n\n.======================== Testing dither_argb ========================.\n"); + BRINTF("\n"); + BRINTF("SOURCE ARGB\n"); + + for (y=0; yc64x_function = C64X_DITHER_ARGB | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM + 0x01200000; + task->c64x_arg[1] = DAVINCI_C64X_MEM + 0x01100000; + task->c64x_arg[2] = 64; + task->c64x_arg[3] = DAVINCI_C64X_MEM + 0x01000000; + task->c64x_arg[4] = 128; + task->c64x_arg[5] = w; + task->c64x_arg[6] = h; + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + BRINTF("-> DST RGB\n"); + + for (y=0; y DST ALPHA\n"); + + for (y=0; y> 4); + } + BRINTF("\n"); + } + + BRINTF("\n"); + + dt = t2 - t1; + total = num; + + BRINTF( "BENCHMARK on DSP - %-15s %lld Calls/sec\n", + "dither_argb", total * 1000000ULL / dt ); +} + + + + +/**********************************************************************************************************************/ +/*** 32 bit scaler ****************************************************************************************************/ +/**********************************************************************************************************************/ + +typedef struct { + DFBRegion clip; + const void *colors; + ulong protect; + ulong key; +} StretchCtx; + +typedef void (*StretchHVx)( void *dst, + int dpitch, + const void *src, + int spitch, + int width, + int height, + int dst_width, + int dst_height, + const StretchCtx *ctx ); + +#define STRETCH_NONE 0 +#define STRETCH_SRCKEY 1 +#define STRETCH_PROTECT 2 +#define STRETCH_SRCKEY_PROTECT 3 +#define STRETCH_NUM 4 + +typedef struct { + struct { + StretchHVx up[STRETCH_NUM]; + StretchHVx down[STRETCH_NUM]; + } f[DFB_NUM_PIXELFORMATS]; +} StretchFunctionTable; + + +#define DST_FORMAT DSPF_ARGB +#define TABLE_NAME stretch_32 +#define FUNC_NAME(UPDOWN,K,P,F) stretch_32_ ## UPDOWN ## _ ## K ## P ## _ ## F +#define SHIFT_R8 8 +#define SHIFT_L8 8 +#define X_00FF00FF 0x00ff00ff +#define X_FF00FF00 0xff00ff00 +#define MASK_RGB 0x00ffffff +#define HAS_ALPHA + +#include + +#undef DST_FORMAT +#undef TABLE_NAME +#undef FUNC_NAME +#undef SHIFT_R8 +#undef SHIFT_L8 +#undef X_00FF00FF +#undef X_FF00FF00 +#undef MASK_RGB +#undef HAS_ALPHA + + +static inline void +bench_stretch_32( DavinciC64x *c64x, int sw, int sh, int dw, int dh ) +{ + int i, x, y, num; + long long t1, t2, dt, total; + bool down = (dw < sw) && (dh < sh); + +#if 0 + int SW = (sw + 5) & ~3; + int SH = (sh + 5) & ~3; + int DW = (dw + 5) & ~3; + int DH = (dh + 5) & ~3; +#else + int SW = sw; + int SH = sh; + int DW = dw; + int DH = dh; +#endif + + num = 1;//0x10000; + + u32 cpu[DW * DH]; + u32 *dst = c64x->mem + 0x1200000; + u32 *src = c64x->mem + 0x1000000; + + memset( src, 0x55, 0x100000 ); + + for (y=0; y %dx%d ) ========================.\n", sw, sh, dw, dh); + BRINTF("\n"); + BRINTF("SOURCE IMAGE (%dx%d) [%dx%d]\n", sw, sh, SW, SH); + + for (y=0; yc64x_function = (down ? + C64X_STRETCH_32_down : + C64X_STRETCH_32_up ) | C64X_FLAG_TODO; + + task->c64x_arg[0] = DAVINCI_C64X_MEM + 0x1200000; + task->c64x_arg[1] = DAVINCI_C64X_MEM + 0x1000000; + task->c64x_arg[2] = (DW * 4) | ((SW * 4) << 16); + task->c64x_arg[3] = dh | (dw << 16); + task->c64x_arg[4] = sh | (sw << 16); + task->c64x_arg[5] = (dw - 1) | ((dh - 1) << 16); + task->c64x_arg[6] = 0 | (0 << 16); + + c64x_submit_task( c64x, task ); + } + + davinci_c64x_write_back_all( c64x ); + + davinci_c64x_wait_low( c64x ); + + t2 = direct_clock_get_abs_micros(); + + + BRINTF("-> DSP RESULT (%dx%d) [%dx%d]\n", dw, dh, DW, DH); + + for (y=0; y CPU RESULT (%dx%d) [%dx%d]\n", dw, dh, DW, DH); + + for (y=0; yfd = fd; + c64x->ctl = map_q; + c64x->mem = map_m; + c64x->QueueL = map_m + 0x01e00000; + + D_INFO( "Davinci/C64X: Low ARM %d / DSP %d, High ARM %d / DSP %d\n", + c64x->ctl->QL_arm, c64x->ctl->QL_dsp, c64x->ctl->QH_arm, c64x->ctl->QH_dsp ); + + D_MAGIC_SET( c64x, DavinciC64x ); + +if (getenv("C64X_TEST")) { +// test_load_block( c64x, false ); + +// test_load_block( c64x, true ); + +// bench_dither_argb( c64x ); + +#if 0 + bench_uyvy_1( c64x, true ); + bench_uyvy_1( c64x, false ); + bench_uyvy_2( c64x, true ); + bench_uyvy_2( c64x, false ); + bench_uyvy_3( c64x, true ); + bench_uyvy_3( c64x, false ); +#endif + +#if 0 + bench_blend_argb( c64x, 0 ); + bench_blend_argb( c64x, 1 ); + bench_blend_argb( c64x, 2 ); + bench_blend_argb( c64x, 3 ); +#endif + +#if 0 + bench_stretch_32( c64x, 2, 1, 16, 1 ); + bench_stretch_32( c64x, 2, 2, 16, 2 ); + + bench_stretch_32( c64x, 2, 1, 3, 1 ); + bench_stretch_32( c64x, 4, 1, 6, 1 ); + + bench_stretch_32( c64x, 3, 1, 2, 1 ); + bench_stretch_32( c64x, 6, 1, 4, 1 ); +#endif + +#if 1 + bench_fetch_uyvy( c64x, false, 0, 0 ); + bench_fetch_uyvy( c64x, false, 1, 0 ); + bench_fetch_uyvy( c64x, false, 0, 1 ); + bench_fetch_uyvy( c64x, false, 1, 1 ); + bench_fetch_uyvy( c64x, true, 0, 0 ); + bench_fetch_uyvy( c64x, true, 1, 0 ); + bench_fetch_uyvy( c64x, true, 0, 1 ); + bench_fetch_uyvy( c64x, true, 1, 1 ); +#endif + +#if 0 + bench_put_mc( c64x, false ); + bench_put_mc( c64x, true ); + + bench_put_sum( c64x, false ); + bench_put_sum( c64x, true ); + + bench_sat_mc( c64x ); +#endif + +#if 0 + bench_mc( c64x, 32, 8, 8, false, "mc_put_o_8" ); + bench_mc( c64x, 33, 8, 8, false, "mc_put_x_8" ); + bench_mc( c64x, 34, 8, 8, false, "mc_put_y_8" ); + bench_mc( c64x, 35, 8, 8, false, "mc_put_xy_8" ); + bench_mc( c64x, 36, 16, 16, false, "mc_put_o_16" ); + bench_mc( c64x, 37, 16, 16, false, "mc_put_x_16" ); + bench_mc( c64x, 38, 16, 16, false, "mc_put_y_16" ); + bench_mc( c64x, 39, 16, 16, false, "mc_put_xy_16" ); +#endif + +#if 0 + bench_mc( c64x, 40, 8, 8, true, "mc_avg_o_8" ); + bench_mc( c64x, 41, 8, 8, true, "mc_avg_x_8" ); + bench_mc( c64x, 42, 8, 8, true, "mc_avg_y_8" ); + bench_mc( c64x, 43, 8, 8, true, "mc_avg_xy_8" ); + bench_mc( c64x, 44, 16, 16, true, "mc_avg_o_16" ); + bench_mc( c64x, 45, 16, 16, true, "mc_avg_x_16" ); + bench_mc( c64x, 46, 16, 16, true, "mc_avg_y_16" ); + bench_mc( c64x, 47, 16, 16, true, "mc_avg_xy_16" ); +#endif + +#if 0 + bench_div( c64x, 1, 3 ); + bench_div( c64x, 1000, 333 ); + bench_div( c64x, 1000, 334 ); + bench_div( c64x, 6666, 2222 ); + bench_div( c64x, 1234, 1234 ); + bench_div( c64x, 4000, 0 ); + bench_div( c64x, 5000, 0 ); + bench_div( c64x, 10000, 3 ); + bench_div( c64x, 14, 3 ); + bench_div( c64x, 0x10000, 0x1000 ); + bench_div( c64x, 0x1000, 0x100 ); + bench_div( c64x, 0x100000, 2 ); +#endif +} + + return DFB_OK; + + +error: + if (map_q) + munmap( map_q, C64X_QLEN ); + + close( fd ); + + return ret; +} + +DFBResult +davinci_c64x_close( DavinciC64x *c64x ) +{ + D_MAGIC_ASSERT( c64x, DavinciC64x ); + + munmap( (void*) c64x->mem, C64X_MLEN ); + munmap( (void*) c64x->ctl, C64X_QLEN ); + + close( c64x->fd ); + + D_MAGIC_CLEAR( c64x ); + + return DFB_OK; +} + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.h b/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.h new file mode 100755 index 0000000..682da22 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_c64x.h @@ -0,0 +1,935 @@ +/* + TI Davinci driver - C64X+ DSP Library + + (c) Copyright 2008 directfb.org + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp and + Olaf Dreesen . + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_C64X_H__ +#define __DAVINCI_C64X_H__ + +#include + +#include + +#include +#include + +#include + +#define mb() __asm__ __volatile__ ("" : : : "memory") + +/**********************************************************************************************************************/ + +typedef struct { + int magic; + + int fd; + c64xTaskControl *ctl; + void *mem; + + c64xTask *QueueL; +} DavinciC64x; + +typedef struct { + int magic; + unsigned int max_tasks; + unsigned int num_tasks; + c64xTask *tasks; +} DavinciC64xTasks; + +typedef enum { + C64X_TEF_NONE = 0x0000, + C64X_TEF_RESET = 0x0001 +} DavinciC64xEmitFlags; + +/**********************************************************************************************************************/ + +DFBResult davinci_c64x_open ( DavinciC64x *c64x ); + +DFBResult davinci_c64x_close ( DavinciC64x *c64x ); + +DFBResult davinci_c64x_wait_low( DavinciC64x *c64x ); + +/**********************************************************************************************************************/ + +DFBResult davinci_c64x_tasks_init ( DavinciC64xTasks *tasks, + unsigned int size ); + +DFBResult davinci_c64x_tasks_destroy( DavinciC64xTasks *tasks ); + +/**********************************************************************************************************************/ + +DFBResult davinci_c64x_emit_tasks( DavinciC64x *c64x, + DavinciC64xTasks *tasks, + DavinciC64xEmitFlags flags ); + +/**********************************************************************************************************************/ + +static const char *state_names[] = { "DONE", "ERROR", "TODO", "RUNNING" }; + +static inline c64xTask * +c64x_get_task( DavinciC64x *c64x ) +{ + c64xTaskControl *ctl = c64x->ctl; + uint32_t idx = ctl->QL_arm; + uint32_t next = (idx + 1) & C64X_QUEUE_MASK; + c64xTask *task = &c64x->QueueL[idx]; + int loops = 0; + uint32_t idle = 0; + + /* Wait for the entry (and next) to be processed by the DSP (rare case). */ + while (task->c64x_flags & C64X_FLAG_TODO || ctl->QL_dsp == next) { + if (loops > 666 || (idle && ctl->idlecounter - idle > 666)) { + c64xTask *dsp_task = &c64x->QueueL[ctl->QL_dsp]; + + D_PERROR( "Davinci/C64X+: Blocked! [DSP %d / %d (%s), ARM %d / %d (%s)]\n", + ctl->QL_dsp, + (dsp_task->c64x_function >> 2) & 0x3fff, + state_names[dsp_task->c64x_function & 3], + ctl->QL_arm, + (task->c64x_function >> 2) & 0x3fff, + state_names[task->c64x_function & 3] ); + + break; + } + + idle = ctl->idlecounter; + + /* Queue is full, waiting 10-20ms should not be too bad. */ + if (loops++ > 10) + usleep( 5000 ); + } + + return task; +} + +static inline void +c64x_submit_task( DavinciC64x *c64x, c64xTask *task ) +{ + c64xTaskControl *ctl = c64x->ctl; + uint32_t idx = ctl->QL_arm; + uint32_t next = (idx + 1) & C64X_QUEUE_MASK; + + mb(); + + ctl->QL_arm = next; + + mb(); +} + +/**********************************************************************************************************************/ + +static inline void +davinci_c64x_wb_inv_range( DavinciC64x *c64x, + unsigned long start, + u32 length, + u32 func ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = start; + task->c64x_arg[1] = length; + task->c64x_arg[2] = func; + + task->c64x_function = C64X_WB_INV_RANGE | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_write_back_all( DavinciC64x *c64x ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_function = C64X_WRITE_BACK_ALL | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +/**********************************************************************************************************************/ + +static inline void +davinci_c64x_load_block__L( DavinciC64xTasks *tasks, + unsigned long words, + u32 num, + u32 flags ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = words; + task->c64x_arg[1] = num; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_LOAD_BLOCK | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_load_block( DavinciC64x *c64x, + unsigned long words, + u32 num, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = words; + task->c64x_arg[1] = num; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_LOAD_BLOCK | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_fetch_uyvy( DavinciC64x *c64x, + unsigned long dest, + unsigned long source, + u32 pitch, + u32 height, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = source; + task->c64x_arg[2] = pitch; + task->c64x_arg[3] = height; + task->c64x_arg[4] = flags; + + task->c64x_function = C64X_FETCH_UYVY | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_mc( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long source0, + unsigned long source1, + u32 spitch, + u32 height, + int func ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = source0; + task->c64x_arg[3] = source1; + task->c64x_arg[4] = spitch; + task->c64x_arg[5] = height; + + task->c64x_function = func | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_put_idct_uyvy_16x16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_IDCT_UYVY_16x16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_put_idct_uyvy_16x16( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_IDCT_UYVY_16x16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_put_mc_uyvy_16x16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_MC_UYVY_16x16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_put_mc_uyvy_16x16( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_MC_UYVY_16x16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_put_sum_uyvy_16x16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_SUM_UYVY_16x16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_put_sum_uyvy_16x16( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = flags; + + task->c64x_function = C64X_PUT_SUM_UYVY_16x16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_dva_begin_frame__L( DavinciC64xTasks *tasks, + u32 pitch, + unsigned long current, + unsigned long past, + unsigned long future, + u32 flags ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = pitch; + task->c64x_arg[1] = current; + task->c64x_arg[2] = past; + task->c64x_arg[3] = future; + task->c64x_arg[4] = flags; + + task->c64x_function = C64X_DVA_BEGIN_FRAME | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_dva_begin_frame( DavinciC64x *c64x, + u32 pitch, + unsigned long current, + unsigned long past, + unsigned long future, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = pitch; + task->c64x_arg[1] = current; + task->c64x_arg[2] = past; + task->c64x_arg[3] = future; + task->c64x_arg[4] = flags; + + task->c64x_function = C64X_DVA_BEGIN_FRAME | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_dva_motion_block__L( DavinciC64xTasks *tasks, + unsigned long macroblock ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = macroblock; + + task->c64x_function = C64X_DVA_MOTION_BLOCK | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_dva_motion_block( DavinciC64x *c64x, + unsigned long macroblock ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = macroblock; + + task->c64x_function = C64X_DVA_MOTION_BLOCK | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +/**********************************************************************************************************************/ + +static inline void +davinci_c64x_dva_idct( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + unsigned long source ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = source; + + task->c64x_function = C64X_DVA_IDCT | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +/**********************************************************************************************************************/ + +static inline void +davinci_c64x_put_uyvy_16x16( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + unsigned long source, + u32 flags ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = source; + task->c64x_arg[3] = flags; + + task->c64x_function = C64X_PUT_UYVY_16x16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_dither_argb__L( DavinciC64xTasks *tasks, + unsigned long dst_rgb, + unsigned long dst_alpha, + u32 dst_pitch, + unsigned long source, + u32 src_pitch, + u32 width, + u32 height ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dst_rgb; + task->c64x_arg[1] = dst_alpha; + task->c64x_arg[2] = dst_pitch; + task->c64x_arg[3] = source; + task->c64x_arg[4] = src_pitch; + task->c64x_arg[5] = width; + task->c64x_arg[6] = height; + + task->c64x_function = C64X_DITHER_ARGB | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_dither_argb( DavinciC64x *c64x, + unsigned long dst_rgb, + unsigned long dst_alpha, + u32 dst_pitch, + unsigned long source, + u32 src_pitch, + u32 width, + u32 height ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dst_rgb; + task->c64x_arg[1] = dst_alpha; + task->c64x_arg[2] = dst_pitch; + task->c64x_arg[3] = source; + task->c64x_arg[4] = src_pitch; + task->c64x_arg[5] = width; + task->c64x_arg[6] = height; + + task->c64x_function = C64X_DITHER_ARGB | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_fill_16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 pitch, + u32 width, + u32 height, + u32 value ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = width; + task->c64x_arg[3] = height; + task->c64x_arg[4] = value; + + task->c64x_function = C64X_FILL_16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_fill_16( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + u32 width, + u32 height, + u32 value ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = width; + task->c64x_arg[3] = height; + task->c64x_arg[4] = value; + + task->c64x_function = C64X_FILL_16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_fill_32__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 pitch, + u32 width, + u32 height, + u32 value ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = width; + task->c64x_arg[3] = height; + task->c64x_arg[4] = value; + + task->c64x_function = C64X_FILL_32 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_fill_32( DavinciC64x *c64x, + unsigned long dest, + u32 pitch, + u32 width, + u32 height, + u32 value ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = pitch; + task->c64x_arg[2] = width; + task->c64x_arg[3] = height; + task->c64x_arg[4] = value; + + task->c64x_function = C64X_FILL_32 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_blit_16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width; + task->c64x_arg[5] = height; + + task->c64x_function = C64X_COPY_16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_blit_16( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width; + task->c64x_arg[5] = height; + + task->c64x_function = C64X_COPY_16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_blit_32__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width; + task->c64x_arg[5] = height; + + task->c64x_function = C64X_COPY_32 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_blit_32( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width; + task->c64x_arg[5] = height; + + task->c64x_function = C64X_COPY_32 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_stretch_32__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 dw, + u32 dh, + u32 sw, + u32 sh, + const DFBRegion *clip ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = src; + task->c64x_arg[2] = dpitch | (spitch << 16); + task->c64x_arg[3] = dh | (dw << 16); + task->c64x_arg[4] = sh | (sw << 16); + task->c64x_arg[5] = clip->x2 | (clip->y2 << 16); + task->c64x_arg[6] = clip->x1 | (clip->y1 << 16); + + if (sw > dw && sh > dh) + task->c64x_function = C64X_STRETCH_32_down | C64X_FLAG_TODO; + else + task->c64x_function = C64X_STRETCH_32_up | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_stretch_32( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 dw, + u32 dh, + u32 sw, + u32 sh, + const DFBRegion *clip ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = src; + task->c64x_arg[2] = dpitch | (spitch << 16); + task->c64x_arg[3] = dh | (dw << 16); + task->c64x_arg[4] = sh | (sw << 16); + task->c64x_arg[5] = clip->x2 | (clip->y2 << 16); + task->c64x_arg[6] = clip->x1 | (clip->y1 << 16); + + if (sw > dw && sh > dh) + task->c64x_function = C64X_STRETCH_32_down | C64X_FLAG_TODO; + else + task->c64x_function = C64X_STRETCH_32_up | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_blit_blend_32__L( DavinciC64xTasks *tasks, + u32 sub_func, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 argb, + u8 alpha ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width | (height << 16); + task->c64x_arg[5] = argb; + task->c64x_arg[6] = alpha; + + task->c64x_function = (sub_func << 16) | C64X_BLEND_32 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_blit_blend_32( DavinciC64x *c64x, + u32 sub_func, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 argb, + u8 alpha ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = dpitch; + task->c64x_arg[2] = src; + task->c64x_arg[3] = spitch; + task->c64x_arg[4] = width | (height << 16); + task->c64x_arg[5] = argb; + task->c64x_arg[6] = alpha; + + task->c64x_function = (sub_func << 16) | C64X_BLEND_32 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_blit_keyed_16__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 key, + u32 mask ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = (dpitch << 16) | (spitch & 0xffff); + task->c64x_arg[2] = src; + task->c64x_arg[3] = width; + task->c64x_arg[4] = height; + task->c64x_arg[5] = key; + task->c64x_arg[6] = mask; + + task->c64x_function = C64X_COPY_KEYED_16 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_blit_keyed_16( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 key, + u32 mask ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = (dpitch << 16) | (spitch & 0xffff); + task->c64x_arg[2] = src; + task->c64x_arg[3] = width; + task->c64x_arg[4] = height; + task->c64x_arg[5] = key; + task->c64x_arg[6] = mask; + + task->c64x_function = C64X_COPY_KEYED_16 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +static inline void +davinci_c64x_blit_keyed_32__L( DavinciC64xTasks *tasks, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 key, + u32 mask ) +{ + c64xTask *task = &tasks->tasks[tasks->num_tasks]; + + D_ASSERT( tasks->num_tasks < tasks->max_tasks ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = (dpitch << 16) | (spitch & 0xffff); + task->c64x_arg[2] = src; + task->c64x_arg[3] = width; + task->c64x_arg[4] = height; + task->c64x_arg[5] = key; + task->c64x_arg[6] = mask; + + task->c64x_function = C64X_COPY_KEYED_32 | C64X_FLAG_TODO; + + tasks->num_tasks++; +} + +static inline void +davinci_c64x_blit_keyed_32( DavinciC64x *c64x, + unsigned long dest, + u32 dpitch, + unsigned long src, + u32 spitch, + u32 width, + u32 height, + u32 key, + u32 mask ) +{ + c64xTask *task = c64x_get_task( c64x ); + + task->c64x_arg[0] = dest; + task->c64x_arg[1] = (dpitch << 16) | (spitch & 0xffff); + task->c64x_arg[2] = src; + task->c64x_arg[3] = width; + task->c64x_arg[4] = height; + task->c64x_arg[5] = key; + task->c64x_arg[6] = mask; + + task->c64x_function = C64X_COPY_KEYED_32 | C64X_FLAG_TODO; + + c64x_submit_task( c64x, task ); +} + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.c b/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.c new file mode 100755 index 0000000..eef72d1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.c @@ -0,0 +1,343 @@ +/* + TI Davinci driver - Graphics Driver + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "davincifb.h" + +#include "davinci_2d.h" +#include "davinci_gfxdriver.h" +#include "davinci_osd.h" +#include "davinci_osd_pool.h" +#include "davinci_screen.h" +#include "davinci_video.h" +#include "davinci_video_pool.h" + + +#include + +DFB_GRAPHICS_DRIVER( davinci ) + +/**********************************************************************************************************************/ + +static DFBResult +open_fb( DavinciDriverData *ddrv, + DavinciDeviceData *ddev, + unsigned int fbnum ) +{ + int ret; + char buf1[16]; + char buf2[16]; + DavinciFB *fb; + struct fb_var_screeninfo var; + + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + D_ASSERT( fbnum < D_ARRAY_SIZE(ddrv->fb) ); + D_ASSERT( fbnum < D_ARRAY_SIZE(ddev->fix) ); + + fb = &ddrv->fb[fbnum]; + + fb->num = fbnum; + + snprintf( buf1, sizeof(buf1), "/dev/fb%u", fbnum ); + snprintf( buf2, sizeof(buf2), "/dev/fb/%u", fbnum ); + + fb->fd = direct_try_open( buf1, buf2, O_RDWR, true ); + if (fb->fd < 0) + return DFB_INIT; + + ret = ioctl( fb->fd, FBIOGET_VSCREENINFO, &var ); + if (ret) { + D_PERROR( "Davinci/Driver: FBIOGET_VSCREENINFO (fb%d) failed!\n", fbnum ); + close( fb->fd ); + return DFB_INIT; + } + + ret = ioctl( fb->fd, FBIOGET_FSCREENINFO, &ddev->fix[fbnum] ); + if (ret) { + D_PERROR( "Davinci/Driver: FBIOGET_FSCREENINFO (fb%d) failed!\n", fbnum ); + close( fb->fd ); + return DFB_INIT; + } + + fb->size = ddev->fix[fbnum].smem_len; + + fb->mem = mmap( NULL, fb->size, PROT_READ | PROT_WRITE, MAP_SHARED, fb->fd, 0 ); + if (fb->mem == MAP_FAILED) { + D_PERROR( "Davinci/Driver: mmap (fb%d, length %d) failed!\n", fbnum, fb->size ); + close( fb->fd ); + return DFB_INIT; + } + + D_INFO( "Davinci/Driver: Mapped fb%d with length %u at %p to %p\n", + fbnum, fb->size, (void*)ddev->fix[fbnum].smem_start, fb->mem ); + + return DFB_OK; +} + +static void +close_fb( DavinciFB *fb ) +{ + munmap( fb->mem, fb->size ); + close( fb->fd ); +} + +/**********************************************************************************************************************/ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + int ret; + int fd; + vpbe_fb_videomode_t videomode; + + switch (dfb_system_type()) { + case CORE_DEVMEM: + case CORE_TI_CMEM: + if (dfb_config->accelerator == 6400) + return 1; + break; + + default: + return 0; + } + + fd = direct_try_open( "/dev/fb0", "/dev/fb/0", O_RDWR, true ); + if (fd < 0) + return 0; + + ret = ioctl( fd, FBIO_GET_TIMING, &videomode); + + close( fd ); + + if (ret) { + D_PERROR( "Davinci/Driver: FBIO_GET_TIMING failed!\n" ); + return 0; + } + + if (videomode.xres > 768 || videomode.yres > 576 || videomode.fps > 60) { + D_ERROR( "Davinci/Driver: Invalid mode %dx%d @%d!\n", videomode.xres, videomode.yres, videomode.fps ); + return 0; + } + + if (strncmp( (char*)videomode.name, "PAL", 3 ) && + strncmp( (char*)videomode.name, "NTSC", 4 )) + { + D_ERROR( "Davinci/Driver: Unknown mode name '%s'!\n", videomode.name ); + return 0; + } + + return 1; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "TI Davinci Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Telio AG" ); + + info->version.major = 0; + info->version.minor = 4; + + info->driver_data_size = sizeof(DavinciDriverData); + info->device_data_size = sizeof(DavinciDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + DFBResult ret; + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = device_data; + bool master = dfb_core_is_master( core ); + + ddrv->ddev = ddev; + ddrv->core = core; + + ret = open_fb( ddrv, ddev, OSD0 ); + if (ret) + return ret; + + ret = open_fb( ddrv, ddev, VID0 ); + if (ret) + goto error_fb1; + + ret = open_fb( ddrv, ddev, OSD1 ); + if (ret) + goto error_fb2; + + ret = open_fb( ddrv, ddev, VID1 ); + if (ret) + goto error_fb3; + + ret = davinci_c64x_open( &ddrv->c64x ); + if (ret) + D_WARN( "running without DSP acceleration" ); + else { + ret = davinci_c64x_tasks_init( &ddrv->tasks, 2048 ); + if (ret) { + D_DERROR( ret, "Davinci/Driver: Error initializing local task buffer!\n" ); + return ret; + } + + ddrv->c64x_present = true; + + /* initialize function pointers */ + funcs->EngineSync = davinciEngineSync; + funcs->EngineReset = davinciEngineReset; + funcs->EmitCommands = davinciEmitCommands; + funcs->FlushTextureCache = davinciFlushTextureCache; + funcs->CheckState = davinciCheckState; + funcs->SetState = davinciSetState; + funcs->StretchBlit = davinciStretchBlit32; + } + + ddrv->screen = dfb_screens_register( device, driver_data, &davinciScreenFuncs ); + + ddrv->osd = dfb_layers_register( ddrv->screen, driver_data, &davinciOSDLayerFuncs ); + ddrv->video = dfb_layers_register( ddrv->screen, driver_data, &davinciVideoLayerFuncs ); + + if (!master) { + dfb_surface_pool_join( core, ddev->osd_pool, &davinciOSDSurfacePoolFuncs ); +// dfb_surface_pool_join( core, ddev->video_pool, &davinciVideoSurfacePoolFuncs ); + } + + if (!dfb_config->software_only && funcs->CheckState) { + dfb_config->font_format = DSPF_ARGB; + dfb_config->font_premult = true; + } + + return DFB_OK; + +error_fb3: + close_fb( &ddrv->fb[OSD1] ); + +error_fb2: + close_fb( &ddrv->fb[VID0] ); + +error_fb1: + close_fb( &ddrv->fb[OSD0] ); + + return DFB_INIT; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = device_data; + + /* fill device info */ + snprintf( device_info->vendor, DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Texas Instruments" ); + snprintf( device_info->name, DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Davinci" ); + + /* device limitations */ + device_info->limits.surface_byteoffset_alignment = 64; + device_info->limits.surface_bytepitch_alignment = 32; + + if (ddrv->c64x_present) { + device_info->caps.flags = 0; + device_info->caps.accel = DAVINCI_SUPPORTED_DRAWINGFUNCTIONS | + DAVINCI_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = DAVINCI_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = DAVINCI_SUPPORTED_BLITTINGFLAGS; + device_info->caps.clip = DFXL_STRETCHBLIT; + } + + dfb_surface_pool_initialize( ddrv->core, &davinciOSDSurfacePoolFuncs, &ddev->osd_pool ); +// dfb_surface_pool_initialize( ddrv->core, &davinciVideoSurfacePoolFuncs, &ddev->video_pool ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + DavinciDriverData *ddrv = driver_data; + + if (ddrv->c64x_present) { + davinci_c64x_tasks_destroy( &ddrv->tasks ); + + davinci_c64x_close( &ddrv->c64x ); + } + + close_fb( &ddrv->fb[VID1] ); + close_fb( &ddrv->fb[OSD1] ); + close_fb( &ddrv->fb[VID0] ); + close_fb( &ddrv->fb[OSD0] ); +} + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.h b/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.h new file mode 100755 index 0000000..4ca79b3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_gfxdriver.h @@ -0,0 +1,169 @@ +/* + TI Davinci driver - Graphics Driver + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_GFXDRIVER_H__ +#define __DAVINCI_GFXDRIVER_H__ + +#include +#include + +#include + +#include "davincifb.h" + +#include "davinci_c64x.h" + + +typedef struct { + /* validation flags */ + int v_flags; + + /* cached/computed values */ + void *dst_addr; + unsigned long dst_phys; + unsigned int dst_size; + unsigned long dst_pitch; + DFBSurfacePixelFormat dst_format; + unsigned long dst_bpp; + + void *src_addr; + unsigned long src_phys; + unsigned long src_pitch; + DFBSurfacePixelFormat src_format; + unsigned long src_bpp; + + unsigned long source_mult; + + unsigned long fillcolor; + + int blit_blend_sub_function; + int draw_blend_sub_function; + + DFBColor color; + unsigned long color_argb; + unsigned long colorkey; + + DFBSurfaceBlittingFlags blitting_flags; + + DFBRegion clip; + + /** Add shared data here... **/ + struct fb_fix_screeninfo fix[4]; + + CoreSurfacePool *osd_pool; + CoreSurfacePool *video_pool; + + bool synced; +} DavinciDeviceData; + + +typedef struct { + int num; + int fd; + void *mem; + int size; +} DavinciFB; + +typedef struct { + DavinciDeviceData *ddev; + + CoreDFB *core; + + CoreScreen *screen; + CoreLayer *osd; + CoreLayer *video; + + DavinciFB fb[4]; + + DavinciC64x c64x; + bool c64x_present; + + DavinciC64xTasks tasks; +} DavinciDriverData; + + +static inline DFBResult +davincifb_pan_display( const DavinciFB *fb, + struct fb_var_screeninfo *var, + const CoreSurfaceBufferLock *lock, + DFBSurfaceFlipFlags flags, + int x, + int y ) +{ + int ret; + + if (lock) { +#ifdef FBIO_SET_START + CoreSurfaceBuffer *buffer = lock->buffer; + struct fb_set_start set_start; + + /* physical mode */ + set_start.offset = -1; + set_start.sync = (flags & DSFLIP_ONSYNC) ? 1 : 0; + + /* life's so easy */ + set_start.physical = lock->phys + DFB_BYTES_PER_LINE( buffer->format, x ) + y * lock->pitch; + + ret = ioctl( fb->fd, FBIO_SET_START, &set_start ); + if (ret < 0) + D_DEBUG( "FBIO_SET_START (0x%08lx, sync %llu) failed!\n", + set_start.physical, set_start.sync ); + + if (ret == 0) { + if (flags & DSFLIP_WAIT) + ioctl( fb->fd, FBIO_WAITFORVSYNC ); + + return DFB_OK; + } + + /* fallback */ +#endif + var->xoffset = x; /* poor version */ + var->yoffset = y + lock->offset / lock->pitch; + } + else { + var->xoffset = x; + var->yoffset = y; + } + + var->activate = /*(flags & DSFLIP_ONSYNC) ? FB_ACTIVATE_VBL :*/ FB_ACTIVATE_NOW; + + ret = ioctl( fb->fd, FBIOPAN_DISPLAY, var ); + if (ret) + D_PERROR( "Davinci/FB: FBIOPAN_DISPLAY (fb%d - %d,%d) failed!\n", + fb->num, var->xoffset, var->yoffset ); + + if (flags & DSFLIP_WAIT) + ioctl( fb->fd, FBIO_WAITFORVSYNC ); + + return DFB_OK; +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_osd.c b/Source/DirectFB/gfxdrivers/davinci/davinci_osd.c new file mode 100755 index 0000000..2effb2e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_osd.c @@ -0,0 +1,681 @@ +/* + TI Davinci driver - Graphics Layer + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include "davincifb.h" + +#include "davinci_gfxdriver.h" +#include "davinci_osd.h" + + +#define D_OSDERROR(x...) do {} while (0) + + +D_DEBUG_DOMAIN( Davinci_OSD, "Davinci/OSD", "TI Davinci OSD" ); + +/**********************************************************************************************************************/ + +static int +osdLayerDataSize( void ) +{ + return sizeof(DavinciOSDLayerData); +} + +static DFBResult +osdInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciOSDLayerData *dosd = layer_data; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + ret = ioctl( ddrv->fb[OSD0].fd, FBIOGET_VSCREENINFO, &dosd->var0 ); + if (ret) { + D_PERROR( "Davinci/OSD: FBIOGET_VSCREENINFO (fb%d) failed!\n", OSD0 ); + return DFB_INIT; + } + + ret = ioctl( ddrv->fb[OSD1].fd, FBIOGET_VSCREENINFO, &dosd->var1 ); + if (ret) { + D_PERROR( "Davinci/OSD: FBIOGET_VSCREENINFO (fb%d) failed!\n", OSD1 ); + return DFB_INIT; + } + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD0, 0 ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD1, 0 ); + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_ALPHACHANNEL | DLCAPS_OPACITY | DLCAPS_SCREEN_POSITION | + DLCAPS_SRC_COLORKEY; + description->type = DLTF_GRAPHICS; + + /* set name */ + snprintf( description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "TI Davinci OSD" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_RGB16; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_ALPHACHANNEL; + + return DFB_OK; +} + +static DFBResult +osdTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + if (config->options & ~DAVINCI_OSD_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + switch (config->format) { + case DSPF_RGB444: + case DSPF_RGB555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB4444: + case DSPF_ARGB1555: + case DSPF_ARGB: + break; + + default: + fail |= CLRCF_FORMAT; + } + + if (config->width < 8 || config->width > 1920) + fail |= CLRCF_WIDTH; + + if (config->height < 8 || config->height > 1080) + fail |= CLRCF_HEIGHT; + + if (config->dest.x < 0 || config->dest.y < 0) + fail |= CLRCF_DEST; + + if (config->dest.x + config->dest.w > 1920) + fail |= CLRCF_DEST; + + if (config->dest.y + config->dest.h > 1080) + fail |= CLRCF_DEST; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +osdSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = ddrv->ddev; + DavinciOSDLayerData *dosd = layer_data; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + D_ASSERT( dosd != NULL ); + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD0, 0 ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD1, 0 ); + + ioctl( ddrv->fb[OSD0].fd, FBIO_WAITFORVSYNC ); + + /* Update blend parameters? */ + if (updated & (CLRCF_OPTIONS | CLRCF_OPACITY | CLRCF_SRCKEY | CLRCF_FORMAT)) { + vpbe_blink_option_t blink = {0}; + vpbe_bitmap_blend_params_t blend = {0}; + + D_DEBUG_AT( Davinci_OSD, " -> %s\n", dfb_pixelformat_name( config->format ) ); + + if (config->options & DLOP_SRC_COLORKEY) { + blend.enable_colorkeying = 1; + blend.colorkey = dfb_color_to_pixel( DSPF_RGB16, + config->src_key.r, + config->src_key.g, + config->src_key.b ); + + D_DEBUG_AT( Davinci_OSD, " -> color key 0x%02x (%02x %02x %02x)\n", + blend.colorkey, config->src_key.r, config->src_key.g, config->src_key.b ); + } + else if (config->options & DLOP_OPACITY) { + blend.bf = config->opacity >> 5; + + D_DEBUG_AT( Davinci_OSD, " -> opacity %d/7\n", blend.bf ); + } + else + blend.bf = 7; + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_SET_BITMAP_BLEND_FACTOR, &blend ); + if (ret) + D_PERROR( "Davinci/OSD: FBIO_SET_BITMAP_BLEND_FACTOR (fb%d)!\n", OSD0 ); + + if (config->options & DLOP_ALPHACHANNEL) + dosd->alpha = DFB_PIXELFORMAT_HAS_ALPHA( config->format ); + else + dosd->alpha = 0; + + D_DEBUG_AT( Davinci_OSD, " -> %salpha channel\n", dosd->alpha ? "" : "no " ); + + if (dosd->alpha) { + if (ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN, dosd->alpha )) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN (fb%d - %d)!\n", OSD0, dosd->alpha ); + } + + if (ioctl( ddrv->fb[OSD1].fd, FBIO_SET_BLINK_INTERVAL, &blink )) + D_OSDERROR( "Davinci/OSD: FBIO_SET_BLINK_INTERVAL (fb%d - disable)!\n", OSD1 ); + } + + /* Update size? */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_BUFFERMODE)) { + vpbe_window_position_t win_pos; + + D_DEBUG_AT( Davinci_OSD, " -> %dx%d\n", config->width, config->height ); + +/*********************************** Start workaround ***********************************/ + win_pos.xpos = 0; + win_pos.ypos = 0; + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_SETPOS (fb%d - %d,%d) failed!\n", OSD0, win_pos.xpos, win_pos.ypos ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_SETPOS (fb%d - %d,%d) failed!\n", OSD1, win_pos.xpos, win_pos.ypos ); + + updated |= CLRCF_DEST; + + dosd->var0.yoffset = dosd->var1.yoffset = 0; +/*********************************** End workaround ***********************************/ + + /* Set width and height. */ + dosd->var0.xres = config->width; + dosd->var0.yres = config->height; + dosd->var1.xres = config->width; + dosd->var1.yres = config->height; + + dosd->var0.yres_virtual = ddrv->fb[OSD0].size / ddev->fix[OSD0].line_length; + + ret = ioctl( ddrv->fb[OSD0].fd, FBIOPUT_VSCREENINFO, &dosd->var0 ); + if (ret) + D_PERROR( "Davinci/OSD: FBIOPUT_VSCREENINFO (fb%d) failed!\n", OSD0 ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIOPUT_VSCREENINFO, &dosd->var1 ); + if (ret) + D_PERROR( "Davinci/OSD: FBIOPUT_VSCREENINFO (fb%d) failed!\n", OSD1 ); + } + + /* Update position? */ + if (updated & CLRCF_DEST) { + vpbe_window_position_t win_pos; + + D_DEBUG_AT( Davinci_OSD, " -> %d, %d\n", config->dest.x, config->dest.y ); + + /* Set horizontal and vertical offset. */ + win_pos.xpos = config->dest.x; + win_pos.ypos = config->dest.y; + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_SETPOS (fb%d - %d,%d) failed!\n", OSD0, config->dest.x, config->dest.y ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_SETPOS (fb%d - %d,%d) failed!\n", OSD1, config->dest.x, config->dest.y ); + } + + davincifb_pan_display( &ddrv->fb[OSD0], &dosd->var0, + (config->format == DSPF_RGB16) ? lock : NULL, DSFLIP_NONE, 0, 0 ); + + ret = ioctl( ddrv->fb[OSD0].fd, FBIOGET_FSCREENINFO, &ddev->fix[OSD0] ); + if (ret) + D_PERROR( "Davinci/OSD: FBIOGET_FSCREENINFO (fb%d) failed!\n", OSD0 ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIOGET_FSCREENINFO, &ddev->fix[OSD1] ); + if (ret) + D_PERROR( "Davinci/OSD: FBIOGET_FSCREENINFO (fb%d) failed!\n", OSD1 ); + + dosd->enable = true; + + if (ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN, 0 )) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN (fb%d - %d)!\n", OSD0, 0 ); + + return DFB_OK; +} + +static DFBResult +osdRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciOSDLayerData *dosd = layer_data; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + D_ASSERT( ddrv != NULL ); + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD0, 0 ); + + ret = ioctl( ddrv->fb[OSD1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD1, 0 ); + + dosd->enable = false; + + return DFB_OK; +} + +static void +update_buffers( DavinciDriverData *ddrv, + DavinciDeviceData *ddev, + CoreSurface *surface, + CoreSurfaceBufferLock *lock, + const DFBRegion *update ) +{ + DFBRectangle rect; + CoreSurfaceBuffer *buffer; + + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + DFB_REGION_ASSERT_IF( update ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + if (update) { + rect = DFB_RECTANGLE_INIT_FROM_REGION( update ); + + if (rect.x & 1) { + rect.x &= ~1; + rect.w++; + } + + if (rect.w & 1) + rect.w++; + } + else { + rect.x = 0; + rect.y = 0; + rect.w = surface->config.size.w; + rect.h = surface->config.size.h; + } + + /* Can we use the DSP? */ + if (ddrv->c64x_present) { + int i; + int lines = ddev->fix[OSD0].line_length == ddev->fix[OSD1].line_length ? rect.h : 1; + unsigned long rgb = ddev->fix[OSD0].smem_start + rect.x * 2 + rect.y * ddev->fix[OSD0].line_length; + unsigned long alpha = ddev->fix[OSD1].smem_start + rect.x / 2 + rect.y * ddev->fix[OSD1].line_length; + unsigned long src = lock->phys + rect.x * 4 + rect.y * lock->pitch; + + //D_ASSUME( ddev->fix[OSD0].line_length == ddev->fix[OSD1].line_length ); + + dfb_gfxcard_lock( GDLF_NONE ); + + /* Dither ARGB to RGB16+A3 using the DSP. */ + for (i=0; i rect.h - i) + lines = rect.h - i; + + davinci_c64x_dither_argb__L( &ddrv->tasks, rgb, alpha, + ddev->fix[OSD0].line_length, src, lock->pitch, rect.w, lines ); + + if (ddev->fix[OSD0].line_length != ddev->fix[OSD1].line_length && lines > 1) { + davinci_c64x_blit_32__L( &ddrv->tasks, + alpha + ddev->fix[OSD1].line_length, ddev->fix[OSD1].line_length, + alpha + ddev->fix[OSD0].line_length, ddev->fix[OSD0].line_length, + rect.w/2, lines - 1 ); + } + + rgb += lines * ddev->fix[OSD0].line_length; + alpha += lines * ddev->fix[OSD1].line_length; + src += lines * lock->pitch; + } + + /* Flush the write cache. */ + davinci_c64x_write_back_all( &ddrv->c64x ); + + + davinci_c64x_emit_tasks( &ddrv->c64x, &ddrv->tasks, C64X_TEF_RESET ); + + + dfb_gfxcard_unlock(); + } + else { + u32 *src32 = lock->addr + rect.y * lock->pitch + DFB_BYTES_PER_LINE( buffer->format, rect.x ); + int sp4 = lock->pitch / 4; + u32 *dst32 = ddrv->fb[OSD0].mem + rect.y * ddev->fix[OSD0].line_length + rect.x * 2; + int dp4 = ddev->fix[OSD0].line_length / 4; + u8 *dst8 = ddrv->fb[OSD1].mem + rect.y * ddev->fix[OSD1].line_length + rect.x / 2; + int dp = ddev->fix[OSD1].line_length; + int w2 = rect.w / 2; + u32 z = 0; + + switch (buffer->format) { + case DSPF_ARGB4444: + while (rect.h--) { + int x; + + for (x=0; x> 1) | + ((src32[x] & 0x000f000f) << 1) | ((src32[x] & 0x00080008) >> 3); + + dst8[x] = ((src32[x] & 0xe0000000) >> 29) | ((src32[x] & 0x0000e000) >> 9); + } + + src32 += sp4; + dst32 += dp4; + dst8 += dp; + } + break; + + case DSPF_ARGB1555: + while (rect.h--) { + int x; + + for (x=0; x> 8) | + ((s0 & 0x0000fc00) >> 5) | + ((s0 & 0x000000f8) >> 3) | + ((s1 & 0x00f80000) << 8) | + ((s1 & 0x0000fc00) << 11) | + ((s1 & 0x000000f8) << 13) ; + +#ifndef DAVINCI_NO_DITHER + if ((s0 & s1) >> 24 == 0xff) + dst8[x] = 0x77; + else { + register int pt, da; + + z ^= ((z << 13) | (z >> 19)); + z += 0x87654321; + pt = s0 - ((s0 & 0xf8000000) >> 3); + da = (((pt >> 29) & 0x07) + ( ((z&0x1f) - ((pt >> 24) & 0x1f))>>31 )) << 4; + + z ^= ((z << 13) | (z >> 19)); + z += 0x87654321; + pt = s1 - ((s1 & 0xf8000000) >> 3); + da |= (((pt >> 29) & 0x07) + ( ((z&0x1f) - ((pt >> 24) & 0x1f))>>31 )); + + + dst8[x] = da; + } +#else + dst8[x] = ((s0 & 0xe0000000) >> 25) | + ((s1 & 0xe0000000) >> 29) ; +#endif + } + + src32 += sp4; + dst32 += dp4; + dst8 += dp; + } + break; + + default: + D_ONCE( "unsupported format" ); + } + } +} + +static void +update_rgb( DavinciDriverData *ddrv, + DavinciDeviceData *ddev, + CoreSurface *surface, + CoreSurfaceBufferLock *lock, + const DFBRegion *update ) +{ + DFBRectangle rect; + CoreSurfaceBuffer *buffer; + + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + DFB_REGION_ASSERT_IF( update ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + if (update) + rect = DFB_RECTANGLE_INIT_FROM_REGION( update ); + else { + rect.x = 0; + rect.y = 0; + rect.w = surface->config.size.w; + rect.h = surface->config.size.h; + } + + dfb_convert_to_rgb16( buffer->format, + lock->addr + rect.y * lock->pitch + DFB_BYTES_PER_LINE( buffer->format, rect.x ), + lock->pitch, + surface->config.size.h, + ddrv->fb[OSD0].mem + rect.y * ddev->fix[OSD0].line_length + rect.x * 2, + ddev->fix[OSD0].line_length, + rect.w, rect.h ); +} + +static void +enable_osd( DavinciDriverData *ddrv, + DavinciOSDLayerData *dosd ) +{ + if (!dosd->enable) + return; + + ioctl( ddrv->fb[OSD0].fd, FBIO_WAITFORVSYNC ); + + if (ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN, dosd->alpha )) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN (fb%d - %d)!\n", OSD0, dosd->alpha ); + + if (ioctl( ddrv->fb[OSD0].fd, FBIO_ENABLE_DISABLE_WIN, 1 )) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD0, 1 ); + + if (ioctl( ddrv->fb[OSD1].fd, FBIO_ENABLE_DISABLE_WIN, dosd->alpha )) + D_OSDERROR( "Davinci/OSD: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", OSD1, dosd->alpha ); + + dosd->enable = false; +} + +static DFBResult +osdFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + CoreSurfaceBuffer *buffer; + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = ddrv->ddev; + DavinciOSDLayerData *dosd = layer_data; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + if (buffer->format != DSPF_RGB16) { + if (DFB_PIXELFORMAT_HAS_ALPHA( buffer->format )) + update_buffers( ddrv, ddev, surface, lock, NULL ); + else + update_rgb( ddrv, ddev, surface, lock, NULL ); + } + else + davincifb_pan_display( &ddrv->fb[OSD0], &dosd->var0, lock, flags, 0, 0 ); + + dfb_surface_flip( surface, false ); + + enable_osd( ddrv, dosd ); + + return DFB_OK; +} + +static DFBResult +osdUpdateRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + const DFBRegion *update, + CoreSurfaceBufferLock *lock ) +{ + CoreSurfaceBuffer *buffer; + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = ddrv->ddev; + DavinciOSDLayerData *dosd = layer_data; + + D_DEBUG_AT( Davinci_OSD, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + if (buffer->format != DSPF_RGB16) { + if (DFB_PIXELFORMAT_HAS_ALPHA( buffer->format )) + update_buffers( ddrv, ddev, surface, lock, update ); + else + update_rgb( ddrv, ddev, surface, lock, update ); + } + + enable_osd( ddrv, dosd ); + + return DFB_OK; +} + +const DisplayLayerFuncs davinciOSDLayerFuncs = { + .LayerDataSize = osdLayerDataSize, + .InitLayer = osdInitLayer, + + .TestRegion = osdTestRegion, + .SetRegion = osdSetRegion, + .RemoveRegion = osdRemoveRegion, + .FlipRegion = osdFlipRegion, + .UpdateRegion = osdUpdateRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_osd.h b/Source/DirectFB/gfxdrivers/davinci/davinci_osd.h new file mode 100755 index 0000000..4487b7f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_osd.h @@ -0,0 +1,53 @@ +/* + TI Davinci driver - Graphics Layer + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_OSD_H__ +#define __DAVINCI_OSD_H__ + +#include + +#include + +#define DAVINCI_OSD_SUPPORTED_OPTIONS (DLOP_ALPHACHANNEL | DLOP_OPACITY | DLOP_SRC_COLORKEY) + + +typedef struct { + struct fb_var_screeninfo var0; + struct fb_var_screeninfo var1; + + bool alpha; + bool enable; +} DavinciOSDLayerData; + + +extern const DisplayLayerFuncs davinciOSDLayerFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.c b/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.c new file mode 100755 index 0000000..6744adb --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.c @@ -0,0 +1,394 @@ +/* + TI Davinci driver - OSD0 FB Memory for direct RGB16 mode + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include + +#include +#include + +#include + +#include + +#include "davincifb.h" + +#include "davinci_gfxdriver.h" + +D_DEBUG_DOMAIN( OSD_Surfaces, "OSD/Surfaces", "OSD Framebuffer Surface Pool" ); +D_DEBUG_DOMAIN( OSD_SurfLock, "OSD/SurfLock", "OSD Framebuffer Surface Pool Locks" ); + +/**********************************************************************************************************************/ + +typedef struct { + int magic; +} OSDPoolData; + +typedef struct { + int magic; + + CoreDFB *core; + void *mem; + unsigned long phys; +} OSDPoolLocalData; + +typedef struct { + int magic; + + int offset; + int pitch; + int size; +} OSDAllocationData; + +/**********************************************************************************************************************/ + +static int +osdPoolDataSize( void ) +{ + return sizeof(OSDPoolData); +} + +static int +osdPoolLocalDataSize( void ) +{ + return sizeof(OSDPoolLocalData); +} + +static int +osdAllocationDataSize( void ) +{ + return sizeof(OSDAllocationData); +} + +static DFBResult +osdInitPool( CoreDFB *core, + CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + void *system_data, + CoreSurfacePoolDescription *ret_desc ) +{ + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + DavinciDriverData *ddrv = dfb_gfxcard_get_driver_data(); + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( OSD_Surfaces, "%s()\n", __FUNCTION__ ); + + D_ASSERT( core != NULL ); + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_ASSERT( data != NULL ); + D_ASSERT( local != NULL ); + D_ASSERT( ret_desc != NULL ); + + ret_desc->caps = CSPCAPS_NONE; + ret_desc->types = CSTF_LAYER | CSTF_SHARED | CSTF_EXTERNAL; + ret_desc->priority = CSPP_PREFERED; + + ret_desc->access[CSAID_CPU] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + ret_desc->access[CSAID_GPU] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + ret_desc->access[CSAID_LAYER0] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + + snprintf( ret_desc->name, DFB_SURFACE_POOL_DESC_NAME_LENGTH, "OSD Pool" ); + + local->core = core; + local->mem = ddrv->fb[OSD0].mem; + local->phys = ddev->fix[OSD0].smem_start; + + D_MAGIC_SET( data, OSDPoolData ); + D_MAGIC_SET( local, OSDPoolLocalData ); + + return DFB_OK; +} + +static DFBResult +osdJoinPool( CoreDFB *core, + CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + void *system_data ) +{ + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + DavinciDriverData *ddrv = dfb_gfxcard_get_driver_data(); + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( OSD_Surfaces, "%s()\n", __FUNCTION__ ); + + D_ASSERT( core != NULL ); + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_ASSERT( local != NULL ); + + (void) data; + + local->core = core; + local->mem = ddrv->fb[OSD0].mem; + local->phys = ddev->fix[OSD0].smem_start; + + D_MAGIC_SET( local, OSDPoolLocalData ); + + return DFB_OK; +} + +static DFBResult +osdDestroyPool( CoreSurfacePool *pool, + void *pool_data, + void *pool_local ) +{ + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + + D_DEBUG_AT( OSD_Surfaces, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_MAGIC_ASSERT( local, OSDPoolLocalData ); + + D_MAGIC_CLEAR( data ); + D_MAGIC_CLEAR( local ); + + return DFB_OK; +} + +static DFBResult +osdLeavePool( CoreSurfacePool *pool, + void *pool_data, + void *pool_local ) +{ + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + + D_DEBUG_AT( OSD_Surfaces, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_MAGIC_ASSERT( local, OSDPoolLocalData ); + + (void) data; + + D_MAGIC_CLEAR( local ); + + return DFB_OK; +} + +static DFBResult +osdTestConfig( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + const CoreSurfaceConfig *config ) +{ + CoreSurface *surface; + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + + D_DEBUG_AT( OSD_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_MAGIC_ASSERT( local, OSDPoolLocalData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + + (void) data; + (void) local; + + surface = buffer->surface; + D_MAGIC_ASSERT( surface, CoreSurface ); + + if ((surface->type & CSTF_LAYER) && surface->resource_id == DLID_PRIMARY && surface->config.format == DSPF_RGB16) + return DFB_OK; + + return DFB_UNSUPPORTED; +} + +static DFBResult +osdAllocateBuffer( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + CoreSurfaceAllocation *allocation, + void *alloc_data ) +{ + CoreSurface *surface; + OSDPoolData *data = pool_data; + OSDPoolLocalData *local = pool_local; + OSDAllocationData *alloc = alloc_data; + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( OSD_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_MAGIC_ASSERT( local, OSDPoolLocalData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + + (void) data; + (void) local; + + surface = buffer->surface; + D_MAGIC_ASSERT( surface, CoreSurface ); + + if ((surface->type & CSTF_LAYER) && surface->resource_id == DLID_PRIMARY && surface->config.format == DSPF_RGB16) { + int index = dfb_surface_buffer_index( buffer ); + + alloc->pitch = ddev->fix[OSD0].line_length; + alloc->size = surface->config.size.h * alloc->pitch; + alloc->offset = index * alloc->size; + + D_DEBUG_AT( OSD_Surfaces, " -> index %d, offset %d, pitch %d, size %d\n", + index, alloc->offset, alloc->pitch, alloc->size ); + + allocation->size = alloc->size; + allocation->offset = alloc->offset; + + D_MAGIC_SET( alloc, OSDAllocationData ); + + return DFB_OK; + } + + return DFB_BUG; +} + +static DFBResult +osdDeallocateBuffer( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + CoreSurfaceAllocation *allocation, + void *alloc_data ) +{ + OSDPoolData *data = pool_data; + OSDAllocationData *alloc = alloc_data; + + D_DEBUG_AT( OSD_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, OSDPoolData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + D_MAGIC_ASSERT( alloc, OSDAllocationData ); + + (void) data; + + D_MAGIC_CLEAR( alloc ); + + return DFB_OK; +} + +static DFBResult +osdLock( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceAllocation *allocation, + void *alloc_data, + CoreSurfaceBufferLock *lock ) +{ + OSDPoolLocalData *local = pool_local; + OSDAllocationData *alloc = alloc_data; + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( allocation, CoreSurfaceAllocation ); + D_MAGIC_ASSERT( alloc, OSDAllocationData ); + D_MAGIC_ASSERT( lock, CoreSurfaceBufferLock ); + + D_DEBUG_AT( OSD_SurfLock, "%s( %p )\n", __FUNCTION__, lock->buffer ); + + int index = alloc->offset / alloc->size; + int height = alloc->size / alloc->pitch; + + alloc->pitch = ddev->fix[OSD0].line_length; + alloc->size = height * alloc->pitch; + alloc->offset = index * alloc->size; + + allocation->size = alloc->size; + allocation->offset = alloc->offset; + + lock->pitch = alloc->pitch; + lock->offset = alloc->offset; + lock->addr = local->mem + alloc->offset; + lock->phys = local->phys + alloc->offset; + + D_DEBUG_AT( OSD_SurfLock, " -> offset %lu, pitch %d, addr %p, phys 0x%08lx\n", + lock->offset, lock->pitch, lock->addr, lock->phys ); + + return DFB_OK; +} + +static DFBResult +osdUnlock( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceAllocation *allocation, + void *alloc_data, + CoreSurfaceBufferLock *lock ) +{ + OSDAllocationData *alloc = alloc_data; + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( allocation, CoreSurfaceAllocation ); + D_MAGIC_ASSERT( alloc, OSDAllocationData ); + D_MAGIC_ASSERT( lock, CoreSurfaceBufferLock ); + + D_DEBUG_AT( OSD_SurfLock, "%s( %p )\n", __FUNCTION__, lock->buffer ); + + (void) alloc; + + return DFB_OK; +} + +const SurfacePoolFuncs davinciOSDSurfacePoolFuncs = { + .PoolDataSize = osdPoolDataSize, + .PoolLocalDataSize = osdPoolLocalDataSize, + .AllocationDataSize = osdAllocationDataSize, + + .InitPool = osdInitPool, + .JoinPool = osdJoinPool, + .DestroyPool = osdDestroyPool, + .LeavePool = osdLeavePool, + + .TestConfig = osdTestConfig, + .AllocateBuffer = osdAllocateBuffer, + .DeallocateBuffer = osdDeallocateBuffer, + + .Lock = osdLock, + .Unlock = osdUnlock, +}; + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.h b/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.h new file mode 100755 index 0000000..05316db --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_osd_pool.h @@ -0,0 +1,39 @@ +/* + TI Davinci driver - OSD0 FB Memory for direct RGB16 mode + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_OSD_POOL_H__ +#define __DAVINCI_OSD_POOL_H__ + +#include + +extern const SurfacePoolFuncs davinciOSDSurfacePoolFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_screen.c b/Source/DirectFB/gfxdrivers/davinci/davinci_screen.c new file mode 100755 index 0000000..65fd751 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_screen.c @@ -0,0 +1,124 @@ +/* + TI Davinci driver - Primary Screen + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include + +#include + +#include + +#include +#include + +#include + +#include "davincifb.h" + +#include "davinci_gfxdriver.h" +#include "davinci_screen.h" + + +D_DEBUG_DOMAIN( Davinci_Screen, "Davinci/Screen", "TI Davinci Screen" ); + +/**********************************************************************************************************************/ + +static DFBResult +davinciInitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + D_DEBUG_AT( Davinci_Screen, "%s()\n", __FUNCTION__ ); + + /* Set the screen capabilities. */ + description->caps = DSCCAPS_VSYNC; + + /* Set the screen name. */ + snprintf( description->name, DFB_SCREEN_DESC_NAME_LENGTH, "TI Davinci Screen" ); + + return DFB_OK; +} + +static DFBResult +davinciGetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + int ret; + vpbe_fb_videomode_t mode; + DavinciDriverData *ddrv = driver_data; + + D_DEBUG_AT( Davinci_Screen, "%s()\n", __FUNCTION__ ); + + D_ASSERT( ret_width != NULL ); + D_ASSERT( ret_height != NULL ); + + ret = ioctl( ddrv->fb[OSD0].fd, FBIO_GET_TIMING, &mode ); + if (ret) { + D_PERROR( "%s: FBIO_GET_TIMING (fb%d, OSD0) failed!\n", __func__, OSD0 ); + return DFB_INIT; + } + + *ret_width = mode.xres; + *ret_height = mode.yres; + + return DFB_OK; +} + +static DFBResult +davinciWaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + DavinciDriverData *ddrv = driver_data; + + D_DEBUG_AT( Davinci_Screen, "%s()\n", __FUNCTION__ ); + + ioctl( ddrv->fb[OSD0].fd, FBIO_WAITFORVSYNC ); + + return DFB_OK; +} + +ScreenFuncs davinciScreenFuncs = { + .InitScreen = davinciInitScreen, + .GetScreenSize = davinciGetScreenSize, + .WaitVSync = davinciWaitVSync, +}; + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_screen.h b/Source/DirectFB/gfxdrivers/davinci/davinci_screen.h new file mode 100755 index 0000000..1aa2494 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_screen.h @@ -0,0 +1,39 @@ +/* + TI Davinci driver - Primary Screen + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_SCREEN_H__ +#define __DAVINCI_SCREEN_H__ + +#include + +extern ScreenFuncs davinciScreenFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_video.c b/Source/DirectFB/gfxdrivers/davinci/davinci_video.c new file mode 100755 index 0000000..1a284a0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_video.c @@ -0,0 +1,744 @@ +/* + TI Davinci driver - Video Layer + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include "davincifb.h" + +#include "davinci_gfxdriver.h" +#include "davinci_video.h" + + +#define D_VIDERROR(x...) do {} while (0) + + +D_DEBUG_DOMAIN( Davinci_Video, "Davinci/Video", "TI Davinci Video" ); + +/**********************************************************************************************************************/ + +static DFBResult ShowBuffer( DavinciDriverData *ddrv, + DavinciVideoLayerData *dvid, + CoreSurfaceBufferLock *lock, + const DFBRectangle *area, + DFBSurfaceFlipFlags flags ); + +static void SetupResizerParams( vpfe_resizer_params_t *params, + int srcWidth, int srcHeight, + int outWidth, int outHeight, + int *ret_outWidth, + int *ret_outHeight ); + +/**********************************************************************************************************************/ + +static int +videoLayerDataSize( void ) +{ + return sizeof(DavinciVideoLayerData); +} + +static DFBResult +videoInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciVideoLayerData *dvid = layer_data; + + D_DEBUG_AT( Davinci_Video, "%s()\n", __FUNCTION__ ); + + /* Initialize with configuration from VID0 to start with a fullscreen (unscaled) layer */ + ret = ioctl( ddrv->fb[VID0].fd, FBIOGET_VSCREENINFO, &dvid->var ); + if (ret) { + D_PERROR( "Davinci/Video: FBIOGET_VSCREENINFO (fb%d) failed!\n", VID0 ); + return DFB_INIT; + } + + /* Disable VID0 (unused) */ + ret = ioctl( ddrv->fb[VID0].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", VID0, 0 ); + + /* Disable VID1 (our layer) */ + ret = ioctl( ddrv->fb[VID1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", VID1, 0 ); + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION; + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "TI Davinci Video" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = dvid->var.xres; + config->height = dvid->var.yres; + config->pixelformat = DSPF_UYVY; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + return DFB_OK; +} + +static DFBResult +videoTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + D_DEBUG_AT( Davinci_Video, "%s()\n", __FUNCTION__ ); + + DFB_CORE_LAYER_REGION_CONFIG_DEBUG_AT( Davinci_Video, config ); + + if (config->options & ~DAVINCI_VIDEO_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + switch (config->format) { + case DSPF_UYVY: + break; + + default: + fail |= CLRCF_FORMAT; + } + + if (config->width < 8 || config->width > 1920) + fail |= CLRCF_WIDTH; + + if (config->height < 8 || config->height > 1080) + fail |= CLRCF_HEIGHT; + + if (config->dest.x < 0 || config->dest.y < 0) + fail |= CLRCF_DEST; + + if (config->dest.x + config->dest.w > 1920) + fail |= CLRCF_DEST; + + if (config->dest.y + config->dest.h > 1080) + fail |= CLRCF_DEST; + + if (failed) + *failed = fail; + + if (fail) { + D_DEBUG_AT( Davinci_Video, " -> FAILED (0x%08x)\n", fail ); + return DFB_UNSUPPORTED; + } + + D_DEBUG_AT( Davinci_Video, " -> OK\n" ); + + return DFB_OK; +} + +static DFBResult +videoSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciDeviceData *ddev = ddrv->ddev; + DavinciVideoLayerData *dvid = layer_data; + CoreLayerRegionConfig *old = &dvid->config; + + D_DEBUG_AT( Davinci_Video, "%s( updated 0x%08x, surface %p )\n", __FUNCTION__, updated, surface ); + + DFB_CORE_LAYER_REGION_CONFIG_DEBUG_AT( Davinci_Video, config ); + + D_ASSERT( ddrv != NULL ); + D_ASSERT( ddev != NULL ); + D_ASSERT( dvid != NULL ); + + /* Update output size? */ + if ((updated & CLRCF_DEST) && (config->dest.w != old->dest.w || config->dest.h != old->dest.h)) { + vpbe_window_position_t win_pos; + + D_DEBUG_AT( Davinci_Video, " => dest %4dx%4d\n", config->dest.w, config->dest.h ); + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", VID1, 0 ); + + dvid->enabled = false; + +/*********************************** Start workaround ***********************************/ + win_pos.xpos = 0; + win_pos.ypos = 0; + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_SETPOS (fb%d - %d,%d) failed!\n", VID1, win_pos.xpos, win_pos.ypos ); + + dvid->var.yoffset = 0; +/*********************************** End workaround ***********************************/ + + /* Set output width and height. */ + dvid->var.xres = config->dest.w; + dvid->var.yres = config->dest.h; + + dvid->var.yres_virtual = ddrv->fb[VID1].size / lock->pitch; + + ret = ioctl( ddrv->fb[VID1].fd, FBIOPUT_VSCREENINFO, &dvid->var ); + if (ret) + D_PERROR( "Davinci/Video: FBIOPUT_VSCREENINFO (fb%d) failed!\n", VID1 ); + + /* Read back new pitch etc. */ + ret = ioctl( ddrv->fb[VID1].fd, FBIOGET_FSCREENINFO, &ddev->fix[VID1] ); + if (ret) + D_PERROR( "Davinci/Video: FBIOGET_FSCREENINFO (fb%d) failed!\n", VID1 ); + } + + /* Update output position? */ + if (updated & CLRCF_DEST) { + vpbe_window_position_t win_pos; + + D_DEBUG_AT( Davinci_Video, " => dest %4d,%4d\n", config->dest.x, config->dest.y ); + + if (dvid->enabled) + ioctl( ddrv->fb[VID1].fd, FBIO_WAITFORVSYNC ); + + /* Set horizontal and vertical offset. */ + win_pos.xpos = config->dest.x; + win_pos.ypos = config->dest.y; + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_SETPOS, &win_pos ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_SETPOS (fb%d - %d,%d) failed!\n", VID1, config->dest.x, config->dest.y ); + } + + /* Update format? */ + if (updated & CLRCF_FORMAT) { + vpbe_video_config_params_t params; + + params.cb_cr_order = (config->format == DSPF_YUY2) ? 1 : 0; + + params.exp_info.horizontal = VPBE_DISABLE; + params.exp_info.vertical = VPBE_DISABLE; + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_SET_VIDEO_CONFIG_PARAMS, ¶ms ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_SET_VIDEO_CONFIG_PARAMS (fb%d - %s) failed!\n", + VID1, params.cb_cr_order ? "CrCb" : "CbCr" ); + } + + /* Update scaling parameters? */ + if ((updated & (CLRCF_SOURCE | CLRCF_DEST)) && + (config->source.w != old->source.w || config->source.h != old->source.h || + config->dest.w != old->dest.w || config->dest.h != old->dest.h) && + (config->dest.w != config->source.w || config->dest.h != config->source.h)) + { + D_DEBUG_AT( Davinci_Video, " => scaling %4dx%4d -> %4dx%4d\n", + config->source.w, config->source.h, config->dest.w, config->dest.h ); + + SetupResizerParams( &dvid->resizer, config->source.w, config->source.h, + config->dest.w, config->dest.h, &dvid->resized.w, &dvid->resized.h ); + + dvid->offset.x = (config->dest.w - dvid->resized.w) / 2; + dvid->offset.y = (config->dest.h - dvid->resized.h) / 2; + + D_DEBUG_AT( Davinci_Video, " => resized %4dx%4d, centered %d,%d\n", + dvid->resized.w, dvid->resized.h, dvid->offset.x, dvid->offset.y ); + + dvid->offset.x += dvid->offset.x & 1; /* Round up to multiple of two */ + + D_DEBUG_AT( Davinci_Video, " => offset %4d,%4d\n", dvid->offset.x, dvid->offset.y ); + + davincifb_pan_display( &ddrv->fb[VID1], &dvid->var, NULL, DSFLIP_NONE, 0, 0 ); + } + + dvid->enable = true; + dvid->config = *config; + + return DFB_OK; +} + +static DFBResult +videoRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + int ret; + DavinciDriverData *ddrv = driver_data; + DavinciVideoLayerData *dvid = layer_data; + + D_DEBUG_AT( Davinci_Video, "%s()\n", __FUNCTION__ ); + + D_ASSERT( ddrv != NULL ); + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_ENABLE_DISABLE_WIN, 0 ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", VID1, 0 ); + + dvid->enabled = false; + dvid->enable = false; + + return DFB_OK; +} + +static DFBResult +videoFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + DavinciDriverData *ddrv = driver_data; + DavinciVideoLayerData *dvid = layer_data; + + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + D_ASSERT( ddrv != NULL ); + D_ASSERT( dvid != NULL ); + + D_DEBUG_AT( Davinci_Video, "%s( 0x%08lx [%d] 0x%04x [%4dx%4d] )\n", __FUNCTION__, + lock->phys, lock->pitch, flags, dvid->config.width, dvid->config.height ); + + ret = ShowBuffer( ddrv, dvid, lock, NULL, flags ); + if (ret) + return ret; + + dfb_surface_flip( surface, false ); + + return DFB_OK; +} + +static DFBResult +videoUpdateRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + const DFBRegion *update, + CoreSurfaceBufferLock *lock ) +{ + DavinciDriverData *ddrv = driver_data; + DavinciVideoLayerData *dvid = layer_data; + + D_ASSERT( surface != NULL ); + D_ASSERT( lock != NULL ); + D_ASSERT( ddrv != NULL ); + D_ASSERT( dvid != NULL ); + + if (update) { + DFBRectangle area = DFB_RECTANGLE_INIT_FROM_REGION( update ); + + D_DEBUG_AT( Davinci_Video, "%s( 0x%08lx [%d], %4d,%4d-%4dx%4d )\n", __FUNCTION__, + lock->phys, lock->pitch, DFB_RECTANGLE_VALS( &area ) ); + + if (!dfb_rectangle_intersect( &area, &dvid->config.source )) { + D_DEBUG_AT( Davinci_Video, " -> NO INTERSECTION with %4d,%4d-%4dx%4d\n", + DFB_RECTANGLE_VALS( &dvid->config.source ) ); + + return DFB_OK; + } + + if (!DFB_RECTANGLE_EQUAL( area, dvid->config.source )) + return ShowBuffer( ddrv, dvid, lock, &area, DSFLIP_NONE ); + } + else + D_DEBUG_AT( Davinci_Video, "%s( 0x%08lx [%d], %4dx%4d )\n", __FUNCTION__, + lock->phys, lock->pitch, dvid->config.width, dvid->config.height ); + + return ShowBuffer( ddrv, dvid, lock, NULL, DSFLIP_NONE ); +} + +const DisplayLayerFuncs davinciVideoLayerFuncs = { + .LayerDataSize = videoLayerDataSize, + .InitLayer = videoInitLayer, + + .TestRegion = videoTestRegion, + .SetRegion = videoSetRegion, + .RemoveRegion = videoRemoveRegion, + .FlipRegion = videoFlipRegion, + .UpdateRegion = videoUpdateRegion, +}; + +/*********************************************************************************************************************** +** Frame Output +*/ + +static void +enable_video( DavinciDriverData *ddrv, + DavinciVideoLayerData *dvid ) +{ + if (dvid->enable && !dvid->enabled) { + ioctl( ddrv->fb[VID1].fd, FBIO_WAITFORVSYNC ); + + if (ioctl( ddrv->fb[VID1].fd, FBIO_ENABLE_DISABLE_WIN, 1 )) + D_VIDERROR( "Davinci/Video: FBIO_ENABLE_DISABLE_WIN (fb%d - %d)!\n", VID1, 1 ); + + dvid->enabled = true; + } +} + +static DFBResult +ShowBuffer( DavinciDriverData *ddrv, + DavinciVideoLayerData *dvid, + CoreSurfaceBufferLock *lock, + const DFBRectangle *area, + DFBSurfaceFlipFlags flags ) +{ + const CoreLayerRegionConfig *config = &dvid->config; + + if (area) + D_DEBUG_AT( Davinci_Video, "%s( 0x%08lx [%d], %4d,%4d-%4dx%4d )\n", __FUNCTION__, + lock->phys, lock->pitch, DFB_RECTANGLE_VALS( area ) ); + else + D_DEBUG_AT( Davinci_Video, "%s( 0x%08lx [%d] )\n", __FUNCTION__, lock->phys, lock->pitch ); + + if (config->dest.w == config->source.w && config->dest.h == config->source.h) { + /* + * Unscaled video, buffer displayed directly + */ + D_DEBUG_AT( Davinci_Video, " -> unscaled %4dx%4d <- %4d,%4d [%4dx%4d]\n", + config->source.w, config->source.h, config->source.x, config->source.y, + config->width, config->height ); + + /* Partial update, assuming proper buffer is shown, saving system calls */ + if (area && dvid->enabled) + return DFB_OK; + + davincifb_pan_display( &ddrv->fb[VID1], &dvid->var, lock, flags, config->source.x, config->source.y ); + } + else { + int ret; + DavinciDeviceData *ddev = ddrv->ddev; + CoreSurfaceBuffer *buffer = lock->buffer; + vpfe_resizer_params_t *params = &dvid->resizer; + + /* + * Scaled video, buffer scaled to output buffer by resizer + */ + D_DEBUG_AT( Davinci_Video, " -> scaled %4dx%4d -> %4dx%4d <- %4d,%4d [%4dx%4d]\n", + config->source.w, config->source.h, config->dest.w, config->dest.h, + config->source.x, config->source.y, config->width, config->height ); + + /* FIXME: Implement scaled partial updates! */ + if (area) + D_UNIMPLEMENTED(); + + params->sdr_inoff = lock->pitch; + params->sdr_inadd = lock->phys + DFB_BYTES_PER_LINE( buffer->format, config->source.x ) + + config->source.y * params->sdr_inoff; + + params->sdr_outoff = ddev->fix[VID1].line_length; + params->sdr_outadd = ddev->fix[VID1].smem_start + dvid->offset.x * 2 + + dvid->offset.y * params->sdr_outoff; + + params->in_start = (params->sdr_outadd & 0x1f) / 2; + params->sdr_outadd &= ~0x1f; + + D_DEBUG_AT( Davinci_Video, " -> FBIO_RESIZER running...\n" ); + + ret = ioctl( ddrv->fb[VID1].fd, FBIO_RESIZER, params ); + if (ret) + D_VIDERROR( "Davinci/Video: FBIO_RESIZER (fb%d)!\n", VID1 ); + + D_DEBUG_AT( Davinci_Video, " => FBIO_RESIZER returned %d\n", ret ); + } + + enable_video( ddrv, dvid ); + + return DFB_OK; +} + +/*********************************************************************************************************************** +** Scaling Setup +*/ + +static int +limitInput(int rsz,int inSize,int outSize,int* pInSize) +{ + int phases; + int phaseShift; + int taps; + int phaseMask; + int coarseShift; + int halfCoarse; + int tmp; + + do { + if (rsz<=512) { + //1/2x to 4x resize uses 8 phase, 4 taps + phaseShift = 3; + taps = 4; + } + else { + //4-phase, 7 taps + phaseShift = 2; + taps = 7; + } + phases = 1<>8) + taps; + if (tmp <= inSize) break; + rsz--; + } while (1); + + *pInSize = tmp; + + return rsz; +} + +static void +SetupCoef(unsigned int* pCoef,int rsz) +{ + int startCoef; + int highCoef; + int c; + int phases; + int taps; + if (rsz<=512) { + //1/2x to 4x resize uses 8 phase, 4 taps + highCoef = 0x100; + c=1; + phases=8; + taps=4; + } + else { + //4-phase, 7 taps + if (rsz<=(256*3)) { + highCoef = 0x100/2; c=2; + } + else { + highCoef = 0x100/4; c=1; + } + phases=4; + taps=7; + } + startCoef = highCoef>>1; + while (phases) { + int prev = startCoef; + int tapNum=0; + int rem=256 - startCoef; + while ( tapNum < (c-1)) { + *pCoef++ = 0; + tapNum+=2; + } + if (c&1) { + *pCoef++ = prev<<16; + tapNum+=2; + } + else { + tapNum++; + } + while ( tapNum < taps) { + int min = (rem (highCoef>>3)) startCoef -= (highCoef>>3); + else { + startCoef = highCoef; c++; + } + phases--; + } +} + +#define SDRAM_SRC (1<<28) +#define BILINEAR (1<<29) + +static void +SetupResizerParams( vpfe_resizer_params_t *params, + int srcWidth, int srcHeight, + int outWidth, int outHeight, + int *ret_outWidth, + int *ret_outHeight ) +{ + int rsz; + int hrsz; + int vrsz; + int tmp; + + D_DEBUG_AT( Davinci_Video, "%s( %4dx%4d->%4dx%4d )\n", __FUNCTION__, srcWidth, srcHeight, outWidth, outHeight ); + + params->sdr_inadd = 0; + params->sdr_inoff = 0; + + params->sdr_outadd = 0; + params->sdr_outoff = 0; + + params->in_start = (0<<16)|(0); + params->yenh = 0; + + params->rsz_cnt = SDRAM_SRC; + + + + + //find scale factor + rsz = (srcWidth<<8)/outWidth; + if (rsz<64) { + //too much upscaling, reduce destination size + rsz = 64; + } + else if (rsz>1024) { + //too much down scaling, reduce source size + rsz=1024; + srcWidth = (outWidth * rsz)>>8; + } + + tmp = ((srcWidth<<8)+255)/rsz; + if (tmp > outWidth) tmp = outWidth; + tmp &= ~1; //force even + if (rsz>256) { + //upsize in vertical direction requires a multiple of 16 bytes (8 pixels) + tmp &= ~0x7; + } + do { + int t; + hrsz = limitInput(rsz,srcWidth,tmp,&t); + if (hrsz>=64) { + srcWidth = t; + break; + } + tmp-=2; + } while (1); + outWidth = tmp; + + if (srcWidth==outWidth) { + int i=0; + params->rsz_cnt |= ((256-1)<<0); //1 to 1 + params->in_size = (srcWidth+3); //4 taps + while (i<16) { + params->hfilt[i] = i? 0 : 0x100; //2 coefficient written at a time + i++; + } + } + else { + SetupCoef(¶ms->hfilt[0],hrsz); + params->rsz_cnt |= ((hrsz-1)<<0) | ((hrsz<256)? BILINEAR : 0); + params->in_size = (srcWidth); + } + + + + + //find scale factor + rsz = (srcHeight<<8)/outHeight; + if (rsz<64) { + //too much upscaling, reduce destination size + rsz = 64; + } + else if (rsz>1024) { + //too much down scaling, reduce source size + rsz=1024; + srcHeight = (outHeight * rsz)>>8; + } + + tmp = ((srcHeight<<8)+255)/rsz; + if (tmp > outHeight) tmp = outHeight; + do { + int t; + vrsz = limitInput(rsz,srcHeight,tmp,&t); + if (vrsz>=64) { + srcHeight = t; + break; + } + tmp--; + } while (1); + outHeight = tmp; + + if (srcHeight==outHeight) { + int i=0; + params->rsz_cnt |= ((256-1)<<10); //1 to 1 + params->in_size |= ((srcHeight+3)<<16); //4 taps + while (i<16) { + params->vfilt[i] = i? 0 : 0x100; //2 coefficient written at a time + i++; + } + } + else { + SetupCoef(¶ms->vfilt[0],vrsz); + params->rsz_cnt |= ((vrsz-1)<<10); + params->in_size |= (srcHeight<<16); + } + + + params->out_size = (outHeight<<16)|(outWidth); + + D_DEBUG_AT( Davinci_Video, " => %4dx%4d->%4dx%4d\n", srcWidth, srcHeight, outWidth, outHeight ); + + if (ret_outWidth) + *ret_outWidth = outWidth; + + if (ret_outHeight) + *ret_outHeight = outHeight; +} + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_video.h b/Source/DirectFB/gfxdrivers/davinci/davinci_video.h new file mode 100755 index 0000000..7d6e206 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_video.h @@ -0,0 +1,58 @@ +/* + TI Davinci driver - Video Layer + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_VIDEO_H__ +#define __DAVINCI_VIDEO_H__ + +#include + +#include + +#define DAVINCI_VIDEO_SUPPORTED_OPTIONS (DLOP_NONE) + + +typedef struct { + struct fb_var_screeninfo var; + + bool enable; + bool enabled; + + CoreLayerRegionConfig config; + + vpfe_resizer_params_t resizer; + DFBDimension resized; + DFBPoint offset; +} DavinciVideoLayerData; + + +extern const DisplayLayerFuncs davinciVideoLayerFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.c b/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.c new file mode 100755 index 0000000..f0f45b5 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.c @@ -0,0 +1,393 @@ +/* + TI Davinci driver - VID1 FB Memory for direct UYVY mode + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include + +#include +#include + +#include + +#include + +#include "davincifb.h" + +#include "davinci_gfxdriver.h" + +D_DEBUG_DOMAIN( Video_Surfaces, "Video/Surfaces", "Video Framebuffer Surface Pool" ); +D_DEBUG_DOMAIN( Video_SurfLock, "Video/SurfLock", "Video Framebuffer Surface Pool Locks" ); + +/**********************************************************************************************************************/ + +typedef struct { + int magic; +} VideoPoolData; + +typedef struct { + int magic; + + CoreDFB *core; + void *mem; + unsigned long phys; +} VideoPoolLocalData; + +typedef struct { + int magic; + + int offset; + int pitch; + int size; +} VideoAllocationData; + +/**********************************************************************************************************************/ + +static int +videoPoolDataSize( void ) +{ + return sizeof(VideoPoolData); +} + +static int +videoPoolLocalDataSize( void ) +{ + return sizeof(VideoPoolLocalData); +} + +static int +videoAllocationDataSize( void ) +{ + return sizeof(VideoAllocationData); +} + +static DFBResult +videoInitPool( CoreDFB *core, + CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + void *system_data, + CoreSurfacePoolDescription *ret_desc ) +{ + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + DavinciDriverData *ddrv = dfb_gfxcard_get_driver_data(); + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( Video_Surfaces, "%s()\n", __FUNCTION__ ); + + D_ASSERT( core != NULL ); + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_ASSERT( data != NULL ); + D_ASSERT( local != NULL ); + D_ASSERT( ret_desc != NULL ); + + ret_desc->caps = CSPCAPS_NONE; + ret_desc->types = CSTF_LAYER | CSTF_SHARED | CSTF_EXTERNAL; + ret_desc->priority = CSPP_DEFAULT; + + ret_desc->access[CSAID_CPU] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + ret_desc->access[CSAID_GPU] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + ret_desc->access[CSAID_LAYER1] = CSAF_READ | CSAF_WRITE | CSAF_SHARED; + + snprintf( ret_desc->name, DFB_SURFACE_POOL_DESC_NAME_LENGTH, "Video Pool" ); + + local->core = core; + local->mem = ddrv->fb[VID1].mem; + local->phys = ddev->fix[VID1].smem_start; + + D_MAGIC_SET( data, VideoPoolData ); + D_MAGIC_SET( local, VideoPoolLocalData ); + + return DFB_OK; +} + +static DFBResult +videoJoinPool( CoreDFB *core, + CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + void *system_data ) +{ + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + DavinciDriverData *ddrv = dfb_gfxcard_get_driver_data(); + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( Video_Surfaces, "%s()\n", __FUNCTION__ ); + + D_ASSERT( core != NULL ); + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_ASSERT( local != NULL ); + + (void) data; + + local->core = core; + local->mem = ddrv->fb[VID1].mem; + local->phys = ddev->fix[VID1].smem_start; + + D_MAGIC_SET( local, VideoPoolLocalData ); + + return DFB_OK; +} + +static DFBResult +videoDestroyPool( CoreSurfacePool *pool, + void *pool_data, + void *pool_local ) +{ + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + + D_DEBUG_AT( Video_Surfaces, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_MAGIC_ASSERT( local, VideoPoolLocalData ); + + D_MAGIC_CLEAR( data ); + D_MAGIC_CLEAR( local ); + + return DFB_OK; +} + +static DFBResult +videoLeavePool( CoreSurfacePool *pool, + void *pool_data, + void *pool_local ) +{ + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + + D_DEBUG_AT( Video_Surfaces, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_MAGIC_ASSERT( local, VideoPoolLocalData ); + + (void) data; + + D_MAGIC_CLEAR( local ); + + return DFB_OK; +} + +static DFBResult +videoTestConfig( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + const CoreSurfaceConfig *config ) +{ + CoreSurface *surface; + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + + D_DEBUG_AT( Video_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_MAGIC_ASSERT( local, VideoPoolLocalData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + + (void) data; + (void) local; + + surface = buffer->surface; + D_MAGIC_ASSERT( surface, CoreSurface ); + + if ((surface->type & CSTF_LAYER) && surface->resource_id == 1) + return DFB_OK; + + return DFB_UNSUPPORTED; +} + +static DFBResult +videoAllocateBuffer( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + CoreSurfaceAllocation *allocation, + void *alloc_data ) +{ + CoreSurface *surface; + VideoPoolData *data = pool_data; + VideoPoolLocalData *local = pool_local; + VideoAllocationData *alloc = alloc_data; + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_DEBUG_AT( Video_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_MAGIC_ASSERT( local, VideoPoolLocalData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + + (void) data; + (void) local; + + surface = buffer->surface; + D_MAGIC_ASSERT( surface, CoreSurface ); + + if ((surface->type & CSTF_LAYER) && surface->resource_id == 1) { + int index = dfb_surface_buffer_index( buffer ); + + alloc->pitch = ddev->fix[VID1].line_length; + alloc->size = surface->config.size.h * alloc->pitch; + alloc->offset = index * alloc->size; + + D_DEBUG_AT( Video_Surfaces, " -> offset %d, pitch %d, size %d\n", alloc->offset, alloc->pitch, alloc->size ); + + allocation->size = alloc->size; + allocation->offset = alloc->offset; + + D_MAGIC_SET( alloc, VideoAllocationData ); + + return DFB_OK; + } + + return DFB_BUG; +} + +static DFBResult +videoDeallocateBuffer( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceBuffer *buffer, + CoreSurfaceAllocation *allocation, + void *alloc_data ) +{ + VideoPoolData *data = pool_data; + VideoAllocationData *alloc = alloc_data; + + D_DEBUG_AT( Video_Surfaces, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( data, VideoPoolData ); + D_MAGIC_ASSERT( buffer, CoreSurfaceBuffer ); + D_MAGIC_ASSERT( alloc, VideoAllocationData ); + + (void) data; + + D_MAGIC_CLEAR( alloc ); + + return DFB_OK; +} + +static DFBResult +videoLock( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceAllocation *allocation, + void *alloc_data, + CoreSurfaceBufferLock *lock ) +{ + VideoPoolLocalData *local = pool_local; + VideoAllocationData *alloc = alloc_data; + DavinciDeviceData *ddev = dfb_gfxcard_get_device_data(); + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( allocation, CoreSurfaceAllocation ); + D_MAGIC_ASSERT( alloc, VideoAllocationData ); + D_MAGIC_ASSERT( lock, CoreSurfaceBufferLock ); + + D_DEBUG_AT( Video_SurfLock, "%s( %p )\n", __FUNCTION__, lock->buffer ); + + int index = alloc->offset / alloc->size; + int height = alloc->size / alloc->pitch; + + alloc->pitch = ddev->fix[VID1].line_length; + alloc->size = height * alloc->pitch; + alloc->offset = index * alloc->size; + + allocation->size = alloc->size; + allocation->offset = alloc->offset; + + lock->pitch = alloc->pitch; + lock->offset = alloc->offset; + lock->addr = local->mem + alloc->offset; + lock->phys = local->phys + alloc->offset; + + D_DEBUG_AT( Video_SurfLock, " -> offset %lu, pitch %d, addr %p, phys 0x%08lx\n", + lock->offset, lock->pitch, lock->addr, lock->phys ); + + return DFB_OK; +} + +static DFBResult +videoUnlock( CoreSurfacePool *pool, + void *pool_data, + void *pool_local, + CoreSurfaceAllocation *allocation, + void *alloc_data, + CoreSurfaceBufferLock *lock ) +{ + VideoAllocationData *alloc = alloc_data; + + D_MAGIC_ASSERT( pool, CoreSurfacePool ); + D_MAGIC_ASSERT( allocation, CoreSurfaceAllocation ); + D_MAGIC_ASSERT( alloc, VideoAllocationData ); + D_MAGIC_ASSERT( lock, CoreSurfaceBufferLock ); + + D_DEBUG_AT( Video_SurfLock, "%s( %p )\n", __FUNCTION__, lock->buffer ); + + (void) alloc; + + return DFB_OK; +} + +const SurfacePoolFuncs davinciVideoSurfacePoolFuncs = { + .PoolDataSize = videoPoolDataSize, + .PoolLocalDataSize = videoPoolLocalDataSize, + .AllocationDataSize = videoAllocationDataSize, + + .InitPool = videoInitPool, + .JoinPool = videoJoinPool, + .DestroyPool = videoDestroyPool, + .LeavePool = videoLeavePool, + + .TestConfig = videoTestConfig, + .AllocateBuffer = videoAllocateBuffer, + .DeallocateBuffer = videoDeallocateBuffer, + + .Lock = videoLock, + .Unlock = videoUnlock, +}; + diff --git a/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.h b/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.h new file mode 100755 index 0000000..dd60b12 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davinci_video_pool.h @@ -0,0 +1,39 @@ +/* + TI Davinci driver - VID1 FB Memory for direct UYVY mode + + (c) Copyright 2007 Telio AG + + Written by Denis Oliver Kropp + + Code is derived from VMWare driver. + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __DAVINCI_VIDEO_POOL_H__ +#define __DAVINCI_VIDEO_POOL_H__ + +#include + +extern const SurfacePoolFuncs davinciVideoSurfacePoolFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/davinci/davincifb.h b/Source/DirectFB/gfxdrivers/davinci/davincifb.h new file mode 100755 index 0000000..35eb169 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/davincifb.h @@ -0,0 +1,581 @@ +/* + * Copyright (C) 2006 Texas Instruments Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * File: davincifb.h + */ + +#ifndef DAVINVI_VPBE_H +#define DAVINVI_VPBE_H + +/* include Linux files */ +#include + +/* define the custom FBIO_WAITFORVSYNC ioctl */ +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#define FBIO_SETATTRIBUTE _IOW('F', 0x21, struct fb_fillrect) + +/* Backported IOCTLS. */ +#define FBIO_SETPOSX _IOW('F', 0x22, u_int32_t) +#define FBIO_SETPOSY _IOW('F', 0x23, u_int32_t) +#define FBIO_SETZOOM _IOW('F', 0x24, struct zoom_params) +#define FBIO_GETSTD _IOR('F', 0x25, u_int32_t) +#define FBIO_RESIZER _IOW('F', 0x26, struct vpfe_resizer_params) +#define FBIO_SYNC _IOW('F', 0x27, u_int32_t) + +typedef struct zoom_params { + u_int32_t window_id; + u_int32_t zoom_h; + u_int32_t zoom_v; +} zoom_params_t; + +typedef struct vpfe_resizer_params +{ + u_int32_t rsz_cnt; //busy-lock + u_int32_t out_size; //busy-lock + u_int32_t in_start; //busy-lock + u_int32_t in_size; //busy-lock + u_int32_t sdr_inadd; //shadowed + u_int32_t sdr_inoff; //shadowed + u_int32_t sdr_outadd; //shadowed + u_int32_t sdr_outoff; //shadowed + u_int32_t hfilt[16]; //busy-lock + u_int32_t vfilt[16]; //busy-lock + u_int32_t yenh; //busy-lock +} vpfe_resizer_params_t; + +typedef struct fb_set_start { + int offset; /* offset from smem_start */ + unsigned long physical; /* absolute physical address when offset < 0 */ + + u_int64_t sync; /* input: target sync counter for change or 0 for no sync at all, + output: sync counter of actual change or 0 if still pending */ +} fb_set_start_t; + + +#ifdef _IOC_TYPECHECK +#undef _IOC_TYPECHECK +#define _IOC_TYPECHECK(x) (sizeof(x)) +#endif + +#define RAM_CLUT_SIZE 256*3 +#define FBIO_ENABLE_DISABLE_WIN \ + _IOW('F', 0x30, unsigned char) +#define FBIO_SET_BITMAP_BLEND_FACTOR \ + _IOW('F', 0x31, vpbe_bitmap_blend_params_t) +#define FBIO_SET_BITMAP_WIN_RAM_CLUT \ + _IOW('F', 0x32, unsigned char)*RAM_CLUT_SIZE) +#define FBIO_ENABLE_DISABLE_ATTRIBUTE_WIN \ + _IOW('F', 0x33, unsigned int) +#define FBIO_GET_BLINK_INTERVAL \ + _IOR('F', 0x34, vpbe_blink_option_t) +#define FBIO_SET_BLINK_INTERVAL \ + _IOW('F', 0x35, vpbe_blink_option_t) +#define FBIO_GET_VIDEO_CONFIG_PARAMS \ + _IOR('F', 0x36, vpbe_video_config_params_t) +#define FBIO_SET_VIDEO_CONFIG_PARAMS \ + _IOW('F', 0x37, vpbe_video_config_params_t) +#define FBIO_GET_BITMAP_CONFIG_PARAMS \ + _IOR('F', 0x38, vpbe_bitmap_config_params_t) +#define FBIO_SET_BITMAP_CONFIG_PARAMS \ + _IOW('F', 0x39, vpbe_bitmap_config_params_t) +#define FBIO_SET_DCLK \ + _IOW('F', 0x40, vpbe_dclk_t) +#define FBIO_SET_INTERFACE \ + _IOW('F', 0x41, unsigned char) +#define FBIO_GET_INTERFACE \ + _IOR('F', 0x42, unsigned char) +#define FBIO_QUERY_TIMING \ + _IOWR('F', 0x43, struct vpbe_mode_info) +#define FBIO_SET_TIMING \ + _IOW('F', 0x44, struct vpbe_fb_videomode) +#define FBIO_GET_TIMING \ + _IOR('F', 0x45, struct vpbe_fb_videomode) +#define FBIO_SET_VENC_CLK_SOURCE \ + _IOW('F', 0x46, unsigned char) +#define FBIO_SET_BACKG_COLOR \ + _IOW('F', 0x47, vpbe_backg_color_t) +#define FBIO_ENABLE_DISPLAY \ + _IOW('F', 0x48, unsigned char) +#define FBIO_SETPOS \ + _IOW('F', 0x49, u_int32_t) +#define FBIO_SET_CURSOR \ + _IOW('F', 0x50, struct fb_cursor) +#define FBIO_SET_START \ + _IOW('F', 0x66, struct fb_set_start) + +/* + * Defines and Constants + */ +#ifdef __KERNEL__ +#define DAVINCIFB_DEVICE "davincifb" +#define DAVINCIFB_DRIVER "davincifb" + +#define MULTIPLE_BUFFERING 1 + +#ifdef MULTIPLE_BUFFERING +#define DOUBLE_BUF 2 +#define TRIPLE_BUF 3 +#else +#define DOUBLE_BUF 1 +#define TRIPLE_BUF 1 +#endif + +/* usage: if (is_win(info->fix.id, OSD0)) ... */ +#define is_win(name, x) ((strcmp(name, x ## _FBNAME) == 0) ? 1 : 0) + +/* + * display controller register I/O routines + */ +u32 dispc_reg_in(u32 offset); +u32 dispc_reg_out(u32 offset, u32 val); +u32 dispc_reg_merge(u32 offset, u32 val, u32 mask); + +#endif /*__KERNEL__*/ + +/* Error return codes */ +#define VPBE_INVALID_PARA_VALUE 700 +#define VPBE_WRONG_WINDOW_ID 701 +#define VPBE_CURRENTLY_IN_REQUIRED_MODE 702 +#define VPBE_INSUFFICIENT_CLUT_VALUES 703 +#define VPBE_CLUT_WRITE_TIMEOUT 704 +#define VPBE_VID0_BUF_ADR_NULL 705 +#define VPBE_WINDOW_NOT_DISABLED 706 +#define VPBE_WINDOW_NOT_ENABLED 707 + +#ifndef __KERNEL__ +/* Window ID definations */ +#define OSD0 0 +#define VID0 1 +#define OSD1 2 +#define VID1 3 +#endif + +/* There are 4 framebuffers, each represented by an fb_info and + * a dm_win_info structure */ +#define OSD0_FBNAME "dm_osd0_fb" +#define OSD1_FBNAME "dm_osd1_fb" +#define VID0_FBNAME "dm_vid0_fb" +#define VID1_FBNAME "dm_vid1_fb" + +/* FIXME: Digital LCD RGB matrix coefficients */ +#define DLCD_DGY_VAL 0 +#define DLCD_DRV_VAL 0 +#define DLCD_DGU_VAL 0 +#define DLCD_DBU_VAL 0 + +/* Defines for bitmap format */ +#define VPBE_BITMAP_BIT_1 1 +#define VPBE_BITMAP_BIT_2 2 +#define VPBE_BITMAP_BIT_4 4 +#define VPBE_BITMAP_BIT_8 8 +#define VPBE_BITMAP_RGB565 16 +#define VPBE_VIDEO_YUV422 16 +#define VPBE_VIDEO_RGB888 24 + +/* Defines foe cursor parameter validation*/ +#define MAX_CURSOR_WIDTH 0x3FF +#define MAX_CURSOR_HEIGHT 0x1FF +#define MAX_CURSOR_LINEWIDTH 7 + +#define BASEX 0x80 +#define BASEY 0x12 +#define BASEX_DLCD 0x59 +#define BASEY_DLCD 0x22 + +/* + * Enumerations + */ +/* Enum for blending factor */ +typedef enum vpbe_blend_factor { + OSD_CONTRIBUTION_ZERO = 0, + OSD_CONTRIBUTION_1_BY_8 = 1, + OSD_CONTRIBUTION_2_BY_8 = 2, + OSD_CONTRIBUTION_3_BY_8 = 3, + OSD_CONTRIBUTION_4_BY_8 = 4, + OSD_CONTRIBUTION_5_BY_8 = 5, + OSD_CONTRIBUTION_6_BY_8 = 6, + OSD_CONTRIBUTION_ONE = 7 +} vpbe_blend_factor_t; + +/* Enum for Boolean variables */ +typedef enum { + SET_0 = 0, + SET_1 = 1 +} CB_CR_ORDER, ATTRIBUTE, ROM_RAM_CLUT; + +/* Defines for Display Interface */ +#define PRGB 0 +#define COMPOSITE 1 +#define SVIDEO 2 +#define COMPONENT 3 +#define RGB 4 +#define YCC16 5 +#define YCC8 6 +#define SRGB 7 +#define EPSON 8 +#define CASIO1G 9 +#define UDISP 10 +#define STN 11 +#define VPBE_MAX_INTERFACES 12 + +/* Defines for Display Mode */ +#define LCD 0 +#define NTSC 1 +#define PAL 2 +#define P525 3 +#define P625 4 + +#define DEFAULT_MODE 0 +#define P480 0 +#define P400 1 +#define P350 2 +#define NON_EXISTING_MODE 255 +/* Enable/Disable enum */ +typedef enum { + VPBE_DISABLE = 0, + VPBE_ENABLE = 1 +} ATTENUATION, TRANSPARENCY, EXPANSION, BLINKING; + +typedef enum clk_source { + CLK_SOURCE_CLK27 = 0, + CLK_SOURCE_CLK54 = 1, + CLK_SOURCE_VPBECLK = 2 +} CLK_SOURCE; + +/* + * Structures and Union Definitions + */ + +/* Structure for transparency and the blending factor for the bitmap window */ +typedef struct vpbe_bitmap_blend_params { + unsigned int colorkey; /* color key to be blend */ + unsigned int enable_colorkeying; /* enable color keying */ + unsigned int bf; /* valid range from 0 to 7 only. */ +} vpbe_bitmap_blend_params_t; + +/* Structure for window expansion */ +typedef struct vpbe_win_expansion { + EXPANSION horizontal; + EXPANSION vertical; /* 1: Enable 0:disable */ +} vpbe_win_expansion_t; + +/* Structure for OSD window blinking options */ +typedef struct vpbe_blink_option { + BLINKING blinking; /* 1: Enable blinking 0: Disable */ + unsigned int interval; /* Valid only if blinking is 1 */ +} vpbe_blink_option_t; + +/* Structure for DCLK parameters */ +typedef struct vpbe_dclk { + unsigned char dclk_pattern_width; + unsigned int dclk_pattern0; + unsigned int dclk_pattern1; + unsigned int dclk_pattern2; + unsigned int dclk_pattern3; +} vpbe_dclk_t; + +/* Structure for display format */ +typedef struct vpbe_display_format { + unsigned char interface; /* Output interface type */ + unsigned char mode; /* output mode */ +} vpbe_display_format_t; + +/* Structure for background color */ +typedef struct vpbe_backg_color { + unsigned char clut_select; /* 2: RAM CLUT 1:ROM1 CLUT 0:ROM0 CLUT */ + unsigned char color_offset; /* index of color */ +} vpbe_backg_color_t; + +/* Structure for Video window configurable parameters */ +typedef struct vpbe_video_config_params { + CB_CR_ORDER cb_cr_order; /*Cb/Cr order in input data for a pixel. */ + /* 0: cb cr 1: cr cb */ + vpbe_win_expansion_t exp_info; /* HZ/VT Expansion enable disable */ +} vpbe_video_config_params_t; + +/*Union of structures giving the CLUT index for the 1, 2, 4 bit bitmap values.*/ +typedef union vpbe_clut_idx { + struct _for_4bit_bimap { + unsigned char bitmap_val_0; + unsigned char bitmap_val_1; + unsigned char bitmap_val_2; + unsigned char bitmap_val_3; + unsigned char bitmap_val_4; + unsigned char bitmap_val_5; + unsigned char bitmap_val_6; + unsigned char bitmap_val_7; + unsigned char bitmap_val_8; + unsigned char bitmap_val_9; + unsigned char bitmap_val_10; + unsigned char bitmap_val_11; + unsigned char bitmap_val_12; + unsigned char bitmap_val_13; + unsigned char bitmap_val_14; + unsigned char bitmap_val_15; + } for_4bit_bimap; + struct _for_2bit_bimap { + unsigned char bitmap_val_0; + unsigned char dummy0[4]; + unsigned char bitmap_val_1; + unsigned char dummy1[4]; + unsigned char bitmap_val_2; + unsigned char dummy2[4]; + unsigned char bitmap_val_3; + } for_2bit_bimap; + struct _for_1bit_bimap { + unsigned char bitmap_val_0; + unsigned char dummy0[14]; + unsigned char bitmap_val_1; + } for_1bit_bimap; +} vpbe_clut_idx_t; + +/* Structure for bitmap window configurable parameters */ +typedef struct vpbe_bitmap_config_params { + /* Only for bitmap width = 1,2,4 bits */ + vpbe_clut_idx_t clut_idx; + /* Attenuation value for YUV o/p for bitmap window */ + unsigned char attenuation_enable; + /* 0: ROM DM270, 1:ROM DM320, 2:RAM CLUT */ + unsigned char clut_select; +} vpbe_bitmap_config_params_t; + +/* Unioun for video/OSD configuration parameters */ +typedef union vpbe_conf_params { + + struct vpbe_video_params { + CB_CR_ORDER cb_cr_order; + /* HZ/VT Expansion enable disable */ + vpbe_win_expansion_t exp_info; + } video_params; + + struct vpbe_bitmap_params { + /* Attenuation value for YUV o/p */ + ATTENUATION attenuation_enable; + /* 0: ROM DM270, 1: ROM DM320, 2:RAM CLUT */ + unsigned char clut_select; + /* Only for bitmap width = 1,2,4 bits */ + vpbe_clut_idx_t clut_idx; + /* 0: OSD window is bitmap window */ + /* 1: OSD window is attribute window */ + ATTRIBUTE enable_attribute; + /* To hold bps value. + Used to switch back from attribute to bitmap. */ + unsigned int stored_bits_per_pixel; + /* Blending information */ + vpbe_bitmap_blend_params_t blend_info; + /* OSD Blinking information */ + vpbe_blink_option_t blink_info; + } bitmap_params; + +} vpbe_conf_params_t; + +typedef struct vpbe_video_params vpbe_video_params_t; +typedef struct vpbe_bitmap_params vpbe_bitmap_params_t; + +/* Structure to hold window position */ +typedef struct vpbe_window_position { + unsigned int xpos; /* X position of the window */ + unsigned int ypos; /* Y position of the window */ +} vpbe_window_position_t; + +#ifdef __KERNEL__ +/* Structure for each window */ +typedef struct vpbe_dm_win_info { + struct fb_info info; + vpbe_window_position_t win_pos; /* X,Y position of window */ + /* Size of window is already there in var_info structure. */ + + dma_addr_t fb_base_phys; /*framebuffer area */ + unsigned int fb_base; /*window memory pointer */ + unsigned int fb_size; /*memory size */ + unsigned int pseudo_palette[17]; + int alloc_fb_mem; + /*flag to identify if framebuffer area is fixed or not */ + unsigned long sdram_address; + struct vpbe_dm_info *dm; + unsigned char window_enable; /*Additions for all windows */ + zoom_params_t zoom; /*Zooming parameters */ + unsigned char field_frame_select; /*To select Field or frame */ + unsigned char numbufs; /*Number of buffers valid 2 or 3 */ + vpbe_conf_params_t conf_params; + /*window configuration parameter union pointer */ +} vpbe_dm_win_info_t; +#endif /*__KERNEL__*/ + +/* + * Videmode structure for display interface and mode settings + */ +typedef struct vpbe_fb_videomode { + unsigned char name[10]; /* Mode name ( NTSC , PAL) */ + unsigned int vmode; /* FB_MODE_INTERLACED or FB_MODE_NON_INTERLACED */ + unsigned int xres; /* X Resolution of the display */ + unsigned int yres; /* Y Resolution of the display */ + unsigned int fps; /* frames per second */ + /* Timing Parameters applicable for std = 0 only */ + unsigned int left_margin; + unsigned int right_margin; + unsigned int upper_margin; + unsigned int lower_margin; + unsigned int hsync_len; + unsigned int vsync_len; + unsigned int sync; /* 0: hsync -ve/vsync -ve */ + /*1: hsync -ve/vsync +ve */ + /*2: hsync +ve/vsync -ve */ + /*3: hsync +ve/vsync +ve */ + unsigned int basepx; /* Display x,y start position */ + unsigned int basepy; +/* 1= Mode s available in modelist 0=Mode is not available in modelist */ + unsigned int std; +} vpbe_fb_videomode_t; + +/* Structure to interface videomode to application*/ +typedef struct vpbe_mode_info { + vpbe_fb_videomode_t vid_mode; + unsigned char interface; + unsigned char mode_idx; +} vpbe_mode_info_t; + +#ifdef __KERNEL__ +/* + * Structure for the driver holding information of windows, + * memory base addresses etc. + */ +typedef struct vpbe_dm_info { + vpbe_dm_win_info_t *osd0; + vpbe_dm_win_info_t *osd1; + vpbe_dm_win_info_t *vid0; + vpbe_dm_win_info_t *vid1; + +/* to map the registers */ + dma_addr_t mmio_base_phys; + unsigned int mmio_base; + unsigned int mmio_size; + + wait_queue_head_t vsync_wait; + unsigned int vsync_cnt; + int timeout; + + /* this is the function that configures the output device (NTSC/PAL/LCD) + * for the required output format (composite/s-video/component/rgb) + */ + void (*output_device_config) (void); + + struct device *dev; + + vpbe_backg_color_t backg; /* background color */ + vpbe_dclk_t dclk; /*DCLK parameters */ + vpbe_display_format_t display; /*Display interface and mode */ + vpbe_fb_videomode_t videomode; /*Cuurent videomode */ + char ram_clut[256][3]; /*RAM CLUT array */ + struct fb_cursor cursor; /* cursor config params from fb.h */ +/*Flag that indicates whether any of the display is enabled or not*/ + int display_enable; +} vpbe_dm_info_t; + +/* + * Functions Definitions for 'davincifb' module + */ +int vpbe_mem_alloc_window_buf(vpbe_dm_win_info_t *); +int vpbe_mem_release_window_buf(vpbe_dm_win_info_t *); +void init_display_function(vpbe_display_format_t *); +int vpbe_mem_alloc_struct(vpbe_dm_win_info_t **); +void set_vid0_default_conf(void); +void set_vid1_default_conf(void); +void set_osd0_default_conf(void); +void set_osd1_default_conf(void); +void set_cursor_default_conf(void); +void set_dm_default_conf(void); +void set_win_enable(char *, unsigned int); +int within_vid0_limits(u32, u32, u32, u32); +void vpbe_set_display_default(void); +#ifdef __KERNEL__ +void set_win_position(char *, u32, u32, u32, u32); +void change_win_param(int); +void set_interlaced(char *, unsigned int); +#endif /* __KERNEL__ */ + +/* + * Function definations for 'osd' module + */ + +int vpbe_enable_window(vpbe_dm_win_info_t *); +int vpbe_disable_window(vpbe_dm_win_info_t *); +int vpbe_vid_osd_select_field_frame(u8 *, u8); +int vpbe_bitmap_set_blend_factor(u8 *, vpbe_bitmap_blend_params_t *); +int vpbe_bitmap_set_ram_clut(void); +int vpbe_enable_disable_attribute_window(u32); +int vpbe_get_blinking(u8 *, vpbe_blink_option_t *); +int vpbe_set_blinking(u8 *, vpbe_blink_option_t *); +int vpbe_set_vid_params(u8 *, vpbe_video_config_params_t *); +int vpbe_get_vid_params(u8 *, vpbe_video_config_params_t *); +int vpbe_bitmap_get_params(u8 *, vpbe_bitmap_config_params_t *); +int vpbe_bitmap_set_params(u8 *, vpbe_bitmap_config_params_t *); +int vpbe_set_cursor_params(struct fb_cursor *); +int vpbe_set_vid_expansion(vpbe_win_expansion_t *); +int vpbe_set_dclk(vpbe_dclk_t *); +int vpbe_set_display_format(vpbe_display_format_t *); +int vpbe_set_backg_color(vpbe_backg_color_t *); +int vpbe_set_interface(u8); +int vpbe_query_mode(vpbe_mode_info_t *); +int vpbe_set_mode(struct vpbe_fb_videomode *); +int vpbe_set_venc_clk_source(u8); +void set_vid0_default_conf(void); +void set_osd0_default_conf(void); +void set_vid1_default_conf(void); +void set_osd1_default_conf(void); +void set_cursor_default_conf(void); +void set_dm_default_conf(void); +/* + * Function definations for 'venc' module + */ + +void davincifb_ntsc_composite_config(void); +void davincifb_ntsc_svideo_config(void); +void davincifb_ntsc_component_config(void); +void davincifb_pal_composite_config(void); +void davincifb_pal_svideo_config(void); +void davincifb_pal_component_config(void); + +void vpbe_davincifb_ntsc_rgb_config(void); +void vpbe_davincifb_pal_rgb_config(void); +void vpbe_davincifb_525p_component_config(void); +void vpbe_davincifb_625p_component_config(void); + +void vpbe_enable_venc(int); +void vpbe_enable_dacs(int); +/* + * Function definations for 'dlcd' module + */ +void vpbe_davincifb_480p_prgb_config(void); +void vpbe_davincifb_400p_prgb_config(void); +void vpbe_davincifb_350p_prgb_config(void); +void vpbe_set_display_timing(struct vpbe_fb_videomode *); + +void vpbe_enable_lcd(int); +/* + * Following functions are not implemented + */ +void vpbe_davincifb_default_ycc16_config(void); +void vpbe_davincifb_default_ycc8_config(void); +void vpbe_davincifb_default_srgb_config(void); +void vpbe_davincifb_default_epson_config(void); +void vpbe_davincifb_default_casio_config(void); +void vpbe_davincifb_default_UDISP_config(void); +void vpbe_davincifb_default_STN_config(void); +#endif /*__KERNEL__*/ + +#endif /* End of #ifndef DAVINCI_VPBE_H */ diff --git a/Source/DirectFB/gfxdrivers/davinci/directfbrc b/Source/DirectFB/gfxdrivers/davinci/directfbrc new file mode 100755 index 0000000..4025926 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/directfbrc @@ -0,0 +1,56 @@ +# +# WM/System +wm = sawman +system = devmem +video-phys = 87000000 +video-length = 16777216 + +# +# Use 640x480 by default (all visible) +mode = 640x480 + +# +# Shared Memory Mount Point +tmpfs = /tmp + +# +# Disable Cursor +no-cursor + +# +# Disable Layer Initialization +no-init-layer = 0 + +# +# Graphics Layer +#init-layer = 0 +#layer-size = 720x576 +#layer-format = RGB16 +#layer-stacking = middle,upper +#layer-bg-color = 000000 +#layer-src-key = 000000 +#layer-buffer-mode = backvideo + +# +# Video Layer +#init-layer = 1 +#layer-size = 720x576 +#layer-format = UYVY +#layer-stacking = lower +#layer-bg-color = 0000ff +#layer-buffer-mode = frontonly +#layer-bg-image = /usr/local/share/images/bg_flower.jpg + +# +# Scaling +smooth-upscale +smooth-downscale + +# +# Debug domains +#debug = Davinci/OSD +#debug = LiTE/Window +#debug = SaWMan/Auto +#debug = Core/GraphicsOps +#debug = Core/Layers +#debug = Core/Surface diff --git a/Source/DirectFB/gfxdrivers/davinci/kernel-module/Makefile b/Source/DirectFB/gfxdrivers/davinci/kernel-module/Makefile new file mode 100755 index 0000000..cb2965a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/kernel-module/Makefile @@ -0,0 +1,34 @@ +KERNEL_VERSION = $(shell uname -r) +KERNEL_MODLIB = /lib/modules/$(KERNEL_VERSION) +KERNEL_BUILD = $(KERNEL_MODLIB)/build +KERNEL_SOURCE = $(KERNEL_MODLIB)/source + +SUB=c64x + +export CONFIG_DAVINCI_C64X=m + +ifeq ($(shell test -e $(KERNEL_BUILD)/include/linux/autoconf.h && echo yes),yes) + AUTOCONF_H = -include $(KERNEL_BUILD)/include/linux/autoconf.h +endif + +ifeq ($(shell test -e $(KERNEL_BUILD)/include/linux/config.h && echo yes),yes) + CPPFLAGS += -DHAVE_LINUX_CONFIG_H +endif + +CPPFLAGS += -DMODULE + +.PHONY: all install clean + +it all: + $(MAKE) -C $(KERNEL_BUILD) \ + KCPPFLAGS="$(CPPFLAGS) -I$(shell pwd)/include -I$(KERNEL_BUILD)/include" \ + SUBDIRS=$(shell pwd)/$(SUB) ARCH=arm CROSS_COMPILE=arm-v4t-linux-gnueabi- modules + +install: all + +clean: + $(RM) -r $(SUB)/.tmp_versions $(SUB)/Module.symvers + find $(SUB) -name *.o -o -name *.ko -o -name .*.cmd -o -name *.mod.* | xargs rm -f + +so: it + find $(SUB) -name "*.ko" | xargs strip -x -R .comment -R .note diff --git a/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/Makefile b/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/Makefile new file mode 100755 index 0000000..8d211a5 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_DAVINCI_C64X) += c64x.o + diff --git a/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/c64x.c b/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/c64x.c new file mode 100755 index 0000000..bbbbfe9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/kernel-module/c64x/c64x.c @@ -0,0 +1,507 @@ +/* + TI Davinci driver - C64X+ DSP Kernel Module + + (c) Copyright 2007 Telio AG + + Written by Olaf Dreesen . + + All rights reserved. + + This module is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define C64X_IRQ + +MODULE_LICENSE("GPL v2"); +//MODULE_LICENSE("Propietary"); +MODULE_AUTHOR("Olaf Dreesen "); +MODULE_DESCRIPTION("A little c64+ handling module."); + +#define C_MOD_MAJOR 400 +#define C_MOD_NUM_DEV 1 +#define C_MOD_NAME "c64x" +#define F_NAME "c64x_drv.bin" + +#define CODE_BASE 0x00800000 + +/* DDR2: + * + * transfer buffer + */ +#define R_BASE DAVINCI_C64X_MEM +#define R_LEN 0x02000000 + +/* L2RAM: + * + * 0x00800000 - 0x0080FFFF C64x+ + * 0x11800000 - 0x1180FFFF ARM + */ +#define D_BASE 0x11800000 +#define D_LEN 0x00010000 + +/* L1DRAM: + * + * 0x00F04000 - 0x00F0FFFF C64x+ + * 0x11F04000 - 0x11F0FFFF ARM + * + * Queue controls @ 0x00F04000 (4096 Bytes) + */ +#define Q_BASE 0x11F04000 +#define Q_LEN 0x00001000 + +#define HQueueDSP (l1dram[0x00>>2]) +#define HQueueARM (l1dram[0x04>>2]) +#define LQueueDSP (l1dram[0x08>>2]) +#define LQueueARM (l1dram[0x0C>>2]) +#define DSPidle (l1dram[0x10>>2]) + +/* IO Register needed: + * + * 0x01C40008 DSPBOOTADDR DSP Boot Address + * 0x01C40010 INTGEN Interrupt Generator + * 0x01C40038 CHP_SHRTSW DSP Power + * 0x01C4169C MDCFG39 DSP Module config + * 0x01C41A9C MDCTL39 DSP Module control + */ +#define IO_BASE 0x01c40000 +#define IO_LEN 0x00010000 + +#define DSPBOOTADDR (mmr[0x0008>>2]) +#define INTGEN (mmr[0x0010>>2]) +#define CHP_SHRTSW (mmr[0x0038>>2]) +#define MDCFG39 (mmr[0x169C>>2]) +#define MDCTL39 (mmr[0x1A9C>>2]) + +MODULE_FIRMWARE(F_NAME); + +static dev_t dev_major; +static struct cdev*dev_cdev; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) +static struct class*dev_class; +#else +static struct class_simple*dev_class; +#endif + +static volatile unsigned int*mmr=0; +static unsigned char*l2ram=0; +static volatile unsigned int*l1dram=0; +static volatile void*dram=0; +static volatile c64xTaskControl*c64xctl=0; +static volatile c64xTask*queue_l=0; + +#ifdef C64X_IRQ +static int dev_irq=46; +static DECLARE_WAIT_QUEUE_HEAD( wait_irq ); + +/* IRQ */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21) +static irqreturn_t dev_irq_handler(int irq,void*dev_id) { +#else +static irqreturn_t dev_irq_handler(int irq,void*dev_id,struct pt_regs*regs) { +#endif + wake_up_all( &wait_irq ); + return IRQ_HANDLED; +} +#endif + +static u32 opencnt=0; + +/* char-dev */ +static int dev_open(struct inode*inode,struct file*filp) { + if (opencnt++==0) { + DSPidle=0; + MDCTL39=0x00000103; /* Go! Go, go Go! */ + while(DSPidle==0); + } + return 0; +} +static int dev_release(struct inode*inode,struct file*filp) { + if (--opencnt==0) { + MDCTL39=0x00000000; /* local reset */ + } + return 0; +} + +static ssize_t dev_write(struct file*filp,const char __user*buffer,size_t len,loff_t*off) { + long ret=0; + unsigned long offset=*off; + if (offset=D_LEN) { len=D_LEN-offset; } +// printk(KERN_INFO "c64x+ : read got offset %08lx %08lx\n",offset,(long)len); + ret=len; + *off+=len; + } + return ret; +} +static ssize_t dev_read(struct file*filp,char __user*buffer,size_t len,loff_t*off) { + long ret=0; + unsigned long offset=*off; + if (offset=D_LEN) { len=D_LEN-offset; } +// printk(KERN_INFO "c64x+ : read got offset %08lx %08lx\n",offset,(long)len); + ret=len; + ret-=copy_to_user(buffer,(l2ram+offset),len); + *off+=len; + } + return ret; +} + +static int dev_mmap(struct file * file, struct vm_area_struct * vma) { + size_t size=vma->vm_end-vma->vm_start; + if (vma->vm_pgoff) { + if (size!=R_LEN) return -EINVAL; +#if defined(pgprot_writecombine) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#else + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +#endif + if (remap_pfn_range(vma, + vma->vm_start, + R_BASE>>PAGE_SHIFT, + size, + vma->vm_page_prot)) + return -EAGAIN; + } + else { + if (size!=Q_LEN) return -EINVAL; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + if (remap_pfn_range(vma, + vma->vm_start, + Q_BASE>>PAGE_SHIFT, + size, + vma->vm_page_prot)) + return -EAGAIN; + } + return 0; +} + +static void +c64x_dump( const char *condition ) +{ + static const char *state_names[] = { "DONE", "ERROR", "TODO", "RUNNING" }; + + uint32_t ql_dsp = c64xctl->QL_dsp; + uint32_t ql_arm = c64xctl->QL_arm; + uint32_t tl_dsp = queue_l[ql_dsp & C64X_QUEUE_MASK].c64x_function; + uint32_t tl_arm = queue_l[ql_arm & C64X_QUEUE_MASK].c64x_function; + int dl; + + dl = ql_arm - ql_dsp; + if (dl < 0) + dl += C64X_QUEUE_LENGTH; + + printk( "C64X+ Queue: %s\n" + " [DSP %d / %d (%s), ARM %d / %d (%s)] <- %d pending\n", + condition, + ql_dsp, (tl_dsp >> 2) & 0x3fff, state_names[tl_dsp & 3], + ql_arm, (tl_arm >> 2) & 0x3fff, state_names[tl_arm & 3], + dl ); +} + +static int +c64x_wait_low( void ) +{ + int ret; + int num = 0; + /* Keep reference values for comparison. */ + u32 idle = c64xctl->idlecounter; + u32 dsp = c64xctl->QL_dsp; + + /* Wait for equal pointers... */ + while (dsp != c64xctl->QL_arm) { + /* ...each time for a 1/50 second... */ + ret = wait_event_interruptible_timeout( wait_irq, c64xctl->QL_dsp == c64xctl->QL_arm, HZ/50 ); + if (ret < 0) + return ret; + + /* ...if after that 1/50 second still the same command is running... */ + if (!ret && c64xctl->QL_dsp == dsp) { + /* ...and almost one second elapsed in total, or the DSP felt idle... */ + if (++num > 42 || c64xctl->idlecounter != idle) { + /* ...timeout! */ + printk( KERN_ERR "c64x+ : timeout waiting for idle queue\n" ); + c64x_dump( "TIMEOUT!!!" ); + return -ETIMEDOUT; + } + } + else { + /* Different command running, reset total elapsed time. */ + num = 0; + } + + /* Update reference values. */ + idle = c64xctl->idlecounter; + dsp = c64xctl->QL_dsp; + } + + return 0; +} + +static int dev_ioctl(struct inode *i, struct file *f, unsigned int cmd, unsigned long arg) { + switch (cmd) { + case C64X_IOCTL_RESET: + MDCTL39=0x00000000; /* local reset */ + mdelay(10); + DSPidle=0; + MDCTL39=0x00000103; + break; + case C64X_IOCTL_WAIT_LOW: + return c64x_wait_low(); + default: + printk(KERN_INFO "c64x+ : unknown ioctl : cmd=%08x\n",cmd); + return -EAGAIN; + break; + } + return 0; +} +static struct file_operations dev_file_ops={ + .owner = THIS_MODULE, + .open = dev_open, + .release = dev_release, + .read = dev_read, + .write = dev_write, + .mmap = dev_mmap, + .ioctl = dev_ioctl, +}; + +/* INIT */ +static __initdata struct device dev_device = { + .bus_id = "c64x0", +}; +static int __init dev_init(void) { + int ret=-EIO; + u8 *at; + const struct firmware*fw = NULL; + + printk(KERN_INFO "c64x+ : module load\n"); + + if ((dram=ioremap(R_BASE,R_LEN))==0) { + printk(KERN_ERR "c64x+ : module couldn't get memory\n"); + goto err0; + } + printk(KERN_INFO "c64x+ : module got memory @ %p\n",dram); + queue_l = dram + 0x01e00000; + + /* get the 'device' memory */ + if ((mmr=ioremap(IO_BASE,IO_LEN))==0) { + printk(KERN_ERR "c64x+ : module couldn't get IO-MMR\n"); + goto err0; + } + printk(KERN_INFO "c64x+ : DSP bootaddr: %08x\n",DSPBOOTADDR); + printk(KERN_INFO "c64x+ : got mmr %p %08x %08x\n",mmr,MDCTL39,MDCFG39); + + printk(KERN_INFO "c64x+ : switch state: %08x\n",CHP_SHRTSW); + + MDCTL39=0x00000000; /* local reset */ + mdelay(10); + DSPBOOTADDR=CODE_BASE; /* set DSP base address */ + +// printk(KERN_INFO "c64x+ : check0: %p %08x %08x\n",mmr,MDCTL39,MDCFG39); + + /* get the 'device' memory */ + if ((l1dram=ioremap(Q_BASE,Q_LEN))==0) { + printk(KERN_ERR "c64x+ : module couldn't get L1 dsp-memory\n"); + goto err1; + } + printk(KERN_INFO "c64x+ : module got L1D @ %p\n",l1dram); + c64xctl = (volatile void*)l1dram; + + if ((l2ram=ioremap(D_BASE,D_LEN))==0) { + printk(KERN_ERR "c64x+ : module couldn't get L2 dsp-memory\n"); + goto err2; + } + printk(KERN_INFO "c64x+ : module got L2 @ %p\n",l2ram); + + /* request firmware */ + device_initialize(&dev_device); + ret=device_add(&dev_device); + if (ret) { + printk(KERN_ERR "c64x+ : device_add failed\n"); + goto err3; + } + printk(KERN_INFO "c64x+ : module requesting firmware '%s'\n",F_NAME); + ret=request_firmware(&fw,F_NAME,&dev_device); + printk(KERN_INFO "c64x+ : module got fw %p\n",fw); + if (ret) { + printk(KERN_ERR "c64x+ : no firmware upload (timeout or file not found?)\n"); + device_del(&dev_device); + goto err3; + } + printk(KERN_INFO "c64x+ : firmware upload %p %zd\n",fw->data,fw->size); + if (fw->size>32767) { + printk(KERN_ERR "c64x+ : firmware too big! 32767 is maximum (for now)\n"); + release_firmware(fw); + device_del(&dev_device); + goto err3; + } + if (memcmp(fw->data+8,"C64x+DV",8)) { + printk(KERN_ERR "c64x+ : firmware signature missing\n"); + release_firmware(fw); + device_del(&dev_device); + goto err3; + } + at = fw->data + fw->size; + while ((ulong)--at > (ulong)fw->data) { + if (*at == '@') + break; + } + if (at == fw->data) { + printk(KERN_ERR "c64x+ : firmware tag missing\n"); + release_firmware(fw); + device_del(&dev_device); + goto err3; + } + printk(KERN_NOTICE "c64x+ : got firmware of length %d at %p with tag '%*s' of length %d at %p+1\n", + fw->size, fw->data, + (int)((ulong)(fw->data + fw->size) - (ulong)at - 1), at + 1, + (int)((ulong)(fw->data + fw->size) - (ulong)at - 1), at ); + /* move firmware into the hardware buffer here. */ + memcpy(l2ram,fw->data,fw->size); + release_firmware(fw); + device_del(&dev_device); + +#if 0 + /* release DSP */ + printk(KERN_INFO "c64x+ : check1: %p %08x %08x\n",mmr,MDCTL39,MDCFG39); + MDCTL39=0x00000103; /* Hopefully run... */ + printk(KERN_INFO "c64x+ : check2: %p %08x %08x\n",mmr,MDCTL39,MDCFG39); + printk(KERN_INFO "c64x+ : check3: %08x\n",DSPBOOTADDR); +#endif + + /* register char-dev */ + dev_major=MKDEV(C_MOD_MAJOR,0); + ret=register_chrdev_region(dev_major,C_MOD_NUM_DEV,C_MOD_NAME); + if (ret) { + printk(KERN_ERR "c64x+ : can't get chrdev %d\n",C_MOD_MAJOR); + goto err3; + } + + /* allocate cdev */ + dev_cdev=cdev_alloc(); + dev_cdev->ops=&dev_file_ops; + /* cdev_init(&dev_data.cdev,&dev_file_ops); */ + ret=cdev_add(dev_cdev,dev_major,1); + if (ret) { + printk(KERN_ERR "c64x+ : can't allocate cdev\n"); + goto err4; + } + +#ifdef C64X_IRQ + /* allocate interrupt slot */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21) + ret=request_irq(dev_irq,dev_irq_handler,IRQF_DISABLED,C_MOD_NAME,NULL); +#else + ret=request_irq(dev_irq,dev_irq_handler,SA_INTERRUPT ,C_MOD_NAME,NULL); +#endif + if (ret) { + printk(KERN_ERR "c64x+ : can't get IRQ %d\n",dev_irq); + goto err5; + } +#endif + + /* tell sysfs/udev */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) + dev_class=class_create(THIS_MODULE,C_MOD_NAME); +#else + dev_class=class_simple_create(THIS_MODULE,C_MOD_NAME); +#endif + if (IS_ERR(dev_class)) { + ret=PTR_ERR(dev_class); + printk(KERN_ERR "c64x+ : can't allocate class\n"); + goto err6; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) + class_device_create(dev_class,NULL,dev_major,NULL,C_MOD_NAME"%d",0); +#else + class_simple_device_add(dev_class,dev_major,NULL,C_MOD_NAME"%d",0); +#endif + + printk(KERN_INFO "c64x+ : module load finished\n"); + return 0; + /* error out */ +err6: +#ifdef C64X_IRQ + free_irq(dev_irq,0); +err5: +#endif + cdev_del(dev_cdev); +err4: + unregister_chrdev_region(dev_major,1); +err3: + iounmap(l2ram); +err2: + iounmap((void*)l1dram); +err1: + iounmap((void*)mmr); +err0: + if (dram) + iounmap((void*)dram); + return ret; +} +module_init(dev_init); + +/* EXIT */ +static void __exit dev_exit(void) { + /* Put the DSP into Reset */ + MDCTL39=0x00000000; + /* release the DSP memory */ + iounmap((void*)mmr); + iounmap((void*)l1dram); + iounmap(l2ram); + /* release all the other resources */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19) + class_device_destroy(dev_class,dev_major); + class_destroy(dev_class); +#else + class_simple_device_remove(dev_major); + class_simple_destroy(dev_class); +#endif +#ifdef C64X_IRQ + free_irq(dev_irq,0); +#endif + cdev_del(dev_cdev); + unregister_chrdev_region(dev_major,C_MOD_NUM_DEV); +} +module_exit(dev_exit); + diff --git a/Source/DirectFB/gfxdrivers/davinci/kernel-module/include/linux/c64x.h b/Source/DirectFB/gfxdrivers/davinci/kernel-module/include/linux/c64x.h new file mode 100755 index 0000000..6117404 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/kernel-module/include/linux/c64x.h @@ -0,0 +1,281 @@ +/* + TI Davinci driver - C64X+ DSP Firmware Interface + + (c) Copyright 2008 directfb.org + (c) Copyright 2007 Telio AG + + Written by Olaf Dreesen and + Denis Oliver Kropp . + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __C64X_H__ +#define __C64X_H__ + +#ifndef __KERNEL__ +#include +#endif + + +#ifndef DAVINCI_C64X_MEM +#define DAVINCI_C64X_MEM 0x8e000000 +#endif + + +typedef volatile struct { + uint32_t c64x_function; + uint32_t c64x_arg[7]; +} c64xTask; + + +#define c64x_return c64x_arg[0] +#define c64x_errno c64x_arg[1] + +#define c64x_flags c64x_function + +typedef enum { + C64X_STATE_DONE = 0, + C64X_STATE_ERROR = 1, + C64X_STATE_TODO = 2, + C64X_STATE_RUNNING = 3 +} C64XTaskState; + +typedef enum { + C64X_FLAG_RUN = 1, + C64X_FLAG_TODO = 2, + C64X_FLAG_INTERRUPT = 0x80000000 +} C64XTaskFlags; + +#define C64X_TASK_STATE(task) ((task)->c64x_flags & 3) + +typedef volatile struct { + uint32_t QH_dsp; + uint32_t QH_arm; + uint32_t QL_dsp; + uint32_t QL_arm; + uint32_t idlecounter; +} c64xTaskControl; + +#define C64X_QUEUE_LENGTH 0x4000 +#define C64X_QUEUE_MASK 0x3fff + + +typedef enum { + C64X_BLEND_SRC_INVSRC = 2, /* old school fader on all channels including alpha on itself */ + C64X_BLEND_ONE_INVSRC = 1, /* SrcOver using premultiplied alpha channel */ + C64X_BLEND_ONE_INVSRC_PREMULT_SRC = 0, /* SrcOver doing premultiplication of source S[rgb] with S[a] */ + C64X_BLEND_ONE_INVSRC_PREMULT_ALPHA = 3, /* SrcOver with Alpha using premultiplied alpha channel, + but doing premultiplication of S[rgb] with Alpha */ +} C64XBlendSubFunction; + +typedef enum { + C64X_FLUSH_WRITE_BACK, + C64X_FLUSH_WB_INVALIDATE, + C64X_FLUSH_INVALIDATE +} C64XFlushFunction; + +#define C64X_IOCTL_RESET _IO( 'c', 0 ) +#define C64X_IOCTL_WAIT_LOW _IO( 'c', 1 ) + + +/* function macro */ +#define _C64XFUNC(val) (((val)&0x3fff)<<2) + + +#define C64X_NOP _C64XFUNC(0) + +/* +void c64x_dither_argb(u32*dst_rgb, u8*dst_alpha, u32 dst_pitch, u32*src, u32 src_pitch, u32 width, u32 height); +*/ +#define C64X_DITHER_ARGB _C64XFUNC(1) + +/* +void c64x_fill_16(u16*dst, u32 pitch, u32 width, u32 height, u16 val); +void c64x_fill_32(u32*dst, u32 pitch, u32 width, u32 height, u32 val); +*/ +#define C64X_FILL_16 _C64XFUNC(2) +#define C64X_FILL_32 _C64XFUNC(3) + +/* +void c64x_copy_16(u16*dst, u32 dst_pitch, u16*src, u32 src_pitch, u32 width, u32 height); +void c64x_copy_32(u32*dst, u32 dst_pitch, u32*src, u32 src_pitch, u32 width, u32 height); +*/ +#define C64X_COPY_16 _C64XFUNC(4) +#define C64X_COPY_32 _C64XFUNC(5) + +/* +void c64x_blend_32(u32*dst, u32 dst_pitch, u32*src, u32 src_pitch, u32 width, u32 height, u8 alpha); +*/ +//#define C64X_BLEND_16 _C64XFUNC(6) +#define C64X_BLEND_32 _C64XFUNC(7) + +/* +void c64x_copy_keyed_16(u16*dst, u32 pitches, u16*src, u32 width, u32 height, u16 key, u16 mask); +void c64x_copy_keyed_32(u32*dst, u32 pitches, u32*src, u32 width, u32 height, u32 key, u32 mask); +*/ +#define C64X_COPY_KEYED_16 _C64XFUNC(8) +#define C64X_COPY_KEYED_32 _C64XFUNC(9) + +/* +void c64x_stretch_32(u32 *dst, u32 *src, u32 pitches, u32 dsize, u32 ssize, u32 clip2, u32 clip1); +*/ +#define C64X_STRETCH_32_up _C64XFUNC(10) +#define C64X_STRETCH_32_down _C64XFUNC(11) + + +/* +void c64x_wb_inv_range(u32 *start, u32 len, C64XFlushFunction func); +*/ +#define C64X_WB_INV_RANGE _C64XFUNC(14) + + +/* +void c64x_write_back_all(void); +*/ +#define C64X_WRITE_BACK_ALL _C64XFUNC(15) + + + +/* +void c64x_load_block(s32*blockwords, u32 num_words, u32 cbp); +*/ +#define C64X_LOAD_BLOCK _C64XFUNC(48) + +/* +void c64x_put_idct_uyvy_16x16(u16*dst, u32 pitch, u32 flags); +*/ +#define C64X_PUT_IDCT_UYVY_16x16 _C64XFUNC(49) + +/* +void c64x_put_mc_uyvy_16x16(u16*dst, u32 pitch, u32 flags); +*/ +#define C64X_PUT_MC_UYVY_16x16 _C64XFUNC(50) + +/* +void c64x_put_sum_uyvy_16x16(u16*dst, u32 pitch, u32 flags); +*/ +#define C64X_PUT_SUM_UYVY_16x16 _C64XFUNC(51) + +/* +void c64x_dva_begin_frame(u32 pitch, u16 *current, u16 *past, u16 *future, u32 flags); +*/ +#define C64X_DVA_BEGIN_FRAME _C64XFUNC(52) + +/* +void c64x_dva_motion(DVAMacroBlock *macroblock); +*/ +#define C64X_DVA_MOTION_BLOCK _C64XFUNC(53) + +/* +void c64x_dva_idct(u16* dst, u32 pitch, u16* src); +*/ +#define C64X_DVA_IDCT _C64XFUNC(59) + + + +/* + * INTERNAL - for testing + */ +#define C64X_FETCH_BUFFER_PITCH 32 +#define C64X_TEMP_BUFFER_PITCH 32 +#define C64X_MC_BUFFER_PITCH 16 +#define C64X_IDCT_BUFFER_PITCH 32 + +#define C64X_FETCH_BUFFER_Y(n) (0xf05840 + ((n) << 10)) +#define C64X_FETCH_BUFFER_U(n) (C64X_FETCH_BUFFER_Y(n) + 18*C64X_FETCH_BUFFER_PITCH) +#define C64X_FETCH_BUFFER_V(n) (C64X_FETCH_BUFFER_U(n) + 16) + +#define C64X_FETCH_BUFFER0_Y C64X_FETCH_BUFFER_Y(0) +#define C64X_FETCH_BUFFER0_U C64X_FETCH_BUFFER_U(0) +#define C64X_FETCH_BUFFER0_V C64X_FETCH_BUFFER_V(0) + +#define C64X_FETCH_BUFFER1_Y C64X_FETCH_BUFFER_Y(1) +#define C64X_FETCH_BUFFER1_U C64X_FETCH_BUFFER_U(1) +#define C64X_FETCH_BUFFER1_V C64X_FETCH_BUFFER_V(1) + +#define C64X_TEMP_BUFFER_Y 0xf06040 +#define C64X_TEMP_BUFFER_U (C64X_TEMP_BUFFER_Y + 16*C64X_TEMP_BUFFER_PITCH) +#define C64X_TEMP_BUFFER_V (C64X_TEMP_BUFFER_U + 8) + +#define C64X_MC_BUFFER_Y 0xf06440 +#define C64X_MC_BUFFER_U (C64X_MC_BUFFER_Y + 16*C64X_MC_BUFFER_PITCH) +#define C64X_MC_BUFFER_V (C64X_MC_BUFFER_U + 8) + +#define C64X_MC_BUFFER_Y_ (C64X_MC_BUFFER_Y + C64X_MC_BUFFER_PITCH) +#define C64X_MC_BUFFER_U_ (C64X_MC_BUFFER_U + C64X_MC_BUFFER_PITCH) +#define C64X_MC_BUFFER_V_ (C64X_MC_BUFFER_V + C64X_MC_BUFFER_PITCH) + +#define C64X_IDCT_BUFFER_Y 0xf06a40 +#define C64X_IDCT_BUFFER_U (C64X_IDCT_BUFFER_Y + 16*C64X_IDCT_BUFFER_PITCH) +#define C64X_IDCT_BUFFER_V (C64X_IDCT_BUFFER_U + 8) + + +/* OBSOLETE +void c64x_dezigzag(u16*dst, u16*src); +*/ +#define C64X_DEZIGZAG _C64XFUNC(16) + +/* OBSOLETE +void c64x_dealternate(u16*dst, u16*src); +*/ +#define C64X_DEALTERNATE _C64XFUNC(17) + +/* +void c64x_put_uyvy_16x16(u16*dst, u32 pitch, u8*src, u32 flags); +*/ +#define C64X_PUT_UYVY_16x16 _C64XFUNC(18) + +/* +void c64x_fetch_uyvy(u8 *dst, u8 *src, u32 spitch, u32 height); +*/ +#define C64X_FETCH_UYVY _C64XFUNC(19) + +/* +void mc_put_o_8 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_x_8 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_y_8 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_xy_8 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +*/ +#define C64X_MC_PUT_8(avgX,avgY) _C64XFUNC(32+(avgX)+(avgY)+(avgY)) + +/* +void mc_put_o_16 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_x_16 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_y_16 (u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +void mc_put_xy_16(u8*dst, u32 dstride, u8*ref_src, u8*ignored, u32 rstride, u32 height); +*/ +#define C64X_MC_PUT_16(avgX,avgY) _C64XFUNC(36+(avgX)+(avgY)+(avgY)) + +/* +void mc_avg_o_8 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_x_8 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_y_8 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_xy_8 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +*/ +#define C64X_MC_AVG_8(avgX,avgY) _C64XFUNC(40+(avgX)+(avgY)+(avgY)) + +/* +void mc_avg_o_16 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_x_16 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_y_16 (u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +void mc_avg_xy_16(u8*dst, u32 dstride, u8*ref_src, u8*ref_dst, u32 rstride, u32 height); +*/ +#define C64X_MC_AVG_16(avgX,avgY) _C64XFUNC(44+(avgX)+(avgY)+(avgY)) + + +#endif diff --git a/Source/DirectFB/gfxdrivers/davinci/patches/ti-davinci-2.6.10-mvl401-fbio_set_start.patch b/Source/DirectFB/gfxdrivers/davinci/patches/ti-davinci-2.6.10-mvl401-fbio_set_start.patch new file mode 100755 index 0000000..60c2730 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/davinci/patches/ti-davinci-2.6.10-mvl401-fbio_set_start.patch @@ -0,0 +1,123 @@ +Index: include/video/davincifb.h +=================================================================== +--- include/video/davincifb.h (revision 765) ++++ include/video/davincifb.h (working copy) +@@ -40,6 +40,21 @@ + u_int32_t zoom_v; + } zoom_params_t; + ++ ++typedef struct fb_set_start { ++ int offset; /* offset from smem_start */ ++ unsigned long physical; /* absolute physical address when offset < 0 */ ++ ++ u_int64_t sync; /* input: target sync counter for change or 0 for no sync at all, ++ output: sync counter of actual change or 0 if still pending */ ++} fb_set_start_t; ++ ++ ++#ifdef _IOC_TYPECHECK ++#undef _IOC_TYPECHECK ++#define _IOC_TYPECHECK(x) (sizeof(x)) ++#endif ++ + #define RAM_CLUT_SIZE 256*3 + #define FBIO_ENABLE_DISABLE_WIN \ + _IOW('F', 0x30, unsigned char) +@@ -83,6 +98,8 @@ + _IOW('F', 0x49, u_int32_t) + #define FBIO_SET_CURSOR \ + _IOW('F', 0x50, struct fb_cursor) ++#define FBIO_SET_START \ ++ _IOW('F', 0x66, struct fb_set_start) + + /* + * Defines and Constants +Index: drivers/video/davincifb.c +=================================================================== +--- drivers/video/davincifb.c (revision 765) ++++ drivers/video/davincifb.c (working copy) +@@ -1095,6 +1095,58 @@ + return 0; + } + ++static int ++davincifb_set_start( struct fb_set_start *set, struct fb_info *info ) ++{ ++ struct vpbe_dm_win_info *win = (struct vpbe_dm_win_info *) info->par; ++ unsigned long start = 0; ++ ++ /* Physical mode (absolute address)? */ ++ if (set->offset < 0) { ++ start = set->physical; ++ ++ /* FIXME: address checks */ ++ } ++ else { ++ /* Offset mode (from frame buffer device base). */ ++ if (set->offset + info->var.yres * info->fix.line_length >= win->fb_size) ++ return -EFAULT; ++ ++ start = win->fb_base_phys + set->offset; ++ } ++ ++ /* Set on explicit sync count? */ ++ if (set->sync > 1) { ++ if (set->sync <= dm->vsync_cnt) { ++ set_sdram_params( info->fix.id, start, info->fix.line_length ); ++ win->sdram_address = start; ++ ++ set->sync = dm->vsync_cnt; ++ } ++ else { ++ /* FIXME: No queue yet. */ ++ win->sdram_address = start; ++ ++ set->sync = 0; ++ } ++ } ++ /* Set on next sync? */ ++ else if (set->sync) { ++ win->sdram_address = start; ++ ++ set->sync = 0; ++ } ++ /* Set now! */ ++ else { ++ set_sdram_params( info->fix.id, start, info->fix.line_length ); ++ win->sdram_address = start; ++ ++ set->sync = dm->vsync_cnt; ++ } ++ ++ return 0; ++} ++ + /* + * davincifb_ioctl - handler for private ioctls. + */ +@@ -1105,6 +1157,7 @@ + struct vpbe_dm_win_info *w = (struct vpbe_dm_win_info *)info->par; + void __user *argp = (void __user *)arg; + struct fb_fillrect rect; ++ struct fb_set_start set_start; + zoom_params_t zoom; + int retval = 0; + long std = 0; +@@ -1414,6 +1467,16 @@ + return -EINVAL; + break; + ++ case FBIO_SET_START: ++ if (copy_from_user(&set_start, argp, sizeof(set_start))) ++ return -EFAULT; ++ retval = davincifb_set_start( &set_start, &w->info ); ++ if (retval) ++ return retval; ++ if (copy_to_user(argp, &set_start, sizeof(set_start))) ++ return -EFAULT; ++ break; ++ + default: + retval = -EINVAL; + break; diff --git a/Source/DirectFB/gfxdrivers/ep9x/Makefile.am b/Source/DirectFB/gfxdrivers/ep9x/Makefile.am new file mode 100755 index 0000000..afbdfb1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ep9x/Makefile.am @@ -0,0 +1,33 @@ +## Makefile.am for DirectFB/src/core/gfxcards/ep9x + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +ep9xdir = $(MODULEDIR)/gfxdrivers +ep9x_LTLIBRARIES = libdirectfb_ep9x.la + +if BUILD_STATIC +ep9x_DATA = $(e9x_LTLIBRARIES:.la=.o) +endif + +libdirectfb_ep9x_la_SOURCES = \ + ep9x.c \ + ep9x.h + +libdirectfb_ep9x_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_ep9x_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/ep9x/Makefile.in b/Source/DirectFB/gfxdrivers/ep9x/Makefile.in new file mode 100755 index 0000000..9ea0945 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ep9x/Makefile.in @@ -0,0 +1,595 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/ep9x +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(ep9xdir)" "$(DESTDIR)$(ep9xdir)" +ep9xLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(ep9x_LTLIBRARIES) +libdirectfb_ep9x_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_ep9x_la_OBJECTS = ep9x.lo +libdirectfb_ep9x_la_OBJECTS = $(am_libdirectfb_ep9x_la_OBJECTS) +libdirectfb_ep9x_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_ep9x_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_ep9x_la_SOURCES) +DIST_SOURCES = $(libdirectfb_ep9x_la_SOURCES) +ep9xDATA_INSTALL = $(INSTALL_DATA) +DATA = $(ep9x_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +ep9xdir = $(MODULEDIR)/gfxdrivers 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install-ep9xLTLIBRARIES install-exec install-exec-am \ + install-html install-html-am install-info install-info-am \ + install-man install-pdf install-pdf-am install-ps \ + install-ps-am install-strip installcheck installcheck-am \ + installdirs maintainer-clean maintainer-clean-generic \ + mostlyclean mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ + uninstall-am uninstall-ep9xDATA uninstall-ep9xLTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/ep9x/ep9x.c b/Source/DirectFB/gfxdrivers/ep9x/ep9x.c new file mode 100755 index 0000000..3fcfade --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ep9x/ep9x.c @@ -0,0 +1,474 @@ +/* + (c) Copyright 2001-2007 The DirectFB Organization (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( ep9x ) + +#include "ep9x.h" + + +D_DEBUG_DOMAIN( ep9x, "ep9x", "Cirrus Logic EP9xx" ); + + +#define EP9X_SUPPORTED_DRAWINGFLAGS (DSDRAW_NOFX) + + +#define EP9X_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE | DFXL_DRAWLINE) + +#define EP9X_SUPPORTED_BLITTINGFLAGS (DSBLIT_NOFX) + +#define EP9X_SUPPORTED_BLITTINGFUNCTIONS (DFXL_NONE) + + +static inline void +ep9x_set_destination( EP9XDriverData *ep9xdrv, + EP9XDeviceData *ep9xdev, + CardState *state ) +{ + CoreSurfaceBuffer *buffer = state->dst.buffer; + + if (ep9xdev->smf_destination) + return; + + ep9xdev->destaddr = state->dst.offset; + + ep9xdev->destpitch = state->dst.pitch; + + switch (buffer->format) { + case DSPF_RGB16: + ep9xdev->pixeldepth = 2; + ep9xdev->pixelformat = DSPF_RGB16; + break; + case DSPF_RGB24: + ep9xdev->pixeldepth = 3; + ep9xdev->pixelformat = DSPF_RGB24; + break; + case DSPF_RGB32: + ep9xdev->pixeldepth = 3; + ep9xdev->pixelformat = DSPF_RGB32; + break; + default: + D_BUG("unexpected pixelformat~"); + } + + ep9xdev->smf_destination = 1; +} + +static inline void +ep9x_set_src(EP9XDriverData *ep9xdrv, + EP9XDeviceData *ep9xdev, + CardState *state) +{ + + if (ep9xdev->smf_source) + return; + + if ( state->src.phys ) { + D_DEBUG_AT(ep9x,"%s:video data is stored in fb and offset is %lx\n",__FUNCTION__,state->src.offset); + ep9xdev->srcaddr = state->src.offset; + ep9xdev->fb_store = true; + } + else if ( state->src.addr ) { + D_DEBUG_AT( ep9x,"%s:video data is stored in system\n",__FUNCTION__); + ep9xdev->srcaddr = (unsigned long) state->src.addr; + ep9xdev->fb_store = false; + } + else + D_ERROR("NOT vaild addr\n"); + + ep9xdev->srcpitch = state->src.pitch; + + ep9xdev->smf_source = 1; + +} + +static inline void ep9x_set_color( EP9XDriverData *ep9xdrv, + EP9XDeviceData *ep9xdev, + CardState *state ) +{ + CoreSurfaceBuffer *buffer = state->dst.buffer; + + if (ep9xdev->smf_color) + return; + + switch (buffer->format) { + case DSPF_RGB16: + ep9xdev->fill_color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB24: + case DSPF_RGB32: + ep9xdev->fill_color = PIXEL_RGB32( state->color.r, + state->color.g, + state->color.b ); + break; + + default: + D_ERROR( "unexpected pixelformat!" ); + } + + ep9xdev->smf_color = 1; + +} + +static inline void ep9x_set_clip( EP9XDriverData *ep9xdrv, + EP9XDeviceData *ep9xdev, + DFBRegion *clip ) +{ + if (ep9xdev->smf_clip) + return; + + ep9xdev->clip.x1 = clip->x1; + ep9xdev->clip.y1 = clip->y1; + ep9xdev->clip.x2 = clip->x2 + 1; + ep9xdev->clip.y2 = clip->y2 + 1; + + ep9xdev->smf_clip = 1; +} + + +static void +ep9xCheckState(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + break; + default: + return; + } + + if (!(accel & ~EP9X_SUPPORTED_DRAWINGFUNCTIONS) && + !(state->drawingflags & ~EP9X_SUPPORTED_DRAWINGFLAGS)) + state->accel |= EP9X_SUPPORTED_DRAWINGFUNCTIONS; + + + if (!(accel & ~EP9X_SUPPORTED_BLITTINGFUNCTIONS) && + !(state->blittingflags & ~EP9X_SUPPORTED_BLITTINGFLAGS)) { + if (state->source->config.format == state->destination->config.format) + state->accel |= EP9X_SUPPORTED_BLITTINGFUNCTIONS; + } + +} + +static void +ep9xSetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + EP9XDriverData *ep9xdrv = (EP9XDriverData *) drv; + EP9XDeviceData *ep9xdev = (EP9XDeviceData *) dev; + + if (state->modified & SMF_SOURCE && state->source ) + ep9xdev->smf_source = 0; + + if (state->modified & SMF_DESTINATION) + ep9xdev->smf_destination = ep9xdev->smf_color = 0; + + if (state->modified & SMF_COLOR) + ep9xdev->smf_color = 0; + + if (state->modified & SMF_CLIP) + ep9xdev->smf_clip = 0; + + ep9x_set_destination( ep9xdrv, ep9xdev, state); + + switch (accel) { + case DFXL_FILLRECTANGLE: + ep9x_set_color( ep9xdrv, ep9xdev, state ); + state->set |= DFXL_FILLRECTANGLE; + break; + case DFXL_DRAWLINE: + ep9x_set_color( ep9xdrv, ep9xdev, state ); + state->set |= DFXL_DRAWLINE ; + break; + + case DFXL_BLIT: + ep9x_set_src( ep9xdrv, ep9xdev, state ); + state->set |= DFXL_BLIT; + break; + default: + D_ERROR( "unexpected drawing/blitting function" ); + break; + + } + + if (state->modified & SMF_CLIP) + ep9x_set_clip( ep9xdrv, ep9xdev, &state->clip); + + state->modified = 0; + +} + +static void +ep9xFlushTextureCache(void *drv, void *dev) +{ + EP9XDeviceData *ep9xdev = (EP9XDeviceData *) dev; + + ep9xdev->srcaddr = ep9xdev->destaddr = 0; + ep9xdev->srcpitch = ep9xdev->destpitch = 0; + ep9xdev->fb_store = false; + +} + +static DFBResult +ep9xEngineSync(void *drv, void *dev) +{ + + return DFB_OK; +} + +static void +ep9xEngineReset(void *drv, void *dev) +{ + memset((void*)dfb_system_video_memory_virtual(0),0,dfb_gfxcard_memory_length()); +} + + +static bool ep9xFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + EP9XDriverData *ep9xdrv = (EP9XDriverData *) drv; + EP9XDeviceData *ep9xdev = (EP9XDeviceData *) dev; + struct ep9x_fill fill; + D_DEBUG_AT(ep9x,"%s:enter\n",__FUNCTION__); + + fill.dx = rect->x; + fill.dy = rect->y; + fill.width = rect->w; + fill.height = rect->h; + fill.color = ep9xdev->fill_color; + ioctl(ep9xdrv->dfb_fbdev->fd,FBIO_EP9X_FILL, &fill); + D_DEBUG_AT(ep9x,"%s:exit\n",__FUNCTION__); + return true; +} + +static bool ep9xDrawLine( void *drv, void *dev, DFBRegion *line ) +{ + EP9XDriverData *ep9xdrv = (EP9XDriverData *) drv; + EP9XDeviceData *ep9xdev = (EP9XDeviceData *) dev; + + struct ep9x_line drawline; + D_DEBUG_AT(ep9x,"%s:enter\n",__FUNCTION__); + drawline.flags = 0; + drawline.x1 = line->x1; + drawline.x2 = line->x2; + drawline.y1 = line->y1; + drawline.y2 = line->y2; + drawline.fgcolor = ep9xdev->fill_color; + drawline.bgcolor = 0; + drawline.pattern = 0; + + ioctl(ep9xdrv->dfb_fbdev->fd,FBIO_EP9X_LINE, &drawline); + D_DEBUG_AT(ep9x,"%s:exit\n",__FUNCTION__); + return true; +} + + +static bool +ep9xBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + + EP9XDriverData *ep9xdrv = (EP9XDriverData *) drv; + EP9XDeviceData *ep9xdev = (EP9XDeviceData *) dev; + struct fb_image image; + + D_DEBUG_AT(ep9x,"%s:enter\n",__FUNCTION__); + + if (!(ep9xdev->clip.x1 <= dx) || !(ep9xdev->clip.y1 <= dy) || + !( ep9xdev->clip.x2 >= (dx + rect->w - 1) ) || !( ep9xdev->clip.y2 >= (dy + rect->h - 1) )) { + D_ERROR("the blit region is not vaild\n"); + return false; + } + + image.dx = ep9xdev->destaddr + dx; + image.dy = dy; + image.width = rect->w; + image.height = rect->h; + image.depth = ep9xdev->pixeldepth; + if ( ep9xdev->fb_store == true ) + image.data = (void*)ep9xdev->fb_addr + ep9xdev->srcaddr + DFB_BYTES_PER_LINE( ep9xdev->pixelformat,rect->x ) + (rect->y * ep9xdev->srcpitch ); + else + image.data = (void*)ep9xdev->srcaddr + DFB_BYTES_PER_LINE( ep9xdev->pixelformat, rect->x ) + (rect->y * ep9xdev->srcpitch ); + + ioctl(ep9xdrv->dfb_fbdev->fd,FBIO_EP9X_BLIT,&image); + + D_DEBUG_AT(ep9x,"%s:exit\n",__FUNCTION__); + + return true; +} + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_EP9X: /* cirrus ep93xx serials */ + return 1; + } + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "ep9x 07/07A/12/15/15A Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "cirruslogic" ); + + snprintf( info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://arm.cirrus.com" ); + + snprintf( info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL" ); + + info->version.major = 0; + info->version.minor = 1; + + info->driver_data_size = sizeof (EP9XDriverData); + info->device_data_size = sizeof (EP9XDeviceData); + + +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + + EP9XDriverData *ep9xdrv = (EP9XDriverData*) driver_data; + EP9XDeviceData *ep9xdev = (EP9XDeviceData*) device_data; + + ep9xdrv->dfb_fbdev = dfb_system_data(); + + ioctl(ep9xdrv->dfb_fbdev->fd,FBIO_EP9X_GET_ADDR,&(ep9xdev->fb_addr)); + + funcs->CheckState = ep9xCheckState; + funcs->SetState = ep9xSetState; + funcs->EngineSync = ep9xEngineSync; + funcs->EngineReset = ep9xEngineReset; + funcs->FlushTextureCache = ep9xFlushTextureCache; + + funcs->FillRectangle = ep9xFillRectangle; + funcs->DrawLine = ep9xDrawLine; + funcs->Blit = ep9xBlit; + + return DFB_OK; +} + + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + + EP9XDeviceData *ep9xdev = (EP9XDeviceData*) device_data; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "ep9x" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "cirruslogic" ); + + device_info->caps.flags = 0; + device_info->caps.accel = EP9X_SUPPORTED_DRAWINGFUNCTIONS | + EP9X_SUPPORTED_BLITTINGFUNCTIONS; + + device_info->caps.drawing = EP9X_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = EP9X_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + ep9xdev->fb_store = false; + + + return DFB_OK; + +} + + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + + EP9XDriverData *ep9xdrv = (EP9XDriverData*) driver_data; + + ep9xdrv->dfb_fbdev = NULL; +} diff --git a/Source/DirectFB/gfxdrivers/ep9x/ep9x.h b/Source/DirectFB/gfxdrivers/ep9x/ep9x.h new file mode 100755 index 0000000..0857240 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/ep9x/ep9x.h @@ -0,0 +1,87 @@ +/* + (c) Copyright 2001-2007 The DirectFB Organization (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by BoLiu + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ +#ifndef __EP9X_H__ +#define __EP9X_H__ +#include +#include +#include + +/* + * The following are the IOCTLs that can be sent to the EP93xx frame buffer + * device. + */ +#define FBIO_EP9X_GET_CAPS 0x000046c0 +#define FBIO_EP9X_CURSOR 0x000046c1 +#define FBIO_EP9X_LINE 0x000046c2 +#define FBIO_EP9X_FILL 0x000046c3 +#define FBIO_EP9X_BLIT 0x000046c4 +#define FBIO_EP9X_COPY 0x000046c5 +#define FBIO_EP9X_GET_ADDR 0x000046c6 + +struct ep9x_line { + __u32 flags; + __s32 x1; + __s32 y1; + __s32 x2; + __s32 y2; + __u32 fgcolor; + __u32 bgcolor; // Only used if LINE_BACKGROUND is set + __u32 pattern; // Only used if LINE_PATTERN is set +}; + +/* + * ioctl(fd, FBIO_EP93XX_FILL, ep93xx_fill *) + * + * Fills from dx to (dx + width - 1), and from dy to (dy + height - 1). + */ +struct ep9x_fill { + __u32 dx; + __u32 dy; + __u32 width; + __u32 height; + __u32 color; +}; + + +typedef struct { + FBDev *dfb_fbdev; +} EP9XDriverData; + +typedef struct { + unsigned long fb_addr; + u32 fill_color; + u32 pixelformat; + u8 pixeldepth; + bool fb_store; + unsigned long srcaddr,destaddr,srcpitch,destpitch; + DFBRegion clip; + /* state validation */ + int smf_source; + int smf_destination; + int smf_color; + int smf_clip; +} EP9XDeviceData; + + +#endif /*__EDB93XX_H__*/ diff --git a/Source/DirectFB/gfxdrivers/gl/Makefile.am b/Source/DirectFB/gfxdrivers/gl/Makefile.am new file mode 100755 index 0000000..ef5deb2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/Makefile.am @@ -0,0 +1,36 @@ +## Makefile.am for DirectFB/src/core/gfxcards/gl + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +gl_LTLIBRARIES = libdirectfb_gl.la + +if BUILD_STATIC +gl_DATA = $(gl_LTLIBRARIES:.la=.o) +endif + +gldir = $(MODULEDIR)/gfxdrivers + +libdirectfb_gl_la_SOURCES = \ + gl_2d.c \ + gl_2d.h \ + gl_gfxdriver.c \ + gl_gfxdriver.h + +libdirectfb_gl_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) -lGL -lX11 + +libdirectfb_gl_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/gl/Makefile.in b/Source/DirectFB/gfxdrivers/gl/Makefile.in new file mode 100755 index 0000000..776f157 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/Makefile.in @@ -0,0 +1,598 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/gl +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(gldir)" "$(DESTDIR)$(gldir)" +glLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(gl_LTLIBRARIES) +libdirectfb_gl_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_gl_la_OBJECTS = gl_2d.lo gl_gfxdriver.lo +libdirectfb_gl_la_OBJECTS = $(am_libdirectfb_gl_la_OBJECTS) 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100755 index 0000000..a56f845 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/gl_2d.c @@ -0,0 +1,928 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "gl_2d.h" +#include "gl_gfxdriver.h" + + +D_DEBUG_DOMAIN( GL__2D, "GL/2D", "OpenGL 2D Acceleration" ); + +/* + * State validation flags. + * + * There's no prefix because of the macros below. + */ +enum { + DESTINATION = 0x00000001, + SCISSOR = 0x00000002, + MATRIX = 0x00000004, + RENDER_OPTS = 0x00000008, + + COLOR_DRAW = 0x00000010, + + SOURCE = 0x00000100, + COLOR_BLIT = 0x00000200, + + BLENDFUNC = 0x00010000, + + ALL = 0x0001031F +}; + +/* + * State handling macros. + */ + +#define GL_VALIDATE(flags) do { gdev->v_flags |= (flags); } while (0) +#define GL_INVALIDATE(flags) do { gdev->v_flags &= ~(flags); } while (0) + +#define GL_CHECK_VALIDATE(flag) do { \ + if ((gdev->v_flags & flag) != flag) \ + gl_validate_##flag( gdrv, gdev, state ); \ + } while (0) + + +/**********************************************************************************************************************/ + +/* + * Called by glSetState() to ensure that the destination parameters are properly set + * for execution of rendering functions. + */ +static inline void +gl_validate_DESTINATION( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + GLBufferData *buffer = state->dst.handle; + + D_DEBUG_AT( GL__2D, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( buffer, GLBufferData ); + + if (buffer->flags & GLBF_UPDATE_TARGET) { + glViewport( 0, 0, surface->config.size.w, surface->config.size.h ); + + glMatrixMode( GL_PROJECTION ); + glLoadIdentity(); + glOrtho( 0, surface->config.size.w, 0, surface->config.size.h, -1, 1 ); + + glMatrixMode( GL_MODELVIEW ); + glLoadIdentity(); + glScalef( 1, -1, 1 ); + glTranslatef( 0, - surface->config.size.h, 0 ); + + glShadeModel( GL_FLAT ); + glDisable( GL_LIGHTING ); + + glDepthMask( GL_FALSE ); + glDisable( GL_DEPTH_TEST ); + + glHint( GL_PERSPECTIVE_CORRECTION_HINT, GL_FASTEST ); + glDisable( GL_CULL_FACE ); + + glEnable( GL_SCISSOR_TEST ); + + GL_INVALIDATE( ALL ); + + buffer->flags &= ~GLBF_UPDATE_TARGET; + } + + /* Set the flag. */ + GL_VALIDATE( DESTINATION ); +} + +/* + * Called by glSetState() to ensure that the clip is properly set + * for execution of rendering functions. + */ +static inline void +gl_validate_SCISSOR( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + glScissor( state->clip.x1, + surface->config.size.h - state->clip.y2 - 1, + state->clip.x2 - state->clip.x1 + 1, + state->clip.y2 - state->clip.y1 + 1 ); + + /* Set the flag. */ + GL_VALIDATE( SCISSOR ); +} + +/* + * Called by glSetState() to ensure that the matrix is properly set + * for execution of rendering functions. + */ +static inline void +gl_validate_MATRIX( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + glMatrixMode( GL_MODELVIEW ); + glLoadIdentity(); + glScalef( 1, -1, 1 ); + glTranslatef( 0, - surface->config.size.h, 0 ); + + if (state->render_options & DSRO_MATRIX) { + float m[16] = { 0 }; + +#define M(n) (state->matrix[n] / 65536.0f) + + m[0] = M(0); m[4] = M(1); m[ 8] = 0.0f; m[12] = M(2); + m[1] = M(3); m[5] = M(4); m[ 9] = 0.0f; m[13] = M(5); + m[2] = 0.0f; m[6] = 0.0f; m[10] = 1.0f; m[14] = 0.0f; + m[3] = M(6); m[7] = M(7); m[11] = 0.0f; m[15] = M(8); + +#undef M + + D_DEBUG_AT( GL__2D, " -> %7.2f %7.2f %7.2f %7.2f\n", m[0], m[4], m[8], m[12] ); + D_DEBUG_AT( GL__2D, " -> %7.2f %7.2f %7.2f %7.2f\n", m[1], m[5], m[9], m[13] ); + D_DEBUG_AT( GL__2D, " -> %7.2f %7.2f %7.2f %7.2f\n", m[2], m[6], m[10], m[14] ); + D_DEBUG_AT( GL__2D, " -> %7.2f %7.2f %7.2f %7.2f\n", m[3], m[7], m[11], m[15] ); + + glMultMatrixf( m ); + } + + /* Set the flag. */ + GL_VALIDATE( MATRIX ); +} + +/* + * Called by glSetState() to ensure that the rendering options are properly set + * for execution of rendering functions. + */ +static inline void +gl_validate_RENDER_OPTS( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + if (state->render_options & DSRO_ANTIALIAS) { + glEnable( GL_LINE_SMOOTH ); + //glEnable( GL_POLYGON_SMOOTH ); + } + else { + glDisable( GL_LINE_SMOOTH ); + //glDisable( GL_POLYGON_SMOOTH ); + } + + /* Set the flag. */ + GL_VALIDATE( RENDER_OPTS ); +} + +/* + * Called by glSetState() to ensure that the color is properly set + * for execution of drawing functions. + */ +static inline void +gl_validate_COLOR_DRAW( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + int A = state->color.a + 1; + + glColor4ub( (state->color.r * A) >> 8, + (state->color.g * A) >> 8, + (state->color.b * A) >> 8, state->color.a ); + } + else + glColor4ub( state->color.r, state->color.g, state->color.b, state->color.a ); + + /* Set the flag. */ + GL_VALIDATE( COLOR_DRAW ); + + /* Invalidates blitting color. */ + GL_INVALIDATE( COLOR_BLIT ); +} + +/* + * Called by glSetState() to ensure that the source parameters are properly set + * for execution of blitting functions. + */ +static inline void +gl_validate_SOURCE( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + GLBufferData *buffer = state->src.handle; + + D_DEBUG_AT( GL__2D, "%s( %p )\n", __FUNCTION__, buffer ); + + D_MAGIC_ASSERT( buffer, GLBufferData ); + + glBindTexture( GL_TEXTURE_RECTANGLE_ARB, buffer->texture ); + + if (buffer->flags & GLBF_UPDATE_TEXTURE) { + glTexParameterf( GL_TEXTURE_RECTANGLE_ARB, GL_TEXTURE_MIN_FILTER, GL_LINEAR ); + glTexParameterf( GL_TEXTURE_RECTANGLE_ARB, GL_TEXTURE_MAG_FILTER, GL_LINEAR ); + + glTexParameterf( GL_TEXTURE_RECTANGLE_ARB, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE ); + glTexParameterf( GL_TEXTURE_RECTANGLE_ARB, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE ); + + buffer->flags &= ~GLBF_UPDATE_TEXTURE; + } + + /* Set the flag. */ + GL_VALIDATE( SOURCE ); +} + +/* + * Called by glSetState() to ensure that the color is properly set + * for execution of blitting functions. + */ +static inline void +gl_validate_COLOR_BLIT( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + int r, g, b, a; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + if (state->blittingflags & DSBLIT_COLORIZE) { + r = state->color.r; + g = state->color.g; + b = state->color.b; + } + else + r = g = b = 0xff; + + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + a = state->color.a; + else + a = 0xff; + + if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + int A = state->color.a + 1; + + r = (r * A) >> 8; + g = (g * A) >> 8; + b = (b * A) >> 8; + } + + glColor4ub( r, g, b, a ); + + /* Set the flag. */ + GL_VALIDATE( COLOR_BLIT ); + + /* Invalidates drawing color. */ + GL_INVALIDATE( COLOR_DRAW ); +} + +/* + * Called by glSetState() to ensure that the blend functions are properly set + * for execution of drawing and blitting functions. + */ +static inline void +gl_validate_BLENDFUNC( GLDriverData *gdrv, + GLDeviceData *gdev, + CardState *state ) +{ + GLenum src = GL_ZERO, dst = GL_ZERO; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + switch (state->src_blend) { + case DSBF_ZERO: + break; + + case DSBF_ONE: + src = GL_ONE; + break; + + case DSBF_SRCCOLOR: + src = GL_SRC_COLOR; + break; + + case DSBF_INVSRCCOLOR: + src = GL_ONE_MINUS_SRC_COLOR; + break; + + case DSBF_SRCALPHA: + src = GL_SRC_ALPHA; + break; + + case DSBF_INVSRCALPHA: + src = GL_ONE_MINUS_SRC_ALPHA; + break; + + case DSBF_DESTALPHA: + src = GL_DST_ALPHA; + break; + + case DSBF_INVDESTALPHA: + src = GL_ONE_MINUS_DST_ALPHA; + break; + + case DSBF_DESTCOLOR: + src = GL_DST_COLOR; + break; + + case DSBF_INVDESTCOLOR: + src = GL_ONE_MINUS_DST_COLOR; + break; + + case DSBF_SRCALPHASAT: + src = GL_SRC_ALPHA_SATURATE; + break; + + default: + D_BUG( "unexpected src blend function %d", state->src_blend ); + } + + switch (state->dst_blend) { + case DSBF_ZERO: + break; + + case DSBF_ONE: + dst = GL_ONE; + break; + + case DSBF_SRCCOLOR: + dst = GL_SRC_COLOR; + break; + + case DSBF_INVSRCCOLOR: + dst = GL_ONE_MINUS_SRC_COLOR; + break; + + case DSBF_SRCALPHA: + dst = GL_SRC_ALPHA; + break; + + case DSBF_INVSRCALPHA: + dst = GL_ONE_MINUS_SRC_ALPHA; + break; + + case DSBF_DESTALPHA: + dst = GL_DST_ALPHA; + break; + + case DSBF_INVDESTALPHA: + dst = GL_ONE_MINUS_DST_ALPHA; + break; + + case DSBF_DESTCOLOR: + dst = GL_DST_COLOR; + break; + + case DSBF_INVDESTCOLOR: + dst = GL_ONE_MINUS_DST_COLOR; + break; + + case DSBF_SRCALPHASAT: + dst = GL_SRC_ALPHA_SATURATE; + break; + + default: + D_BUG( "unexpected dst blend function %d", state->dst_blend ); + } + + glBlendFunc( src, dst ); + + /* Set the flag. */ + GL_VALIDATE( BLENDFUNC ); +} + +/**********************************************************************************************************************/ + +/* + * Wait for the blitter to be idle. + * + * This function is called before memory that has been written to by the hardware is about to be + * accessed by the CPU (software driver) or another hardware entity like video encoder (by Flip()). + * It can also be called by applications explicitly, e.g. at the end of a benchmark loop to include + * execution time of queued commands in the measurement. + */ +DFBResult +glEngineSync( void *drv, void *dev ) +{ + GLDriverData *gdrv = drv; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + if (gdrv->calls > 0) { + glFinish(); + + gdrv->calls = 0; + } + + return DFB_OK; +} + +/* + * Reset the graphics engine. + */ +void +glEngineReset( void *drv, void *dev ) +{ + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); +} + +/* + * Start processing of queued commands if required. + * + * This function is called before returning from the graphics core to the application. + * Usually that's after each rendering function. The only functions causing multiple commands + * to be queued with a single emition at the end are DrawString(), TileBlit(), BatchBlit(), + * DrawLines() and possibly FillTriangle() which is emulated using multiple FillRectangle() calls. + */ +void +glEmitCommands( void *drv, void *dev ) +{ + GLDriverData *gdrv = drv; + + D_DEBUG_AT( GL__2D, "%s()\n", __FUNCTION__ ); + + if (gdrv->calls > 523) { + glFlush(); + + gdrv->calls = 1; + } +} + +/**********************************************************************************************************************/ + +/* + * Check for acceleration of 'accel' using the given 'state'. + */ +void +glCheckState( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ) +{ + D_DEBUG_AT( GL__2D, "%s( state %p, accel 0x%08x ) <- dest %p [%lu]\n", __FUNCTION__, + state, accel, state->destination, state->dst.offset ); + + /* Return if the desired function is not supported at all. */ + if (accel & ~(GL_SUPPORTED_DRAWINGFUNCTIONS | GL_SUPPORTED_BLITTINGFUNCTIONS)) { + D_DEBUG_AT( GL__2D, " -> unsupported function\n" ); + return; + } + + /* Return if the destination format is not supported. */ + switch (state->destination->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + break; + + default: + D_DEBUG_AT( GL__2D, " -> unsupported destination format %s\n", + dfb_pixelformat_name(state->destination->config.format) ); + return; + } + + /* Check if drawing or blitting is requested. */ + if (DFB_DRAWING_FUNCTION( accel )) { + /* Return if unsupported drawing flags are set. */ + if (state->drawingflags & ~GL_SUPPORTED_DRAWINGFLAGS) { + D_DEBUG_AT( GL__2D, " -> unsupported drawing flags 0x%08x\n", state->drawingflags ); + return; + } + } + else { + /* Return if the source format is not supported. */ + switch (state->source->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + break; + + default: + D_DEBUG_AT( GL__2D, " -> unsupported source format %s\n", + dfb_pixelformat_name(state->source->config.format) ); + return; + } + + /* Return if unsupported blitting flags are set. */ + if (state->blittingflags & ~GL_SUPPORTED_BLITTINGFLAGS) { + D_DEBUG_AT( GL__2D, " -> unsupported blitting flags 0x%08x\n", state->blittingflags ); + return; + } + } + + /* Enable acceleration of the function. */ + state->accel |= accel; + + D_DEBUG_AT( GL__2D, " => OK\n" ); +} + +/* + * Make sure that the hardware is programmed for execution of 'accel' according to the 'state'. + */ +void +glSetState( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ) +{ + GLDriverData *gdrv = drv; + GLDeviceData *gdev = dev; + StateModificationFlags modified = state->mod_hw; + + D_DEBUG_AT( GL__2D, "%s( state %p, accel 0x%08x ) <- dest %p, modified 0x%08x\n", __FUNCTION__, + state, accel, state->destination, modified ); + + /* + * 1) Invalidate hardware states + * + * Each modification to the hw independent state invalidates one or more hardware states. + */ + + /* Simply invalidate all? */ + if (modified == SMF_ALL) { + GL_INVALIDATE( ALL ); + } + else if (modified) { + if (modified & SMF_DESTINATION) + GL_INVALIDATE( DESTINATION ); + + if (modified & SMF_CLIP) + GL_INVALIDATE( SCISSOR ); + + if (modified & SMF_MATRIX) + GL_INVALIDATE( MATRIX ); + + if (modified & SMF_RENDER_OPTIONS) + GL_INVALIDATE( MATRIX | RENDER_OPTS ); + + if (modified & SMF_COLOR) + GL_INVALIDATE( COLOR_DRAW | COLOR_BLIT ); + + if (modified & SMF_DRAWING_FLAGS) + GL_INVALIDATE( COLOR_DRAW ); + + if (modified & SMF_BLITTING_FLAGS) + GL_INVALIDATE( COLOR_BLIT ); + + if (modified & SMF_SOURCE) + GL_INVALIDATE( SOURCE ); + + if (modified & (SMF_SRC_BLEND | SMF_DST_BLEND)) + GL_INVALIDATE( BLENDFUNC ); + } + + /* + * 2) Validate hardware states + * + * Each function has its own set of states that need to be validated. + */ + + /* Always requiring valid destination, clip, matrix and options... */ + GL_CHECK_VALIDATE( DESTINATION ); + GL_CHECK_VALIDATE( SCISSOR ); + GL_CHECK_VALIDATE( MATRIX ); + GL_CHECK_VALIDATE( RENDER_OPTS ); + + /* Depending on the function... */ + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + glDisable( GL_TEXTURE_RECTANGLE_ARB ); + + /* ...require valid drawing color. */ + GL_CHECK_VALIDATE( COLOR_DRAW ); + + /* If alpha blending is used... */ + if (state->drawingflags & DSDRAW_BLEND) { + /* ...require valid blend functions. */ + GL_CHECK_VALIDATE( BLENDFUNC ); + + glEnable( GL_BLEND ); + } + else + glDisable( GL_BLEND ); + + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = GL_SUPPORTED_DRAWINGFUNCTIONS; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + glEnable( GL_TEXTURE_RECTANGLE_ARB ); + + /* ...require valid source. */ + GL_CHECK_VALIDATE( SOURCE ); + + + /* If alpha blending is used... */ + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + /* ...require valid blend functions. */ + GL_CHECK_VALIDATE( BLENDFUNC ); + + glEnable( GL_BLEND ); + } + else + glDisable( GL_BLEND ); + + + /* If colorizing or premultiplication of global alpha is used... */ + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + /* ...require valid color. */ + GL_CHECK_VALIDATE( COLOR_BLIT ); + + /* Enable texture modulation */ + glTexEnvi( GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_MODULATE ); + } + else + /* Disable texture modulation */ + glTexEnvi( GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_REPLACE ); + + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = GL_SUPPORTED_BLITTINGFUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + gdrv->blittingflags = state->blittingflags; + + /* + * 4) Clear modification flags + * + * All flags have been evaluated in 1) and remembered for further validation. + * If the hw independent state is not modified, this function won't get called + * for subsequent rendering functions, unless they aren't defined by 3). + */ + state->mod_hw = 0; +} + +/**********************************************************************************************************************/ + +/* + * Render a filled rectangle using the current hardware state. + */ +bool +glFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + GLDriverData *gdrv = drv; + + int x1 = rect->x; + int y1 = rect->y; + int x2 = rect->w + x1; + int y2 = rect->h + y1; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4dx%4d )\n", __FUNCTION__, DFB_RECTANGLE_VALS( rect ) ); + + glBegin( GL_QUADS ); + + glVertex2i( x1, y1 ); + glVertex2i( x2, y1 ); + glVertex2i( x2, y2 ); + glVertex2i( x1, y2 ); + + glEnd(); + + + gdrv->calls += 1 + rect->w * rect->h / (23 * 42); + + return true; +} + +/* + * Render a rectangle outline using the current hardware state. + */ +bool +glDrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + GLDriverData *gdrv = drv; + + int x1 = rect->x + 1; + int y1 = rect->y; + int x2 = rect->x + rect->w; + int y2 = rect->y + rect->h - 1; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4dx%4d )\n", __FUNCTION__, DFB_RECTANGLE_VALS( rect ) ); + + glBegin( GL_LINE_LOOP ); + + glVertex2i( x1, y1 ); + glVertex2i( x2, y1 ); + glVertex2i( x2, y2 ); + glVertex2i( x1, y2 ); + + glEnd(); + + + gdrv->calls++; + + return true; +} + +/* + * Render a line using the current hardware state. + */ +bool +glDrawLine( void *drv, void *dev, DFBRegion *line ) +{ + GLDriverData *gdrv = drv; + + int x1 = line->x1; + int y1 = line->y1; + int x2 = line->x2; + int y2 = line->y2; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4d,%4d )\n", __FUNCTION__, DFB_REGION_VALS( line ) ); + + glBegin( GL_LINES ); + + glVertex2i( x1, y1 ); + glVertex2i( x2, y2 ); + + glEnd(); + + + gdrv->calls++; + + return true; +} + +/* + * Render a line using the current hardware state. + */ +bool +glFillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + GLDriverData *gdrv = drv; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4d,%4d-%4d,%4d )\n", __FUNCTION__, + tri->x1, tri->y1, tri->x2, tri->y2, tri->x3, tri->y3 ); + + glBegin( GL_TRIANGLES ); + + glVertex2i( tri->x1, tri->y1 ); + glVertex2i( tri->x2, tri->y2 ); + glVertex2i( tri->x3, tri->y3 ); + + glEnd(); + + + gdrv->calls += 23; + + return true; +} + +/* + * Blit a rectangle using the current hardware state. + */ +bool +glBlit( void *drv, void *dev, DFBRectangle *srect, int dx, int dy ) +{ + GLDriverData *gdrv = drv; + + int x1 = dx; + int y1 = dy; + int x2 = srect->w + x1; + int y2 = srect->h + y1; + + int tx1 = srect->x; + int ty1 = srect->y; + int tx2 = srect->w + tx1; + int ty2 = srect->h + ty1; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d )\n", __FUNCTION__, + dx, dy, srect->w, srect->h, srect->x, srect->y ); + + /* Might also use GL_TEXTURE matrix, but isn't this less overhead in state management? */ + if (gdrv->blittingflags & DSBLIT_ROTATE180) { + int tmp; + + tmp = tx1; tx1 = tx2; tx2 = tmp; + tmp = ty1; ty1 = ty2; ty2 = tmp; + } + + glBegin( GL_QUADS ); + + glTexCoord2i( tx1, ty1 ); + glVertex2i( x1, y1 ); + + glTexCoord2i( tx2, ty1 ); + glVertex2i( x2, y1 ); + + glTexCoord2i( tx2, ty2 ); + glVertex2i( x2, y2 ); + + glTexCoord2i( tx1, ty2 ); + glVertex2i( x1, y2 ); + + glEnd(); + + + gdrv->calls += 1 + srect->w * srect->h / (23 * 42); + + return true; +} + +/* + * Blit a scaled rectangle using the current hardware state. + */ +bool +glStretchBlit( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ) +{ + GLDriverData *gdrv = drv; + + int x1 = drect->x; + int y1 = drect->y; + int x2 = drect->w + x1; + int y2 = drect->h + y1; + + int tx1 = srect->x; + int ty1 = srect->y; + int tx2 = srect->w + tx1; + int ty2 = srect->h + ty1; + + D_DEBUG_AT( GL__2D, "%s( %4d,%4d-%4dx%4d <- %4d,%4d-%4dx%4d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( drect ), DFB_RECTANGLE_VALS( srect ) ); + + /* Might also use GL_TEXTURE matrix, but isn't this less overhead in state management? */ + if (gdrv->blittingflags & DSBLIT_ROTATE180) { + int tmp; + + tmp = tx1; tx1 = tx2; tx2 = tmp; + tmp = ty1; ty1 = ty2; ty2 = tmp; + } + + glBegin( GL_QUADS ); + + glTexCoord2i( tx1, ty1 ); + glVertex2i( x1, y1 ); + + glTexCoord2i( tx2, ty1 ); + glVertex2i( x2, y1 ); + + glTexCoord2i( tx2, ty2 ); + glVertex2i( x2, y2 ); + + glTexCoord2i( tx1, ty2 ); + glVertex2i( x1, y2 ); + + glEnd(); + + + gdrv->calls += 1 + drect->w * drect->h / (23 * 42); + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/gl/gl_2d.h b/Source/DirectFB/gfxdrivers/gl/gl_2d.h new file mode 100755 index 0000000..fa67106 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/gl_2d.h @@ -0,0 +1,93 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __GL_2D_H__ +#define __GL_2D_H__ + + +#define GL_SUPPORTED_DRAWINGFLAGS (DSDRAW_BLEND | \ + DSDRAW_SRC_PREMULTIPLY) + +#define GL_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE | \ + DFXL_FILLTRIANGLE) + +#define GL_SUPPORTED_BLITTINGFLAGS (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_ROTATE180 | \ + DSBLIT_SRC_PREMULTCOLOR) + +#define GL_SUPPORTED_BLITTINGFUNCTIONS (DFXL_BLIT | \ + DFXL_STRETCHBLIT) + + +DFBResult glEngineSync ( void *drv, + void *dev ); + +void glEngineReset ( void *drv, + void *dev ); + +void glEmitCommands ( void *drv, + void *dev ); + +void glCheckState ( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ); + +void glSetState ( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ); + +bool glFillRectangle( void *drv, + void *dev, + DFBRectangle *rect ); + +bool glDrawRectangle( void *drv, + void *dev, + DFBRectangle *rect ); + +bool glDrawLine ( void *drv, + void *dev, + DFBRegion *line ); + +bool glFillTriangle ( void *drv, + void *dev, + DFBTriangle *tri ); + +bool glBlit ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +bool glStretchBlit ( void *drv, + void *dev, + DFBRectangle *srect, + DFBRectangle *drect ); + +#endif + diff --git a/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.c b/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.c new file mode 100755 index 0000000..1f84097 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.c @@ -0,0 +1,217 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include + +#include +#include + +#include + +#include + +#include + +#include "gl_2d.h" +#include "gl_gfxdriver.h" + +D_DEBUG_DOMAIN( GL_Driver, "GL/Driver", "GL graphics driver for X11" ); + +#include + +DFB_GRAPHICS_DRIVER( gl ) + +static int error_code = 0; + +/**********************************************************************************************************************/ + +static int +error_handler( Display *display, XErrorEvent *event ) +{ + char buf[512]; + + XGetErrorText( display, event->error_code, buf, sizeof(buf) ); + + D_ERROR( "GL/Driver: Error! %s\n", buf ); + + error_code = event->error_code; + + return 0; +} + +/**********************************************************************************************************************/ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_system_type()) { + case CORE_X11: { + int ee; + DFBX11 *x11 = dfb_system_data(); + + return glXQueryExtension( x11->display, &ee, &ee ); + } + + default: + break; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "OpenGL Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Denis Oliver Kropp" ); + + info->version.major = 0; + info->version.minor = 5; + + info->driver_data_size = sizeof(GLDriverData); + info->device_data_size = sizeof(GLDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + D_DEBUG_AT( GL_Driver, "%s()\n", __FUNCTION__ ); + + /* initialize function pointers */ + funcs->EngineSync = glEngineSync; + funcs->EngineReset = glEngineReset; + funcs->EmitCommands = glEmitCommands; + funcs->CheckState = glCheckState; + funcs->SetState = glSetState; + funcs->FillRectangle = glFillRectangle; + funcs->DrawRectangle = glDrawRectangle; + funcs->DrawLine = glDrawLine; + funcs->FillTriangle = glFillTriangle; + funcs->Blit = glBlit; + funcs->StretchBlit = glStretchBlit; + + /* Choose accelerated font format */ + if (!dfb_config->software_only) { + dfb_config->font_format = DSPF_ARGB; + dfb_config->font_premult = true; + } + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + const char *renderer; + Display *display; + XVisualInfo *visual; + GLXContext context; + DFBX11 *x11; + + int attr[] = { + GLX_RGBA, + GLX_RED_SIZE, 1, + GLX_GREEN_SIZE, 1, + GLX_BLUE_SIZE, 1, + None + }; + + D_DEBUG_AT( GL_Driver, "%s()\n", __FUNCTION__ ); + + XSetErrorHandler( error_handler ); + error_code = 0; + + x11 = dfb_system_data(); + + display = x11->display; + + visual = glXChooseVisual( display, DefaultScreen(display), attr ); + if (!visual || error_code) { + D_ERROR( "GL/Driver: Could not find a suitable visual!\n" ); + return DFB_INIT; + } + + context = glXCreateContext( display, visual, NULL, GL_TRUE ); + if (!context || error_code) { + D_ERROR( "GL/Driver: Could not create a context!\n" ); + return DFB_INIT; + } + + glXMakeCurrent( display, RootWindowOfScreen(DefaultScreenOfDisplay(display)), context ); + if( error_code ) + return DFB_INIT; + + renderer = (const char*) glGetString( GL_RENDERER ); + + glXMakeCurrent( display, None, NULL ); + + /* fill device info */ + snprintf( device_info->vendor, DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "OpenGL Acceleration -" ); + snprintf( device_info->name, DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "%s", renderer ?: "Unknown" ); + + glXDestroyContext( display, context ); + + /* device limitations */ + device_info->limits.surface_byteoffset_alignment = 8; + device_info->limits.surface_bytepitch_alignment = 8; + + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = GL_SUPPORTED_DRAWINGFUNCTIONS | + GL_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = GL_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = GL_SUPPORTED_BLITTINGFLAGS; + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} + diff --git a/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.h b/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.h new file mode 100755 index 0000000..4752349 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/gl/gl_gfxdriver.h @@ -0,0 +1,63 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __GL_GFXDRIVER_H__ +#define __GL_GFXDRIVER_H__ + +#include + + +typedef enum { + GLBF_UPDATE_TARGET = 0x00000001, + GLBF_UPDATE_TEXTURE = 0x00000002, +} GLBufferFlags; + +typedef struct { + int magic; + + /* Update flags for OpenGL driver */ + GLBufferFlags flags; + + /* Texture object bound to buffer */ + GLuint texture; +} GLBufferData; + + +typedef struct { + /* validation flags */ + int v_flags; + + /** Add shared data here... **/ +} GLDeviceData; + + +typedef struct { + DFBSurfaceBlittingFlags blittingflags; + + /* Flush every bunch of commands to avoid issue with the XServer... */ + unsigned int calls; + + /** Add local data here... **/ +} GLDriverData; + + +#endif diff --git a/Source/DirectFB/gfxdrivers/i810/Makefile.am b/Source/DirectFB/gfxdrivers/i810/Makefile.am new file mode 100755 index 0000000..76e3d95 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i810/Makefile.am @@ -0,0 +1,35 @@ +## Makefile.am for DirectFB/src/core/gfxcards/i810 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +i810_LTLIBRARIES = libdirectfb_i810.la + +if BUILD_STATIC +i810_DATA = $(i810_LTLIBRARIES:.la=.o) +endif + +i810dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_i810_la_SOURCES = \ + i810.c \ + i810.h \ + i810_overlay.c + +libdirectfb_i810_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_i810_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/i810/Makefile.in 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pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-i810DATA \ + uninstall-i810LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/i810/i810.c b/Source/DirectFB/gfxdrivers/i810/i810.c new file mode 100755 index 0000000..0c3d0ff --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i810/i810.c @@ -0,0 +1,1044 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +/* need fb handle to get accel, MMIO programming in the i810 is useless */ +#include +#include +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( i810 ) + +#include "i810.h" + + +#define TIMER_LOOP 1000000000 +#define BUFFER_PADDING 2 +#define MMIO_SIZE 512 * 1024 + +#define I810_SUPPORTED_DRAWINGFLAGS (DSDRAW_NOFX) + +#define I810_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_FILLTRIANGLE) + +#define I810_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY) + +#define I810_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT) + +static void +i810_lring_enable(I810DriverData *i810drv, u32 mode) +{ + u32 tmp; + + tmp = i810_readl(i810drv->mmio_base, LRING + 12); + tmp = (!mode) ? tmp & ~1 : tmp | 1; + + i810_writel(i810drv->mmio_base, LRING + 12, tmp); +} + + +static inline void +i810_wait_for_blit_idle(I810DriverData *i810drv, + I810DeviceData *i810dev ) +{ + u32 count = 0; + + if (i810dev != NULL) + i810dev->idle_calls++; + + while ((i810_readw(i810drv->mmio_base, INSTDONE) & 0x7b) != 0x7b && + count++ < TIMER_LOOP) { + if (i810dev != NULL) + i810dev->idle_waitcycles++; + } + + if (count >= TIMER_LOOP) { + if (i810dev != NULL) + i810dev->idle_timeoutsum++; + D_BUG("warning: idle timeout exceeded"); + } +} + +static void +i810_init_ringbuffer(I810DriverData *i810drv, + I810DeviceData *i810dev ) +{ + u32 tmp1, tmp2; + + i810_wait_for_blit_idle(i810drv, i810dev); + i810_lring_enable(i810drv, 0); + + i810_writel(i810drv->mmio_base, LRING, 0); + i810_writel(i810drv->mmio_base, LRING + 4, 0); + i810dev->cur_tail = 0; + + tmp2 = i810_readl(i810drv->mmio_base, LRING + 8) & ~RBUFFER_START_MASK; + tmp1 = i810dev->lring_bind.pg_start * 4096; + i810_writel(i810drv->mmio_base, LRING + 8, tmp2 | tmp1); + + tmp1 = i810_readl(i810drv->mmio_base, LRING + 12); + tmp1 &= ~RBUFFER_SIZE_MASK; + tmp2 = (RINGBUFFER_SIZE - 4096) & RBUFFER_SIZE_MASK; + i810_writel(i810drv->mmio_base, LRING + 12, tmp1 | tmp2); + i810_lring_enable(i810drv, 1); +} + +static inline int +i810_wait_for_space(I810DriverData *i810drv, + I810DeviceData *i810dev, + u32 space ) +{ + u32 head, count = TIMER_LOOP, tail, tries = 0; + + i810dev->waitfifo_calls++; + + tail = i810dev->cur_tail; + + space += BUFFER_PADDING; + space <<= 2; + i810dev->waitfifo_sum += space; + + while (count--) { + i810dev->fifo_waitcycles++; + head = i810_readl(i810drv->mmio_base, LRING + 4) & RBUFFER_HEAD_MASK; + if ((tail == head) || + (tail > head && (RINGBUFFER_SIZE - tail + head) >= space) || + (tail < head && (head - tail) >= space)) { + if (!tries) + i810dev->fifo_cache_hits++; + return 0; + } + tries++; + } + D_BUG("warning: buffer space timout error"); + return 1; +} + + +static void +i810FlushTextureCache(void *drv, void *dev) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + + if (BEGIN_LRING(i810drv, i810dev, 2)) return; + + PUT_LRING(PARSER | FLUSH); + PUT_LRING(NOP); + + END_LRING(i810drv); +} + +static DFBResult +i810EngineSync(void *drv, void *dev) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + + i810_wait_for_blit_idle(i810drv, i810dev); + + return DFB_OK; +} + +/* + * Set State routines + */ +static inline void +i810_set_src(I810DriverData *i810drv, + I810DeviceData *i810dev, + CardState *state) +{ + if (i810dev->i_src) + return; + i810dev->srcaddr = dfb_gfxcard_memory_physical((CoreGraphicsDevice *) i810dev, + state->src.offset); + i810dev->srcpitch = state->src.pitch; + + i810dev->i_src = 1; +} + +static inline void +i810_set_dest(I810DriverData *i810drv, + I810DeviceData *i810dev, + CardState *state) +{ + CoreSurface *destination = state->destination; + + if (i810dev->i_dst) + return; + i810dev->destaddr = dfb_gfxcard_memory_physical((CoreGraphicsDevice *) i810dev, + state->dst.offset); + i810dev->destpitch = state->dst.pitch; + + switch (destination->config.format) { + case DSPF_LUT8: + i810dev->pixeldepth = 1; + i810dev->blit_color = BPP8; + break; + case DSPF_ARGB1555: + i810dev->pixeldepth = 2; + i810dev->blit_color = BPP16; + break; + case DSPF_RGB16: + i810dev->pixeldepth = 2; + i810dev->blit_color = BPP16; + break; + case DSPF_RGB24: + i810dev->pixeldepth = 3; + i810dev->blit_color = BPP24; + break; + default: + D_BUG("unexpected pixelformat~"); + } + i810dev->i_dst = 1; +} + +static inline void +i810_set_colorkey(I810DriverData *i810drv, + I810DeviceData *i810dev, + CardState *state) +{ + if (i810dev->i_colorkey) + return; + + i810dev->colorkey_bit = 0; + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + i810dev->colorkey_bit = 1 << 8; + i810dev->colorkey = state->src_colorkey; + } + else { + i810dev->colorkey_bit = 7 << 8; + i810dev->colorkey = state->dst_colorkey; + } + + i810dev->i_colorkey = 1; +} + +static inline void +i810_set_color(I810DriverData *i810drv, + I810DeviceData *i810dev, + CardState *state) +{ + if (i810dev->i_color) + return; + + switch (state->destination->config.format) { + case DSPF_LUT8: + i810dev->color_value = state->color_index; + break; + case DSPF_ARGB1555: + i810dev->color_value = PIXEL_ARGB1555(state->color.a, + state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB16: + i810dev->color_value = PIXEL_RGB16(state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB24: + i810dev->color_value = PIXEL_RGB32(state->color.r, + state->color.g, + state->color.b); + break; + default: + D_BUG("unexpected pixelformat~"); + } + i810dev->i_color = 1; +} + +static inline void +i810_set_clip(I810DriverData *i810drv, + I810DeviceData *i810dev, + DFBRegion *clip ) +{ + if (i810dev->i_clip) + return; + + i810dev->clip_x1 = clip->x1; + i810dev->clip_x2 = clip->x2 + 1; + i810dev->clip_y1 = clip->y1; + i810dev->clip_y2 = clip->y2 + 1; + + i810dev->i_clip = 1; +} + +static void +i810CheckState(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + case DSPF_LUT8: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + break; + default: + return; + } + + if (!(accel & ~I810_SUPPORTED_DRAWINGFUNCTIONS) && + !(state->drawingflags & ~I810_SUPPORTED_DRAWINGFLAGS)) + state->accel |= I810_SUPPORTED_DRAWINGFUNCTIONS; + + if (!(accel & ~I810_SUPPORTED_BLITTINGFUNCTIONS) && + !(state->blittingflags & ~I810_SUPPORTED_BLITTINGFLAGS)) { + if (state->source->config.format == state->destination->config.format) + state->accel |= I810_SUPPORTED_BLITTINGFUNCTIONS; + } +} + +static void +i810SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + + if (state->mod_hw) { + if ((state->mod_hw & SMF_SOURCE) && state->source) + i810dev->i_src = 0; + if (state->mod_hw & SMF_DESTINATION) + i810dev->i_dst = 0; + if (state->mod_hw & SMF_COLOR) + i810dev->i_color = 0; + if (state->mod_hw & SMF_CLIP) + i810dev->i_clip = 0; + if (state->mod_hw & SMF_SRC_COLORKEY || + state->mod_hw & SMF_DST_COLORKEY) { + i810dev->i_colorkey = 0; + } + } + + switch (accel) { + case DFXL_DRAWRECTANGLE: + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + i810_set_dest(i810drv, i810dev, state); + i810_set_color(i810drv, i810dev, state); + i810_set_clip(i810drv, i810dev, &state->clip); + state->set |= DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE; + break; + case DFXL_BLIT: + i810_set_src( i810drv, i810dev, state); + i810_set_dest(i810drv, i810dev, state); + i810_set_color(i810drv, i810dev, state); + i810_set_clip(i810drv, i810dev, &state->clip); + if (state->blittingflags & DSBLIT_SRC_COLORKEY || + state->blittingflags & DSBLIT_DST_COLORKEY) + i810_set_colorkey(i810drv, i810dev, state); + state->set |= DFXL_BLIT; + break; + default: + D_BUG("unexpected drawing/blitting function"); + } + state->mod_hw = 0; +} + +static bool +i810FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + u32 dest; + + + if (rect->x < i810dev->clip_x1) + rect->x = i810dev->clip_x1; + if (i810dev->clip_x2 < rect->x + rect->w) + rect->w = i810dev->clip_x2 - rect->x; + if (rect->y < i810dev->clip_y1) + rect->y = i810dev->clip_y1; + if (i810dev->clip_y2 < rect->y + rect->h) + rect->h = i810dev->clip_y2 - rect->y; + + rect->x *= i810dev->pixeldepth; + rect->w *= i810dev->pixeldepth; + dest = i810dev->destaddr + rect->x + (rect->y * i810dev->destpitch); + + if (BEGIN_LRING(i810drv, i810dev, 6)) return false; + + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | SOLIDPATTERN | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(rect->h << 16 | rect->w); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + PUT_LRING(NOP); + + END_LRING(i810drv); + + return true; +} + +static bool +i810DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + u32 dest; + + + if (rect->x < i810dev->clip_x1) + rect->x = i810dev->clip_x1; + if (i810dev->clip_x2 < rect->x + rect->w) + rect->w = i810dev->clip_x2 - rect->x; + if (rect->y < i810dev->clip_y1) + rect->y = i810dev->clip_y1; + if (i810dev->clip_y2 < rect->y + rect->h) + rect->h = i810dev->clip_y2 - rect->y; + + + + rect->x *= i810dev->pixeldepth; + rect->w *= i810dev->pixeldepth; + + if (BEGIN_LRING(i810drv, i810dev, 20)) return false; + + /* horizontal line 1 */ + dest = i810dev->destaddr + rect->x + (rect->y * i810dev->destpitch); + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | SOLIDPATTERN | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(1 << 16 | rect->w); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + + /* vertical line 1 */ + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | SOLIDPATTERN | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(rect->h << 16 | i810dev->pixeldepth); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + + /* vertical line 2 */ + dest += rect->w; + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | SOLIDPATTERN | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(rect->h << 16 | i810dev->pixeldepth); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + + /* horizontal line 2 */ + dest -= rect->w; + dest += rect->h * i810dev->destpitch; + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | SOLIDPATTERN | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(1 << 16 | rect->w); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + + END_LRING(i810drv); + + return true; +} + +static bool +i810Blit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + int xdir = INCREMENT, spitch = 0, dpitch = 0, src, dest; + + if (dx < i810dev->clip_x1) { + rect->w = MIN((i810dev->clip_x2 - i810dev->clip_x1), + (dx + rect->w) - i810dev->clip_x1); + rect->x += i810dev->clip_x1 - dx; + dx = i810dev->clip_x1; + } + if (i810dev->clip_x2 < dx + rect->w) + rect->w = i810dev->clip_x2 - dx; + + if (dy < i810dev->clip_y1) { + rect->h = MIN((i810dev->clip_y2 - i810dev->clip_y1), + (dy + rect->h) - i810dev->clip_y1); + rect->y += i810dev->clip_y1 - dy; + dy = i810dev->clip_y1; + } + if (i810dev->clip_y2 < dy + rect->h) + rect->h = i810dev->clip_y2 - dy; + + rect->x *= i810dev->pixeldepth; + dx *= i810dev->pixeldepth; + rect->w *= i810dev->pixeldepth; + + spitch = i810dev->srcpitch; + dpitch = i810dev->destpitch; + + if (i810dev->srcaddr == i810dev->destaddr) { + if (dx > rect->x && dx < rect->x + rect->w) { + xdir = DECREMENT; + rect->x += rect->w - 1; + dx += rect->w - 1; + } + if (dy > rect->y && dy < rect->y + rect->h) { + i810dev->srcpitch = (-(i810dev->srcpitch)) & 0xFFFF; + i810dev->destpitch = (-(i810dev->destpitch)) & 0xFFFF; + rect->y += rect->h - 1; + dy += rect->h - 1; + } + } + + src = i810dev->srcaddr + rect->x + (rect->y * spitch); + dest = i810dev->destaddr + dx + (dy * dpitch); + + BEGIN_LRING(i810drv, i810dev, 8); + + PUT_LRING(BLIT | FULL_BLIT | 0x6 | i810dev->colorkey_bit); + PUT_LRING(xdir | PAT_COPY_ROP << 16 | i810dev->destpitch | + DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING((rect->h << 16) | rect->w); + PUT_LRING(dest); + PUT_LRING(i810dev->srcpitch); + PUT_LRING(src); + PUT_LRING(i810dev->colorkey); + PUT_LRING((u32)(unsigned long) i810drv->pattern_base); + + END_LRING(i810drv); + + return true; +} + +/* + * The software rasterizer when rendering non-axis aligned + * edges uses line spanning. In our case, it will use + * FillRect to render a 1 pixel-high rectangle. However, + * this would be slow in the i810 since for each rectangle, + * an ioctl has to be done which is very slow. As a temporary + * replacement, I'll include a SpanLine function that will + * not do an ioctl for every line. This should be + * significantly faster. + */ + +/* borrowed heavily and shamelessly from gfxcard.c */ + +typedef struct { + int xi; + int xf; + int mi; + int mf; + int _2dy; +} DDA; + +#define SETUP_DDA(xs,ys,xe,ye,dda) \ + do { \ + int dx = xe - xs; \ + int dy = ye - ys; \ + dda.xi = xs; \ + if (dy != 0) { \ + dda.mi = dx / dy; \ + dda.mf = 2*(dx % dy); \ + dda.xf = -dy; \ + dda._2dy = 2*dy; \ + if (dda.mf < 0) { \ + dda.mf += ABS(dy)*2; \ + dda.mi--; \ + } \ + } \ + else { \ + dda.mi = 0; \ + dda.mf = 0; \ + dda.xf = 0; \ + dda._2dy = 0; \ + } \ + } while (0) + + +#define INC_DDA(dda) \ + do { \ + dda.xi += dda.mi; \ + dda.xf += dda.mf; \ + if (dda.xf > 0) { \ + dda.xi++; \ + dda.xf -= dda._2dy; \ + } \ + } while (0) + + + +/* + * The i810fill_tri function takes advantage of the buffer. + * It will fill up the buffer until it's done rendering the + * triangle. + */ +static inline bool +i810fill_tri( DFBTriangle *tri, + I810DriverData *i810drv, + I810DeviceData *i810dev ) +{ + int y, yend; + + DDA dda1, dda2; + u32 total, dest = 0; + + y = tri->y1; + yend = tri->y3; + + if (y < i810dev->clip_y1) + y = i810dev->clip_y1; + if (yend > i810dev->clip_y2) + yend = i810dev->clip_y2; + + + SETUP_DDA(tri->x1, tri->y1, tri->x3, tri->y3, dda1); + SETUP_DDA(tri->x1, tri->y1, tri->x2, tri->y2, dda2); + + total = (yend - y) * 5; + if (total + BUFFER_PADDING > RINGBUFFER_SIZE/4) { + D_BUG("fill_triangle: buffer size is too small\n"); + return false; + } + + BEGIN_LRING(i810drv, i810dev, total); + + while (y < yend) { + DFBRectangle rect; + + if (y == tri->y2) { + if (tri->y2 == tri->y3) + return true; + SETUP_DDA(tri->x2, tri->y2, tri->x3, tri->y3, dda2); + } + + rect.w = ABS(dda1.xi - dda2.xi); + rect.x = MIN(dda1.xi, dda2.xi); + + if (rect.w > 0) { + rect.y = y; + dest = i810dev->destaddr + (y * i810dev->destpitch) + (rect.x * i810dev->pixeldepth); + PUT_LRING(BLIT | COLOR_BLT | 3); + PUT_LRING(COLOR_COPY_ROP << 16 | i810dev->destpitch | + SOLIDPATTERN | DYN_COLOR_EN | i810dev->blit_color); + PUT_LRING(1 << 16 | rect.w * i810dev->pixeldepth); + PUT_LRING(dest); + PUT_LRING(i810dev->color_value); + } + + INC_DDA(dda1); + INC_DDA(dda2); + + y++; + } + END_LRING(i810drv); + return true; +} + +static bool +i810FillTriangle( void *drv, void *dev, DFBTriangle *tri) +{ + I810DriverData *i810drv = (I810DriverData *) drv; + I810DeviceData *i810dev = (I810DeviceData *) dev; + bool err = true; + + dfb_sort_triangle(tri); + + if (tri->y3 - tri->y1 > 0) + err = i810fill_tri(tri, i810drv, i810dev); + + return err; +} + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_I810: /* Intel 810 */ + return 1; + } + return 0; +} + + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Intel 810/810E/810-DC100/815 Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Tony Daplas" ); + + snprintf( info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://i810fb.sourceforge.net" ); + + snprintf( info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL" ); + + info->version.major = 0; + info->version.minor = 5; + + info->driver_data_size = sizeof (I810DriverData); + info->device_data_size = sizeof (I810DeviceData); +} + +static void +i810_release_resource( I810DriverData *idrv, I810DeviceData *idev ) +{ + agp_unbind unbind; + + if (idrv->flags & I810RES_STATE_SAVE) { + i810_writel( idrv->mmio_base, LP_RING, idev->lring1 ); + i810_writel( idrv->mmio_base, LP_RING + RING_HEAD, idev->lring2 ); + i810_writel( idrv->mmio_base, LP_RING + RING_START, idev->lring3 ); + i810_writel( idrv->mmio_base, LP_RING + RING_LEN, idev->lring4 ); + } + + if (idrv->flags & I810RES_MMAP) { + munmap((void *) idrv->aper_base, idev->info.aper_size * 1024 * 1024); + idrv->flags &= ~I810RES_MMAP; + } + + if (idrv->flags & I810RES_LRING_BIND) { + unbind.key = idev->lring_bind.key; + ioctl(idrv->agpgart, AGPIOC_UNBIND, &unbind); + } + + if (idrv->flags & I810RES_LRING_ACQ) + ioctl(idrv->agpgart, AGPIOC_DEALLOCATE, idev->lring_mem.key); + + if (idrv->flags & I810RES_OVL_BIND) { + unbind.key = idev->ovl_bind.key; + ioctl(idrv->agpgart, AGPIOC_UNBIND, &unbind); + } + + if (idrv->flags & I810RES_OVL_ACQ) + ioctl(idrv->agpgart, AGPIOC_DEALLOCATE, idev->ovl_mem.key); + + if (idrv->flags & I810RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I810RES_GART_ACQ; + } + + if (idrv->flags & I810RES_GART) { + close(idrv->agpgart); + idrv->flags &= ~I810RES_GART; + } +} + +static DFBResult +i810_agp_setup( CoreGraphicsDevice *device, + I810DriverData *idrv, + I810DeviceData *idev ) +{ + idrv->agpgart = open("/dev/agpgart", O_RDWR); + if (idrv->agpgart == -1) + return DFB_IO; + D_FLAGS_SET( idrv->flags, I810RES_GART ); + + + if (ioctl(idrv->agpgart, AGPIOC_ACQUIRE)) { + D_PERROR( "I810/AGP: AGPIOC_ACQUIRE failed!\n" ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_GART_ACQ ); + + + if (!idev->initialized) { + agp_setup setup; + + setup.agp_mode = 0; + if (ioctl(idrv->agpgart, AGPIOC_SETUP, &setup)) { + D_PERROR( "I810/AGP: AGPIOC_SETUP failed!\n" ); + return DFB_IO; + } + + if (ioctl(idrv->agpgart, AGPIOC_INFO, &idev->info)) { + D_PERROR( "I810/AGP: AGPIOC_INFO failed!\n" ); + return DFB_IO; + } + } + + + idrv->aper_base = mmap( NULL, idev->info.aper_size * 1024 * 1024, PROT_WRITE, + MAP_SHARED, idrv->agpgart, 0 ); + if (idrv->aper_base == MAP_FAILED) { + D_PERROR( "I810/AGP: mmap() failed!\n" ); + i810_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_MMAP ); + + + if (!idev->initialized) { + u32 base; + + /* We'll attempt to bind at fb_base + fb_len + 1 MB, + to be safe */ + base = dfb_gfxcard_memory_physical(device, 0) - idev->info.aper_base; + base += dfb_gfxcard_memory_length(); + base += (1024 * 1024); + + idev->lring_mem.pg_count = RINGBUFFER_SIZE/4096; + idev->lring_mem.type = AGP_NORMAL_MEMORY; + if (ioctl(idrv->agpgart, AGPIOC_ALLOCATE, &idev->lring_mem)) { + D_PERROR( "I810/AGP: AGPIOC_ALLOCATE failed!\n" ); + i810_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_LRING_ACQ ); + + idev->lring_bind.key = idev->lring_mem.key; + idev->lring_bind.pg_start = base/4096; + if (ioctl(idrv->agpgart, AGPIOC_BIND, &idev->lring_bind)) { + D_PERROR( "I810/AGP: AGPIOC_BIND failed!\n" ); + i810_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_LRING_BIND ); + + idev->ovl_mem.pg_count = 1; + idev->ovl_mem.type = AGP_PHYSICAL_MEMORY; + if (ioctl(idrv->agpgart, AGPIOC_ALLOCATE, &idev->ovl_mem)) { + D_PERROR( "I810/AGP: AGPIOC_ALLOCATE failed!\n" ); + i810_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_OVL_ACQ ); + + idev->ovl_bind.key = idev->ovl_mem.key; + idev->ovl_bind.pg_start = (base + RINGBUFFER_SIZE)/4096; + if (ioctl(idrv->agpgart, AGPIOC_BIND, &idev->ovl_bind)) { + D_PERROR( "I810/AGP: AGPIOC_BIND failed!\n" ); + i810_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I810RES_OVL_BIND ); + } + + + if (idrv->flags & I810RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I810RES_GART_ACQ; + } + + + idrv->lring_base = idrv->aper_base + idev->lring_bind.pg_start * 4096; + idrv->ovl_base = idrv->aper_base + idev->ovl_bind.pg_start * 4096; + idrv->pattern_base = idrv->ovl_base + 1024; + + if (!idev->initialized) { + memset((void *) idrv->ovl_base, 0xff, 1024); + memset((void *) idrv->pattern_base, 0xff, 4096 - 1024); + + idev->lring1 = 0;//i810_readl(idrv->mmio_base, LP_RING); + idev->lring2 = 0;//i810_readl(idrv->mmio_base, LP_RING + RING_HEAD); + idev->lring3 = 0;//i810_readl(idrv->mmio_base, LP_RING + RING_START); + idev->lring4 = 0;//i810_readl(idrv->mmio_base, LP_RING + RING_LEN); + + D_FLAGS_SET( idrv->flags, I810RES_STATE_SAVE ); + } + + idev->initialized = true; + + return DFB_OK; +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + DFBResult ret; + I810DriverData *idrv = driver_data; + I810DeviceData *idev = device_data; + + idrv->idev = device_data; + + idrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!idrv->mmio_base) + return DFB_IO; + + ret = i810_agp_setup( device, idrv, idev ); + if (ret) { + dfb_gfxcard_unmap_mmio( device, idrv->mmio_base, -1 ); + return ret; + } + + idrv->info = idev->info; + + + funcs->CheckState = i810CheckState; + funcs->SetState = i810SetState; + funcs->EngineSync = i810EngineSync; + funcs->FlushTextureCache = i810FlushTextureCache; + + funcs->FillRectangle = i810FillRectangle; + funcs->DrawRectangle = i810DrawRectangle; + funcs->Blit = i810Blit; + funcs->FillTriangle = i810FillTriangle; + + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), driver_data, &i810OverlayFuncs ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + I810DriverData *idrv = driver_data; + I810DeviceData *idev = device_data; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "810/810E/810-DC100/815" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Intel" ); + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = I810_SUPPORTED_DRAWINGFUNCTIONS | + I810_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = I810_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = I810_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + dfb_config->pollvsync_after = 1; + + i810_init_ringbuffer( idrv, idev ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + I810DeviceData *i810dev = (I810DeviceData *) device_data; + I810DriverData *i810drv = (I810DriverData *) driver_data; + + i810ovlOnOff( i810drv, i810dev, false ); + + i810_wait_for_blit_idle( i810drv, i810dev ); + i810_lring_enable( i810drv, 0 ); + + i810_release_resource( i810drv, i810dev ); + + + D_DEBUG( "DirectFB/I810: DMA Buffer Performance Monitoring:\n"); + D_DEBUG( "DirectFB/I810: %9d DMA buffer size in KB\n", + RINGBUFFER_SIZE/1024 ); + D_DEBUG( "DirectFB/I810: %9d i810_wait_for_blit_idle calls\n", + i810dev->idle_calls ); + D_DEBUG( "DirectFB/I810: %9d i810_wait_for_space calls\n", + i810dev->waitfifo_calls ); + D_DEBUG( "DirectFB/I810: %9d BUFFER transfers (i810_wait_for_space sum)\n", + i810dev->waitfifo_sum ); + D_DEBUG( "DirectFB/I810: %9d BUFFER wait cycles (depends on GPU/CPU)\n", + i810dev->fifo_waitcycles ); + D_DEBUG( "DirectFB/I810: %9d IDLE wait cycles (depends on GPU/CPU)\n", + i810dev->idle_waitcycles ); + D_DEBUG( "DirectFB/I810: %9d BUFFER space cache hits(depends on BUFFER size)\n", + i810dev->fifo_cache_hits ); + D_DEBUG( "DirectFB/I810: %9d BUFFER timeout sum (possible hardware crash)\n", + i810dev->fifo_timeoutsum ); + D_DEBUG( "DirectFB/I810: %9d IDLE timeout sum (possible hardware crash)\n", + i810dev->idle_timeoutsum ); + D_DEBUG( "DirectFB/I810: Conclusion:\n" ); + D_DEBUG( "DirectFB/I810: Average buffer transfers per i810_wait_for_space " + "call: %.2f\n", + i810dev->waitfifo_sum/(float)(i810dev->waitfifo_calls) ); + D_DEBUG( "DirectFB/I810: Average wait cycles per i810_wait_for_space call:" + " %.2f\n", + i810dev->fifo_waitcycles/(float)(i810dev->waitfifo_calls) ); + D_DEBUG( "DirectFB/I810: Average wait cycles per i810_wait_for_blit_idle call:" + " %.2f\n", + i810dev->idle_waitcycles/(float)(i810dev->idle_calls) ); + D_DEBUG( "DirectFB/I810: Average buffer space cache hits: %02d%%\n", + (int)(100 * i810dev->fifo_cache_hits/ + (float)(i810dev->waitfifo_calls)) ); + +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + I810DriverData *idrv = (I810DriverData *) driver_data; + + dfb_gfxcard_unmap_mmio( device, idrv->mmio_base, -1); + + if (idrv->flags & I810RES_MMAP) { + munmap((void *) idrv->aper_base, idrv->info.aper_size * 1024 * 1024); + idrv->flags &= ~I810RES_MMAP; + } + + if (idrv->flags & I810RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I810RES_GART_ACQ; + } + + if (idrv->flags & I810RES_GART) { + close(idrv->agpgart); + idrv->flags &= ~I810RES_GART; + } +} + diff --git a/Source/DirectFB/gfxdrivers/i810/i810.h b/Source/DirectFB/gfxdrivers/i810/i810.h new file mode 100755 index 0000000..444c7c2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i810/i810.h @@ -0,0 +1,832 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +/* + * Intel 810 Chipset Family PRM 15 3.1 + * GC Register Memory Address Map + * + * Based on: + * Intel (R) 810 Chipset Family + * Programmer s Reference Manual + * November 1999 + * Revision 1.0 + * Order Number: 298026-001 R + * + * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers + * are I/O mapped. + */ + +#ifndef __I810_H__ +#define __I810_H__ + +#include +#include +#include + +#include +#include + + +#define LP_RING 0x2030 +#define HP_RING 0x2040 + +#define RING_TAIL 0x00 +#define RING_HEAD 0x04 +#define RING_START 0x08 +#define RING_LEN 0x0C + + +/* Instruction and Interrupt Control Registers (01000h 02FFFh) */ +#define FENCE 0x02000 +#define PGTBL_CTL 0x02020 +#define PGTBL_ER 0x02024 +#define RINGBUFFER 0x02030 +#define LRING 0x02030 +#define IRING 0x02040 +#define HWS_PGA 0x02080 +#define IPEIR 0x02088 +#define IPEHR 0x0208C +#define INSTDONE 0x02090 +#define NOPID 0x02094 +#define HWSTAM 0x02098 +#define IER 0x020A0 +#define IIR 0x020A4 +#define IMR 0x020A8 +#define ISR 0x020AC +#define EIR 0x020B0 +#define EMR 0x020B4 +#define ESR 0x020B8 +#define INSTPM 0x020C0 +#define INSTPS 0x020C4 +#define BBP_PTR 0x020C8 +#define ABB_SRT 0x020CC +#define ABB_END 0x020D0 +#define DMA_FADD 0x020D4 +#define FW_BLC 0x020D8 +#define MEM_MODE 0x020DC + +/* Memory Control Registers (03000h 03FFFh) */ +#define DRT 0x03000 +#define DRAMCL 0x03001 +#define DRAMCH 0x03002 + + +/* Span Cursor Registers (04000h 04FFFh) */ +#define UI_SC_CTL 0x04008 + +/* I/O Control Registers (05000h 05FFFh) */ +#define HVSYNC 0x05000 +#define GPIOA 0x05010 +#define GPIOB 0x05014 + +/* Clock Control and Power Management Registers (06000h 06FFFh) */ +#define DCLK_0D 0x06000 +#define DCLK_1D 0x06004 +#define DCLK_2D 0x06008 +#define LCD_CLKD 0x0600C +#define DCLK_0DS 0x06010 +#define PWR_CLKC 0x06014 + +/* Graphics Translation Table Range Definition (10000h 1FFFFh) */ +#define GTT 0x10000 + +/* Overlay Registers (30000h 03FFFFh) */ +#define OV0ADDR 0x30000 +#define DOV0STA 0x30008 +#define GAMMA 0x30010 +#define OBUF_0Y 0x30100 +#define OBUF_1Y 0x30104 +#define OBUF_0U 0x30108 +#define OBUF_0V 0x3010C +#define OBUF_1U 0x30110 +#define OBUF_1V 0x30114 +#define OV0STRIDE 0x30118 +#define YRGB_VPH 0x3011C +#define UV_VPH 0x30120 +#define HORZ_PH 0x30124 +#define INIT_PH 0x30128 +#define DWINPOS 0x3012C +#define DWINSZ 0x30130 +#define SWID 0x30134 +#define SWIDQW 0x30138 +#define SHEIGHT 0x3013C +#define YRGBSCALE 0x30140 +#define UVSCALE 0x30144 +#define OV0CLRCO 0x30148 +#define OV0CLRC1 0x3014C +#define DCLRKV 0x30150 +#define DLCRKM 0x30154 +#define SCLRKVH 0x30158 +#define SCLRKVL 0x3015C +#define SCLRKM 0x30160 +#define OV0CONF 0x30164 +#define OV0CMD 0x30168 +#define AWINPOS 0x30170 +#define AWINZ 0x30174 + +/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */ +#define BR00 0x40000 +#define BRO1 0x40004 +#define BR02 0x40008 +#define BR03 0x4000C +#define BR04 0x40010 +#define BR05 0x40014 +#define BR06 0x40018 +#define BR07 0x4001C +#define BR08 0x40020 +#define BR09 0x40024 +#define BR10 0x40028 +#define BR11 0x4002C +#define BR12 0x40030 +#define BR13 0x40034 +#define BR14 0x40038 +#define BR15 0x4003C +#define BR16 0x40040 +#define BR17 0x40044 +#define BR18 0x40048 +#define BR19 0x4004C +#define SSLADD 0x40074 +#define DSLH 0x40078 +#define DSLRADD 0x4007C + + +/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */ +/* LCD/TV-Out */ +#define HTOTAL 0x60000 +#define HBLANK 0x60004 +#define HSYNC 0x60008 +#define VTOTAL 0x6000C +#define VBLANK 0x60010 +#define VSYNC 0x60014 +#define LCDTV_C 0x60018 +#define OVRACT 0x6001C +#define BCLRPAT 0x60020 + +/* Display and Cursor Control Registers (70000h 7FFFFh) */ +#define DISP_SL 0x70000 +#define DISP_SLC 0x70004 +#define PIXCONF 0x70008 +#define PIXCONF1 0x70009 +#define BLTCNTL 0x7000C +#define SWF 0x70014 +#define DPLYBASE 0x70020 +#define DPLYSTAS 0x70024 +#define CURCNTR 0x70080 +#define CURBASE 0x70084 +#define CURPOS 0x70088 + + +/* VGA Registers */ + +/* SMRAM Registers */ +#define SMRAM 0x10 + +/* Graphics Control Registers */ +#define GR_INDEX 0x3CE +#define GR_DATA 0x3CF + +#define GR10 0x10 +#define GR11 0x11 + +/* CRT Controller Registers */ +#define CR_INDEX_MDA 0x3B4 +#define CR_INDEX_CGA 0x3D4 +#define CR_DATA_MDA 0x3B5 +#define CR_DATA_CGA 0x3D5 + +#define CR30 0x30 +#define CR31 0x31 +#define CR32 0x32 +#define CR33 0x33 +#define CR35 0x35 +#define CR39 0x39 +#define CR40 0x40 +#define CR41 0x41 +#define CR42 0x42 +#define CR70 0x70 +#define CR80 0x80 +#define CR81 0x82 + +/* Extended VGA Registers */ + +/* General Control and Status Registers */ +#define ST00 0x3C2 +#define ST01_MDA 0x3BA +#define ST01_CGA 0x3DA +#define FRC_READ 0x3CA +#define FRC_WRITE_MDA 0x3BA +#define FRC_WRITE_CGA 0x3DA +#define MSR_READ 0x3CC +#define MSR_WRITE 0x3C2 + +/* Sequencer Registers */ +#define SR_INDEX 0x3C4 +#define SR_DATA 0x3C5 + +#define SR01 0x01 +#define SR02 0x02 +#define SR03 0x03 +#define SR04 0x04 +#define SR07 0x07 + +/* Graphics Controller Registers */ +#define GR00 0x00 +#define GR01 0x01 +#define GR02 0x02 +#define GR03 0x03 +#define GR04 0x04 +#define GR05 0x05 +#define GR06 0x06 +#define GR07 0x07 +#define GR08 0x08 + +/* Attribute Controller Registers */ +#define ATTR_WRITE 0x3C0 +#define ATTR_READ 0x3C1 + +/* VGA Color Palette Registers */ + +/* CLUT */ +#define CLUT_DATA 0x3C9 /* DACDATA */ +#define CLUT_INDEX_READ 0x3C7 /* DACRX */ +#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */ +#define DACMASK 0x3C6 + +/* CRT Controller Registers */ +#define CR00 0x00 +#define CR01 0x01 +#define CR02 0x02 +#define CR03 0x03 +#define CR04 0x04 +#define CR05 0x05 +#define CR06 0x06 +#define CR07 0x07 +#define CR08 0x08 +#define CR09 0x09 +#define CR0A 0x0A +#define CR0B 0x0B +#define CR0C 0x0C +#define CR0D 0x0D +#define CR0E 0x0E +#define CR0F 0x0F +#define CR10 0x10 +#define CR11 0x11 +#define CR12 0x12 +#define CR13 0x13 +#define CR14 0x14 +#define CR15 0x15 +#define CR16 0x16 +#define CR17 0x17 +#define CR18 0x18 + + +/* Raster ops */ +#define COLOR_COPY_ROP 0xF0 +#define PAT_COPY_ROP 0xCC +#define CLEAR_ROP 0x00 +#define WHITE_ROP 0xFF +#define INVERT_ROP 0x55 + +/* 2D Engine definitions */ +#define SOLIDPATTERN 0x80000000 +#define NONSOLID 0x00000000 +#define BPP8 0x00000000 +#define BPP16 0x01 << 24 +#define BPP24 0x02 << 24 +#define DYN_COLOR_EN 0x00400000 +#define DYN_COLOR_DIS 0x00000000 +#define INCREMENT 0x00000000 +#define DECREMENT 0x01 << 30 +#define ARB_ON 0x00000001 +#define ARB_OFF 0x00000000 +#define SYNC_FLIP 0x00000000 +#define ASYNC_FLIP 0x00000040 +#define OPTYPE_MASK 0xE0000000 +#define PARSER_MASK 0x001F8000 +#define D2_MASK 0x001FC000 /* 2D mask */ + +/* Instruction type */ +/* There are more but pertains to 3D */ +#define PARSER 0x00000000 +#define BLIT 0x02 << 29 +#define RENDER 0x03 << 29 + +/* Parser */ +#define NOP 0x00 /* No operation, padding */ +#define BP_INT 0x01 << 23 /* Breakpoint interrupt */ +#define USR_INT 0x02 << 23 /* User interrupt */ +#define WAIT_FOR_EVNT 0x03 << 23 /* Wait for event */ +#define FLUSH 0x04 << 23 +#define CONTEXT_SEL 0x05 << 23 +#define REPORT_HEAD 0x07 << 23 +#define ARB_ON_OFF 0x08 << 23 +#define OVERLAY_FLIP 0x11 << 23 +#define LOAD_SCAN_INC 0x12 << 23 +#define LOAD_SCAN_EX 0x13 << 23 +#define FRONT_BUFFER 0x14 << 23 +#define DEST_BUFFER 0x15 << 23 +#define Z_BUFFER 0x16 << 23 /* we won't need this */ +#define STORE_DWORD_IMM 0x20 << 23 +#define STORE_DWORD_IDX 0x21 << 23 +#define BATCH_BUFFER 0x30 << 23 + +/* Blit */ +#define SETUP_BLIT 0x00 +#define SETUP_MONO_PATTERN_SL_BLT 0x10 << 22 +#define PIXEL_BLT 0x20 << 22 +#define SCANLINE_BLT 0x21 << 22 +#define TEXT_BLT 0x22 << 22 +#define TEXT_IMM_BLT 0x30 << 22 +#define COLOR_BLT 0x40 << 22 +#define MONO_PAT_BLIT 0x42 << 22 +#define SOURCE_COPY_BLIT 0x43 << 22 +#define FULL_BLIT 0x45 << 22 + +/* Primitive */ +#define TRILIST 0 +#define TRISTRIP 1 << 18 +#define TRISTRIP_REV 2 << 18 +#define TRIFAN 3 << 18 +#define POLYGON 4 << 18 +#define LINELIST 5 << 18 +#define LINESTRIP 6 << 18 +#define RECTANGLE 7 << 18 +#define V0_ENABLE 1 +#define V1_ENABLE 2 +#define V2_ENABLE 4 + +/* Vertex Flags */ +#define COORD_1 0 +#define COORD_2 1 << 8 +#define COORD_3 2 << 8 +#define FOG_ENABLE 1 << 7 +#define ARGB_ENABLE 1 << 6 +#define Z_OFFSET_PRESENT 1 << 5 +#define XYZ 0x01 << 1 +#define XYZW 0x02 << 1 +#define XY 0x03 << 1 +#define XYW 0x04 << 1 + +/* Antialiasing */ +#define AA_UPDATE_EDGEFLAG (1<<13) +#define AA_ENABLE_EDGEFLAG (1<<12) +#define AA_UPDATE_POLYWIDTH (1<<11) +#define AA_POLYWIDTH_05 (1<<9) +#define AA_POLYWIDTH_10 (2<<9) +#define AA_POLYWIDTH_20 (3<<9) +#define AA_POLYWIDTH_40 (4<<9) +#define AA_UPDATE_LINEWIDTH (1<<8) +#define AA_LINEWIDTH_05 (1<<6) +#define AA_LINEWIDTH_10 (2<<6) +#define AA_LINEWIDTH_20 (3<<6) +#define AA_LINEWIDTH_40 (4<<6) +#define AA_UPDATE_BB_EXPANSION (1<<5) +#define AA_BB_EXPANSION_SHIFT 2 +#define AA_UPDATE_AA_ENABLE (1<<1) +#define AA_ENABLE (1<<0) + +/* Pixelization Rule */ +#define PVK_SMALL_TRI_UPDATE 1 << 12 +#define PVK_SMALL_TRI 1 << 11 +#define PVK_PIX_RULE_UPDATE 1 << 10 +#define PVK_PIX_RULE 1 << 9 +#define PVK_LINE_UPDATE 1 << 8 +#define PVK_LINE_V0 0 +#define PVK_LINE_V1 1 << 6 +#define PVK_TRIFAN_UPDATE 1 << 5 +#define PVK_TRIFAN_V0 0 +#define PVK_TRIFAN_V1 1 << 3 +#define PVK_TRIFAN_V2 2 << 3 +#define PVK_TRISTRIP_UPDATE 1 << 2 +#define PVK_TRISTRIP_V0 0 +#define PVK_TRISTRIP_V1 1 +#define PVK_TRISTRIP_V2 2 + +/* Boolean Enable 1 */ +#define B1_ALPHA_SETUP_ENABLE_UPDATE 1 << 17 +#define B1_ALPHA_SETUP_ENABLE 1 << 16 +#define B1_FOG_ENABLE_UPDATE 1 << 7 +#define B1_FOG_ENABLE 1 << 6 +#define B1_ALPHA_STATE_ENABLE_UPDATE 1 << 5 +#define B1_ALPHA_STATE_ENABLE 1 << 4 +#define B1_BLEND_ENABLE_UPDATE 1 << 3 +#define B1_BLEND_ENABLE 1 << 2 +#define B1_Z_ENABLE_UPDATE 1 << 1 +#define B1_Z_ENABLE 1 + +/* Boolean Enable 2 */ +#define B2_MCE_UPDATE 1 << 17 +#define B2_MCE 1 << 16 +#define B2_ALPHA_DITHER_UPDATE 1 << 15 +#define B2_ALPHA_DITHER 1 << 14 +#define B2_FOG_DITHER_UPDATE 1 << 13 +#define B2_FOG_DITHER 1 << 12 +#define B2_SPEC_DITHER_UPDATE 1 << 11 +#define B2_SPEC_DITHER 1 << 10 +#define B2_COLOR_DITHER_UPDATE 1 << 9 +#define B2_COLOR_DITHER 1 << 8 +#define B2_FB_WRITE_UPDATE 1 << 3 +#define B2_FB_WRITE 1 << 2 +#define B2_ZB_WRITE_UPDATE 1 << 1 +#define B2_ZB_WRITE 1 + +/* Cull Shade Mode */ +#define CULL_Z_UPDATE 1 << 20 +#define CULL_Z_ALWAYS 0 +#define CULL_Z_NEVER 1 << 16 +#define CULL_Z_LESS 2 << 16 +#define CULL_Z_EQUAL 3 << 16 +#define CULL_Z_LEQUAL 4 << 16 +#define CULL_Z_GREATER 5 << 16 +#define CULL_Z_NOTEQUAL 6 << 16 +#define CULL_Z_GEQUAL 7 << 16 +#define CULL_LINE_WIDTH_UPDATE 1 << 15 +#define CULL_LINE_WIDTH_MASK 7 << 12 +#define CULL_ALPHA_SHADE_UPDATE 1 << 11 +#define CULL_ALPHA_SHADE 1 << 10 +#define CULL_FOG_SHADE_UPDATE 1 << 9 +#define CULL_FOG_SHADE 1 << 8 +#define CULL_SPEC_SHADE_UPDATE 1 << 7 +#define CULL_SPEC_SHADE 1 << 6 +#define CULL_COLOR_SHADE_UPDATE 1 << 5 +#define CULL_COLOR_SHADE 1 << 4 +#define CULL_MODE_UPDATE 1 << 3 +#define CULL_NONE 1 << 2 +#define CULL_CW 2 << 2 +#define CULL_CCW 3 << 2 +#define CULL_BOTH 4 << 2 + +/* texel map */ +#define UPDATE_TEXEL1 1 << 15 +#define UPDATE_TEXEL0 1 << 7 +#define ENABLE_TEXEL1 1 << 14 +#define ENABLE_TEXEL0 1 << 6 +#define TEXEL1_COORD_IDX 1 << 11 +#define TEXEL0_COORD_IDX 1 << 3 +#define TEXEL1_MAP_IDX 1 << 8 +#define TEXEL0_MAP_IDX 1 + +/* color blend stage */ +#define COLOR_STAGE0 0 +#define COLOR_STAGE1 1 << 20 +#define COLOR_STAGE2 2 << 20 +#define UPDATE_COLOR_SELECT_MASK 1 << 19 +#define SELECT_COLOR_ACC 1 << 18 +#define SELECT_COLOR_CURRENT 0 +#define UPDATE_COLOR_ARG1 1 << 17 +#define ARG1_COLOR_FACTOR 1 << 14 +#define ARG1_COLOR_ACC 2 << 14 +#define ARG1_COLOR_ITERATED 3 << 14 +#define ARG1_COLOR_SPEC 4 << 14 +#define ARG1_COLOR_CURRENT 5 << 14 +#define ARG1_COLOR_TEXEL0 6 << 14 +#define ARG1_COLOR_TEXEL1 7 << 14 +#define ARG1_REPLICATE_ALPHA_TO_COLOR 1 << 13 +#define ARG1_COLOR_INVERT 1 << 12 +#define UPDATE_COLOR_ARG2 1 << 11 +#define ARG2_COLOR_FACTOR 1 << 8 +#define ARG2_COLOR_ACC 2 << 8 +#define ARG2_COLOR_ITERATED 3 << 8 +#define ARG2_COLOR_SPEC 4 << 8 +#define ARG2_COLOR_CURRENT 5 << 8 +#define ARG2_COLOR_TEXEL0 6 << 8 +#define ARG2_COLOR_TEXEL1 7 << 8 +#define ARG2_REPLICATE_ALPHA_TO_COLOR 1 << 7 +#define ARG2_COLORINVERT 1 << 6 +#define UPDATE_COLOR_OP 1 << 5 +#define DISABLE_COLOR_OP 0 +#define SELECT_COLOR_ARG1_OP 1 +#define SELECT_COLOR_ARG2_OP 2 +#define MODULATE_COLOR_OP 3 +#define MODULATE2X_COLOR_OP 4 +#define MODULATE4X_COLOR_OP 5 +#define ADD_COLOR_OP 6 +#define ADD_SIGNED_COLOR_OP 7 +#define LINEAR_ALPHA_ITER_OP 8 +#define LINEAR_ALPHA_FACTOR_OP 0x0a +#define LINEAR_TEXEL0_ALPHA_OP 0x10 +#define LINEAR_TEXEL1_ALPHA_OP 0x11 +#define LINEAR_TEXEL0_COLOR_OP 0x12 +#define LINEAR_TEXEL1_COLOR_OP 0x13 +#define SUBTRACT_COLOR_OP 0x14 + +/* alpha blend stage */ +#define ALPHA_STAGE0 0 +#define ALPHA_STAGE1 1 << 20 +#define ALPHA_STAGE2 2 << 20 +#define UPDATE_ALPHA_SELECT_MASK 1 << 19 +#define UPDATE_ALPHA_ARG1 1 << 18 +#define ARG1_ALPHA_FACTOR 1 << 15 +#define ARG1_ALPHA_ITERATED 3 << 15 +#define ARG1_ALPHA_CURRENT 5 << 15 +#define ARG1_ALPHA_TEXEL0 6 << 15 +#define ARG1_ALPHA_TEXEL1 7 << 15 +#define ARG1_ALPHA_INVERT 1 << 13 +#define UPDATE_ALPHA_ARG2 1 << 12 +#define ARG2_ALPHA_FACTOR 1 << 8 +#define ARG2_ALPHA_ITERATED 3 << 8 +#define ARG2_ALPHA_CURRENT 5 << 8 +#define ARG2_ALPHA_TEXEL0 6 << 8 +#define ARG2_ALPHA_TEXEL1 7 << 8 +#define ARG2_ALPHAINVERT 1 << 6 +#define UPDATE_ALPHA_OP 1 << 5 +#define DISABLE_ALPHA_OP 0 +#define SELECT_ALPHA_ARG1_OP 1 +#define SELECT_ALPHA_ARG2_OP 2 +#define MODULATE_ALPHA_OP 3 +#define MODULATE2X_ALPHA_OP 4 +#define MODULATE4X_ALPHA_OP 5 +#define ADD_ALPHA_OP 6 +#define ADD_SIGNED_ALPHA_OP 7 +#define LINEAR_ALPHA_ITER_OP 8 +#define LINEAR_ALPHA_FACTOR_OP 0x0a +#define LINEAR_TEXEL0_ALPHA_OP 0x10 +#define LINEAR_TEXEL1_ALPHA_OP 0x11 + +/* Source-Dest Blend Mono */ +#define UPDATE_MONO 1 << 13 +#define ENABLE_MONO 1 << 12 +#define DISABLE_MONO 0 +#define UPDATE_SRC_MONO_BLEND 1 << 11 +#define UPDATE_DEST_MONO_BLEND 1 << 5 + +#define SRC_ZERO 1 >>6 +#define SRC_ONE 2 << 6 +#define SRC_SRC_COLOR 3 << 6 +#define SRC_INV_SRC_COLOR 4 << 6 +#define SRC_SRC_ALPHA 5 << 6 +#define SRC_INV_SRC_ALPHA 6 << 6 +#define SRC_DST_COLOR 9 << 6 +#define SRC_INV_DST_COLOR 0x0a << 6 +#define SRC_BOTH_SRC_ALPHA 0x0c << 6 +#define SRC_BOTH_INV_SRC_ALPHA 0x0d << 6 + +#define DEST_ZERO 1 +#define DEST_ONE 2 +#define DEST_SRC_COLOR 3 +#define DEST_INV_SRC_COLOR 4 +#define DEST_SRC_ALPHA 5 +#define DEST_INV_SRC_ALPHA 6 +#define DEST_DST_COLOR 9 +#define DEST_INV_DST_COLOR 0x0a +#define DEST_BOTH_SRC_ALPHA 0x0c +#define DEST_BOTH_INV_SRC_ALPHA 0x0d + +/* Destination Render Buffer */ +#define RENDER_RGB8 0 +#define RENDER_RGB15 1 << 8 +#define RENDER_RGB16 2 << 8 +#define YUV_YSWAP 4 << 8 +#define YUV_NORMAL 5 << 8 +#define YUV_UVSWAP 6 << 8 +#define YUV_YUVSWAP 7 << 8 + +#define ORG_XBIASMASK 0x0F << 20 +#define ORG_YBIASMASK 0x0F << 16 +#define VSTRIDE 2 +#define VSTRIDE_OFFSET 1 + +/* Alpha Z-bias */ +#define UPDATE_ZBIAS 1 << 22 +#define UPDATE_ALPHA_FX 1 << 13 +#define UPDATE_ALPHA_REFERENCE 1 << 8 + +#define ALPHAFX_NEVER 1 << 9 +#define ALPHAFX_LESS 2 << 9 +#define ALPHAFX_EQUAL 3 << 9 +#define ALPHAFX_LEQUAL 4 << 9 +#define ALPHAFX_GREATER 5 << 9 +#define ALPHAFX_NOTEQUAL 6 << 9 +#define ALPHAFX_GEQUAL 7 << 9 +#define ALPHAFX_ALWAYS 8 << 9 + +/* Scissor */ +#define SCISSOR_ENABLE_UPDATE 1 << 1 +#define SCISSOR_ENABLE 1 + +/* Stipple */ +#define STIPPLE_ENABLE 1 << 16 + +/* Rendering Packets */ +/* state pipelined */ +#define COLOR_BLEND_STAGE RENDER | 0x00 << 24 +#define ALPHA_BLEND_STAGE RENDER | 0x01 << 24 +#define LINE_WIDTH_CULL_SHADE RENDER | 0x02 << 24 +#define BOOL_ENABLE_1 RENDER | 0x03 << 24 +#define BOOL_ENABLE_2 RENDER | 0x04 << 24 +#define VERTEX_FORMAT RENDER | 0x05 << 24 +#define ANTIALIAS RENDER | 0x06 << 24 +#define PVK_PIXEL_RULE RENDER | 0x07 << 24 +#define SRC_DEST_BLEND_MONO RENDER | 0x08 << 24 +#define MAP_TEXEL RENDER | 0x1C << 24 +#define PRIMITIVE RENDER | 0x1F << 24 + +/* multiple dwords */ +#define COLOR_FACTOR RENDER | 0x1D << 24 | 0x01 << 16 | 0 +#define COLOR_CHROMA_KEY RENDER | 0x1D << 24 | 0x02 << 16 | 1 +#define DRAWING_RECT_INFO RENDER | 0x1D << 24 | 0x80 << 16 | 3 +#define RENDER_BUF_DEST RENDER | 0x1D << 24 | 0x85 << 16 | 0 +#define SCISSOR_INFO RENDER | 0x1D << 24 | 0x81 << 16 | 1 +#define STIPPLE RENDER | 0x1D << 24 | 0x83 << 16 | 0 + +/* non-pipelined */ +#define ALPHA_Z_BIAS RENDER | 0x14 << 24 +#define FOG_COLOR RENDER | 0x15 << 24 +#define SCISSOR RENDER | 0x1C << 24 | 0x10 << 19 + + +#define RBUFFER_START_MASK 0xFFFFF000 +#define RBUFFER_SIZE_MASK 0x001FF000 +#define RBUFFER_HEAD_MASK 0x001FFFFC +#define RBUFFER_TAIL_MASK 0x001FFFF8 +#define RINGBUFFER_SIZE (128 * 1024) +#define RING_SIZE_MASK (RINGBUFFER_SIZE - 1) + +#define I810RES_GART 1 +#define I810RES_LRING_ACQ 2 +#define I810RES_LRING_BIND 4 +#define I810RES_OVL_ACQ 8 +#define I810RES_OVL_BIND 16 +#define I810RES_GART_ACQ 32 +#define I810RES_MMAP 64 +#define I810RES_STATE_SAVE 128 + +#ifndef AGP_NORMAL_MEMORY +#define AGP_NORMAL_MEMORY 0 +#endif + +#ifndef AGP_PHYSICAL_MEMORY +#define AGP_PHYSICAL_MEMORY 2 +#endif + +struct i810_ovl_regs { + u32 obuf_0y; + u32 obuf_1y; + u32 obuf_0u; + u32 obuf_0v; + u32 obuf_1u; + u32 obuf_1v; + u32 ov0stride; + u32 yrgb_vph; + u32 uv_vph; + u32 horz_ph; + u32 init_ph; + u32 dwinpos; + u32 dwinsz; + u32 swid; + u32 swidqw; + u32 sheight; + u32 yrgbscale; + u32 uvscale; + u32 ov0clrc0; + u32 ov0clrc1; + u32 dclrkv; + u32 dclrkm; + u32 sclrkvh; + u32 sclrkvl; + u32 sclrkm; + u32 ov0conf; + u32 ov0cmd; + u32 reserved; + u32 awinpos; + u32 awinsz; +}; + +typedef struct { + CoreLayerRegionConfig config; + int planar_bug; +} I810OverlayLayerData; + + +typedef struct { + unsigned int tail_mask; + + int size; + int head; + int tail; + int space; +} I810RingBuffer; + +typedef struct { + volatile void *virt; + unsigned int tail_mask; + unsigned int outring; +} I810RingBlock; + + +typedef struct { + bool initialized; + + I810RingBuffer lp_ring; + + bool overlayOn; + I810OverlayLayerData *iovl; + + agp_info info; + agp_allocate lring_mem; + agp_allocate ovl_mem; + agp_bind lring_bind; + agp_bind ovl_bind; + + u32 pattern; + u32 lring1; + u32 lring2; + u32 lring3; + u32 lring4; + + u32 i810fb_version; + u32 cur_tail; + int srcaddr, destaddr, srcpitch, destpitch; + int color_value, color_value3d, pixeldepth, blit_color; + int colorkey_bit, colorkey, render_color; + int clip_x1, clip_x2, clip_y1, clip_y2; + + /* state validation */ + int i_src; + int i_dst; + int i_color; + int i_colorkey; + int i_clip; + /* benchmarking */ + u32 waitfifo_sum; + u32 waitfifo_calls; + u32 idle_calls; + u32 fifo_waitcycles; + u32 idle_waitcycles; + u32 fifo_cache_hits; + u32 fifo_timeoutsum; + u32 idle_timeoutsum; +} I810DeviceData; + +typedef struct { + I810DeviceData *idev; + + volatile struct i810_ovl_regs *oregs; + + u32 flags; + int agpgart; + agp_info info; + volatile u8 *aper_base; + volatile u8 *lring_base; + volatile u8 *ovl_base; + volatile u8 *mmio_base; + volatile u8 *pattern_base; +} I810DriverData; + +extern DisplayLayerFuncs i810OverlayFuncs; + +void i810ovlOnOff( I810DriverData *idrv, + I810DeviceData *idev, + bool on ); + + +#define i810_readb(mmio_base, where) \ + *((volatile u8 *) (mmio_base + where)) \ + +#define i810_readw(mmio_base, where) \ + *((volatile u16 *) (mmio_base + where)) \ + +#define i810_readl(mmio_base, where) \ + *((volatile u32 *) (mmio_base + where)) \ + +#define i810_writeb(mmio_base, where, val) \ + *((volatile u8 *) (mmio_base + where)) = (volatile u8) val \ + +#define i810_writew(mmio_base, where, val) \ + *((volatile u16 *) (mmio_base + where)) = (volatile u16) val \ + +#define i810_writel(mmio_base, where, val) \ + *((volatile u32 *) (mmio_base + where)) = (volatile u32) val \ + +#define PUT_LRING(val) { \ + i810_writel(i810drv->lring_base, i810dev->cur_tail, val); \ + i810dev->cur_tail += 4; \ + i810dev->cur_tail &= RING_SIZE_MASK; \ +} + +#define BEGIN_LRING i810_wait_for_space + +#define END_LRING(i810drv) i810_writel(LRING, i810drv->mmio_base, i810dev->cur_tail) + +#endif /* __I810_H__ */ diff --git a/Source/DirectFB/gfxdrivers/i810/i810_overlay.c b/Source/DirectFB/gfxdrivers/i810/i810_overlay.c new file mode 100755 index 0000000..ccb0ffc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i810/i810_overlay.c @@ -0,0 +1,598 @@ +/* + i810_overlay.c -- Video Overlay Support (based partly from + XFree86 i810_video.c) + + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include "i810.h" + + +/* + * OV0CMD - Overlay Command Register + */ +#define VERTICAL_CHROMINANCE_FILTER 0x70000000 +#define VC_SCALING_OFF 0x00000000 +#define VC_LINE_REPLICATION 0x10000000 +#define VC_UP_INTERPOLATION 0x20000000 +#define VC_PIXEL_DROPPING 0x50000000 +#define VC_DOWN_INTERPOLATION 0x60000000 +#define VERTICAL_LUMINANCE_FILTER 0x0E000000 +#define VL_SCALING_OFF 0x00000000 +#define VL_LINE_REPLICATION 0x02000000 +#define VL_UP_INTERPOLATION 0x04000000 +#define VL_PIXEL_DROPPING 0x0A000000 +#define VL_DOWN_INTERPOLATION 0x0C000000 +#define HORIZONTAL_CHROMINANCE_FILTER 0x01C00000 +#define HC_SCALING_OFF 0x00000000 +#define HC_LINE_REPLICATION 0x00400000 +#define HC_UP_INTERPOLATION 0x00800000 +#define HC_PIXEL_DROPPING 0x01400000 +#define HC_DOWN_INTERPOLATION 0x01800000 +#define HORIZONTAL_LUMINANCE_FILTER 0x00380000 +#define HL_SCALING_OFF 0x00000000 +#define HL_LINE_REPLICATION 0x00080000 +#define HL_UP_INTERPOLATION 0x00100000 +#define HL_PIXEL_DROPPING 0x00280000 +#define HL_DOWN_INTERPOLATION 0x00300000 + +#define Y_ADJUST 0x00010000 +#define OV_BYTE_ORDER 0x0000C000 +#define UV_SWAP 0x00004000 +#define Y_SWAP 0x00008000 +#define Y_AND_UV_SWAP 0x0000C000 +#define SOURCE_FORMAT 0x00003C00 +#define RGB_555 0x00000800 +#define RGB_565 0x00000C00 +#define YUV_422 0x00002000 +#define YUV_411 0x00002400 +#define YUV_420 0x00003000 +#define YUV_410 0x00003800 +#define FIELD_MODE 0x00000020 +#define FRAME_MODE 0x00000000 +#define BUFFER_AND_FIELD 0x00000006 +#define BUFFER0_FIELD0 0x00000000 +#define BUFFER1_FIELD0 0x00000004 +#define OVERLAY_ENABLE 0x00000001 + +#define UV_VERT_BUF1 0x02 +#define UV_VERT_BUF0 0x04 + +#define SRC_CONSTANT_ALPHA_BLEND 1 << 31 +#define MINUV_SCALE 0x1 + +#define I810FB_IOC_UPDATEOVERLAY _IOW ('F', 0xF7, struct i810_ovl_regs) +#define I810FB_IOC_UPDATEOVERLAYCMD _IOW ('F', 0xF6, int) + +extern u32 i810_wait_for_space(I810DriverData *i810drv, + I810DeviceData *i810dev, + u32 space ); + +#define I810_OVERLAY_SUPPORTED_OPTIONS (DLOP_DST_COLORKEY | DLOP_DEINTERLACING) + +static void ovl_calc_regs (I810DriverData *i810drv, + I810OverlayLayerData *i810ovl, + CoreLayer *layer, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ); + +static void update_overlay(I810DriverData *i810drv, + I810DeviceData *i810dev) +{ + i810_writel(i810drv->mmio_base, OV0ADDR, i810dev->ovl_mem.physical); +} + +void +i810ovlOnOff( I810DriverData *idrv, + I810DeviceData *idev, + bool on ) +{ + if (on) + idrv->oregs->ov0cmd |= 1; + else + idrv->oregs->ov0cmd &= ~1; + + update_overlay( idrv, idev ); +} + +static int +ovlLayerDataSize( void ) +{ + return sizeof(I810OverlayLayerData); +} + +static DFBResult +ovlInitLayer( + CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + I810OverlayLayerData *i810ovl = (I810OverlayLayerData *) layer_data; + I810DriverData *idrv = driver_data; + I810DeviceData *idev = idrv->idev; + + idev->iovl = i810ovl; + + idrv->oregs = (volatile struct i810_ovl_regs*) idrv->ovl_base; + + memset( (void*) idrv->oregs, 0, sizeof(struct i810_ovl_regs) ); + + /* set_capabilities */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | DLCAPS_SATURATION | + DLCAPS_DST_COLORKEY | DLCAPS_OPACITY | DLCAPS_DEINTERLACING; + + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Intel 810/815 Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + + idrv->oregs->yrgb_vph = 0; + idrv->oregs->uv_vph = 0; + idrv->oregs->horz_ph = 0; + idrv->oregs->init_ph = 0; + idrv->oregs->dwinpos = 0; + idrv->oregs->dwinsz = (640 << 16) | 480; + idrv->oregs->swid = 640 | (640 << 15); + idrv->oregs->swidqw = (640 >> 3) | (640 << 12); + idrv->oregs->sheight = 480 | (480 << 15); + idrv->oregs->yrgbscale = 0x80004000; /* scale factor 1 */ + idrv->oregs->uvscale = 0x80004000; /* scale factor 1 */ + idrv->oregs->ov0clrc0 = 0x4000; /* brightness: 0 contrast: 1.0 */ + idrv->oregs->ov0clrc1 = 0x80; /* saturation: bypass */ + + idrv->oregs->sclrkvh = 0; + idrv->oregs->sclrkvl = 0; + idrv->oregs->sclrkm = 0; /* source color key disable */ + idrv->oregs->ov0conf = 0; /* two 720 pixel line buffers */ + + idrv->oregs->ov0cmd = VC_UP_INTERPOLATION | HC_UP_INTERPOLATION | Y_ADJUST | YUV_420; + + update_overlay( idrv, idev ); + + /* + * FIXME: If the fence registers are enabled, then the buffer pointers + * require specific alignment. This is a problem with planar formats + * which have separate pointers for each of the U and V planes. Packed + * formats should not be a problem. + */ + i810ovl->planar_bug = 0; + if (i810_readl(idrv->mmio_base, FENCE) & 1) + i810ovl->planar_bug = 1; + + return DFB_OK; +} + +static DFBResult +ovlTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + DFBDisplayLayerConfigFlags fail = 0; + I810OverlayLayerData *i810ovl = (I810OverlayLayerData *) layer_data; + + if (config->options & ~I810_OVERLAY_SUPPORTED_OPTIONS) + fail |= DLCONF_OPTIONS; + + switch (config->format) { + case DSPF_I420: + case DSPF_YV12: + case DSPF_YUY2: + case DSPF_UYVY: + break; + default: + fail |= DLCONF_PIXELFORMAT; + } + if (i810ovl->planar_bug && (config->format == DSPF_I420 || + config->format == DSPF_YV12 )) { + D_DEBUG("Sorry, planar formats will not work when memory tiling " + "is enabled\n"); + fail |= DLCONF_PIXELFORMAT; + } + + if (config->width > 1440 || config->width < 1) + fail |= DLCONF_WIDTH; + + if (config->height > 1023 || config->height < 1) + fail |= DLCONF_HEIGHT; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ovlSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock) +{ + I810DriverData *i810drv = (I810DriverData *) driver_data; + I810OverlayLayerData *i810ovl = (I810OverlayLayerData *) layer_data; + + i810ovl->config = *config; + + ovl_calc_regs (i810drv, i810ovl, layer, surface, config, lock); + update_overlay(i810drv, i810drv->idev); + + i810ovlOnOff(i810drv, i810drv->idev, 1); + + return DFB_OK; +} + +static DFBResult +ovlRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + I810DriverData *i810drv = (I810DriverData *) driver_data; + + /* disable overlay */ + i810ovlOnOff( i810drv, i810drv->idev, 0 ); + + return DFB_OK; +} + +static DFBResult +ovlFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + I810DriverData *i810drv = (I810DriverData *) driver_data; + I810OverlayLayerData *i810ovl = (I810OverlayLayerData *) layer_data; + u32 current_buffer; + + dfb_surface_flip( surface, false ); + + /* select buffer */ + current_buffer = (i810drv->oregs->ov0cmd & 4) >> 2; + + if (current_buffer) { + i810drv->oregs->ov0cmd &= ~4; + } + else { + i810drv->oregs->ov0cmd |= 4; + } + + ovl_calc_regs (i810drv, i810ovl, layer, surface, &i810ovl->config, lock); + update_overlay(i810drv, i810drv->idev); + + if (flags & DSFLIP_WAIT) + dfb_screen_wait_vsync( dfb_screens_at( DSCID_PRIMARY ) ); + + return DFB_OK; +} + +static DFBResult +ovlSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + I810DriverData *i810drv = (I810DriverData*) driver_data; + + i810drv->oregs->ov0clrc0 = (((adj->brightness >> 8) - 128) & 0xFF) | + ((adj->contrast >> 9) << 8); + i810drv->oregs->ov0clrc1 = (adj->saturation >> 8) & 0xFF; + + update_overlay(i810drv, i810drv->idev); + return DFB_OK; +} + +static DFBResult +ovlSetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + I810DriverData *i810drv = (I810DriverData*) driver_data; + + i810drv->oregs->ov0cmd &= ~2; + i810drv->oregs->ov0cmd |= (field) ? 2 : 0; + + update_overlay(i810drv, i810drv->idev); + return DFB_OK; +} + +DisplayLayerFuncs i810OverlayFuncs = { + .LayerDataSize = ovlLayerDataSize, + .InitLayer = ovlInitLayer, + .TestRegion = ovlTestRegion, + .SetRegion = ovlSetRegion, + .RemoveRegion = ovlRemoveRegion, + .FlipRegion = ovlFlipRegion, + .SetColorAdjustment = ovlSetColorAdjustment, + .SetInputField = ovlSetInputField, +}; + + +static void ovl_calc_regs (I810DriverData *i810drv, + I810OverlayLayerData *i810ovl, + CoreLayer *layer, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ) +{ + u32 swidth = 0, y_offset, v_offset = 0, u_offset = 0; + u32 drw_w, src_w, drw_h, src_h, xscaleInt, xscaleFract, yscaleInt; + u32 xscaleFractUV = 0, xscaleIntUV, yscaleIntUV = 0, yscaleFract, yscaleFractUV = 0; + + DFBSurfacePixelFormat primary_format; + + drw_w = config->dest.w; + drw_h = config->dest.h; + src_w = surface->config.size.w; + src_h = surface->config.size.h; + + if (config->options & DLOP_DEINTERLACING) + src_h >>= 1; + + /* reset command register except the enable bit and buffer select bits */ + i810drv->oregs->ov0cmd &= 7; + + /* Set source dimension in bytes */ + switch (surface->config.format) { + case DSPF_I420: + case DSPF_YV12: + swidth = (src_w + 7) & ~7; + i810drv->oregs->swid = (swidth << 15) | swidth; + i810drv->oregs->swidqw = (swidth << 12) | (swidth >> 3); + break; + case DSPF_UYVY: + case DSPF_YUY2: + swidth = ((src_w + 3) & ~3) << 1; + i810drv->oregs->swid = swidth; + i810drv->oregs->swidqw = swidth >> 3; + break; + default: + break; + } + i810drv->oregs->sheight = src_h | (src_h << 15); + + /* select buffer size */ + if (swidth > 720) + i810drv->oregs->ov0conf = 1; + else + i810drv->oregs->ov0conf = 0; + + /* set dest window position and dimension */ + i810drv->oregs->dwinpos = (config->dest.y << 16) | config->dest.x; + i810drv->oregs->dwinsz = (drw_h << 16) | drw_w; + + /* Set buffer pointers */ + y_offset = (dfb_gfxcard_memory_physical(NULL, lock->offset)); + + switch (surface->config.format) { + case DSPF_I420: + u_offset = y_offset + surface->config.size.h * lock->pitch; + v_offset = u_offset + ((surface->config.size.h >> 1) * (lock->pitch >> 1)); + break; + case DSPF_YV12: + v_offset = y_offset + surface->config.size.h * lock->pitch; + u_offset = v_offset + ((surface->config.size.h >> 1) * (lock->pitch >> 1)); + break; + default: + break; + } + + if (i810drv->oregs->ov0cmd & 4) { + i810drv->oregs->obuf_1y = y_offset; + i810drv->oregs->obuf_1v = v_offset; + i810drv->oregs->obuf_1u = u_offset; + } + else { + i810drv->oregs->obuf_0y = y_offset; + i810drv->oregs->obuf_0v = v_offset; + i810drv->oregs->obuf_0u = u_offset; + } + + /* set scaling */ + i810drv->oregs->yrgbscale = 0x80004000; + i810drv->oregs->uvscale = 0x80004000; + + i810drv->oregs->ov0cmd |= VC_UP_INTERPOLATION | HC_UP_INTERPOLATION | Y_ADJUST | FRAME_MODE; + + if (config->options & DLOP_DEINTERLACING) + i810drv->oregs->ov0cmd |= FIELD_MODE; + + if ((drw_w != src_w) || (drw_h != src_h)) + { + xscaleInt = (src_w / drw_w) & 0x3; + xscaleFract = (src_w << 12) / drw_w; + yscaleInt = (src_h / drw_h) & 0x3; + yscaleFract = (src_h << 12) / drw_h; + + i810drv->oregs->yrgbscale = (xscaleInt << 15) | + ((xscaleFract & 0xFFF) << 3) | + (yscaleInt) | + ((yscaleFract & 0xFFF) << 20); + + if (drw_w > src_w) + { + i810drv->oregs->ov0cmd &= ~HORIZONTAL_CHROMINANCE_FILTER; + i810drv->oregs->ov0cmd &= ~HORIZONTAL_LUMINANCE_FILTER; + i810drv->oregs->ov0cmd |= (HC_UP_INTERPOLATION | HL_UP_INTERPOLATION); + } + + if (drw_h > src_h) + { + i810drv->oregs->ov0cmd &= ~VERTICAL_CHROMINANCE_FILTER; + i810drv->oregs->ov0cmd &= ~VERTICAL_LUMINANCE_FILTER; + i810drv->oregs->ov0cmd |= (VC_UP_INTERPOLATION | VL_UP_INTERPOLATION); + } + + if (drw_w < src_w) + { + i810drv->oregs->ov0cmd &= ~HORIZONTAL_CHROMINANCE_FILTER; + i810drv->oregs->ov0cmd &= ~HORIZONTAL_LUMINANCE_FILTER; + i810drv->oregs->ov0cmd |= (HC_DOWN_INTERPOLATION | HL_DOWN_INTERPOLATION); + } + + if (drw_h < src_h) + { + i810drv->oregs->ov0cmd &= ~VERTICAL_CHROMINANCE_FILTER; + i810drv->oregs->ov0cmd &= ~VERTICAL_LUMINANCE_FILTER; + i810drv->oregs->ov0cmd |= (VC_DOWN_INTERPOLATION | VL_DOWN_INTERPOLATION); + } + + if (xscaleFract) + { + xscaleFractUV = xscaleFract >> MINUV_SCALE; + i810drv->oregs->ov0cmd &= ~HC_DOWN_INTERPOLATION; + i810drv->oregs->ov0cmd |= HC_UP_INTERPOLATION; + } + + if (xscaleInt) + { + xscaleIntUV = xscaleInt >> MINUV_SCALE; + if (xscaleIntUV) + { + i810drv->oregs->ov0cmd &= ~HC_UP_INTERPOLATION; + } + } + + if (yscaleFract) + { + yscaleFractUV = yscaleFract >> MINUV_SCALE; + i810drv->oregs->ov0cmd &= ~VC_DOWN_INTERPOLATION; + i810drv->oregs->ov0cmd |= VC_UP_INTERPOLATION; + } + + if (yscaleInt) + { + yscaleIntUV = yscaleInt >> MINUV_SCALE; + if (yscaleIntUV) + { + i810drv->oregs->ov0cmd &= ~VC_UP_INTERPOLATION; + i810drv->oregs->ov0cmd |= VC_DOWN_INTERPOLATION; + } + } + + i810drv->oregs->uvscale = yscaleIntUV | ((xscaleFractUV & 0xFFF) << 3) | + ((yscaleFractUV & 0xFFF) << 20); + } + + switch(surface->config.format) { + case DSPF_YV12: + case DSPF_I420: + /* set UV vertical phase to -0.25 */ + i810drv->oregs->uv_vph = 0x30003000; + i810drv->oregs->init_ph = UV_VERT_BUF0 | UV_VERT_BUF1; + i810drv->oregs->ov0stride = (lock->pitch) | (lock->pitch << 15); + i810drv->oregs->ov0cmd &= ~SOURCE_FORMAT; + i810drv->oregs->ov0cmd |= YUV_420; + break; + case DSPF_UYVY: + case DSPF_YUY2: + i810drv->oregs->uv_vph = 0; + i810drv->oregs->init_ph = 0; + i810drv->oregs->ov0stride = lock->pitch; + i810drv->oregs->ov0cmd &= ~SOURCE_FORMAT; + i810drv->oregs->ov0cmd |= YUV_422; + i810drv->oregs->ov0cmd &= ~OV_BYTE_ORDER; + if (surface->config.format == DSPF_UYVY) + i810drv->oregs->ov0cmd |= Y_SWAP; + break; + default: + D_BUG("unexpected pixelformat"); + break; + } + + /* Set alpha window */ + i810drv->oregs->awinpos = i810drv->oregs->dwinpos; + i810drv->oregs->awinsz = i810drv->oregs->dwinsz; + + + /* + * Destination color keying. + */ + + primary_format = dfb_primary_layer_pixelformat(); + + i810drv->oregs->dclrkv = dfb_color_to_pixel( primary_format, + config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + + i810drv->oregs->dclrkm = (1 << DFB_COLOR_BITS_PER_PIXEL( primary_format )) - 1; + + if (config->options & DLOP_DST_COLORKEY) + i810drv->oregs->dclrkm |= 0x80000000; +} diff --git a/Source/DirectFB/gfxdrivers/i830/Makefile.am b/Source/DirectFB/gfxdrivers/i830/Makefile.am new file mode 100755 index 0000000..115f671 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i830/Makefile.am @@ -0,0 +1,35 @@ +## Makefile.am for DirectFB/src/core/gfxcards/i830 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +i830_LTLIBRARIES = libdirectfb_i830.la + +if BUILD_STATIC +i830_DATA = $(i830_LTLIBRARIES:.la=.o) +endif + +i830dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_i830_la_SOURCES = \ + i830.c \ + i830.h \ + i830_overlay.c + +libdirectfb_i830_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_i830_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/i830/Makefile.in b/Source/DirectFB/gfxdrivers/i830/Makefile.in new file mode 100755 index 0000000..926c125 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i830/Makefile.in @@ -0,0 +1,597 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/i830 +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(i830dir)" "$(DESTDIR)$(i830dir)" +i830LTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(i830_LTLIBRARIES) +libdirectfb_i830_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_i830_la_OBJECTS = i830.lo i830_overlay.lo +libdirectfb_i830_la_OBJECTS = $(am_libdirectfb_i830_la_OBJECTS) +libdirectfb_i830_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_i830_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_i830_la_SOURCES) +DIST_SOURCES = $(libdirectfb_i830_la_SOURCES) +i830DATA_INSTALL = $(INSTALL_DATA) +DATA = $(i830_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +i830_LTLIBRARIES = libdirectfb_i830.la +@BUILD_STATIC_TRUE@i830_DATA = $(i830_LTLIBRARIES:.la=.o) +i830dir = $(MODULEDIR)/gfxdrivers +libdirectfb_i830_la_SOURCES = \ + i830.c \ + i830.h \ + i830_overlay.c + +libdirectfb_i830_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_i830_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: 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'$(DESTDIR)$(i830dir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(i830dir)/$$p"; \ + done + +clean-i830LTLIBRARIES: + -test -z "$(i830_LTLIBRARIES)" || rm -f $(i830_LTLIBRARIES) + @list='$(i830_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libdirectfb_i830.la: $(libdirectfb_i830_la_OBJECTS) $(libdirectfb_i830_la_DEPENDENCIES) + $(libdirectfb_i830_la_LINK) -rpath $(i830dir) $(libdirectfb_i830_la_OBJECTS) $(libdirectfb_i830_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i830_overlay.Plo@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< +@am__fastdepCC_TRUE@ mv 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"$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-am + +clean-am: clean-generic clean-i830LTLIBRARIES clean-libtool \ + mostlyclean-am + +distclean: distclean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-tags + +dvi: dvi-am + +dvi-am: + +html: html-am + +info: info-am + +info-am: + +install-data-am: install-i830DATA install-i830LTLIBRARIES + +install-dvi: install-dvi-am + +install-exec-am: + +install-html: install-html-am + +install-info: install-info-am + +install-man: + +install-pdf: install-pdf-am + +install-ps: install-ps-am + +installcheck-am: + +maintainer-clean: maintainer-clean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-i830DATA uninstall-i830LTLIBRARIES + +.MAKE: install-am install-strip + +.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ + clean-i830LTLIBRARIES clean-libtool ctags distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-tags distdir dvi dvi-am html html-am info info-am \ + install install-am install-data install-data-am install-dvi \ + install-dvi-am install-exec install-exec-am install-html \ + install-html-am install-i830DATA install-i830LTLIBRARIES \ + install-info install-info-am install-man install-pdf \ + install-pdf-am install-ps install-ps-am install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-i830DATA \ + uninstall-i830LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/i830/i830.c b/Source/DirectFB/gfxdrivers/i830/i830.c new file mode 100755 index 0000000..895b16d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i830/i830.c @@ -0,0 +1,635 @@ +/* + Intel i830 DirectFB graphics driver + + (c) Copyright 2005 Servision Ltd. + http://www.servision.net/ + + All rights reserved. + + Based on i810 driver written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include "i830.h" + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +/* need fb handle to get accel, MMIO programming in the i830 is useless */ +#include +#include +#include +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( i830 ) + + +/**************************************************************************************************/ + +#define TIMER_LOOP 1000000000 +#define BUFFER_PADDING 2 +#define MMIO_SIZE 512 * 1024 + +#define I830_SUPPORTED_DRAWINGFLAGS (DSDRAW_NOFX) + +#define I830_SUPPORTED_DRAWINGFUNCTIONS (DFXL_NONE) + +#define I830_SUPPORTED_BLITTINGFLAGS (DSBLIT_NOFX) + +#define I830_SUPPORTED_BLITTINGFUNCTIONS (DFXL_NONE) + +/**************************************************************************************************/ + +static void +i830_lring_enable( I830DriverData *idrv, u32 mode ) +{ + u32 tmp; + + D_DEBUG_AT( I830_Ring, "%s lp ring...\n", mode ? "Enabling" : "Disabling" ); + + tmp = i830_readl(idrv->mmio_base, LP_RING + RING_LEN); + tmp = (!mode) ? tmp & ~1 : tmp | 1; + + i830_writel( idrv->mmio_base, LP_RING + RING_LEN, tmp ); +} + + +static inline void +i830_wait_for_blit_idle( I830DriverData *idrv, + I830DeviceData *idev ) +{ + u32 count = 0; + u32 head , tail; + + if (idev != NULL) + idev->idle_calls++; + + head = i830_readl(idrv->mmio_base, LP_RING + RING_HEAD) & I830_HEAD_MASK; + tail = i830_readl(idrv->mmio_base, LP_RING + RING_TAIL) & I830_TAIL_MASK; + while ((head != tail) && (count++ < TIMER_LOOP)) { + if (idev != NULL) + idev->idle_waitcycles++; + head = i830_readl(idrv->mmio_base, LP_RING + RING_HEAD) & I830_HEAD_MASK; + tail = i830_readl(idrv->mmio_base, LP_RING + RING_TAIL) & I830_TAIL_MASK; + } + + if (count >= TIMER_LOOP) { + if (idev != NULL) + idev->idle_timeoutsum++; + D_BUG("warning: idle timeout exceeded"); + } +} + +static void +i830_init_ringbuffer( I830DriverData *idrv, + I830DeviceData *idev ) +{ + u32 ring_enabled; + + D_DEBUG_AT( I830_Ring, "Previous lp ring config: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + i830_readl(idrv->mmio_base, LP_RING), + i830_readl(idrv->mmio_base, LP_RING + RING_HEAD), + i830_readl(idrv->mmio_base, LP_RING + RING_START), + i830_readl(idrv->mmio_base, LP_RING + RING_LEN) ); + + ring_enabled = i830_readl(idrv->mmio_base, LP_RING + RING_LEN) & 1; + if (ring_enabled) + i830_wait_for_blit_idle(idrv, idev); + i830_lring_enable(idrv, 0); + + idev->lring1 = i830_readl(idrv->mmio_base, LP_RING); + idev->lring2 = i830_readl(idrv->mmio_base, LP_RING + RING_HEAD); + idev->lring3 = i830_readl(idrv->mmio_base, LP_RING + RING_START); + idev->lring4 = i830_readl(idrv->mmio_base, LP_RING + RING_LEN); + + D_FLAGS_SET( idrv->flags, I830RES_STATE_SAVE ); + + i830_writel(idrv->mmio_base, LP_RING + RING_LEN, 0); + i830_writel(idrv->mmio_base, LP_RING + RING_HEAD, 0); + i830_writel(idrv->mmio_base, LP_RING + RING_TAIL, 0); + i830_writel(idrv->mmio_base, LP_RING + RING_START, 0); + + D_DEBUG_AT( I830_Ring, "INST_DONE: 0x%04x\n", i830_readw(idrv->mmio_base, INST_DONE) ); + + + idev->lp_ring.size = RINGBUFFER_SIZE; + idev->lp_ring.tail_mask = idev->lp_ring.size - 1; + + i830_writel( idrv->mmio_base, LP_RING + RING_START, + (idev->lring_bind.pg_start * 4096) & I830_RING_START_MASK ); + + i830_writel( idrv->mmio_base, LP_RING + RING_LEN, + (idev->lp_ring.size - 4096) & I830_RING_NR_PAGES ); + + i830_lring_enable(idrv, 1); + + D_DEBUG_AT( I830_Ring, "Wrote lp ring config: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", + i830_readl(idrv->mmio_base, LP_RING), + i830_readl(idrv->mmio_base, LP_RING + RING_HEAD), + i830_readl(idrv->mmio_base, LP_RING + RING_START), + i830_readl(idrv->mmio_base, LP_RING + RING_LEN) ); +} + +DFBResult +i830_wait_lp_ring( I830DriverData *idrv, + I830DeviceData *idev, + int space ) +{ + I830RingBuffer *buf = &idev->lp_ring; + + idev->waitfifo_calls++; + idev->waitfifo_sum += space; + + D_DEBUG_AT( I830_Ring, "Waiting for %d...\n", space ); + + if (buf->space < space) { + int head = 0; + int loops = 0; + + do { + idev->fifo_waitcycles++; + + if (loops++ > 100000000) { + D_ERROR( "timeout waiting for ring buffer space\n" ); + return DFB_TIMEOUT; + } + + buf->head = i830_readl( idrv->mmio_base, + LP_RING + RING_HEAD ) & I830_HEAD_MASK; + buf->space = buf->head - (buf->tail + 8); + + if (buf->space < 0) + buf->space += buf->size; + + //D_DEBUG_AT( I830_Ring, "... have %d space\n", buf->space ); + + if (buf->head != head) + loops = 0; + + head = buf->head; + } while (buf->space < space); + } + else + idev->fifo_cache_hits++; + + return DFB_OK; +} + +/**************************************************************************************************/ + +static void +i830FlushTextureCache( void *drv, void *dev ) +{ + I830DriverData *idrv = drv; + I830DeviceData *idev = dev; + I830RingBlock block = { .virt = NULL }; + + if (i830_begin_lp_ring( idrv, idev, 2, &block )) + return; + + i830_out_ring( &block, MI_FLUSH ); + i830_out_ring( &block, MI_NOOP ); + + i830_advance_lp_ring( idrv, idev, &block ); +} + +static DFBResult +i830EngineSync( void *drv, void *dev ) +{ + I830DriverData *idrv = drv; + I830DeviceData *idev = dev; + + i830_wait_for_blit_idle( idrv, idev ); + + return DFB_OK; +} + +/**************************************************************************************************/ + +static void +i830CheckState(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + default: + return; + } + + if (!(accel & ~I830_SUPPORTED_DRAWINGFUNCTIONS) && + !(state->drawingflags & ~I830_SUPPORTED_DRAWINGFLAGS)) + state->accel |= I830_SUPPORTED_DRAWINGFUNCTIONS; + + if (!(accel & ~I830_SUPPORTED_BLITTINGFUNCTIONS) && + !(state->blittingflags & ~I830_SUPPORTED_BLITTINGFLAGS)) { + if (state->source->config.format == state->destination->config.format) + state->accel |= I830_SUPPORTED_BLITTINGFUNCTIONS; + } +} + +static void +i830SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + switch (accel) { + default: + D_BUG("unexpected drawing/blitting function"); + } + + state->mod_hw = 0; +} + +/**************************************************************************************************/ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_I830: /* Intel 830 */ + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Intel 830/845G/852GM/855GM/865G Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Denis Oliver Kropp" ); + + info->version.major = 0; + info->version.minor = 1; + + info->driver_data_size = sizeof (I830DriverData); + info->device_data_size = sizeof (I830DeviceData); +} + +static void +i830_release_resource( I830DriverData *idrv, I830DeviceData *idev ) +{ + agp_unbind unbind; + + if (idrv->flags & I830RES_STATE_SAVE) { + i830_writel( idrv->mmio_base, LP_RING, idev->lring1 ); + i830_writel( idrv->mmio_base, LP_RING + RING_HEAD, idev->lring2 ); + i830_writel( idrv->mmio_base, LP_RING + RING_START, idev->lring3 ); + i830_writel( idrv->mmio_base, LP_RING + RING_LEN, idev->lring4 ); + } + + if (idrv->flags & I830RES_MMAP) { + munmap((void *) idrv->aper_base, idev->info.aper_size * 1024 * 1024); + idrv->flags &= ~I830RES_MMAP; + } + + if (idrv->flags & I830RES_LRING_BIND) { + unbind.key = idev->lring_bind.key; + ioctl(idrv->agpgart, AGPIOC_UNBIND, &unbind); + } + + if (idrv->flags & I830RES_LRING_ACQ) + ioctl(idrv->agpgart, AGPIOC_DEALLOCATE, idev->lring_mem.key); + + if (idrv->flags & I830RES_OVL_BIND) { + unbind.key = idev->ovl_bind.key; + ioctl(idrv->agpgart, AGPIOC_UNBIND, &unbind); + } + + if (idrv->flags & I830RES_OVL_ACQ) + ioctl(idrv->agpgart, AGPIOC_DEALLOCATE, idev->ovl_mem.key); + + if (idrv->flags & I830RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I830RES_GART_ACQ; + } + + if (idrv->flags & I830RES_GART) { + close(idrv->agpgart); + idrv->flags &= ~I830RES_GART; + } +} + +static DFBResult +i830_agp_setup( CoreGraphicsDevice *device, + I830DriverData *idrv, + I830DeviceData *idev ) +{ + idrv->agpgart = open("/dev/agpgart", O_RDWR); + if (idrv->agpgart == -1) + return DFB_IO; + D_FLAGS_SET( idrv->flags, I830RES_GART ); + + + if (ioctl(idrv->agpgart, AGPIOC_ACQUIRE)) { + D_PERROR( "I830/AGP: AGPIOC_ACQUIRE failed!\n" ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_GART_ACQ ); + + + if (!idev->initialized) { + agp_setup setup; + + setup.agp_mode = 0; + if (ioctl(idrv->agpgart, AGPIOC_SETUP, &setup)) { + D_PERROR( "I830/AGP: AGPIOC_SETUP failed!\n" ); + return DFB_IO; + } + + if (ioctl(idrv->agpgart, AGPIOC_INFO, &idev->info)) { + D_PERROR( "I830/AGP: AGPIOC_INFO failed!\n" ); + return DFB_IO; + } + } + + + idrv->aper_base = mmap( NULL, idev->info.aper_size * 1024 * 1024, PROT_WRITE, + MAP_SHARED, idrv->agpgart, 0 ); + if (idrv->aper_base == MAP_FAILED) { + D_PERROR( "I830/AGP: mmap() failed!\n" ); + i830_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_MMAP ); + + + if (!idev->initialized) { + u32 base; + + /* We'll attempt to bind at fb_base + fb_len + 1 MB, + to be safe */ + base = dfb_gfxcard_memory_physical(device, 0) - idev->info.aper_base; + base += dfb_gfxcard_memory_length(); + base += (1024 * 1024); + + idev->lring_mem.pg_count = RINGBUFFER_SIZE/4096; + idev->lring_mem.type = AGP_NORMAL_MEMORY; + if (ioctl(idrv->agpgart, AGPIOC_ALLOCATE, &idev->lring_mem)) { + D_PERROR( "I830/AGP: AGPIOC_ALLOCATE failed!\n" ); + i830_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_LRING_ACQ ); + + idev->lring_bind.key = idev->lring_mem.key; + idev->lring_bind.pg_start = base/4096; + if (ioctl(idrv->agpgart, AGPIOC_BIND, &idev->lring_bind)) { + D_PERROR( "I830/AGP: AGPIOC_BIND failed!\n" ); + i830_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_LRING_BIND ); + + idev->ovl_mem.pg_count = 1; + idev->ovl_mem.type = AGP_PHYSICAL_MEMORY; + if (ioctl(idrv->agpgart, AGPIOC_ALLOCATE, &idev->ovl_mem)) { + D_PERROR( "I830/AGP: AGPIOC_ALLOCATE failed!\n" ); + i830_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_OVL_ACQ ); + + idev->ovl_bind.key = idev->ovl_mem.key; + idev->ovl_bind.pg_start = (base + RINGBUFFER_SIZE)/4096; + if (ioctl(idrv->agpgart, AGPIOC_BIND, &idev->ovl_bind)) { + D_PERROR( "I830/AGP: AGPIOC_BIND failed!\n" ); + i830_release_resource( idrv, idev ); + return DFB_IO; + } + D_FLAGS_SET( idrv->flags, I830RES_OVL_BIND ); + } + + + if (idrv->flags & I830RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I830RES_GART_ACQ; + } + + + idrv->lring_base = idrv->aper_base + idev->lring_bind.pg_start * 4096; + idrv->ovl_base = idrv->aper_base + idev->ovl_bind.pg_start * 4096; + idrv->pattern_base = idrv->ovl_base + 1024; + + if (!idev->initialized) { + memset((void *) idrv->lring_base, 0x00, RINGBUFFER_SIZE); + memset((void *) idrv->ovl_base, 0xff, 1024); + memset((void *) idrv->pattern_base, 0xff, 4096 - 1024); + + idev->lring1 = 0;//i830_readl(idrv->mmio_base, LP_RING); + idev->lring2 = 0;//i830_readl(idrv->mmio_base, LP_RING + RING_HEAD); + idev->lring3 = 0;//i830_readl(idrv->mmio_base, LP_RING + RING_START); + idev->lring4 = 0;//i830_readl(idrv->mmio_base, LP_RING + RING_LEN); + } + + idev->initialized = true; + + return DFB_OK; +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + DFBResult ret; + I830DriverData *idrv = driver_data; + I830DeviceData *idev = device_data; + + idrv->idev = device_data; + + idrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!idrv->mmio_base) + return DFB_IO; + + ret = i830_agp_setup( device, idrv, idev ); + if (ret) { + dfb_gfxcard_unmap_mmio( device, idrv->mmio_base, -1 ); + return ret; + } + + idrv->info = idev->info; + + funcs->CheckState = i830CheckState; + funcs->SetState = i830SetState; + funcs->EngineSync = i830EngineSync; + funcs->FlushTextureCache = i830FlushTextureCache; + + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), driver_data, &i830OverlayFuncs ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = device_data; + +// int offset; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "830/845G/852GM/855GM/865G" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Intel" ); + + device_info->caps.flags = 0; + device_info->caps.accel = I830_SUPPORTED_DRAWINGFUNCTIONS | + I830_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = I830_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = I830_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + device_info->limits.surface_bytepitch_alignment = 64; + + dfb_config->pollvsync_after = 1; + + +/* offset = dfb_gfxcard_reserve_memory( device, RINGBUFFER_SIZE ); + + idrv->lring_mem.physical = dfb_gfxcard_memory_physical( device, offset ); + idrv->lring_base = dfb_gfxcard_memory_virtual( device, offset ); + + + offset = dfb_gfxcard_reserve_memory( device, 4096 ); + + idrv->ovl_mem.physical = dfb_gfxcard_memory_physical( device, offset ); + idrv->ovl_base = dfb_gfxcard_memory_virtual( device, offset );*/ + +/* D_DEBUG_AT( I830_Ring, "lp_ring at 0x%08x (%p)\n", + idrv->lring_mem.physical, idrv->lring_base ); + + D_DEBUG_AT( I830_Ring, "ovl at 0x%08x (%p)\n", + idrv->ovl_mem.physical, idrv->ovl_base );*/ + + i830_init_ringbuffer( idrv, idev ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + I830DeviceData *idev = device_data; + I830DriverData *idrv = driver_data; + + i830ovlOnOff( idrv, idev, false ); + + i830_wait_for_blit_idle(idrv, idev); + i830_lring_enable(idrv, 0); + + i830_release_resource( idrv, idev ); + + + D_DEBUG( "DirectFB/I830: DMA Buffer Performance Monitoring:\n"); + D_DEBUG( "DirectFB/I830: %9d DMA buffer size in KB\n", + RINGBUFFER_SIZE/1024 ); + D_DEBUG( "DirectFB/I830: %9d i830_wait_for_blit_idle calls\n", + idev->idle_calls ); + D_DEBUG( "DirectFB/I830: %9d i830_wait_for_space calls\n", + idev->waitfifo_calls ); + D_DEBUG( "DirectFB/I830: %9d BUFFER transfers (i830_wait_for_space sum)\n", + idev->waitfifo_sum ); + D_DEBUG( "DirectFB/I830: %9d BUFFER wait cycles (depends on GPU/CPU)\n", + idev->fifo_waitcycles ); + D_DEBUG( "DirectFB/I830: %9d IDLE wait cycles (depends on GPU/CPU)\n", + idev->idle_waitcycles ); + D_DEBUG( "DirectFB/I830: %9d BUFFER space cache hits(depends on BUFFER size)\n", + idev->fifo_cache_hits ); + D_DEBUG( "DirectFB/I830: %9d BUFFER timeout sum (possible hardware crash)\n", + idev->fifo_timeoutsum ); + D_DEBUG( "DirectFB/I830: %9d IDLE timeout sum (possible hardware crash)\n", + idev->idle_timeoutsum ); + D_DEBUG( "DirectFB/I830: Conclusion:\n" ); + D_DEBUG( "DirectFB/I830: Average buffer transfers per i830_wait_for_space " + "call: %.2f\n", + idev->waitfifo_sum/(float)(idev->waitfifo_calls) ); + D_DEBUG( "DirectFB/I830: Average wait cycles per i830_wait_for_space call:" + " %.2f\n", + idev->fifo_waitcycles/(float)(idev->waitfifo_calls) ); + D_DEBUG( "DirectFB/I830: Average wait cycles per i830_wait_for_blit_idle call:" + " %.2f\n", + idev->idle_waitcycles/(float)(idev->idle_calls) ); + D_DEBUG( "DirectFB/I830: Average buffer space cache hits: %02d%%\n", + (int)(100 * idev->fifo_cache_hits/ + (float)(idev->waitfifo_calls)) ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + I830DriverData *idrv = (I830DriverData *) driver_data; + + dfb_gfxcard_unmap_mmio( device, idrv->mmio_base, -1 ); + + if (idrv->flags & I830RES_MMAP) { + munmap((void *) idrv->aper_base, idrv->info.aper_size * 1024 * 1024); + idrv->flags &= ~I830RES_MMAP; + } + + if (idrv->flags & I830RES_GART_ACQ) { + ioctl(idrv->agpgart, AGPIOC_RELEASE); + idrv->flags &= ~I830RES_GART_ACQ; + } + + if (idrv->flags & I830RES_GART) { + close(idrv->agpgart); + idrv->flags &= ~I830RES_GART; + } +} + diff --git a/Source/DirectFB/gfxdrivers/i830/i830.h b/Source/DirectFB/gfxdrivers/i830/i830.h new file mode 100755 index 0000000..62c8d6d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i830/i830.h @@ -0,0 +1,406 @@ +/* + Intel i830 DirectFB graphics driver + + (c) Copyright 2005 Servision Ltd. + http://www.servision.net/ + + All rights reserved. + + Based on i810 driver written by Antonino Daplas + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __I830_H__ +#define __I830_H__ + +#include + +#include +#include + +#include +#include + + +#define RINGBUFFER_SIZE (128 * 1024) + + + +/* Ring buffer registers, p277, overview p19 + */ +#define LP_RING 0x2030 +#define HP_RING 0x2040 + +#define RING_TAIL 0x00 +#define TAIL_ADDR 0x000FFFF8 +#define I830_TAIL_MASK 0x001FFFF8 + +#define RING_HEAD 0x04 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define I830_HEAD_MASK 0x001FFFFC + +#define RING_START 0x08 +#define START_ADDR 0x00FFFFF8 +#define I830_RING_START_MASK 0xFFFFF000 + +#define RING_LEN 0x0C +#define RING_NR_PAGES 0x000FF000 +#define I830_RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 + + +/* Overlay Flip */ +#define MI_OVERLAY_FLIP (0x11<<23) +#define MI_OVERLAY_FLIP_CONTINUE (0<<21) +#define MI_OVERLAY_FLIP_ON (1<<21) +#define MI_OVERLAY_FLIP_OFF (2<<21) + +/* Wait for Events */ +#define MI_WAIT_FOR_EVENT (0x03<<23) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) + +/* Flush */ +#define MI_FLUSH (0x04<<23) +#define MI_WRITE_DIRTY_STATE (1<<4) +#define MI_END_SCENE (1<<3) +#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) +#define MI_INVALIDATE_MAP_CACHE (1<<0) + +/* Noop */ +#define MI_NOOP 0x00 +#define MI_NOOP_WRITE_ID (1<<22) +#define MI_NOOP_ID_MASK (1<<22 - 1) + + +/* Instruction Parser Mode Register + * - p281 + * - 2 new bits. + */ +#define INST_PM 0x20c0 +#define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */ +#define SYNC_PACKET_FLUSH_ENABLE 0x10 +#define TWO_D_INST_DISABLE 0x08 +#define THREE_D_INST_DISABLE 0x04 +#define STATE_VAR_UPDATE_DISABLE 0x02 +#define PAL_STIP_DISABLE 0x01 + +#define INST_DONE 0x2090 +#define INST_PS 0x20c4 + +#define MEMMODE 0x20dc + + + +#define I830RES_GART 1 +#define I830RES_LRING_ACQ 2 +#define I830RES_LRING_BIND 4 +#define I830RES_OVL_ACQ 8 +#define I830RES_OVL_BIND 16 +#define I830RES_GART_ACQ 32 +#define I830RES_MMAP 64 +#define I830RES_STATE_SAVE 128 + +#ifndef AGP_NORMAL_MEMORY +#define AGP_NORMAL_MEMORY 0 +#endif + +#ifndef AGP_PHYSICAL_MEMORY +#define AGP_PHYSICAL_MEMORY 2 +#endif + + + + +/* + * OCMD - Overlay Command Register + */ +#define MIRROR_MODE (0x3<<17) +#define MIRROR_HORIZONTAL (0x1<<17) +#define MIRROR_VERTICAL (0x2<<17) +#define MIRROR_BOTH (0x3<<17) +#define OV_BYTE_ORDER (0x3<<14) +#define UV_SWAP (0x1<<14) +#define Y_SWAP (0x2<<14) +#define Y_AND_UV_SWAP (0x3<<14) +#define SOURCE_FORMAT (0xf<<10) +#define RGB_888 (0x1<<10) +#define RGB_555 (0x2<<10) +#define RGB_565 (0x3<<10) +#define YUV_422 (0x8<<10) +#define YUV_411 (0x9<<10) +#define YUV_420 (0xc<<10) +#define YUV_422_PLANAR (0xd<<10) +#define YUV_410 (0xe<<10) +#define TVSYNC_FLIP_PARITY (0x1<<9) +#define TVSYNC_FLIP_ENABLE (0x1<<7) +#define BUF_TYPE (0x1<<5) +#define BUF_TYPE_FRAME (0x0<<5) +#define BUF_TYPE_FIELD (0x1<<5) +#define TEST_MODE (0x1<<4) +#define BUFFER_SELECT (0x3<<2) +#define BUFFER0 (0x0<<2) +#define BUFFER1 (0x1<<2) +#define FIELD_SELECT (0x1<<1) +#define FIELD0 (0x0<<1) +#define FIELD1 (0x1<<1) +#define OVERLAY_ENABLE 0x1 + +/* OCONFIG register */ +#define CC_OUT_8BIT (0x1<<3) +#define OVERLAY_PIPE_MASK (0x1<<18) +#define OVERLAY_PIPE_A (0x0<<18) +#define OVERLAY_PIPE_B (0x1<<18) + +/* DCLRKM register */ +#define DEST_KEY_ENABLE (0x1<<31) + +/* Polyphase filter coefficients */ +#define N_HORIZ_Y_TAPS 5 +#define N_VERT_Y_TAPS 3 +#define N_HORIZ_UV_TAPS 3 +#define N_VERT_UV_TAPS 3 +#define N_PHASES 17 +#define MAX_TAPS 5 + +/* Filter cutoff frequency limits. */ +#define MIN_CUTOFF_FREQ 1.0 +#define MAX_CUTOFF_FREQ 3.0 + +typedef volatile struct { + u32 OBUF_0Y; + u32 OBUF_1Y; + u32 OBUF_0U; + u32 OBUF_0V; + u32 OBUF_1U; + u32 OBUF_1V; + u32 OSTRIDE; + u32 YRGB_VPH; + u32 UV_VPH; + u32 HORZ_PH; + u32 INIT_PHS; + u32 DWINPOS; + u32 DWINSZ; + u32 SWIDTH; + u32 SWIDTHSW; + u32 SHEIGHT; + u32 YRGBSCALE; + u32 UVSCALE; + u32 OCLRC0; + u32 OCLRC1; + u32 DCLRKV; + u32 DCLRKM; + u32 SCLRKVH; + u32 SCLRKVL; + u32 SCLRKEN; + u32 OCONFIG; + u32 OCMD; + u32 RESERVED1; /* 0x6C */ + u32 AWINPOS; + u32 AWINSZ; + u32 RESERVED2; /* 0x78 */ + u32 RESERVED3; /* 0x7C */ + u32 RESERVED4; /* 0x80 */ + u32 RESERVED5; /* 0x84 */ + u32 RESERVED6; /* 0x88 */ + u32 RESERVED7; /* 0x8C */ + u32 RESERVED8; /* 0x90 */ + u32 RESERVED9; /* 0x94 */ + u32 RESERVEDA; /* 0x98 */ + u32 RESERVEDB; /* 0x9C */ + u32 FASTHSCALE; /* 0xA0 */ + u32 UVSCALEV; /* 0xA4 */ + + u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ + u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ + u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; + u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ + u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; + u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ + u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; + u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ + u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; +} I830OverlayRegs; + +typedef struct { + CoreLayerRegionConfig config; +} I830OverlayLayerData; + + +typedef struct { + unsigned int tail_mask; + + int size; + int head; + int tail; + int space; +} I830RingBuffer; + +typedef struct { + volatile void *virt; + unsigned int tail_mask; + unsigned int outring; +} I830RingBlock; + + +typedef struct { + bool initialized; + + I830RingBuffer lp_ring; + + bool overlayOn; + I830OverlayLayerData *iovl; + + agp_info info; + agp_allocate lring_mem; + agp_allocate ovl_mem; + agp_bind lring_bind; + agp_bind ovl_bind; + + u32 pattern; + u32 lring1; + u32 lring2; + u32 lring3; + u32 lring4; + + /* benchmarking */ + u32 waitfifo_sum; + u32 waitfifo_calls; + u32 idle_calls; + u32 fifo_waitcycles; + u32 idle_waitcycles; + u32 fifo_cache_hits; + u32 fifo_timeoutsum; + u32 idle_timeoutsum; +} I830DeviceData; + +typedef struct { + I830DeviceData *idev; + + I830OverlayRegs *oregs; + + u32 flags; + int agpgart; + agp_info info; + volatile u8 *aper_base; + volatile u8 *lring_base; + volatile u8 *ovl_base; + volatile u8 *mmio_base; + volatile u8 *pattern_base; +} I830DriverData; + +extern DisplayLayerFuncs i830OverlayFuncs; + +void i830ovlOnOff( I830DriverData *idrv, + I830DeviceData *idev, + bool on ); + + + +#define i830_readb(mmio_base, where) \ + *((volatile u8 *) (mmio_base + where)) \ + +#define i830_readw(mmio_base, where) \ + *((volatile u16 *) (mmio_base + where)) \ + +#define i830_readl(mmio_base, where) \ + *((volatile u32 *) (mmio_base + where)) \ + +#define i830_writeb(mmio_base, where, val) \ + *((volatile u8 *) (mmio_base + where)) = (volatile u8) val \ + +#define i830_writew(mmio_base, where, val) \ + *((volatile u16 *) (mmio_base + where)) = (volatile u16) val \ + +#define i830_writel(mmio_base, where, val) \ + *((volatile u32 *) (mmio_base + where)) = (volatile u32) val \ + + + +DFBResult i830_wait_lp_ring( I830DriverData *idrv, + I830DeviceData *idev, + int space ); + +D_DEBUG_DOMAIN( I830_Ring, "I830/Ring", "I830 Ring Buffer" ); + + +static inline DFBResult +i830_begin_lp_ring( I830DriverData *idrv, + I830DeviceData *idev, + int needed, + I830RingBlock *ret_block ) +{ + DFBResult ret; + I830RingBuffer *buf = &idev->lp_ring; + + D_DEBUG_AT( I830_Ring, "begin_lp_ring( %d ) <- head 0x%08x\n", needed, i830_readl( idrv->mmio_base, LP_RING + RING_HEAD ) ); + + if (needed & 1) + D_ERROR( "i830_begin_ring called with odd argument: %d\n", needed); + + needed *= 4; + + if (buf->space < needed) { + ret = i830_wait_lp_ring( idrv, idev, needed ); + if (ret) + return ret; + } + + buf->space -= needed; + + ret_block->virt = idrv->lring_base; + ret_block->tail_mask = buf->tail_mask; + ret_block->outring = buf->tail; + + return DFB_OK; +} + +static inline void +i830_out_ring( I830RingBlock *block, + u32 value ) +{ + D_DEBUG_AT( I830_Ring, "out_ring( 0x%08x, 0x%08x )\n", block->outring, value ); + + *(volatile u32*)(block->virt + block->outring) = value; + + block->outring = (block->outring + 4) & block->tail_mask; +} + +static inline void +i830_advance_lp_ring( I830DriverData *idrv, + I830DeviceData *idev, + const I830RingBlock *block ) +{ + D_DEBUG_AT( I830_Ring, "advance_lp_ring( 0x%08x )\n", block->outring ); + + idev->lp_ring.tail = block->outring; + + if (block->outring & 0x07) + D_ERROR( "i830_advance_lp_ring: " + "outring (0x%x) isn't on a QWord boundary", block->outring ); + + i830_writel( idrv->mmio_base, LP_RING + RING_TAIL, block->outring ); +} + +#endif /* __I830_H__ */ diff --git a/Source/DirectFB/gfxdrivers/i830/i830_overlay.c b/Source/DirectFB/gfxdrivers/i830/i830_overlay.c new file mode 100755 index 0000000..5f64602 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/i830/i830_overlay.c @@ -0,0 +1,807 @@ +/* + Intel i830 DirectFB graphics driver + + (c) Copyright 2005 Servision Ltd. + http://www.servision.net/ + + All rights reserved. + + Based on i810 driver written by Antonino Daplas + + Video Overlay Support based partly on XFree86's "i830_video.c" + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +/* + * i830_video.c: i830/i845 Xv driver. + * + * Copyright © 2002 by Alan Hourihane and David Dawes + * + * Authors: + * Alan Hourihane + * David Dawes + * + * Derived from i830 Xv driver: + * + * Authors of i830 code: + * Jonathan Bian + * Offscreen Images: + * Matt Sottek + */ + +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include "i830.h" + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include + +#define I830_OVERLAY_SUPPORTED_OPTIONS (DLOP_DST_COLORKEY) + +static void ovl_calc_regs( I830DriverData *idrv, + I830DeviceData *idev, + I830OverlayLayerData *iovl, + CoreLayer *layer, + CoreSurface *surface, + CoreLayerRegionConfig *config, + bool buffers_only, + CoreSurfaceBufferLock *lock ); + + +/* + * This is more or less the correct way to initalise, update, and shut down + * the overlay. Note OVERLAY_OFF should be used only after disabling the + * overlay in OCMD and calling OVERLAY_UPDATE. + * + * XXX Need to make sure that the overlay engine is cleanly shutdown in + * all modes of server exit. + */ + +static void +update_overlay( I830DriverData *idrv, + I830DeviceData *idev ) +{ + I830RingBlock block = { NULL, 0, 0 }; + + i830_begin_lp_ring( idrv, idev, 6, &block ); + + i830_out_ring( &block, MI_FLUSH | MI_WRITE_DIRTY_STATE ); + i830_out_ring( &block, MI_NOOP ); + + if (!idev->overlayOn) { + idev->overlayOn = true; + + i830_out_ring( &block, MI_NOOP ); + i830_out_ring( &block, MI_NOOP ); + i830_out_ring( &block, MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_ON ); + } + else { + i830_out_ring( &block, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP ); + i830_out_ring( &block, MI_NOOP ); + i830_out_ring( &block, MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_CONTINUE ); + } + + i830_out_ring( &block, idev->ovl_mem.physical | 1 ); + + i830_advance_lp_ring( idrv, idev, &block ); +} + +static void +disable_overlay( I830DriverData *idrv, + I830DeviceData *idev ) +{ + I830RingBlock block = { NULL, 0, 0 }; + + if (!idev->overlayOn) + return; + + i830_begin_lp_ring( idrv, idev, 8, &block ); + + i830_out_ring( &block, MI_FLUSH | MI_WRITE_DIRTY_STATE ); + i830_out_ring( &block, MI_NOOP ); + i830_out_ring( &block, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP ); + i830_out_ring( &block, MI_NOOP ); + i830_out_ring( &block, MI_OVERLAY_FLIP | MI_OVERLAY_FLIP_OFF ); + i830_out_ring( &block, idev->ovl_mem.physical | 1 ); + i830_out_ring( &block, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP ); + i830_out_ring( &block, MI_NOOP ); + + i830_advance_lp_ring( idrv, idev, &block ); + + idev->overlayOn = false; +} + +void +i830ovlOnOff( I830DriverData *idrv, + I830DeviceData *idev, + bool on ) +{ + if (on) + idrv->oregs->OCMD |= OVERLAY_ENABLE; + else + idrv->oregs->OCMD &= ~OVERLAY_ENABLE; + + update_overlay( idrv, idev ); + + if (!on) + disable_overlay( idrv, idev ); +} + +static int +ovlLayerDataSize( void ) +{ + return sizeof(I830OverlayLayerData); +} + +static DFBResult +ovlInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + I830OverlayLayerData *iovl = layer_data; + + idev->iovl = iovl; + + idrv->oregs = (I830OverlayRegs*) idrv->ovl_base; + + memset( (void*) idrv->oregs, 0, sizeof(I830OverlayRegs) ); + + /* set_capabilities */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | DLCAPS_SATURATION | + DLCAPS_DST_COLORKEY; + + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Intel 830/845/855/865 Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + + + idrv->oregs->OCLRC0 = 64 << 18; + idrv->oregs->OCLRC1 = 0x80; + + return DFB_OK; +} + +static DFBResult +ovlTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = CLRCF_NONE; + + if (config->options & ~I830_OVERLAY_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + switch (config->format) { + case DSPF_I420: + case DSPF_YV12: + case DSPF_YUY2: + case DSPF_UYVY: + break; + default: + fail |= CLRCF_FORMAT; + } + + if (config->width > 1440 || config->width < 1) + fail |= CLRCF_WIDTH; + + if (config->height > 1023 || config->height < 1) + fail |= CLRCF_HEIGHT; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ovlSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + I830OverlayLayerData *iovl = layer_data; + + iovl->config = *config; + + ovl_calc_regs ( idrv, idev, iovl, layer, surface, config, false, lock ); + + i830ovlOnOff( idrv, idev, true ); + + return DFB_OK; +} + +static DFBResult +ovlRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + + /* disable overlay */ + i830ovlOnOff( idrv, idev, false ); + + return DFB_OK; +} + +static DFBResult +ovlFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + I830OverlayLayerData *iovl = layer_data; + + dfb_surface_flip( surface, false ); + + ovl_calc_regs ( idrv, idev, iovl, layer, surface, &iovl->config, true, lock ); + + update_overlay( idrv, idev ); + + if (flags & DSFLIP_WAIT) + dfb_screen_wait_vsync( dfb_screens_at( DSCID_PRIMARY ) ); + + return DFB_OK; +} + +static DFBResult +ovlSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + u16 b, c, s; + + if (adj->flags & DCAF_BRIGHTNESS) + b = ((adj->brightness >> 8) - 128) & 0xFF; + else + b = idrv->oregs->OCLRC0 & 0xFF; + + if (adj->flags & DCAF_CONTRAST) + c = (adj->contrast >> 8) & 0xFF; + else + c = (idrv->oregs->OCLRC0 >> 18) & 0xFF; + + if (adj->flags & DCAF_SATURATION) + s = (adj->saturation >> 8) & 0xFF; + else + s = idrv->oregs->OCLRC1 & 0xFF; + + idrv->oregs->OCLRC0 = b | (c << 18); + idrv->oregs->OCLRC1 = s; + + update_overlay( idrv, idev ); + + return DFB_OK; +} + +static DFBResult +ovlSetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + I830DriverData *idrv = driver_data; + I830DeviceData *idev = idrv->idev; + + idrv->oregs->OCMD &= ~FIELD_SELECT; + idrv->oregs->OCMD |= (field) ? FIELD1 : FIELD0; + + update_overlay( idrv, idev ); + + return DFB_OK; +} + +DisplayLayerFuncs i830OverlayFuncs = { + .LayerDataSize = ovlLayerDataSize, + .InitLayer = ovlInitLayer, + .TestRegion = ovlTestRegion, + .SetRegion = ovlSetRegion, + .RemoveRegion = ovlRemoveRegion, + .FlipRegion = ovlFlipRegion, + .SetColorAdjustment = ovlSetColorAdjustment, + .SetInputField = ovlSetInputField, +}; + + +typedef struct { + u8 sign; + u16 mantissa; + u8 exponent; +} coeffRec, *coeffPtr; + +static bool +SetCoeffRegs(double *coeff, int mantSize, coeffPtr pCoeff, int pos) +{ + int maxVal, icoeff, res; + int sign; + double c; + + sign = 0; + maxVal = 1 << mantSize; + c = *coeff; + if (c < 0.0) { + sign = 1; + c = -c; + } + + res = 12 - mantSize; + if ((icoeff = (int)(c * 4 * maxVal + 0.5)) < maxVal) { + pCoeff[pos].exponent = 3; + pCoeff[pos].mantissa = icoeff << res; + *coeff = (double)icoeff / (double)(4 * maxVal); + } + else if ((icoeff = (int)(c * 2 * maxVal + 0.5)) < maxVal) { + pCoeff[pos].exponent = 2; + pCoeff[pos].mantissa = icoeff << res; + *coeff = (double)icoeff / (double)(2 * maxVal); + } + else if ((icoeff = (int)(c * maxVal + 0.5)) < maxVal) { + pCoeff[pos].exponent = 1; + pCoeff[pos].mantissa = icoeff << res; + *coeff = (double)icoeff / (double)(maxVal); + } + else if ((icoeff = (int)(c * maxVal * 0.5 + 0.5)) < maxVal) { + pCoeff[pos].exponent = 0; + pCoeff[pos].mantissa = icoeff << res; + *coeff = (double)icoeff / (double)(maxVal / 2); + } + else { + /* Coeff out of range */ + return false; + } + + pCoeff[pos].sign = sign; + if (sign) + *coeff = -(*coeff); + return true; +} + +static void +UpdateCoeff(int taps, double fCutoff, bool isHoriz, bool isY, coeffPtr pCoeff) +{ + int i, j, j1, num, pos, mantSize; + double pi = 3.1415926535, val, sinc, window, sum; + double rawCoeff[MAX_TAPS * 32], coeffs[N_PHASES][MAX_TAPS]; + double diff; + int tapAdjust[MAX_TAPS], tap2Fix; + bool isVertAndUV; + + if (isHoriz) + mantSize = 7; + else + mantSize = 6; + + isVertAndUV = !isHoriz && !isY; + num = taps * 16; + for (i = 0; i < num * 2; i++) { + val = (1.0 / fCutoff) * taps * pi * (i - num) / (2 * num); + if (val == 0.0) + sinc = 1.0; + else + sinc = sin(val) / val; + + /* Hamming window */ + window = (0.5 - 0.5 * cos(i * pi / num)); + rawCoeff[i] = sinc * window; + } + + for (i = 0; i < N_PHASES; i++) { + /* Normalise the coefficients. */ + sum = 0.0; + for (j = 0; j < taps; j++) { + pos = i + j * 32; + sum += rawCoeff[pos]; + } + for (j = 0; j < taps; j++) { + pos = i + j * 32; + coeffs[i][j] = rawCoeff[pos] / sum; + } + + /* Set the register values. */ + for (j = 0; j < taps; j++) { + pos = j + i * taps; + if ((j == (taps - 1) / 2) && !isVertAndUV) + SetCoeffRegs(&coeffs[i][j], mantSize + 2, pCoeff, pos); + else + SetCoeffRegs(&coeffs[i][j], mantSize, pCoeff, pos); + } + + tapAdjust[0] = (taps - 1) / 2; + for (j = 1, j1 = 1; j <= tapAdjust[0]; j++, j1++) { + tapAdjust[j1] = tapAdjust[0] - j; + tapAdjust[++j1] = tapAdjust[0] + j; + } + + /* Adjust the coefficients. */ + sum = 0.0; + for (j = 0; j < taps; j++) + sum += coeffs[i][j]; + if (sum != 1.0) { + for (j1 = 0; j1 < taps; j1++) { + tap2Fix = tapAdjust[j1]; + diff = 1.0 - sum; + coeffs[i][tap2Fix] += diff; + pos = tap2Fix + i * taps; + if ((tap2Fix == (taps - 1) / 2) && !isVertAndUV) + SetCoeffRegs(&coeffs[i][tap2Fix], mantSize + 2, pCoeff, pos); + else + SetCoeffRegs(&coeffs[i][tap2Fix], mantSize, pCoeff, pos); + + sum = 0.0; + for (j = 0; j < taps; j++) + sum += coeffs[i][j]; + if (sum == 1.0) + break; + } + } + } +} + +static void +ovl_calc_regs( I830DriverData *idrv, + I830DeviceData *idev, + I830OverlayLayerData *iovl, + CoreLayer *layer, + CoreSurface *surface, + CoreLayerRegionConfig *config, + bool buffers_only, + CoreSurfaceBufferLock *lock ) +{ + I830OverlayRegs *regs = idrv->oregs; + int width = config->width; + int height = config->height; + + int y_offset, u_offset = 0, v_offset = 0; + + unsigned int swidth; + + + /* Set buffer pointers */ + y_offset = dfb_gfxcard_memory_physical( NULL, lock->offset ); + + switch (config->format) { + case DSPF_I420: + u_offset = y_offset + height * lock->pitch; + v_offset = u_offset + ((height >> 1) * (lock->pitch >> 1)); + break; + + case DSPF_YV12: + v_offset = y_offset + height * lock->pitch; + u_offset = v_offset + ((height >> 1) * (lock->pitch >> 1)); + break; + + case DSPF_UYVY: + case DSPF_YUY2: + break; + + default: + D_BUG( "unexpected format" ); + return; + } + + /* buffer locations */ + regs->OBUF_0Y = y_offset; + regs->OBUF_0U = u_offset; + regs->OBUF_0V = v_offset; + + //D_INFO("Buffers: Y0: 0x%08x, U0: 0x%08x, V0: 0x%08x\n", regs->OBUF_0Y, + // regs->OBUF_0U, regs->OBUF_0V); + + if (buffers_only) + return; + + switch (config->format) { + case DSPF_YV12: + case DSPF_I420: + swidth = (width + 1) & ~1 & 0xfff; + regs->SWIDTH = swidth; + + swidth /= 2; + regs->SWIDTH |= (swidth & 0x7ff) << 16; + + swidth = ((y_offset + width + 0x1f) >> 5) - (y_offset >> 5) - 1; + + //D_INFO("Y width is %d, swidthsw is %d\n", width, swidth); + + regs->SWIDTHSW = swidth << 2; + + swidth = ((u_offset + (width / 2) + 0x1f) >> 5) - (u_offset >> 5) - 1; + //D_INFO("UV width is %d, swidthsw is %d\n", width / 2, swidth); + + regs->SWIDTHSW |= swidth << 18; + break; + + case DSPF_UYVY: + case DSPF_YUY2: + /* XXX Check for i845 */ + + swidth = ((width + 31) & ~31) << 1; + regs->SWIDTH = swidth; + regs->SWIDTHSW = swidth >> 3; + break; + + default: + D_BUG( "unexpected format" ); + return; + } + + regs->SHEIGHT = height | ((height / 2) << 16); + +#if NOT_PORTED_YET + if (pPriv->oneLineMode) { + /* change the coordinates with panel fitting active */ + dstBox->y1 = (((dstBox->y1 - 1) * pPriv->scaleRatio) >> 16) + 1; + dstBox->y2 = ((dstBox->y2 * pPriv->scaleRatio) >> 16) + 1; + + /* Now, alter the height, so we scale to the correct size */ + drw_h = dstBox->y2 - dstBox->y1; + if (drw_h < height) drw_h = height; + } +#endif + + regs->DWINPOS = (config->dest.y << 16) | config->dest.x; + regs->DWINSZ = (config->dest.h << 16) | config->dest.w; + + //D_INFO("pos: 0x%08x, size: 0x%08x\n", regs->DWINPOS, regs->DWINSZ); + + + regs->OCMD = OVERLAY_ENABLE; + regs->OCONFIG = CC_OUT_8BIT; + + /* + * Calculate horizontal and vertical scaling factors and polyphase + * coefficients. + */ + + { + bool scaleChanged = false; + int xscaleInt, xscaleFract, yscaleInt, yscaleFract; + int xscaleIntUV, xscaleFractUV; + int yscaleIntUV, yscaleFractUV; + /* UV is half the size of Y -- YUV420 */ + int uvratio = 2; + u32 newval; + coeffRec xcoeffY[N_HORIZ_Y_TAPS * N_PHASES]; + coeffRec xcoeffUV[N_HORIZ_UV_TAPS * N_PHASES]; + int i, j, pos; + + /* + * Y down-scale factor as a multiple of 4096. + */ + xscaleFract = (config->source.w << 12) / config->dest.w; + yscaleFract = (config->source.h << 12) / config->dest.h; + + /* Calculate the UV scaling factor. */ + xscaleFractUV = xscaleFract / uvratio; + yscaleFractUV = yscaleFract / uvratio; + + /* + * To keep the relative Y and UV ratios exact, round the Y scales + * to a multiple of the Y/UV ratio. + */ + xscaleFract = xscaleFractUV * uvratio; + yscaleFract = yscaleFractUV * uvratio; + + /* Integer (un-multiplied) values. */ + xscaleInt = xscaleFract >> 12; + yscaleInt = yscaleFract >> 12; + + xscaleIntUV = xscaleFractUV >> 12; + yscaleIntUV = yscaleFractUV >> 12; + + //D_INFO("xscale: 0x%x.%03x, yscale: 0x%x.%03x\n", xscaleInt, + // xscaleFract & 0xFFF, yscaleInt, yscaleFract & 0xFFF); + //D_INFO("UV xscale: 0x%x.%03x, UV yscale: 0x%x.%03x\n", xscaleIntUV, + // xscaleFractUV & 0xFFF, yscaleIntUV, yscaleFractUV & 0xFFF); + + newval = (xscaleInt << 16) | + ((xscaleFract & 0xFFF) << 3) | ((yscaleFract & 0xFFF) << 20); + if (newval != regs->YRGBSCALE) { + scaleChanged = true; + regs->YRGBSCALE = newval; + } + + newval = (xscaleIntUV << 16) | ((xscaleFractUV & 0xFFF) << 3) | + ((yscaleFractUV & 0xFFF) << 20); + if (newval != regs->UVSCALE) { + scaleChanged = true; + regs->UVSCALE = newval; + } + + newval = yscaleInt << 16 | yscaleIntUV; + if (newval != regs->UVSCALEV) { + scaleChanged = true; + regs->UVSCALEV = newval; + } + + /* Recalculate coefficients if the scaling changed. */ + + /* + * Only Horizontal coefficients so far. + */ + if (scaleChanged) { + double fCutoffY; + double fCutoffUV; + + fCutoffY = xscaleFract / 4096.0; + fCutoffUV = xscaleFractUV / 4096.0; + + /* Limit to between 1.0 and 3.0. */ + if (fCutoffY < MIN_CUTOFF_FREQ) + fCutoffY = MIN_CUTOFF_FREQ; + if (fCutoffY > MAX_CUTOFF_FREQ) + fCutoffY = MAX_CUTOFF_FREQ; + if (fCutoffUV < MIN_CUTOFF_FREQ) + fCutoffUV = MIN_CUTOFF_FREQ; + if (fCutoffUV > MAX_CUTOFF_FREQ) + fCutoffUV = MAX_CUTOFF_FREQ; + + UpdateCoeff(N_HORIZ_Y_TAPS, fCutoffY, true, true, xcoeffY); + UpdateCoeff(N_HORIZ_UV_TAPS, fCutoffUV, true, false, xcoeffUV); + + for (i = 0; i < N_PHASES; i++) { + for (j = 0; j < N_HORIZ_Y_TAPS; j++) { + pos = i * N_HORIZ_Y_TAPS + j; + regs->Y_HCOEFS[pos] = xcoeffY[pos].sign << 15 | + xcoeffY[pos].exponent << 12 | + xcoeffY[pos].mantissa; + } + } + for (i = 0; i < N_PHASES; i++) { + for (j = 0; j < N_HORIZ_UV_TAPS; j++) { + pos = i * N_HORIZ_UV_TAPS + j; + regs->UV_HCOEFS[pos] = xcoeffUV[pos].sign << 15 | + xcoeffUV[pos].exponent << 12 | + xcoeffUV[pos].mantissa; + } + } + } + } + + switch (config->format) { + case DSPF_YV12: + case DSPF_I420: + //D_INFO("YUV420\n"); +#if 0 + /* set UV vertical phase to -0.25 */ + regs->UV_VPH = 0x30003000; +#endif + + regs->OSTRIDE = lock->pitch | (lock->pitch << 15); + regs->OCMD |= YUV_420; + break; + + case DSPF_UYVY: + case DSPF_YUY2: + //D_INFO("YUV422\n"); + + regs->OSTRIDE = lock->pitch; + regs->OCMD |= YUV_422; + + if (config->format == DSPF_UYVY) + regs->OCMD |= Y_SWAP; + break; + + default: + D_BUG( "unexpected format" ); + return; + } + + + /* + * Destination color keying. + */ + regs->DCLRKV = PIXEL_RGB32 (config->dst_key.r, config->dst_key.g, config->dst_key.b ); + + switch (DFB_COLOR_BITS_PER_PIXEL( dfb_primary_layer_pixelformat() )) { + case 8: + regs->DCLRKM = 0xffffff; + break; + case 15: + regs->DCLRKM = 0x070707; + break; + case 16: + regs->DCLRKM = 0x070307; + break; + default: + regs->DCLRKM = 0; + break; + } + + if(dfb_config->i8xx_overlay_pipe_b) + regs->OCONFIG |= OVERLAY_PIPE_B; + + if (config->options & DLOP_DST_COLORKEY) + regs->DCLRKM |= DEST_KEY_ENABLE; + + /* + * Disable source color keying if not selected + */ + if (!(config->options & DLOP_SRC_COLORKEY)) { + regs -> SCLRKVH = 0; + regs -> SCLRKVL = 0; + regs -> SCLRKEN = 0; + } + + + //D_INFO("OCMD is 0x%08x\n", regs->OCMD); +} + diff --git a/Source/DirectFB/gfxdrivers/mach64/Makefile.am b/Source/DirectFB/gfxdrivers/mach64/Makefile.am new file mode 100755 index 0000000..89b9a0e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/Makefile.am @@ -0,0 +1,39 @@ +## Makefile.am for DirectFB/gfxdrivers/mach64 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +mach64_LTLIBRARIES = libdirectfb_mach64.la + +if BUILD_STATIC +mach64_DATA = $(mach64_LTLIBRARIES:.la=.o) +endif + +mach64dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_mach64_la_SOURCES = \ + mach64.c \ + mach64.h \ + mach64_state.c \ + mach64_state.h \ + mach64_overlay.c \ + regs.h \ + mmio.h + +libdirectfb_mach64_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_mach64_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/mach64/Makefile.in b/Source/DirectFB/gfxdrivers/mach64/Makefile.in new file mode 100755 index 0000000..edcb305 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/Makefile.in @@ -0,0 +1,603 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/mach64 +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(mach64dir)" "$(DESTDIR)$(mach64dir)" +mach64LTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(mach64_LTLIBRARIES) +libdirectfb_mach64_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_mach64_la_OBJECTS = mach64.lo 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$(INSTALL_DATA) +DATA = $(mach64_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ 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+%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/mach64/mach64.c b/Source/DirectFB/gfxdrivers/mach64/mach64.c new file mode 100755 index 0000000..84fd571 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mach64.c @@ -0,0 +1,1640 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include + + +DFB_GRAPHICS_DRIVER( mach64 ) + + +#include "regs.h" +#include "mmio.h" +#include "mach64_state.h" +#include "mach64.h" + + +/* driver capability flags */ + + +#define MACH64_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_DST_COLORKEY | DSDRAW_SRC_PREMULTIPLY) + +#define MACH64_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY) + +#define MACH64_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE) + +#define MACH64_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT) + + +#define MACH64GT_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_DST_COLORKEY | DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY) + +#define MACH64GT_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY | DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_COLORIZE | DSBLIT_DEINTERLACE | \ + DSBLIT_SRC_PREMULTCOLOR) + +#define MACH64GT_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE | DFXL_FILLTRIANGLE) + +#define MACH64GT_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) + + +static bool mach64DrawLine2D( void *drv, void *dev, DFBRegion *line ); +static bool mach64DrawLine3D( void *drv, void *dev, DFBRegion *line ); + +static bool mach64Blit2D( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +static bool mach64BlitScaleOld( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); +static bool mach64StretchBlitScaleOld( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ); + +static bool mach64BlitScale( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); +static bool mach64StretchBlitScale( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ); + +static bool mach64BlitTexOld( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); +static bool mach64StretchBlitTexOld( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ); + +static bool mach64BlitTex( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); +static bool mach64StretchBlitTex( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ); + +/* required implementations */ + +static void mach64EngineReset( void *drv, void *dev ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitidle( mdrv, mdev ); + + mach64_waitfifo( mdrv, mdev, 2 ); + + mach64_out32( mmio, DP_WRITE_MSK, 0xFFFFFFFF ); + mach64_out32( mmio, DP_MIX, FRGD_MIX_SRC | BKGD_MIX_DST ); + + if (mdrv->accelerator == FB_ACCEL_ATI_MACH64GT) { + mach64_waitfifo( mdrv, mdev, 12 ); + + /* Some 3D registers aren't accessible without this. */ + mach64_out32( mmio, SCALE_3D_CNTL, SCALE_3D_FCN_SHADE ); + + mach64_out32( mmio, SRC_CNTL, 0 ); + mach64_out32( mmio, Z_CNTL, 0 ); + + mach64_out32( mmio, RED_X_INC, 0 ); + mach64_out32( mmio, RED_Y_INC, 0 ); + mach64_out32( mmio, GREEN_X_INC, 0 ); + mach64_out32( mmio, GREEN_Y_INC, 0 ); + mach64_out32( mmio, BLUE_X_INC, 0 ); + mach64_out32( mmio, BLUE_Y_INC, 0 ); + mach64_out32( mmio, ALPHA_X_INC, 0 ); + mach64_out32( mmio, ALPHA_Y_INC, 0 ); + + mach64_out32( mmio, SCALE_3D_CNTL, 0 ); + } + + if (mdev->chip >= CHIP_3D_RAGE_PRO) + mach64_out32( mmio, HW_DEBUG, mdev->hw_debug ); +} + +static DFBResult mach64EngineSync( void *drv, void *dev ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64_waitidle( mdrv, mdev ); + + return DFB_OK; +} + +static void mach64FlushTextureCache( void *drv, void *dev ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, TEX_CNTL, TEX_CACHE_FLUSH ); + } +} + +static bool mach64_use_scaler( Mach64DeviceData *mdev, + CardState *state, DFBAccelerationMask accel ) +{ + if (accel & DFXL_STRETCHBLIT || + state->source->config.format != state->destination->config.format || + state->blittingflags & (DSBLIT_BLEND_COLORALPHA | DSBLIT_DEINTERLACE)) + return true; + + return false; +} + +static bool mach64_use_tex( Mach64DeviceData *mdev, + CardState *state, DFBAccelerationMask accel ) +{ + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + return true; + + /* + * 3D Rage II chips lock up if the scaler is used with destination + * color keying. Using the texture engine works however. + */ + if (mdev->chip < CHIP_3D_RAGE_PRO && + mach64_use_scaler( mdev, state, accel ) && + state->blittingflags & DSBLIT_DST_COLORKEY) + return true; + + return false; +} + +static bool mach64_use_scaler_3d( Mach64DeviceData *mdev, + CardState *state, DFBAccelerationMask accel ) +{ + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & DSDRAW_BLEND) + return true; + } else { + if (accel & DFXL_STRETCHBLIT || + state->source->config.format != state->destination->config.format || + state->blittingflags & (DSBLIT_BLEND_COLORALPHA | DSBLIT_DEINTERLACE | + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_COLORIZE | + DSBLIT_SRC_PREMULTCOLOR)) + return true; + } + + return false; +} + +static bool mach64_check_blend( Mach64DeviceData *mdev, CardState *state ) +{ + switch (state->src_blend) { + case DSBF_SRCCOLOR: + case DSBF_INVSRCCOLOR: + return false; + case DSBF_DESTALPHA: + case DSBF_INVDESTALPHA: + case DSBF_SRCALPHASAT: + if (mdev->chip < CHIP_3D_RAGE_PRO) + return false; + default: + break; + } + + switch (state->dst_blend) { + case DSBF_DESTCOLOR: + case DSBF_INVDESTCOLOR: + case DSBF_SRCALPHASAT: + return false; + case DSBF_DESTALPHA: + case DSBF_INVDESTALPHA: + if (mdev->chip < CHIP_3D_RAGE_PRO) + return false; + default: + break; + } + + return true; +} + +static void mach64CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MACH64_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= MACH64_SUPPORTED_DRAWINGFUNCTIONS; + } else { + if (state->source->config.format != state->destination->config.format) + return; + + if (state->blittingflags & ~MACH64_SUPPORTED_BLITTINGFLAGS) + return; + + /* Can't do source and destination color keying at the same time. */ + if (state->blittingflags & DSBLIT_SRC_COLORKEY && + state->blittingflags & DSBLIT_DST_COLORKEY) + return; + + state->accel |= MACH64_SUPPORTED_BLITTINGFUNCTIONS; + } +} + +static void mach64GTCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + switch (state->destination->config.format) { + case DSPF_RGB444: + case DSPF_ARGB4444: + /* Not supported. */ + if (mdev->chip < CHIP_3D_RAGE_PRO) + return; + + /* Causes the chip to lock up. */ + if (mdev->chip < CHIP_3D_RAGE_XLXC && + mach64_use_scaler_3d( mdev, state, accel )) + return; + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MACH64GT_SUPPORTED_DRAWINGFLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + !mach64_check_blend( mdev, state )) + return; + + /* Causes the chip to lock up. */ + if (state->drawingflags & DSDRAW_BLEND && + state->drawingflags & DSDRAW_DST_COLORKEY) + return; + + state->accel |= MACH64GT_SUPPORTED_DRAWINGFUNCTIONS; + } else { + CoreSurface *source = state->source; + + switch (source->config.format) { + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (state->blittingflags & ~MACH64GT_SUPPORTED_BLITTINGFLAGS) + return; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA) && + !mach64_check_blend( mdev, state )) + return; + + /* Can't do alpha modulation. */ + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && + state->blittingflags & DSBLIT_BLEND_COLORALPHA) + return; + + /* Can't do source and destination color keying at the same time. */ + if (state->blittingflags & DSBLIT_SRC_COLORKEY && + state->blittingflags & DSBLIT_DST_COLORKEY) + return; + + /* Causes the chip to lock up. */ + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA) && + state->blittingflags & DSBLIT_DST_COLORKEY) + return; + + if (mach64_use_tex( mdev, state, accel )) { + /* Max texture size is 1024x1024. */ + if (source->config.size.w > 1024 || source->config.size.h > 1024) + return; + + state->accel |= MACH64GT_SUPPORTED_BLITTINGFUNCTIONS; + } else if (mach64_use_scaler( mdev, state, accel )) { + /* Max scaler source size depends on the chip type. */ + if (mdev->chip < CHIP_3D_RAGE_PRO) { + /* Tested on 3D Rage II+ and IIC. */ + if (source->config.size.w > 4095 || source->config.size.h > 4095) + return; + } else { + /* Tested on 3D Rage LT Pro, XL and Mobility. */ + if (source->config.size.w > 4096 || source->config.size.h > 16384) + return; + } + + state->accel |= MACH64GT_SUPPORTED_BLITTINGFUNCTIONS; + } else + state->accel |= accel; + } +} + +static void mach64SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + if (state->mod_hw == SMF_ALL) { + mdev->valid = 0; + } else if (state->mod_hw) { + if (state->mod_hw & SMF_SOURCE) + MACH64_INVALIDATE( m_source | m_srckey ); + + if (state->mod_hw & SMF_SRC_COLORKEY) + MACH64_INVALIDATE( m_srckey ); + + if (state->mod_hw & SMF_DESTINATION) + MACH64_INVALIDATE( m_color | m_dstkey ); + + if (state->mod_hw & SMF_COLOR) + MACH64_INVALIDATE( m_color ); + + if (state->mod_hw & SMF_DST_COLORKEY) + MACH64_INVALIDATE( m_dstkey ); + + if (state->mod_hw & SMF_BLITTING_FLAGS) + MACH64_INVALIDATE( m_srckey | m_dstkey | m_disable_key ); + + if (state->mod_hw & SMF_DRAWING_FLAGS) + MACH64_INVALIDATE( m_color | m_dstkey | m_disable_key ); + } + + if (state->mod_hw & SMF_DESTINATION) + mach64_set_destination( mdrv, mdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + mach64_waitfifo( mdrv, mdev, 2 ); + mach64_out32( mmio, DP_SRC, FRGD_SRC_FRGD_CLR ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + mach64_set_color( mdrv, mdev, state ); + + if (state->drawingflags & DSDRAW_DST_COLORKEY) + mach64_set_dst_colorkey( mdrv, mdev, state ); + else + mach64_disable_colorkey( mdrv, mdev ); + + funcs->DrawLine = mach64DrawLine2D; + + state->set = DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE; + break; + case DFXL_BLIT: + mach64_set_source( mdrv, mdev, state ); + + mach64_waitfifo( mdrv, mdev, 2 ); + mach64_out32( mmio, DP_SRC, FRGD_SRC_BLIT ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + if (state->blittingflags & DSBLIT_DST_COLORKEY) + mach64_set_dst_colorkey( mdrv, mdev, state ); + else if (state->blittingflags & DSBLIT_SRC_COLORKEY) + mach64_set_src_colorkey( mdrv, mdev, state ); + else + mach64_disable_colorkey( mdrv, mdev ); + + funcs->Blit = mach64Blit2D; + + state->set = DFXL_BLIT; + break; + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + if (state->mod_hw & SMF_CLIP) { + mach64_set_clip( mdrv, mdev, state ); + mdev->clip = state->clip; + } + + state->mod_hw = 0; +} + +static void mach64GTSetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + bool use_scaler_3d; + + if (state->mod_hw == SMF_ALL) { + mdev->valid = 0; + } else if (state->mod_hw) { + if (state->mod_hw & SMF_SOURCE) + MACH64_INVALIDATE( m_source | m_source_scale | m_srckey | m_srckey_scale | m_blit_blend ); + + if (state->mod_hw & SMF_SRC_COLORKEY) + MACH64_INVALIDATE( m_srckey | m_srckey_scale ); + + if (state->mod_hw & SMF_DESTINATION) + MACH64_INVALIDATE( m_color | m_dstkey ); + + if (state->mod_hw & SMF_COLOR) + MACH64_INVALIDATE( m_color | m_color_3d | m_color_tex ); + + if (state->mod_hw & SMF_DST_COLORKEY) + MACH64_INVALIDATE( m_dstkey ); + + if (state->mod_hw & SMF_BLITTING_FLAGS) + MACH64_INVALIDATE( m_color_tex | m_source_scale | m_srckey | m_srckey_scale | m_dstkey | m_disable_key | m_blit_blend ); + + if (state->mod_hw & SMF_DRAWING_FLAGS) + MACH64_INVALIDATE( m_color | m_color_3d | m_dstkey | m_disable_key | m_draw_blend ); + + if (state->mod_hw & (SMF_SRC_BLEND | SMF_DST_BLEND)) + MACH64_INVALIDATE( m_draw_blend | m_blit_blend ); + } + + use_scaler_3d = mach64_use_scaler_3d( mdev, state, accel ); + + /* At least 3D Rage II+ and IIC chips _will_ lock up without this. */ + if (mdev->chip < CHIP_3D_RAGE_PRO && use_scaler_3d != mdev->use_scaler_3d) + mach64_waitidle( mdrv, mdev ); + + mdev->use_scaler_3d = use_scaler_3d; + + if (state->mod_hw & SMF_DESTINATION) + mach64gt_set_destination( mdrv, mdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + if (use_scaler_3d) { + mach64_waitfifo( mdrv, mdev, 3 ); + /* Some 3D registers aren't accessible without this. */ + mach64_out32( mmio, SCALE_3D_CNTL, SCALE_3D_FCN_SHADE ); + + mach64_out32( mmio, DP_SRC, FRGD_SRC_SCALE ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + mach64_set_color_3d( mdrv, mdev, state ); + + mach64_set_draw_blend( mdrv, mdev, state ); + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, SCALE_3D_CNTL, SCALE_3D_FCN_SHADE | mdev->draw_blend ); + + funcs->DrawLine = mach64DrawLine3D; + } else { + mach64_waitfifo( mdrv, mdev, 3 ); + mach64_out32( mmio, SCALE_3D_CNTL, 0 ); + + mach64_out32( mmio, DP_SRC, FRGD_SRC_FRGD_CLR ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + mach64_set_color( mdrv, mdev, state ); + + funcs->DrawLine = mach64DrawLine2D; + } + + if (state->drawingflags & DSDRAW_DST_COLORKEY) + mach64_set_dst_colorkey( mdrv, mdev, state ); + else + mach64_disable_colorkey( mdrv, mdev ); + + state->set = DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE | DFXL_FILLTRIANGLE; + break; + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + mdev->blit_deinterlace = state->blittingflags & DSBLIT_DEINTERLACE; + + if (use_scaler_3d) { + mach64_waitfifo( mdrv, mdev, 1 ); + /* Some 3D registers aren't accessible without this. */ + mach64_out32( mmio, SCALE_3D_CNTL, SCALE_3D_FCN_SHADE ); + + mach64gt_set_source_scale( mdrv, mdev, state ); + + mach64_waitfifo( mdrv, mdev, 2 ); + mach64_out32( mmio, DP_SRC, FRGD_SRC_SCALE ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + mach64_set_color_tex( mdrv, mdev, state ); + + mach64_set_blit_blend( mdrv, mdev, state ); + + if (state->blittingflags & DSBLIT_DST_COLORKEY) + mach64_set_dst_colorkey( mdrv, mdev, state ); + else if (state->blittingflags & DSBLIT_SRC_COLORKEY) + mach64_set_src_colorkey_scale( mdrv, mdev, state ); + else + mach64_disable_colorkey( mdrv, mdev ); + + if (mdev->chip < CHIP_3D_RAGE_PRO) { + if (mach64_use_tex( mdev, state, accel )) { + funcs->Blit = mach64BlitTexOld; + funcs->StretchBlit = mach64StretchBlitTexOld; + } else { + funcs->Blit = mach64BlitScaleOld; + funcs->StretchBlit = mach64StretchBlitScaleOld; + } + } else { + if (mach64_use_tex( mdev, state, accel )) { + funcs->Blit = mach64BlitTex; + funcs->StretchBlit = mach64StretchBlitTex; + } else { + funcs->Blit = mach64BlitScale; + funcs->StretchBlit = mach64StretchBlitScale; + } + } + + state->set = DFXL_BLIT | DFXL_STRETCHBLIT; + } else { + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, SCALE_3D_CNTL, 0 ); + + mach64gt_set_source( mdrv, mdev, state ); + + mach64_waitfifo( mdrv, mdev, 2 ); + mach64_out32( mmio, DP_SRC, FRGD_SRC_BLIT ); + mach64_out32( mmio, DP_PIX_WIDTH, mdev->pix_width ); + + if (state->blittingflags & DSBLIT_DST_COLORKEY) + mach64_set_dst_colorkey( mdrv, mdev, state ); + else if (state->blittingflags & DSBLIT_SRC_COLORKEY) + mach64_set_src_colorkey( mdrv, mdev, state ); + else + mach64_disable_colorkey( mdrv, mdev ); + + funcs->Blit = mach64Blit2D; + + state->set = DFXL_BLIT; + } + break; + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + if (state->mod_hw & SMF_CLIP) { + mach64_set_clip( mdrv, mdev, state ); + mdev->clip = state->clip; + } + + state->mod_hw = 0; +} + +/* */ + +static bool mach64FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 3 ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( rect->x ) << 16) | S14( rect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (rect->w << 16) | rect->h ); + + return true; +} + +static bool mach64DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + int x2 = rect->x + rect->w - 1; + int y2 = rect->y + rect->h - 1; + + mach64_waitfifo( mdrv, mdev, 8 ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( rect->x ) << 16) | S14( rect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | rect->h ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (rect->w << 16) | 1 ); + + mach64_out32( mmio, DST_CNTL, 0 ); + mach64_out32( mmio, DST_Y_X, (S13( x2 ) << 16) | S14( y2 ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | rect->h ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (rect->w << 16) | 1 ); + + return true; +} + +static void mach64_draw_line( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + int x1, int y1, + int x2, int y2, + bool draw_3d ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 dst_cntl = 0; + int dx, dy; + + dx = x2 - x1; + dy = y2 - y1; + + if (dx < 0) + dx = -dx; + else + dst_cntl |= DST_X_DIR; + + if (dy < 0) + dy = -dy; + else + dst_cntl |= DST_Y_DIR; + + if (!dx || !dy) { + /* horizontal / vertical line */ + mach64_waitfifo( mdrv, mdev, 3 ); + + mach64_out32( mmio, DST_CNTL, dst_cntl); + mach64_out32( mmio, DST_Y_X, (S13( x1 ) << 16) | S14( y1 ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, ((dx+1) << 16) | (dy+1) ); + + return; + } + + if (dx < dy) { + int tmp = dx; + dx = dy; + dy = tmp; + dst_cntl |= DST_Y_MAJOR; + } + + mach64_waitfifo( mdrv, mdev, 6 ); + + mach64_out32( mmio, DST_CNTL, DST_LAST_PEL | dst_cntl ); + mach64_out32( mmio, DST_Y_X, (S13( x1 ) << 16) | S14( y1 ) ); + + /* Bresenham parameters must be calculated differently + * for the 2D and 3D engines. + */ + if (draw_3d) { + mach64_out32( mmio, DST_BRES_ERR, -dx ); + mach64_out32( mmio, DST_BRES_INC, 2*dy ); + mach64_out32( mmio, DST_BRES_DEC, -2*dx ); + mach64_out32( mmio, DST_BRES_LNTH, dx+1 ); + } else { + mach64_out32( mmio, DST_BRES_ERR, 2*dy-dx ); + mach64_out32( mmio, DST_BRES_INC, 2*dy ); + mach64_out32( mmio, DST_BRES_DEC, 2*dy-2*dx ); + mach64_out32( mmio, DST_BRES_LNTH, dx+1 ); + } +} + +static bool mach64DrawLine2D( void *drv, void *dev, DFBRegion *line ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64_draw_line( mdrv, mdev, + line->x1, line->y1, + line->x2, line->y2, + false ); + + return true; +} + +static bool mach64DrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64_draw_line( mdrv, mdev, + line->x1, line->y1, + line->x2, line->y2, + true ); + + return true; +} + +static void mach64_fill_trapezoid( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + int X1l, int X1r, + int X2l, int X2r, + int Y, int dY ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 dst_cntl; + int dXl, dXr; + + X1r++; X2r++; + + dst_cntl = DST_Y_DIR | TRAP_FILL_DIR; + + dXl = X2l - X1l; + if (dXl < 0) + dXl = -dXl; + else + dst_cntl |= DST_X_DIR; + + dXr = X2r - X1r; + if (dXr < 0) + dXr = -dXr; + else + dst_cntl |= TRAIL_X_DIR; + + mach64_waitfifo( mdrv, mdev, 9 ); + + mach64_out32( mmio, DST_CNTL, dst_cntl ); + mach64_out32( mmio, DST_Y_X, (S13( X1l ) << 16) | S14( Y ) ); + + mach64_out32( mmio, LEAD_BRES_ERR, -dY ); + mach64_out32( mmio, LEAD_BRES_INC, 2*dXl ); + mach64_out32( mmio, LEAD_BRES_DEC, -2*dY ); + + mach64_out32( mmio, TRAIL_BRES_ERR, -dY ); + mach64_out32( mmio, TRAIL_BRES_INC, 2*dXr ); + mach64_out32( mmio, TRAIL_BRES_DEC, -2*dY ); + + mach64_out32( mmio, LEAD_BRES_LNTH, (S14( X1r ) << 16) | (dY+1) | DRAW_TRAP | LINE_DIS ); +} + +static bool mach64FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + dfb_sort_triangle( tri ); + + if (tri->y2 == tri->y3) { + mach64_fill_trapezoid( mdrv, mdev, + tri->x1, tri->x1, + MIN( tri->x2, tri->x3), MAX( tri->x2, tri->x3 ), + tri->y1, tri->y3 - tri->y1 ); + } else if (tri->y1 == tri->y2) { + mach64_fill_trapezoid( mdrv, mdev, + MIN( tri->x1, tri->x2), MAX( tri->x1, tri->x2 ), + tri->x3, tri->x3, + tri->y1, tri->y3 - tri->y1 ); + } else { + int majDx = tri->x3 - tri->x1; + int majDy = tri->y3 - tri->y1; + int topDx = tri->x2 - tri->x1; + int topDy = tri->y2 - tri->y1; + int botDy = tri->y3 - tri->y2; + + int topXperY = (topDx << 20) / topDy; + int X2a = tri->x1 + (((topXperY * topDy) + (1<<19)) >> 20); + + int majXperY = (majDx << 20) / majDy; + int majX2 = tri->x1 + (((majXperY * topDy) + (1<<19)) >> 20); + int majX2a = majX2 - ((majXperY + (1<<19)) >> 20); + + mach64_fill_trapezoid( mdrv, mdev, + tri->x1, tri->x1, + MIN( X2a, majX2a ), MAX( X2a, majX2a ), + tri->y1, topDy - 1 ); + mach64_fill_trapezoid( mdrv, mdev, + MIN( tri->x2, majX2 ), MAX( tri->x2, majX2 ), + tri->x3, tri->x3, + tri->y2, botDy ); + } + + return true; +} + +static void mach64DoBlit2D( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 dst_cntl = 0; + + if (srect->x <= drect->x) { + srect->x += srect->w - 1; + drect->x += drect->w - 1; + } else + dst_cntl |= DST_X_DIR; + + if (srect->y <= drect->y) { + srect->y += srect->h - 1; + drect->y += drect->h - 1; + } else + dst_cntl |= DST_Y_DIR; + + mach64_waitfifo( mdrv, mdev, 5 ); + + mach64_out32( mmio, SRC_Y_X, (S13( srect->x ) << 16) | S14( srect->y ) ); + mach64_out32( mmio, SRC_HEIGHT1_WIDTH1, (srect->w << 16) | srect->h ); + + mach64_out32( mmio, DST_CNTL, dst_cntl ); + mach64_out32( mmio, DST_Y_X, (S13( drect->x ) << 16) | S14( drect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (drect->w << 16) | drect->h ); +} + +static void mach64DoBlitScaleOld( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *source = mdev->source; + + u32 scale_3d_cntl = SCALE_3D_FCN_SCALE | mdev->blit_blend; + int hacc, vacc; + + if (!filter) + scale_3d_cntl |= SCALE_PIX_REP; + + if (mdev->blit_deinterlace) { + srect->y /= 2; + srect->h /= 2; + } + + srect->x <<= 16; + srect->y <<= 16; + srect->w <<= 16; + srect->h <<= 16; + + /* + * SCALE_HACC and SCALE_VACC have limited scale so we need to change + * SCALE_Y_OFF in order to handle the full range of source coordinates. + */ + hacc = srect->x & 0xFFFF0; /* s4.12 */ + vacc = srect->y & 0xFFFF0; /* s4.12 */ + srect->x &= ~0xFFFFF; + srect->y &= ~0xFFFFF; + + mach64_waitfifo( mdrv, mdev, 14 ); + + mach64_out32( mmio, SCALE_3D_CNTL, scale_3d_cntl ); + mach64_out32( mmio, SCALE_Y_OFF, mdev->scale_offset + + (srect->y >> 16) * mdev->scale_pitch + + (srect->x >> 16) * DFB_BYTES_PER_PIXEL( source->config.format ) ); + + + mach64_out32( mmio, SCALE_WIDTH, (srect->w + hacc) >> 16 ); + mach64_out32( mmio, SCALE_HEIGHT, (srect->h + vacc) >> 16 ); + + mach64_out32( mmio, SCALE_Y_PITCH, mdev->scale_pitch / DFB_BYTES_PER_PIXEL( source->config.format ) ); + + mach64_out32( mmio, SCALE_X_INC, srect->w / drect->w ); + mach64_out32( mmio, SCALE_Y_INC, srect->h / drect->h ); + + if (mdev->blit_deinterlace && mdev->field) + vacc += 0x8000; + + mach64_out32( mmio, SCALE_VACC, vacc ); + mach64_out32( mmio, SCALE_HACC, hacc ); + mach64_out32( mmio, SCALE_XUV_INC, (srect->w/2) / (drect->w/2) ); + mach64_out32( mmio, SCALE_UV_HACC, hacc >> 1 ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( drect->x ) << 16) | S14( drect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (drect->w << 16) | drect->h ); + + /* Some scaler and 3D color registers are shared. */ + MACH64_INVALIDATE( m_color_3d | m_color_tex ); +} + +static void mach64DoBlitScale( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *source = mdev->source; + + u32 scale_3d_cntl = SCALE_3D_FCN_SCALE | mdev->blit_blend; + int hacc, vacc; + + if (!filter) + scale_3d_cntl |= SCALE_PIX_REP; + + if (mdev->blit_deinterlace) { + srect->y /= 2; + srect->h /= 2; + } + + srect->x <<= 16; + srect->y <<= 16; + srect->w <<= 16; + srect->h <<= 16; + + /* Hardware bug: Hitting SC_TOP results in incorrect rendering. */ + if (drect->y < mdev->clip.y1) { + int sy, dy; + dy = mdev->clip.y1 - drect->y; + sy = (u64) srect->h * dy / drect->h; + srect->y += sy; + srect->h -= sy; + drect->y += dy; + drect->h -= dy; + } + + /* + * SCALE_HACC and SCALE_VACC have limited scale so we need to change + * SCALE_OFF in order to handle the full range of source coordinates. + */ + hacc = srect->x & 0xFFFFF0; /* s8.12 */ + vacc = srect->y & 0xFFFF0; /* s4.12 */ + srect->x &= ~0xFFFFFF; + srect->y &= ~0xFFFFF; + + mach64_waitfifo( mdrv, mdev, 12 ); + + mach64_out32( mmio, SCALE_3D_CNTL, scale_3d_cntl ); + mach64_out32( mmio, SCALE_OFF, mdev->scale_offset + + (srect->y >> 16) * mdev->scale_pitch + + (srect->x >> 16) * DFB_BYTES_PER_PIXEL( source->config.format ) ); + + mach64_out32( mmio, SCALE_WIDTH, (srect->w + hacc) >> 16 ); + mach64_out32( mmio, SCALE_HEIGHT, (srect->h + vacc) >> 16 ); + + mach64_out32( mmio, SCALE_PITCH, mdev->scale_pitch / DFB_BYTES_PER_PIXEL( source->config.format ) ); + + mach64_out32( mmio, SCALE_X_INC, srect->w / drect->w ); + mach64_out32( mmio, SCALE_Y_INC, srect->h / drect->h ); + + if (mdev->blit_deinterlace && mdev->field) + vacc += 0x8000; + + mach64_out32( mmio, SCALE_VACC, vacc ); + mach64_out32( mmio, SCALE_HACC, hacc ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( drect->x ) << 16) | S14( drect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (drect->w << 16) | drect->h ); + + /* Some scaler and 3D color registers are shared. */ + MACH64_INVALIDATE( m_color_3d | m_color_tex ); +} + +static void mach64DoBlitTexOld( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 scale_3d_cntl = SCALE_3D_FCN_TEXTURE | MIP_MAP_DISABLE | mdev->blit_blend; + + if (mdev->blit_deinterlace) { + srect->y /= 2; + srect->h /= 2; + } + + srect->x <<= 1; + srect->y <<= 1; + srect->w <<= 1; + srect->h <<= 1; + + /* Must add 0.5 to get correct rendering. */ + srect->x += 0x1; + srect->y += 0x1; + + if (filter) { + /* Avoid using texels outside of texture. */ + srect->w -= 0x2; + srect->h -= 0x2; + + scale_3d_cntl |= BILINEAR_TEX_EN | TEX_BLEND_FCN_LINEAR_MIPMAP_NEAREST; + } + + if (mdev->blit_deinterlace && mdev->field) + srect->y += 0x1; + + mach64_waitfifo( mdrv, mdev, 14 ); + + mach64_out32( mmio, SCALE_3D_CNTL, scale_3d_cntl ); + mach64_out32( mmio, TEX_0_OFF + (mdev->tex_size << 2), mdev->tex_offset ); + + mach64_out32( mmio, S_X_INC2, 0 ); + mach64_out32( mmio, S_Y_INC2, 0 ); + mach64_out32( mmio, S_XY_INC2, 0 ); + mach64_out32( mmio, S_X_INC_START, (srect->w << (25 - mdev->tex_size)) / drect->w ); + mach64_out32( mmio, S_Y_INC, 0 ); + mach64_out32( mmio, S_START, (srect->x << (25 - mdev->tex_size)) ); + + mach64_out32( mmio, T_X_INC2, 0 ); + mach64_out32( mmio, T_Y_INC2, 0 ); + mach64_out32( mmio, T_XY_INC2, 0 ); + mach64_out32( mmio, T_X_INC_START, 0 ); + mach64_out32( mmio, T_Y_INC, (srect->h << (25 - mdev->tex_size)) / drect->h ); + mach64_out32( mmio, T_START, (srect->y << (25 - mdev->tex_size)) ); + + mach64_waitfifo( mdrv, mdev, 3 ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( drect->x ) << 16) | S14( drect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (drect->w << 16) | drect->h ); +} + +static void mach64DoBlitTex( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 scale_3d_cntl = SCALE_3D_FCN_TEXTURE | MIP_MAP_DISABLE | mdev->blit_blend; + + if (mdev->blit_deinterlace) { + srect->y /= 2; + srect->h /= 2; + } + + srect->x <<= 1; + srect->y <<= 1; + srect->w <<= 1; + srect->h <<= 1; + + /* Must add 0.5 to get correct rendering. */ + srect->x += 0x1; + srect->y += 0x1; + + if (filter) { + /* Avoid using texels outside of texture. */ + srect->w -= 0x2; + srect->h -= 0x2; + + scale_3d_cntl |= BILINEAR_TEX_EN | TEX_BLEND_FCN_LINEAR_MIPMAP_NEAREST; + } + + if (mdev->blit_deinterlace && mdev->field) + srect->y += 0x1; + + mach64_waitfifo( mdrv, mdev, 13 ); + + mach64_out32( mmio, SCALE_3D_CNTL, scale_3d_cntl ); + mach64_out32( mmio, TEX_0_OFF + (mdev->tex_size << 2), mdev->tex_offset ); + + mach64_out32( mmio, STW_EXP, (1 << 16) | (0 << 8) | (0 << 0) ); + + /* This register doesn't seem to have any effect on the result. */ + mach64_out32( mmio, LOG_MAX_INC, 0 ); + + mach64_out32( mmio, S_X_INC, (srect->w << (23 - mdev->tex_pitch)) / drect->w ); + mach64_out32( mmio, S_Y_INC, 0 ); + mach64_out32( mmio, S_START, (srect->x << (23 - mdev->tex_pitch)) ); + + mach64_out32( mmio, W_X_INC, 0 ); + mach64_out32( mmio, W_Y_INC, 0 ); + mach64_out32( mmio, W_START, 1 << 23 ); + + mach64_out32( mmio, T_X_INC, 0 ); + mach64_out32( mmio, T_Y_INC, (srect->h << (23 - mdev->tex_height)) / drect->h ); + mach64_out32( mmio, T_START, (srect->y << (23 - mdev->tex_height)) ); + + mach64_waitfifo( mdrv, mdev, 3 ); + + mach64_out32( mmio, DST_CNTL, DST_X_DIR | DST_Y_DIR ); + mach64_out32( mmio, DST_Y_X, (S13( drect->x ) << 16) | S14( drect->y ) ); + mach64_out32( mmio, DST_HEIGHT_WIDTH, (drect->w << 16) | drect->h ); +} + +static bool mach64Blit2D( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + mach64DoBlit2D( mdrv, mdev, rect, &drect ); + + return true; +} + +static bool mach64BlitScaleOld( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + mach64DoBlitScaleOld( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool mach64StretchBlitScaleOld( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64DoBlitScaleOld( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool mach64BlitScale( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + mach64DoBlitScale( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool mach64StretchBlitScale( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64DoBlitScale( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool mach64BlitTexOld( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + mach64DoBlitTexOld( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool mach64StretchBlitTexOld( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64DoBlitTexOld( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool mach64BlitTex( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + mach64DoBlitTex( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool mach64StretchBlitTex( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) drv; + Mach64DeviceData *mdev = (Mach64DeviceData*) dev; + + mach64DoBlitTex( mdrv, mdev, srect, drect, true ); + + return true; +} + +/* */ + +#define MACH64_CFG_CHIP_TYPE( a, b ) (((a) << 8) | (b)) + +static Mach64ChipType +mach64_chip_type_vt( Mach64DriverData *mdrv, + GraphicsDeviceInfo *device_info ) +{ + u32 config_chip_id = mach64_in32( mdrv->mmio_base, CONFIG_CHIP_ID ); + u32 cfg_chip_type = config_chip_id & CFG_CHIP_TYPE; + + switch (cfg_chip_type) { + case MACH64_CFG_CHIP_TYPE( 'V', 'T' ): + switch ((config_chip_id & CFG_CHIP_MAJOR) >> 24) { + case 0: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, + (config_chip_id & CFG_CHIP_MINOR) ? "ATI-264VT2 (%c%c)" : "ATI-264VT (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_264VT; + case 1: + case 2: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "ATI-264VT3 (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_264VT3; + } + break; + case MACH64_CFG_CHIP_TYPE( 'V', 'U' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "ATI-264VT3 (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_264VT3; + case MACH64_CFG_CHIP_TYPE( 'V', 'V' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "ATI-264VT4 (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_264VT4; + } + D_WARN( "DirectFB/Mach64: Unknown VT chip type %c%c (0x%08x)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF, config_chip_id ); + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Mach64 VT" ); + return CHIP_UNKNOWN; +} + +static Mach64ChipType +mach64_chip_type_gt( Mach64DriverData *mdrv, + GraphicsDeviceInfo *device_info ) +{ + u32 config_chip_id = mach64_in32( mdrv->mmio_base, CONFIG_CHIP_ID ); + u32 cfg_chip_type = config_chip_id & CFG_CHIP_TYPE; + + switch (cfg_chip_type) { + case MACH64_CFG_CHIP_TYPE( 'G', 'T' ): + switch ((config_chip_id & CFG_CHIP_MAJOR) >> 24) { + case 0: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE; + case 1: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage II (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_II; + case 2: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage II+ (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_IIPLUS; + } + break; + case MACH64_CFG_CHIP_TYPE( 'G', 'U' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage II+ (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_IIPLUS; + case MACH64_CFG_CHIP_TYPE( 'L', 'G' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage LT (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_LT; + case MACH64_CFG_CHIP_TYPE( 'G', 'V' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'W' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'Y' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'Z' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage IIC (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_IIC; + case MACH64_CFG_CHIP_TYPE( 'G', 'B' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'D' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'I' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'P' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'Q' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage Pro (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_PRO; + case MACH64_CFG_CHIP_TYPE( 'L', 'B' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'D' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'I' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'P' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'Q' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage LT Pro (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_LT_PRO; + case MACH64_CFG_CHIP_TYPE( 'G', 'M' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'O' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'R' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage XL (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_XLXC; + case MACH64_CFG_CHIP_TYPE( 'G', 'L' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'N' ): + case MACH64_CFG_CHIP_TYPE( 'G', 'S' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage XC (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_XLXC; + case MACH64_CFG_CHIP_TYPE( 'L', 'M' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'N' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'R' ): + case MACH64_CFG_CHIP_TYPE( 'L', 'S' ): + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "3D Rage Mobility (%c%c)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF ); + return CHIP_3D_RAGE_MOBILITY; + } + D_WARN( "DirectFB/Mach64: Unknown GT chip type %c%c (0x%08x)", + cfg_chip_type >> 8, cfg_chip_type & 0xFF, config_chip_id ); + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Mach64 GT" ); + return CHIP_UNKNOWN; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_ATI_MACH64GX: + case FB_ACCEL_ATI_MACH64CT: + case FB_ACCEL_ATI_MACH64VT: + case FB_ACCEL_ATI_MACH64GT: + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "ATI Mach64 Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Ville Syrjala" ); + + info->version.major = 0; + info->version.minor = 13; + + info->driver_data_size = sizeof (Mach64DriverData); + info->device_data_size = sizeof (Mach64DeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + + mdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!mdrv->mmio_base) + return DFB_IO; + + mdrv->device_data = (Mach64DeviceData*) device_data; + + mdrv->accelerator = dfb_gfxcard_get_accelerator( device ); + + funcs->EngineReset = mach64EngineReset; + funcs->EngineSync = mach64EngineSync; + funcs->CheckState = mach64CheckState; + funcs->SetState = mach64SetState; + funcs->FillRectangle = mach64FillRectangle; + funcs->DrawRectangle = mach64DrawRectangle; + + /* Set dynamically: funcs->DrawLine, funcs->Blit, funcs->StretchBlit */ + + switch (mdrv->accelerator) { + case FB_ACCEL_ATI_MACH64GT: + if (!dfb_config->font_format) + dfb_config->font_format = DSPF_ARGB; + funcs->FlushTextureCache = mach64FlushTextureCache; + funcs->CheckState = mach64GTCheckState; + funcs->SetState = mach64GTSetState; + funcs->FillTriangle = mach64FillTriangle; + case FB_ACCEL_ATI_MACH64VT: + mdrv->mmio_base += 0x400; + + dfb_layers_register( dfb_screens_at( DSCID_PRIMARY ), + driver_data, &mach64OverlayFuncs ); + break; + } + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = (Mach64DeviceData*) device_data; + volatile u8 *mmio = mdrv->mmio_base; + + /* fill device info */ + device_info->caps.flags = CCF_CLIPPING; + + switch (mdrv->accelerator) { + case FB_ACCEL_ATI_MACH64GT: + device_info->caps.drawing = MACH64GT_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = MACH64GT_SUPPORTED_BLITTINGFLAGS; + device_info->caps.accel = MACH64GT_SUPPORTED_DRAWINGFUNCTIONS | + MACH64GT_SUPPORTED_BLITTINGFUNCTIONS; + break; + default: + device_info->caps.drawing = MACH64_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = MACH64_SUPPORTED_BLITTINGFLAGS; + device_info->caps.accel = MACH64_SUPPORTED_DRAWINGFUNCTIONS | + MACH64_SUPPORTED_BLITTINGFUNCTIONS; + break; + } + + switch (mdrv->accelerator) { + case FB_ACCEL_ATI_MACH64GX: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Mach64 GX" ); + break; + case FB_ACCEL_ATI_MACH64CT: + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Mach64 CT" ); + break; + case FB_ACCEL_ATI_MACH64VT: + mdev->chip = mach64_chip_type_vt( mdrv, device_info ); + break; + case FB_ACCEL_ATI_MACH64GT: + mdev->chip = mach64_chip_type_gt( mdrv, device_info ); + + /* Max texture size is 1024x1024 */ + device_info->limits.surface_max_power_of_two_pixelpitch = 1024; + device_info->limits.surface_max_power_of_two_height = 1024; + break; + } + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "ATI" ); + + device_info->limits.surface_byteoffset_alignment = 8; + device_info->limits.surface_bytepitch_alignment = 16; + device_info->limits.surface_pixelpitch_alignment = 8; + + /* 3D Rage Pro is the first chip that supports auto fast fill/block write. */ + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + mdev->hw_debug = mach64_in32( mmio, HW_DEBUG ); + + /* Save original HW_DEBUG. */ + mdev->hw_debug_orig = mdev->hw_debug; + + /* Enable auto fast fill and fast fill/block write scissoring. */ + mdev->hw_debug &= ~(AUTO_FF_DIS | INTER_PRIM_DIS); + + if ((mach64_in32( mmio, CONFIG_STAT0 ) & CFG_MEM_TYPE) == CFG_MEM_TYPE_SGRAM) { + /* Enable auto block write and auto color register updates. */ + mdev->hw_debug &= ~(AUTO_BLKWRT_DIS | AUTO_BLKWRT_COLOR_DIS); + + device_info->limits.surface_byteoffset_alignment = 64; + device_info->limits.surface_bytepitch_alignment = 64; + } + } + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = (Mach64DeviceData*) device_data; + volatile u8 *mmio = mdrv->mmio_base; + + D_DEBUG( "DirectFB/Mach64: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/Mach64: %9d mach64_waitfifo calls\n", + mdev->waitfifo_calls ); + D_DEBUG( "DirectFB/Mach64: %9d register writes (mach64_waitfifo sum)\n", + mdev->waitfifo_sum ); + D_DEBUG( "DirectFB/Mach64: %9d FIFO wait cycles (depends on CPU)\n", + mdev->fifo_waitcycles ); + D_DEBUG( "DirectFB/Mach64: %9d IDLE wait cycles (depends on CPU)\n", + mdev->idle_waitcycles ); + D_DEBUG( "DirectFB/Mach64: %9d FIFO space cache hits(depends on CPU)\n", + mdev->fifo_cache_hits ); + D_DEBUG( "DirectFB/Mach64: Conclusion:\n" ); + D_DEBUG( "DirectFB/Mach64: Average register writes/mach64_waitfifo" + "call:%.2f\n", + mdev->waitfifo_sum/(float)(mdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/Mach64: Average wait cycles/mach64_waitfifo call:" + " %.2f\n", + mdev->fifo_waitcycles/(float)(mdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/Mach64: Average fifo space cache hits: %02d%%\n", + (int)(100 * mdev->fifo_cache_hits/ + (float)(mdev->waitfifo_calls)) ); + + switch (mdrv->accelerator) { + case FB_ACCEL_ATI_MACH64GT: + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, SCALE_3D_CNTL, 0 ); + case FB_ACCEL_ATI_MACH64VT: + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, OVERLAY_SCALE_CNTL, 0 ); + break; + } + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + /* Restore original HW_DEBUG. */ + mach64_out32( mmio, HW_DEBUG, mdev->hw_debug_orig ); + } +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + + switch (mdrv->accelerator) { + case FB_ACCEL_ATI_MACH64VT: + case FB_ACCEL_ATI_MACH64GT: + mdrv->mmio_base -= 0x400; + break; + } + + dfb_gfxcard_unmap_mmio( device, mdrv->mmio_base, -1 ); +} diff --git a/Source/DirectFB/gfxdrivers/mach64/mach64.h b/Source/DirectFB/gfxdrivers/mach64/mach64.h new file mode 100755 index 0000000..86e4b68 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mach64.h @@ -0,0 +1,120 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___MACH64_H__ +#define ___MACH64_H__ + +#include +#include +#include + +#define S13( val ) ((val) & 0x3FFF) +#define S14( val ) ((val) & 0x7FFF) + +typedef enum { + m_source = 0x001, + m_source_scale = 0x002, + m_color = 0x004, + m_color_3d = 0x008, + m_color_tex = 0x010, + m_srckey = 0x020, + m_srckey_scale = 0x040, + m_dstkey = 0x080, + m_disable_key = 0x100, + m_draw_blend = 0x200, + m_blit_blend = 0x400, +} Mach64StateBits; + +#define MACH64_VALIDATE(b) (mdev->valid |= (b)) +#define MACH64_INVALIDATE(b) (mdev->valid &= ~(b)) +#define MACH64_IS_VALID(b) (mdev->valid & (b)) + +typedef enum { + CHIP_UNKNOWN = 0, + CHIP_264VT, + CHIP_3D_RAGE, + CHIP_264VT3, + CHIP_3D_RAGE_II, + CHIP_3D_RAGE_IIPLUS, + CHIP_3D_RAGE_LT, + CHIP_264VT4, + CHIP_3D_RAGE_IIC, + CHIP_3D_RAGE_PRO, + CHIP_3D_RAGE_LT_PRO, + CHIP_3D_RAGE_XLXC, + CHIP_3D_RAGE_MOBILITY, +} Mach64ChipType; + +typedef struct { + Mach64ChipType chip; + + /* for fifo/performance monitoring */ + unsigned int fifo_space; + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; + + Mach64StateBits valid; + + u32 hw_debug; + u32 hw_debug_orig; + + u32 pix_width; + + u32 draw_blend; + u32 blit_blend; + + int tex_offset; + int tex_pitch; + int tex_height; + int tex_size; + + int scale_offset; + int scale_pitch; + + CoreSurface *source; + + bool blit_deinterlace; + int field; + + DFBRegion clip; + + bool use_scaler_3d; +} Mach64DeviceData; + +typedef struct { + int accelerator; + volatile u8 *mmio_base; + Mach64DeviceData *device_data; +} Mach64DriverData; + +extern DisplayLayerFuncs mach64OverlayFuncs; + +#endif diff --git a/Source/DirectFB/gfxdrivers/mach64/mach64_overlay.c b/Source/DirectFB/gfxdrivers/mach64/mach64_overlay.c new file mode 100755 index 0000000..11cff28 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mach64_overlay.c @@ -0,0 +1,724 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include +#include +#include + +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "mach64.h" + +typedef struct { + CoreLayerRegionConfig config; + bool visible; + + /* overlay registers */ + struct { + u32 overlay_Y_X_START; + u32 overlay_Y_X_END; + u32 overlay_GRAPHICS_KEY_CLR; + u32 overlay_GRAPHICS_KEY_MSK; + u32 overlay_VIDEO_KEY_CLR; + u32 overlay_VIDEO_KEY_MSK; + u32 overlay_KEY_CNTL; + u32 overlay_SCALE_INC; + u32 overlay_SCALE_CNTL; + u32 scaler_HEIGHT_WIDTH; + u32 scaler_BUF_PITCH; + u32 scaler_BUF0_OFFSET; + u32 scaler_BUF1_OFFSET; + u32 scaler_BUF0_OFFSET_U; + u32 scaler_BUF0_OFFSET_V; + u32 scaler_BUF1_OFFSET_U; + u32 scaler_BUF1_OFFSET_V; + u32 video_FORMAT; + u32 capture_CONFIG; + } regs; +} Mach64OverlayLayerData; + +static void ov_reset( Mach64DriverData *mdrv ); +static void ov_set_regs( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov ); +static void ov_calc_regs( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config, CoreSurface *surface, + CoreSurfaceBufferLock *lock ); +static void ov_set_buffer( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov ); +static void ov_calc_buffer( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config, CoreSurface *surface, + CoreSurfaceBufferLock *lock ); +static void ov_set_colorkey( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov ); +static void ov_calc_colorkey( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config ); +static void ov_set_opacity( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov ); +static void ov_calc_opacity( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config ); +static void ov_set_field( Mach64DriverData *mdrv, Mach64OverlayLayerData *mov ); + +#define OV_SUPPORTED_OPTIONS (DLOP_SRC_COLORKEY | DLOP_DST_COLORKEY | DLOP_DEINTERLACING) + +/**********************/ + +static int +ovLayerDataSize( void ) +{ + return sizeof(Mach64OverlayLayerData); +} + +static DFBResult +ovInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = mdrv->device_data; + + /* set capabilities and type */ + description->caps = DLCAPS_SCREEN_LOCATION | DLCAPS_SURFACE | + DLCAPS_DST_COLORKEY | DLCAPS_DEINTERLACING; + + if (mdev->chip >= CHIP_264VT3) + description->caps |= DLCAPS_SRC_COLORKEY; + + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Mach64 Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = (mdev->chip >= CHIP_264VT3) ? 640 : 320; + config->height = (mdev->chip >= CHIP_264VT3) ? 480 : 240; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + adjustment->flags = DCAF_NONE; + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + description->caps |= DLCAPS_BRIGHTNESS | DLCAPS_SATURATION; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags |= DCAF_BRIGHTNESS | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->saturation = 0x8000; + } + + return DFB_OK; +} + +static DFBResult +ovTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = mdrv->device_data; + CoreLayerRegionConfigFlags fail = 0; + int max_width, max_height = 1024; + + switch (mdev->chip) { + case CHIP_264VT: /* 264VT2 verified */ + case CHIP_3D_RAGE: /* not verified */ + max_width = 384; + break; + case CHIP_264VT3: /* not verified */ + case CHIP_3D_RAGE_II: /* not verified */ + case CHIP_3D_RAGE_IIPLUS: + case CHIP_264VT4: /* not verified */ + case CHIP_3D_RAGE_IIC: + case CHIP_3D_RAGE_XLXC: + case CHIP_3D_RAGE_MOBILITY: + max_width = 720; + break; + case CHIP_3D_RAGE_PRO: /* not verified */ + case CHIP_3D_RAGE_LT_PRO: + max_width = 768; + break; + default: + D_BUG( "unknown chip" ); + return DFB_UNSUPPORTED; + } + + if (config->options & DLOP_DEINTERLACING) + max_height = 2048; + + /* check for unsupported options */ + if (config->options & ~OV_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* + * Video keying doesn't work the same way on 264VT2 as it does + * on later chips. If enabled the overlay goes completely black + * so clearly it does something but not what we want. + */ + if (mdev->chip < CHIP_264VT3 && config->options & DLOP_SRC_COLORKEY) + fail |= CLRCF_OPTIONS; + + /* check pixel format */ + switch (config->format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_YUY2: + case DSPF_UYVY: + break; + case DSPF_I420: + case DSPF_YV12: + if (mdev->chip >= CHIP_3D_RAGE_PRO) + break; + default: + fail |= CLRCF_FORMAT; + } + + switch (config->format) { + case DSPF_I420: + case DSPF_YV12: + if (config->height & 1) + fail |= CLRCF_HEIGHT; + case DSPF_YUY2: + case DSPF_UYVY: + if (config->width & 1) + fail |= CLRCF_WIDTH; + default: + break; + } + + /* check width */ + if (config->width > max_width || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > max_height || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ovSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64OverlayLayerData *mov = (Mach64OverlayLayerData*) layer_data; + + /* remember configuration */ + mov->config = *config; + + if (updated == CLRCF_ALL) + ov_reset( mdrv ); + + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS)) { + ov_calc_buffer( mdrv, mov, config, surface, lock ); + ov_calc_regs( mdrv, mov, config, surface, lock ); + ov_set_buffer( mdrv, mov ); + ov_set_regs( mdrv, mov ); + } + + if (updated & (CLRCF_OPTIONS | CLRCF_SRCKEY | CLRCF_DSTKEY)) { + ov_calc_colorkey( mdrv, mov, config ); + ov_set_colorkey( mdrv, mov ); + } + + if (updated & CLRCF_OPTIONS) + ov_set_field( mdrv, mov ); + + if (updated & (CLRCF_DEST | CLRCF_OPACITY)) { + ov_calc_opacity( mdrv, mov, config ); + ov_set_opacity( mdrv, mov ); + } + + return DFB_OK; +} + +static DFBResult +ovRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 2 ); + + /* + * On 264VT2 the keyer sometimes remains active + * even after the overlay has been disabled. + */ + mach64_out32( mmio, OVERLAY_KEY_CNTL, + VIDEO_KEY_FN_FALSE | GRAPHICS_KEY_FN_FALSE | OVERLAY_CMP_MIX_OR ); + + mach64_out32( mmio, OVERLAY_SCALE_CNTL, 0 ); + + return DFB_OK; +} + +static DFBResult +ovFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64OverlayLayerData *mov = (Mach64OverlayLayerData*) layer_data; + + ov_calc_buffer( mdrv, mov, &mov->config, surface, lock ); + ov_set_buffer( mdrv, mov ); + + dfb_surface_flip( surface, false ); + + return DFB_OK; +} + +static DFBResult +ovSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + if (mdev->chip < CHIP_3D_RAGE_PRO) + return DFB_UNSUPPORTED; + + mach64_waitfifo( mdrv, mdev, 1 ); + + mach64_out32( mmio, SCALER_COLOUR_CNTL, + (((adj->brightness >> 9) - 64) & 0x0000007F) | + ((adj->saturation >> 3) & 0x00001F00) | + ((adj->saturation << 5) & 0x001F0000) ); + + return DFB_OK; +} + +static DFBResult +ovSetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + Mach64DriverData *mdrv = (Mach64DriverData*) driver_data; + Mach64OverlayLayerData *mov = (Mach64OverlayLayerData*) layer_data; + + mov->regs.capture_CONFIG = OVL_BUF_MODE_SINGLE | (field ? OVL_BUF_NEXT_BUF1 : OVL_BUF_NEXT_BUF0); + + ov_set_field( mdrv, mov ); + + return DFB_OK; +} + +DisplayLayerFuncs mach64OverlayFuncs = { + .LayerDataSize = ovLayerDataSize, + .InitLayer = ovInitLayer, + + .TestRegion = ovTestRegion, + .SetRegion = ovSetRegion, + .RemoveRegion = ovRemoveRegion, + .FlipRegion = ovFlipRegion, + .SetColorAdjustment = ovSetColorAdjustment, + .SetInputField = ovSetInputField, +}; + +/* internal */ + +static void ov_reset( Mach64DriverData *mdrv ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + mach64_waitfifo( mdrv, mdev, 6 ); + + mach64_out32( mmio, SCALER_H_COEFF0, 0x00002000 ); + mach64_out32( mmio, SCALER_H_COEFF1, 0x0D06200D ); + mach64_out32( mmio, SCALER_H_COEFF2, 0x0D0A1C0D ); + mach64_out32( mmio, SCALER_H_COEFF3, 0x0C0E1A0C ); + mach64_out32( mmio, SCALER_H_COEFF4, 0x0C14140C ); + mach64_out32( mmio, SCALER_COLOUR_CNTL, 0x00101000 ); + } + + if (mdev->chip >= CHIP_264VT3) { + mach64_waitfifo( mdrv, mdev, 2 ); + + mach64_out32( mmio, OVERLAY_EXCLUSIVE_HORZ, 0 ); + mach64_out32( mmio, OVERLAY_EXCLUSIVE_VERT, 0 ); + } + + mach64_waitfifo( mdrv, mdev, 2 ); + + mach64_out32( mmio, OVERLAY_SCALE_CNTL, 0 ); + mach64_out32( mmio, SCALER_TEST, 0 ); +} + +static void ov_set_regs( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, (mdev->chip >= CHIP_264VT3) ? 6 : 7 ); + + mach64_out32( mmio, VIDEO_FORMAT, mov->regs.video_FORMAT ); + mach64_out32( mmio, OVERLAY_Y_X_START, mov->regs.overlay_Y_X_START ); + mach64_out32( mmio, OVERLAY_Y_X_END, mov->regs.overlay_Y_X_END ); + mach64_out32( mmio, OVERLAY_SCALE_INC, mov->regs.overlay_SCALE_INC ); + mach64_out32( mmio, SCALER_HEIGHT_WIDTH, mov->regs.scaler_HEIGHT_WIDTH ); + + if (mdev->chip >= CHIP_264VT3) { + mach64_out32( mmio, SCALER_BUF_PITCH, mov->regs.scaler_BUF_PITCH ); + } else { + mach64_out32( mmio, BUF0_PITCH, mov->regs.scaler_BUF_PITCH ); + mach64_out32( mmio, BUF1_PITCH, mov->regs.scaler_BUF_PITCH ); + } +} + +static void ov_set_buffer( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, (mdev->chip >= CHIP_3D_RAGE_PRO) ? 6 : 2 ); + + if (mdev->chip >= CHIP_264VT3) { + mach64_out32( mmio, SCALER_BUF0_OFFSET, mov->regs.scaler_BUF0_OFFSET ); + mach64_out32( mmio, SCALER_BUF1_OFFSET, mov->regs.scaler_BUF1_OFFSET ); + } else { + mach64_out32( mmio, BUF0_OFFSET, mov->regs.scaler_BUF0_OFFSET ); + mach64_out32( mmio, BUF1_OFFSET, mov->regs.scaler_BUF1_OFFSET ); + } + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + mach64_out32( mmio, SCALER_BUF0_OFFSET_U, mov->regs.scaler_BUF0_OFFSET_U ); + mach64_out32( mmio, SCALER_BUF0_OFFSET_V, mov->regs.scaler_BUF0_OFFSET_V ); + mach64_out32( mmio, SCALER_BUF1_OFFSET_U, mov->regs.scaler_BUF1_OFFSET_U ); + mach64_out32( mmio, SCALER_BUF1_OFFSET_V, mov->regs.scaler_BUF1_OFFSET_V ); + } +} + +static void ov_set_colorkey( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 5 ); + + mach64_out32( mmio, OVERLAY_GRAPHICS_KEY_CLR, mov->regs.overlay_GRAPHICS_KEY_CLR ); + mach64_out32( mmio, OVERLAY_GRAPHICS_KEY_MSK, mov->regs.overlay_GRAPHICS_KEY_MSK ); + mach64_out32( mmio, OVERLAY_VIDEO_KEY_CLR, mov->regs.overlay_VIDEO_KEY_CLR ); + mach64_out32( mmio, OVERLAY_VIDEO_KEY_MSK, mov->regs.overlay_VIDEO_KEY_MSK ); + mach64_out32( mmio, OVERLAY_KEY_CNTL, mov->regs.overlay_KEY_CNTL ); +} + +static void ov_set_opacity( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 1 ); + + mach64_out32( mmio, OVERLAY_SCALE_CNTL, mov->regs.overlay_SCALE_CNTL ); +} + +static void ov_set_field( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 1 ); + + mach64_out32( mmio, CAPTURE_CONFIG, mov->regs.capture_CONFIG ); +} + +static void ov_calc_regs( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + Mach64DeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + VideoMode *mode = dfb_system_current_mode(); + int yres = mode->yres; + unsigned int pitch = lock->pitch / DFB_BYTES_PER_PIXEL( surface->config.format ); + DFBRectangle source = config->source; + DFBRectangle dest = config->dest; + + DFBRegion dst; + int h_inc, v_inc; + u32 lcd_gen_ctrl, vert_stretching; + u8 ecp_div; + + if (mode->doubled) { + dest.y *= 2; + dest.h *= 2; + yres *= 2; + } + + if (config->options & DLOP_DEINTERLACING) { + source.y /= 2; + source.h /= 2; + pitch *= 2; + } else + mov->regs.capture_CONFIG = OVL_BUF_MODE_SINGLE | OVL_BUF_NEXT_BUF0; + + dst.x1 = dest.x; + dst.y1 = dest.y; + dst.x2 = dest.x + dest.w - 1; + dst.y2 = dest.y + dest.h - 1; + + mov->visible = dfb_region_intersect( &dst, 0, 0, mode->xres - 1, yres - 1 ); + + if (mode->laced) { + dest.y /= 2; + dest.h /= 2; + } + + ecp_div = (mach64_in_pll( mmio, PLL_VCLK_CNTL ) & ECP_DIV) >> 4; + h_inc = (source.w << (12 + ecp_div)) / dest.w; + + lcd_gen_ctrl = mach64_in_lcd( mdev, mmio, LCD_GEN_CTRL ); + vert_stretching = mach64_in_lcd( mdev, mmio, VERT_STRETCHING ); + if ((lcd_gen_ctrl & LCD_ON) && (vert_stretching & VERT_STRETCH_EN)) + v_inc = (source.h << 2) * (vert_stretching & VERT_STRETCH_RATIO0) / dest.h; + else + v_inc = (source.h << 12) / dest.h; + + switch (surface->config.format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + mov->regs.video_FORMAT = SCALER_IN_RGB15; + break; + case DSPF_RGB16: + mov->regs.video_FORMAT = SCALER_IN_RGB16; + break; + case DSPF_RGB32: + mov->regs.video_FORMAT = SCALER_IN_RGB32; + break; + case DSPF_UYVY: + mov->regs.video_FORMAT = SCALER_IN_YVYU422; + break; + case DSPF_YUY2: + mov->regs.video_FORMAT = SCALER_IN_VYUY422; + break; + case DSPF_I420: + case DSPF_YV12: + mov->regs.video_FORMAT = SCALER_IN_YUV12; + break; + default: + D_BUG( "unexpected pixelformat" ); + } + + mov->regs.scaler_HEIGHT_WIDTH = (source.w << 16) | source.h; + mov->regs.scaler_BUF_PITCH = pitch; + + mov->regs.overlay_Y_X_START = (dst.x1 << 16) | dst.y1 | OVERLAY_LOCK_START; + mov->regs.overlay_Y_X_END = (dst.x2 << 16) | dst.y2; + mov->regs.overlay_SCALE_INC = (h_inc << 16) | v_inc; +} + +static void ov_calc_buffer( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + unsigned int pitch = lock->pitch; + DFBRectangle source = config->source; + + u32 offset, offset_u, offset_v; + int cropleft, croptop; + + if (config->options & DLOP_DEINTERLACING) { + source.y /= 2; + source.h /= 2; + pitch *= 2; + } + + /* Source cropping */ + cropleft = source.x; + croptop = source.y; + + /* Add destination cropping */ + if (config->dest.x < 0) + cropleft += -config->dest.x * source.w / config->dest.w; + if (config->dest.y < 0) + croptop += -config->dest.y * source.h / config->dest.h; + + switch (surface->config.format) { + case DSPF_I420: + cropleft &= ~15; + croptop &= ~1; + + offset_u = lock->offset + surface->config.size.h * lock->pitch; + offset_v = offset_u + surface->config.size.h/2 * lock->pitch/2; + offset_u += croptop/2 * pitch/2 + cropleft/2; + offset_v += croptop/2 * pitch/2 + cropleft/2; + break; + + case DSPF_YV12: + cropleft &= ~15; + croptop &= ~1; + + offset_v = lock->offset + surface->config.size.h * lock->pitch; + offset_u = offset_v + surface->config.size.h/2 * lock->pitch/2; + offset_v += croptop/2 * pitch/2 + cropleft/2; + offset_u += croptop/2 * pitch/2 + cropleft/2; + break; + + default: + offset_u = 0; + offset_v = 0; + break; + } + + offset = lock->offset; + offset += croptop * pitch + cropleft * DFB_BYTES_PER_PIXEL( surface->config.format ); + + mov->regs.scaler_BUF0_OFFSET = offset; + mov->regs.scaler_BUF0_OFFSET_U = offset_u; + mov->regs.scaler_BUF0_OFFSET_V = offset_v; + + mov->regs.scaler_BUF1_OFFSET = offset + lock->pitch; + mov->regs.scaler_BUF1_OFFSET_U = offset_u + lock->pitch/2; + mov->regs.scaler_BUF1_OFFSET_V = offset_v + lock->pitch/2; +} + +static u32 ovColorKey[] = { + VIDEO_KEY_FN_TRUE | GRAPHICS_KEY_FN_TRUE | OVERLAY_CMP_MIX_OR, /* 0 */ + VIDEO_KEY_FN_NOT_EQUAL | GRAPHICS_KEY_FN_FALSE | OVERLAY_CMP_MIX_OR, /* DLOP_SRC_COLORKEY */ + VIDEO_KEY_FN_FALSE | GRAPHICS_KEY_FN_EQUAL | OVERLAY_CMP_MIX_OR, /* DLOP_DST_COLORKEY */ + VIDEO_KEY_FN_NOT_EQUAL | GRAPHICS_KEY_FN_EQUAL | OVERLAY_CMP_MIX_AND /* DLOP_SRC_COLORKEY | + DLOP_DST_COLORKEY */ +}; + +static void ov_calc_colorkey( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config ) +{ + DFBSurfacePixelFormat primary_format = dfb_primary_layer_pixelformat(); + + /* Video key is always RGB24 */ + mov->regs.overlay_VIDEO_KEY_CLR = PIXEL_RGB32( config->src_key.r, + config->src_key.g, + config->src_key.b ); + + /* The same mask is used for all three components */ + mov->regs.overlay_VIDEO_KEY_MSK = 0xFF; + + switch (primary_format) { + case DSPF_RGB332: + mov->regs.overlay_GRAPHICS_KEY_CLR = PIXEL_RGB332( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + case DSPF_RGB555: + mov->regs.overlay_GRAPHICS_KEY_CLR = PIXEL_RGB555( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + case DSPF_ARGB1555: + mov->regs.overlay_GRAPHICS_KEY_CLR = PIXEL_RGB555( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + case DSPF_RGB16: + mov->regs.overlay_GRAPHICS_KEY_CLR = PIXEL_RGB16( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + case DSPF_ARGB: + case DSPF_RGB32: + mov->regs.overlay_GRAPHICS_KEY_CLR = PIXEL_RGB32( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + default: + D_BUG( "unexpected pixelformat" ); + } + + mov->regs.overlay_GRAPHICS_KEY_MSK = (1 << DFB_COLOR_BITS_PER_PIXEL( primary_format )) - 1; + + mov->regs.overlay_KEY_CNTL = ovColorKey[(config->options >> 3) & 3]; +} + +static void ov_calc_opacity( Mach64DriverData *mdrv, + Mach64OverlayLayerData *mov, + CoreLayerRegionConfig *config ) +{ + mov->regs.overlay_SCALE_CNTL = SCALE_PIX_EXPAND | SCALE_Y2R_TEMP; + + if (config->opacity && mov->visible) + mov->regs.overlay_SCALE_CNTL |= OVERLAY_EN | SCALE_EN; +} diff --git a/Source/DirectFB/gfxdrivers/mach64/mach64_state.c b/Source/DirectFB/gfxdrivers/mach64/mach64_state.c new file mode 100755 index 0000000..8e798cc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mach64_state.c @@ -0,0 +1,654 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "mach64.h" + +#include "mach64_state.h" + + +void mach64_set_destination( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *destination = state->destination; + unsigned int pitch = state->dst.pitch / DFB_BYTES_PER_PIXEL( destination->config.format ); + + mdev->pix_width &= ~DST_PIX_WIDTH; + switch (destination->config.format) { + case DSPF_RGB332: + mdev->pix_width |= DST_PIX_WIDTH_8BPP; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mdev->pix_width |= DST_PIX_WIDTH_15BPP; + break; + case DSPF_RGB16: + mdev->pix_width |= DST_PIX_WIDTH_16BPP; + break; + case DSPF_RGB32: + case DSPF_ARGB: + mdev->pix_width |= DST_PIX_WIDTH_32BPP; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, DST_OFF_PITCH, (state->dst.offset/8) | ((pitch/8) << 22) ); +} + +void mach64gt_set_destination( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *destination = state->destination; + unsigned int pitch = state->dst.pitch / DFB_BYTES_PER_PIXEL( destination->config.format ); + + mdev->pix_width &= ~DST_PIX_WIDTH; + switch (destination->config.format) { + case DSPF_RGB332: + mdev->pix_width |= DST_PIX_WIDTH_RGB332; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mdev->pix_width |= DST_PIX_WIDTH_ARGB1555; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + mdev->pix_width |= DST_PIX_WIDTH_ARGB4444; + break; + case DSPF_RGB16: + mdev->pix_width |= DST_PIX_WIDTH_RGB565; + break; + case DSPF_RGB32: + case DSPF_ARGB: + mdev->pix_width |= DST_PIX_WIDTH_ARGB8888; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mdev->draw_blend &= ~DITHER_EN; + mdev->blit_blend &= ~DITHER_EN; + if (DFB_COLOR_BITS_PER_PIXEL( destination->config.format ) < 24) { + mdev->draw_blend |= DITHER_EN; + mdev->blit_blend |= DITHER_EN; + } + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, DST_OFF_PITCH, (state->dst.offset/8) | ((pitch/8) << 22) ); +} + +void mach64_set_source( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *source = state->source; + unsigned int pitch = state->src.pitch / DFB_BYTES_PER_PIXEL( source->config.format ); + + if (MACH64_IS_VALID( m_source )) + return; + + mdev->pix_width &= ~SRC_PIX_WIDTH; + switch (source->config.format) { + case DSPF_RGB332: + mdev->pix_width |= SRC_PIX_WIDTH_8BPP; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mdev->pix_width |= SRC_PIX_WIDTH_15BPP; + break; + case DSPF_RGB16: + mdev->pix_width |= SRC_PIX_WIDTH_16BPP; + break; + case DSPF_RGB32: + case DSPF_ARGB: + mdev->pix_width |= SRC_PIX_WIDTH_32BPP; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, SRC_OFF_PITCH, (state->src.offset/8) | ((pitch/8) << 22) ); + + MACH64_VALIDATE( m_source ); +} + +void mach64gt_set_source( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *source = state->source; + unsigned int pitch = state->src.pitch / DFB_BYTES_PER_PIXEL( source->config.format ); + + if (MACH64_IS_VALID( m_source )) + return; + + mdev->pix_width &= ~SRC_PIX_WIDTH; + switch (source->config.format) { + case DSPF_RGB332: + mdev->pix_width |= SRC_PIX_WIDTH_RGB332; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mdev->pix_width |= SRC_PIX_WIDTH_ARGB1555; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + mdev->pix_width |= SRC_PIX_WIDTH_ARGB4444; + break; + case DSPF_RGB16: + mdev->pix_width |= SRC_PIX_WIDTH_RGB565; + break; + case DSPF_RGB32: + case DSPF_ARGB: + mdev->pix_width |= SRC_PIX_WIDTH_ARGB8888; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, SRC_OFF_PITCH, (state->src.offset/8) | ((pitch/8) << 22) ); + + MACH64_VALIDATE( m_source ); +} + +void mach64gt_set_source_scale( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *source = state->source; + unsigned int offset = state->src.offset; + unsigned int pitch = state->src.pitch; + int height = source->config.size.h; + + if (MACH64_IS_VALID( m_source_scale )) + return; + + mdev->pix_width &= ~SCALE_PIX_WIDTH; + switch (source->config.format) { + case DSPF_RGB332: + mdev->pix_width |= SCALE_PIX_WIDTH_RGB332; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mdev->pix_width |= SCALE_PIX_WIDTH_ARGB1555; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + mdev->pix_width |= SCALE_PIX_WIDTH_ARGB4444; + break; + case DSPF_RGB16: + mdev->pix_width |= SCALE_PIX_WIDTH_RGB565; + break; + case DSPF_RGB32: + case DSPF_ARGB: + mdev->pix_width |= SCALE_PIX_WIDTH_ARGB8888; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mdev->blit_blend &= ~SCALE_PIX_EXPAND; + if (DFB_COLOR_BITS_PER_PIXEL( source->config.format ) < 24) + mdev->blit_blend |= SCALE_PIX_EXPAND; + + mdev->field = source->field; + if (mdev->blit_deinterlace) { + if (mdev->field) { + if (source->config.caps & DSCAPS_SEPARATED) { + offset += height/2 * pitch; + } else { + offset += pitch; + pitch *= 2; + } + } + height /= 2; + } + + mdev->source = source; + + mdev->scale_offset = offset; + mdev->scale_pitch = pitch; + + mdev->tex_offset = offset; + mdev->tex_pitch = direct_log2( pitch / DFB_BYTES_PER_PIXEL( source->config.format ) ); + mdev->tex_height = direct_log2( height ); + mdev->tex_size = MAX( mdev->tex_pitch, mdev->tex_height ); + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, TEX_SIZE_PITCH, (mdev->tex_pitch << 0) | + (mdev->tex_size << 4) | + (mdev->tex_height << 8) ); + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, TEX_CNTL, TEX_CACHE_FLUSH ); + } + + MACH64_VALIDATE( m_source_scale ); +} + +void mach64_set_clip( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mach64_waitfifo( mdrv, mdev, 2 ); + mach64_out32( mmio, SC_LEFT_RIGHT, (S13( state->clip.x2 ) << 16) | S13( state->clip.x1 ) ); + mach64_out32( mmio, SC_TOP_BOTTOM, (S14( state->clip.y2 ) << 16) | S14( state->clip.y1 ) ); +} + +void mach64_set_color( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + DFBColor color = state->color; + u32 clr; + + if (MACH64_IS_VALID( m_color )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } + + switch (state->destination->config.format) { + case DSPF_RGB332: + clr = PIXEL_RGB332( color.r, + color.g, + color.b ); + break; + case DSPF_RGB555: + clr = PIXEL_RGB555( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB1555: + clr = PIXEL_ARGB1555( color.a, + color.r, + color.g, + color.b ); + break; + case DSPF_RGB444: + clr = PIXEL_RGB444( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB4444: + clr = PIXEL_ARGB4444( color.a, + color.r, + color.g, + color.b ); + break; + case DSPF_RGB16: + clr = PIXEL_RGB16( color.r, + color.g, + color.b ); + break; + case DSPF_RGB32: + clr = PIXEL_RGB32( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB: + clr = PIXEL_ARGB( color.a, + color.r, + color.g, + color.b ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, DP_FRGD_CLR, clr ); + + MACH64_VALIDATE( m_color ); +} + +void mach64_set_color_3d( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + DFBColor color = state->color; + + if (MACH64_IS_VALID( m_color_3d )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } + + /* Some 3D color registers scaler registers are shared. */ + mach64_waitfifo( mdrv, mdev, 7 ); + mach64_out32( mmio, RED_X_INC, 0 ); + mach64_out32( mmio, RED_START, color.r << 16 ); + mach64_out32( mmio, GREEN_X_INC, 0 ); + mach64_out32( mmio, GREEN_START, color.g << 16 ); + mach64_out32( mmio, BLUE_X_INC, 0 ); + mach64_out32( mmio, BLUE_START, color.b << 16 ); + mach64_out32( mmio, ALPHA_START, color.a << 16 ); + + MACH64_INVALIDATE( m_color_tex | m_blit_blend ); + MACH64_VALIDATE( m_color_3d ); +} + +void mach64_set_color_tex( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + DFBColor color = state->color; + + if (MACH64_IS_VALID( m_color_tex )) + return; + + if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + if (state->blittingflags & DSBLIT_COLORIZE) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } else { + color.r = color.g = color.b = color.a; + } + } + + /* Some 3D color registers scaler registers are shared. */ + mach64_waitfifo( mdrv, mdev, 7 ); + mach64_out32( mmio, RED_X_INC, 0 ); + mach64_out32( mmio, RED_START, color.r << 16 ); + mach64_out32( mmio, GREEN_X_INC, 0 ); + mach64_out32( mmio, GREEN_START, color.g << 16 ); + mach64_out32( mmio, BLUE_X_INC, 0 ); + mach64_out32( mmio, BLUE_START, color.b << 16 ); + mach64_out32( mmio, ALPHA_START, color.a << 16 ); + + MACH64_INVALIDATE( m_color_3d | m_blit_blend ); + MACH64_VALIDATE( m_color_tex ); +} + +void mach64_set_src_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (MACH64_IS_VALID( m_srckey )) + return; + + mach64_waitfifo( mdrv, mdev, 3 ); + mach64_out32( mmio, CLR_CMP_MSK, + (1 << DFB_COLOR_BITS_PER_PIXEL( state->source->config.format )) - 1 ); + mach64_out32( mmio, CLR_CMP_CLR, state->src_colorkey ); + mach64_out32( mmio, CLR_CMP_CNTL, CLR_CMP_FN_EQUAL | CLR_CMP_SRC_2D ); + + MACH64_VALIDATE( m_srckey ); + MACH64_INVALIDATE( m_srckey_scale | m_dstkey | m_disable_key ); +} + +void mach64_set_src_colorkey_scale( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + u32 clr, msk; + + if (MACH64_IS_VALID( m_srckey_scale )) + return; + + if (mdev->chip < CHIP_3D_RAGE_PRO) { + switch (state->source->config.format) { + case DSPF_RGB332: + clr = ((state->src_colorkey & 0xE0) << 16) | + ((state->src_colorkey & 0x1C) << 11) | + ((state->src_colorkey & 0x03) << 6); + msk = 0xE0E0C0; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + clr = ((state->src_colorkey & 0x0F00) << 12) | + ((state->src_colorkey & 0x00F0) << 8) | + ((state->src_colorkey & 0x000F) << 4); + msk = 0xF0F0F0; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + clr = ((state->src_colorkey & 0x7C00) << 9) | + ((state->src_colorkey & 0x03E0) << 6) | + ((state->src_colorkey & 0x001F) << 3); + msk = 0xF8F8F8; + break; + case DSPF_RGB16: + clr = ((state->src_colorkey & 0xF800) << 8) | + ((state->src_colorkey & 0x07E0) << 5) | + ((state->src_colorkey & 0x001F) << 3); + msk = 0xF8FCF8; + break; + case DSPF_RGB32: + case DSPF_ARGB: + clr = state->src_colorkey; + msk = 0xFFFFFF; + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + } else { + clr = state->src_colorkey; + msk = (1 << DFB_COLOR_BITS_PER_PIXEL( state->source->config.format )) - 1; + } + + mach64_waitfifo( mdrv, mdev, 3 ); + mach64_out32( mmio, CLR_CMP_MSK, msk ); + mach64_out32( mmio, CLR_CMP_CLR, clr ); + mach64_out32( mmio, CLR_CMP_CNTL, CLR_CMP_FN_EQUAL | CLR_CMP_SRC_SCALE ); + + MACH64_VALIDATE( m_srckey_scale ); + MACH64_INVALIDATE( m_srckey | m_dstkey | m_disable_key ); +} + +void mach64_set_dst_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (MACH64_IS_VALID( m_dstkey )) + return; + + mach64_waitfifo( mdrv, mdev, 3 ); + mach64_out32( mmio, CLR_CMP_MSK, + (1 << DFB_COLOR_BITS_PER_PIXEL( state->destination->config.format )) - 1 ); + mach64_out32( mmio, CLR_CMP_CLR, state->dst_colorkey ); + mach64_out32( mmio, CLR_CMP_CNTL, CLR_CMP_FN_NOT_EQUAL | CLR_CMP_SRC_DEST ); + + MACH64_VALIDATE( m_dstkey ); + MACH64_INVALIDATE( m_srckey | m_srckey_scale | m_disable_key ); +} + +void mach64_disable_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (MACH64_IS_VALID( m_disable_key )) + return; + + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, CLR_CMP_CNTL, CLR_CMP_FN_FALSE ); + + MACH64_VALIDATE( m_disable_key ); + MACH64_INVALIDATE( m_srckey | m_srckey_scale | m_dstkey ); +} + +static u32 mach64SourceBlend[] = { + ALPHA_BLND_SRC_ZERO, + ALPHA_BLND_SRC_ONE, + 0, + 0, + ALPHA_BLND_SRC_SRCALPHA, + ALPHA_BLND_SRC_INVSRCALPHA, + ALPHA_BLND_SRC_DSTALPHA, + ALPHA_BLND_SRC_INVDSTALPHA, + ALPHA_BLND_SRC_DSTCOLOR, + ALPHA_BLND_SRC_INVDSTCOLOR, + ALPHA_BLND_SAT +}; + +static u32 mach64DestBlend[] = { + ALPHA_BLND_DST_ZERO, + ALPHA_BLND_DST_ONE, + ALPHA_BLND_DST_SRCCOLOR, + ALPHA_BLND_DST_INVSRCCOLOR, + ALPHA_BLND_DST_SRCALPHA, + ALPHA_BLND_DST_INVSRCALPHA, + ALPHA_BLND_DST_DSTALPHA, + ALPHA_BLND_DST_INVDSTALPHA, + 0, + 0, + 0 +}; + +void mach64_set_draw_blend( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (MACH64_IS_VALID( m_draw_blend )) + return; + + mdev->draw_blend &= DITHER_EN; + mdev->draw_blend |= ALPHA_FOG_EN_ALPHA | + mach64SourceBlend[state->src_blend - 1] | + mach64DestBlend [state->dst_blend - 1]; + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + /* FIXME: This is wrong. */ + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, ALPHA_TST_CNTL, ALPHA_DST_SEL_DSTALPHA ); + } + + MACH64_VALIDATE( m_draw_blend ); +} + +void mach64_set_blit_blend( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (MACH64_IS_VALID( m_blit_blend )) + return; + + mdev->blit_blend &= SCALE_PIX_EXPAND | DITHER_EN; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + /* Disable dithering because it is applied even when + * the source pixels are completely transparent. + */ + if (DFB_PIXELFORMAT_HAS_ALPHA( state->source->config.format )) + mdev->blit_blend &= ~DITHER_EN; + + mdev->blit_blend |= ALPHA_FOG_EN_ALPHA | + mach64SourceBlend[state->src_blend - 1] | + mach64DestBlend [state->dst_blend - 1]; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (DFB_PIXELFORMAT_HAS_ALPHA( state->source->config.format )) { + mdev->blit_blend |= TEX_MAP_AEN; + } else { + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, ALPHA_START, 0xFF << 16 ); + MACH64_INVALIDATE( m_color_3d | m_color_tex ); + } + } + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + /* FIXME: This is wrong. */ + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, ALPHA_TST_CNTL, ALPHA_DST_SEL_DSTALPHA ); + } + } else { + /* This needs to be set even without alpha blending. + * Otherwise alpha channel won't get copied. + */ + if (DFB_PIXELFORMAT_HAS_ALPHA( state->source->config.format )) + mdev->blit_blend |= TEX_MAP_AEN; + + if (mdev->chip >= CHIP_3D_RAGE_PRO) { + /* FIXME: This is wrong. */ + mach64_waitfifo( mdrv, mdev, 1 ); + mach64_out32( mmio, ALPHA_TST_CNTL, ALPHA_DST_SEL_SRCALPHA ); + } + } + + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + mdev->blit_blend |= TEX_LIGHT_FCN_MODULATE; + + MACH64_VALIDATE( m_blit_blend ); +} diff --git a/Source/DirectFB/gfxdrivers/mach64/mach64_state.h b/Source/DirectFB/gfxdrivers/mach64/mach64_state.h new file mode 100755 index 0000000..8957d8a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mach64_state.h @@ -0,0 +1,90 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___MACH64_STATE_H__ +#define ___MACH64_STATE_H__ + +#include "mach64.h" + +void mach64_set_destination( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); +void mach64gt_set_destination( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_source( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); +void mach64gt_set_source( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); +void mach64gt_set_source_scale( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_clip( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_color( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_color_3d( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_color_tex( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_src_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_src_colorkey_scale( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_dst_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_disable_colorkey( Mach64DriverData *mdrv, + Mach64DeviceData *mdev ); + +void mach64_set_draw_blend( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +void mach64_set_blit_blend( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + CardState *state ); + +#endif diff --git a/Source/DirectFB/gfxdrivers/mach64/mmio.h b/Source/DirectFB/gfxdrivers/mach64/mmio.h new file mode 100755 index 0000000..c8aed85 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/mmio.h @@ -0,0 +1,198 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + + +#ifndef ___MACH64_MMIO_H__ +#define ___MACH64_MMIO_H__ + +#include + +#include "mach64.h" + +static inline void +mach64_out8( volatile u8 *mmioaddr, u32 reg, u8 value ) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static inline u8 +mach64_in8( volatile u8 *mmioaddr, u32 reg ) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static inline void +mach64_out32( volatile u8 *mmioaddr, u32 reg, u32 value ) +{ +#ifdef __powerpc__ + if (reg >= 0x400) + asm volatile("stwbrx %0,%1,%2;eieio" : : "r"(value), "b"(reg-0x800), + "r"(mmioaddr) : "memory"); + else + asm volatile("stwbrx %0,%1,%2;eieio" : : "r"(value), "b"(reg), + "r"(mmioaddr) : "memory"); +#else + if (reg >= 0x400) + *((volatile u32*)(mmioaddr+reg-0x800)) = value; + else + *((volatile u32*)(mmioaddr+reg)) = value; +#endif +} + +static inline u32 +mach64_in32( volatile u8 *mmioaddr, u32 reg ) +{ +#ifdef __powerpc__ + u32 value; + + if (reg >= 0x400) + asm volatile("lwbrx %0,%1,%2;eieio" : "=r"(value) : "b"(reg-0x800), "r"(mmioaddr)); + else + asm volatile("lwbrx %0,%1,%2;eieio" : "=r"(value) : "b"(reg), "r"(mmioaddr)); + + return value; +#else + if (reg >= 0x400) + return *((volatile u32*)(mmioaddr+reg-0x800)); + else + return *((volatile u32*)(mmioaddr+reg)); +#endif +} + +static const u32 lt_lcd_regs[] = { + CONFIG_PANEL_LT, + LCD_GEN_CTRL_LT, + DSTN_CONTROL_LT, + HFB_PITCH_ADDR_LT, + HORZ_STRETCHING_LT, + VERT_STRETCHING_LT, + 0, /* EXT_VERT_STRETCH */ + LT_GIO_LT, + POWER_MANAGEMENT_LT +}; + +#if 0 +static inline void +mach64_in_lcd( Mach64DeviceData *mdev, + volatile u8 *mmioaddr, u8 reg, u32 value ) +{ + if (mdev->chip == CHIP_3D_RAGE_LT) { + mach64_out32( mmioaddr, lt_lcd_regs[reg], value ); + } else if (mdev->chip >= CHIP_3D_RAGE_LT_PRO) { + mach64_out8( mmioaddr, LCD_INDEX, reg ); + mach64_out32( mmioaddr, LCD_DATA, value ); + } +} +#endif + +static inline u32 +mach64_in_lcd( Mach64DeviceData *mdev, + volatile u8 *mmioaddr, u8 reg ) +{ + if (mdev->chip == CHIP_3D_RAGE_LT) { + return mach64_in32( mmioaddr, lt_lcd_regs[reg] ); + } else if (mdev->chip >= CHIP_3D_RAGE_LT_PRO) { + mach64_out8( mmioaddr, LCD_INDEX, reg ); + return mach64_in32( mmioaddr, LCD_DATA ); + } else { + return 0; + } +} + +#if 0 +static inline void +mach64_out_pll( volatile u8 *mmioaddr, u8 reg, u8 value ) +{ + mach64_out8( mmioaddr, CLOCK_CNTL1, (reg << 2) | PLL_WR_EN ); + mach64_out8( mmioaddr, CLOCK_CNTL2, value ); +} +#endif + +static inline u8 +mach64_in_pll( volatile u8 *mmioaddr, u8 reg ) +{ + mach64_out8( mmioaddr, CLOCK_CNTL1, reg << 2 ); + return mach64_in8( mmioaddr, CLOCK_CNTL2 ); +} + +static inline void mach64_waitidle( Mach64DriverData *mdrv, + Mach64DeviceData *mdev ) +{ + int timeout = 1000000; + + while (timeout--) { + if ((mach64_in32( mdrv->mmio_base, FIFO_STAT ) & 0x0000FFFF) == 0) + break; + + mdev->idle_waitcycles++; + } + + timeout = 1000000; + + while (timeout--) { + if ((mach64_in32( mdrv->mmio_base, GUI_STAT ) & GUI_ACTIVE) == 0) + break; + + mdev->idle_waitcycles++; + } + + mdev->fifo_space = 16; +} + +static inline void mach64_waitfifo( Mach64DriverData *mdrv, + Mach64DeviceData *mdev, + unsigned int requested_fifo_space ) +{ + u32 fifo_stat; + int timeout = 1000000; + + mdev->waitfifo_sum += requested_fifo_space; + mdev->waitfifo_calls++; + + if (mdev->fifo_space < requested_fifo_space) { + while (timeout--) { + mdev->fifo_waitcycles++; + + fifo_stat = mach64_in32( mdrv->mmio_base, FIFO_STAT ) & 0x0000FFFF; + mdev->fifo_space = 16; + while (fifo_stat) { + mdev->fifo_space--; + fifo_stat >>= 1; + } + + if (mdev->fifo_space >= requested_fifo_space) + break; + } + } + else { + mdev->fifo_cache_hits++; + } + mdev->fifo_space -= requested_fifo_space; +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/mach64/regs.h b/Source/DirectFB/gfxdrivers/mach64/regs.h new file mode 100755 index 0000000..d764fea --- /dev/null +++ b/Source/DirectFB/gfxdrivers/mach64/regs.h @@ -0,0 +1,883 @@ +#ifndef __MACH64_REGS_H__ +#define __MACH64_REGS_H__ + +/* LCD Panel registers */ +#define CONFIG_PANEL 0x00 +#define LCD_GEN_CTRL 0x01 +#define DSTN_CONTROL 0x02 +#define HFB_PITCH_ADDR 0x03 +#define HORZ_STRETCHING 0x04 +#define VERT_STRETCHING 0x05 +#define EXT_VERT_STRETCH 0x06 +#define LT_GIO 0x07 +#define POWER_MANAGEMENT 0x08 +#define ZVGPIO 0x09 +#define ICON_CLR0 0x0A +#define ICON_CLR1 0x0B +#define ICON_OFFSET 0x0C +#define ICON_HORZ_VERT_POSN 0x0D +#define ICON_HORZ_VERT_OFF 0x0E +#define ICON2_CLR0 0x0F +#define ICON2_CLR1 0x10 +#define ICON2_OFFSET 0x11 +#define ICON2_HORZ_VERT_POSN 0x12 +#define ICON2_HORZ_VERT_OFF 0x13 +#define LCD_MISC_CNTL 0x14 +#define TMDS_CNTL 0x15 +#define SCRATCH_PAD_4 0x15 +#define TMDS_SYNC_CHAR_SETA 0x16 +#define SCRATCH_PAD_5 0x16 +#define TMDS_SYNC_CHAR_SETB 0x17 +#define SCRATCH_PAD_6 0x17 +#define TMDS_CRC 0x18 +#define SCRATCH_PAD_7 0x18 +#define PLTSTBLK_GEN_SEED 0x19 +#define SCRATCH_PAD_8 0x19 +#define SYNC_GEN_CNTL 0x1A +#define PATTERN_GEN_SEED 0x1B +#define APC_CNTL 0x1C +#define POWER_MANAGEMENT_2 0x1D +#define PRI_ERR_PATTERN 0x1E +#define CUR_ERR_PATTERN 0x1F +#define PLTSTBLK_RPT 0x20 +#define SYNC_RPT 0x21 +#define CRC_PATTERN_RPT 0x22 +#define PL_TRANSMITTER_CNTL 0x23 +#define PL_PLL_CNTL 0x24 +#define ALPHA_BLENDING 0x25 +#define PORTRAIT_GEN_CNTL 0x26 +#define APC_CTRL_IO 0x27 +#define TEST_IO 0x28 +#define TEST_OUTPUTS 0x29 +#define DP1_MEM_ACCESS 0x2A +#define DP0_MEM_ACCESS 0x2B +#define DP0_DEBUG_A 0x2C +#define DP0_DEBUG_B 0x2D +#define DP1_DEBUG_A 0x2E +#define DP1_DEBUG_B 0x2F +#define DPCTRL_DEBUG_A 0x30 +#define DPCTRL_DEBUG_B 0x31 +#define MEMBLK_DEBUG 0x32 +/* #define SCRATCH_PAD_4 0x33 */ +#define APC_LUT_AB 0x33 +/* #define SCRATCH_PAD_5 0x34 */ +#define APC_LUT_CD 0x34 +/* #define SCRATCH_PAD_6 0x35 */ +#define APC_LUT_EF 0x25 +/* #define SCRATCH_PAD_7 0x36 */ +#define APC_LUT_GH 0x36 +/* #define SCRATCH_PAD_8 0x37 */ +#define APC_LUT_IJ 0x37 +#define APC_LUT_KL 0x38 +#define APC_LUT_MN 0x39 +#define APC_LUT_OP 0x3A + +/* LCD_GEN_CTRL */ +#define LCD_ON 0x00000002 + +/* VERT_STRETCHING */ +#define VERT_STRETCH_RATIO0 0x000003FF +#define VERT_STRETCH_EN 0x80000000 + + +/* PLL registers */ +#define MPLL_CNTL 0x00 +#define VPLL_CNTL 0x01 +#define PLL_REF_DIV 0x02 +#define PLL_GEN_CNTL 0x03 +#define MCLK_FB_DIV 0x04 +#define PLL_VCLK_CNTL 0x05 +#define VCLK_POST_DIV 0x06 +#define VCLK0_FB_DIV 0x07 +#define VCLK1_FB_DIV 0x08 +#define VCLK2_FB_DIV 0x09 +#define VCLK3_FB_DIV 0x0A +#define PLL_EXT_CNTL 0x0B +#define DLL_CNTL 0x0C +#define DLL1_CNTL 0x0C +#define VFC_CNTL 0x0D +#define PLL_TEST_CNTL 0x0E +#define PLL_TEST_COUNT 0x0F +#define LVDSPLL_CNTL0 0x10 +#define LVDS_CNTL0 0x10 +#define LVDSPLL_CNTL1 0x11 +#define LVDS_CNTL1 0x11 +#define AGP1_CNTL 0x12 +#define AGP2_CNTL 0x13 +#define DLL2_CNTL 0x14 +#define SCLK_FB_DIV 0x15 +#define SPLL_CNTL1 0x16 +#define SPLL_CNTL2 0x17 +#define APLL_STRAPS 0x18 +#define EXT_VPLL_CNTL 0x19 +#define EXT_VPLL_REF_DIV 0x1A +#define EXT_VPLL_FB_DIV 0x1B +#define EXT_VPLL_MSB 0x1C +#define HTOTAL_CNTL 0x1D +#define BYTE_CLK_CNTL 0x1E +#define TV_PLL_CNTL1 0x1F +#define TV_PLL_CNTL2 0x20 +#define TV_PLL_CNTL 0x21 +#define EXT_TV_PLL 0x22 +#define V2PLL_CNTL 0x23 +#define PLL_V2CLK_CNTL 0x24 +#define EXT_V2PLL_REF_DIV 0x25 +#define EXT_V2PLL_FB_DIV 0x26 +#define EXT_V2PLL_MSB 0x27 +#define HTOTAL2_CNTL 0x28 +#define PLL_YCLK_CNTL 0x29 +#define PM_DYN_CLK_CNTL 0x2A + +/* PLL_VCLK_CNTL */ +#define ECP_DIV 0x30 + + +/* TV Out registers */ +/* 0x00 - 0x0F */ +#define TV_MASTER_CNTL 0x10 +/* 0x11 */ +#define TV_RGB_CNTL 0x12 +/* 0x13 */ +#define TV_SYNC_CNTL 0x14 +/* 0x15 - 1F */ +#define TV_HTOTAL 0x20 +#define TV_HDISP 0x21 +#define TV_HSIZE 0x22 +#define TV_HSTART 0x23 +#define TV_HCOUNT 0x24 +#define TV_VTOTAL 0x25 +#define TV_VDISP 0x26 +#define TV_VCOUNT 0x27 +#define TV_FTOTAL 0x28 +#define TV_FCOUNT 0x29 +#define TV_FRESTART 0x2A +#define TV_HRESTART 0x2B +#define TV_VRESTART 0x2C +/* 0x2D - 0x5F */ +#define TV_HOST_READ_DATA 0x60 +#define TV_HOST_WRITE_DATA 0x61 +#define TV_HOST_RD_WT_CNTL 0x62 +/* 0x63 - 0x6F */ +#define TV_VSCALER_CNTL 0x70 +#define TV_TIMING_CNTL 0x71 +#define TV_GAMMA_CNTL 0x72 +#define TV_Y_FALL_CNTL 0x73 +#define TV_Y_RISE_CNTL 0x74 +#define TV_Y_SAW_TOOTH_CNTL 0x75 +/* 0x76 - 0x7F */ +#define TV_MODULATOR_CNTL1 0x80 +#define TV_MODULATOR_CNTL2 0x81 +/* 0x82 - 0x8F */ +#define TV_PRE_DAC_MUX_CNTL 0x90 +/* 0x91 - 0x9F */ +#define TV_DAC_CNTL 0xA0 +/* 0xA1 - 0xAF */ +#define TV_CRC_CNTL 0xB0 +#define TV_VIDEO_PORT_SIG 0xB1 +/* 0xB2 - 0xB7 */ +#define TV_VBI_CC_CNTL 0xB8 +#define TV_VBI_EDS_CNTL 0xB9 +#define TV_VBI_20BIT_CNTL 0xBA +/* 0xBB - 0xBC */ +#define TV_VBI_DTO_CNTL 0xBD +#define TV_VBI_LEVEL_CNTL 0xBE +/* 0xBF */ +#define TV_UV_ADR 0xC0 +#define TV_FIFO_TEST_CNTL 0xC1 +/* 0xC2 - 0xFF */ + + +/* Main registers */ +#define CRTC_H_TOTAL_DISP 0x000 +#define CRTC2_H_TOTAL_DISP 0x000 +#define CRTC_H_SYNC_STRT_WID 0x004 +#define CRTC2_H_SYNC_STRT_WID 0x004 +#define CRTC_V_TOTAL_DISP 0x008 +#define CRTC2_V_TOTAL_DISP 0x008 +#define CRTC_V_SYNC_STRT_WID 0x00C +#define CRTC2_V_SYNC_STRT_WID 0x00C +#define CRTC_VLINE_CRNT_VLINE 0x010 +#define CRTC2_VLINE_CRNT_VLINE 0x010 +#define CRTC_OFF_PITCH 0x014 +#define CRTC_INT_CNTL 0x018 +#define CRTC_GEN_CNTL 0x01C +#define TV_OUT_INDEX 0x01D +#define DSP_CONFIG 0x020 +#define PM_DSP_CONFIG 0x020 +#define DSP_ON_OFF 0x024 +#define PM_DSP_ON_OFF 0x024 +#define TV_OUT_DATA 0x01D +#define TIMER_CONFIG 0x028 +#define MEM_BUF_CNTL 0x02C +#define SHARED_CNTL 0x030 +#define SHARED_MEM_CONFIG 0x034 +#define MEM_ADDR_CONFIG 0x034 +#define CRT_TRAP 0x038 +#define I2C_CNTL_0 0x03C +#define DSTN_CONTROL_LT 0x03C +#define OVR_CLR 0x040 +#define OVR2_CLR 0x040 +#define OVR_WID_LEFT_RIGHT 0x044 +#define OVR2_WID_LEFT_RIGHT 0x044 +#define OVR_WID_TOP_BOTTOM 0x048 +#define OVR2_WID_TOP_BOTTOM 0x048 +#define VGA_DSP_CONFIG 0x04C +#define PM_VGA_DSP_CONFIG 0x04C +#define VGA_DSP_ON_OFF 0x050 +#define PM_VGA_DSP_ON_OFF 0x050 +#define DSP2_CONFIG 0x054 +#define PM_DSP2_CONFIG 0x054 +#define DSP2_ON_OFF 0x058 +#define PM_DSP2_ON_OFF 0x058 +#define CRTC2_OFF_PITCH 0x05C +#define CUR_CLR0 0x060 +#define CUR2_CLR0 0x060 +#define CUR_CLR1 0x064 +#define CUR2_CLR1 0x064 +#define CUR_OFFSET 0x068 +#define CUR2_OFFSET 0x068 +#define CUR_HORZ_VERT_POSN 0x06C +#define CUR2_HORZ_VERT_POSN 0x06C +#define CUR_HORZ_VERT_OFF 0x070 +#define CUR2_HORZ_VERT_OFF 0x070 +#define CONFIG_PANEL_LT 0x074 +#define GP_IO 0x078 +#define HW_DEBUG 0x07C +#define SCRATCH_REG0 0x080 +#define SCRATCH_REG1 0x084 +#define SCRATCH_REG2 0x088 +#define SCRATCH_REG3 0x08C +#define CLOCK_CNTL 0x090 +#define CLOCK_CNTL0 0x090 +#define CLOCK_CNTL1 0x091 +#define CLOCK_CNTL2 0x092 +#define CLOCK_CNTL3 0x093 +#define CONFIG_STAT1 0x094 +#define CONFIG_STAT2 0x098 +/* 0x09C */ +#define BUS_CNTL 0x0A0 +#define LCD_INDEX 0x0A4 +#define LCD_DATA 0x0A8 +#define HFB_PITCH_ADDR_LT 0x0A8 +#define EXT_MEM_CNTL 0x0AC +#define MEM_CNTL 0x0B0 +#define MEM_VGA_WP_SEL 0x0B4 +#define MEM_VGA_RP_SEL 0x0B8 +#define I2C_CNTL_1 0x0BC +#define LT_GIO_LT 0x0BC +#define DAC_REGS 0x0C0 +#define DAC_CNTL 0x0C4 +#define EXT_DAC_REGS 0x0C8 +#define HORZ_STRETCHING_LT 0x0C8 +#define VERT_STRETCHING_LT 0x0CC +#define GEN_TEST_CNTL 0x0D0 +#define CUSTOM_MACRO_CNTL 0x0D4 +#define LCD_GEN_CTRL_LT 0x0D4 +#define POWER_MANAGEMENT_LT 0x0D8 +#define CONFIG_CNTL 0x0DC +#define CONFIG_CHIP_ID 0x0E0 +#define CONFIG_STAT0 0x0E4 +#define CRC_SIG 0x0E8 +#define CRC2_SIG 0x0E8 +/* 0x0EC - 0x0FC */ +#define DST_OFF_PITCH 0x100 +#define DST_X 0x104 +#define DST_Y 0x108 +#define DST_Y_X 0x10C +#define DST_WIDTH 0x110 +#define DST_HEIGHT 0x114 +#define DST_HEIGHT_WIDTH 0x118 +#define DST_X_WIDTH 0x11C +#define DST_BRES_LNTH 0x120 +/* #define LEAD_BRES_LNTH 0x120 */ +#define DST_BRES_ERR 0x124 +#define LEAD_BRES_ERR 0x124 +#define DST_BRES_INC 0x128 +#define LEAD_BRES_INC 0x128 +#define DST_BRES_DEC 0x12C +#define LEAD_BRES_DEC 0x12C +#define DST_CNTL 0x130 +/* #define DST_Y_X 0x134 */ +#define TRAIL_BRES_ERR 0x138 +#define TRAIL_BRES_INC 0x13C +#define TRAIL_BRES_DEC 0x140 +#define LEAD_BRES_LNTH 0x144 +#define Z_OFF_PITCH 0x148 +#define Z_CNTL 0x14C +#define ALPHA_TST_CNTL 0x150 +/* 0x154 */ +#define SECONDARY_STW_EXP 0x158 +#define SECONDARY_S_X_INC 0x15C +#define SECONDARY_S_Y_INC 0x160 +#define SECONDARY_S_START 0x164 +#define SECONDARY_W_X_INC 0x168 +#define SECONDARY_W_Y_INC 0x16C +#define SECONDARY_W_START 0x170 +#define SECONDARY_T_X_INC 0x174 +#define SECONDARY_T_Y_INC 0x178 +#define SECONDARY_T_START 0x17C +#define SRC_OFF_PITCH 0x180 +#define SRC_X 0x184 +#define SRC_Y 0x188 +#define SRC_Y_X 0x18C +#define SRC_WIDTH1 0x190 +#define SRC_HEIGHT1 0x194 +#define SRC_HEIGHT1_WIDTH1 0x198 +#define SRC_X_START 0x19C +#define SRC_Y_START 0x1A0 +#define SRC_Y_X_START 0x1A4 +#define SRC_WIDTH2 0x1A8 +#define SRC_HEIGHT2 0x1AC +#define SRC_HEIGHT2_WIDTH2 0x1B0 +#define SRC_CNTL 0x1B4 +/* 0x1B8 - 0x1BC */ +#define SCALE_Y_OFF 0x1C0 +#define SCALE_OFF 0x1C0 +#define TEX_0_OFF 0x1C0 +#define SECONDARY_SCALE_OFF 0x1C4 +#define TEX_1_OFF 0x1C4 +#define TEX_2_OFF 0x1C8 +#define TEX_3_OFF 0x1CC +#define TEX_4_OFF 0x1D0 +#define TEX_5_OFF 0x1D4 +#define TEX_6_OFF 0x1D8 +#define SCALE_WIDTH 0x1DC +#define TEX_7_OFF 0x1DC +#define SCALE_HEIGHT 0x1E0 +#define TEX_8_OFF 0x1E0 +#define TEX_9_OFF 0x1E4 +#define TEX_10_OFF 0x1E8 +#define SCALE_Y_PITCH 0x1EC +#define SCALE_PITCH 0x1EC +/* #define S_Y_INC 0x1EC */ +#define SCALE_X_INC 0x1F0 +/* #define RED_X_INC 0x1F0 */ +#define SCALE_Y_INC 0x1F4 +/* #define GREEN_X_INC 0x1F4 */ +#define SCALE_VACC 0x1F8 +#define SCALE_3D_CNTL 0x1FC +#define HOST_DATA0 0x200 +#define HOST_DATA1 0x204 +#define HOST_DATA2 0x208 +#define HOST_DATA3 0x20C +#define HOST_DATA4 0x210 +#define HOST_DATA5 0x214 +#define HOST_DATA6 0x218 +#define HOST_DATA7 0x21C +#define HOST_DATA8 0x220 +#define HOST_DATA9 0x224 +#define HOST_DATAA 0x228 +#define HOST_DATAB 0x22C +#define HOST_DATAC 0x230 +#define HOST_DATAD 0x234 +#define HOST_DATAE 0x238 +#define HOST_DATAF 0x23C +#define HOST_CNTL 0x240 +#define BM_HOSTDATA 0x244 +#define BM_ADDR 0x248 +#define BM_DATA 0x248 +#define BM_GUI_TABLE_CMD 0x24C +/* 0x250 - 0x27C */ +#define PAT_REG0 0x280 +#define PAT_REG1 0x284 +#define PAT_CNTL 0x288 +/* 0x28C - 0x29C */ +#define SC_LEFT 0x2A0 +#define SC_RIGHT 0x2A4 +#define SC_LEFT_RIGHT 0x2A8 +#define SC_TOP 0x2AC +#define SC_BOTTOM 0x2B0 +#define SC_TOP_BOTTOM 0x2B4 +#define USR1_DST_OFF_PITCH 0x2B8 +#define USR2_DST_OFF_PITCH 0x2BC +#define DP_BKGD_CLR 0x2C0 +#define DP_FRGD_CLR 0x2C4 +#define DP_FOG_CLR 0x2C4 +#define DP_WRITE_MSK 0x2C8 +#define DP_CHAIN_MSK 0x2CC +#define DP_PIX_WIDTH 0x2D0 +#define DP_MIX 0x2D4 +#define DP_SRC 0x2D8 +#define DP_FRGD_CLR_MIX 0x2DC +#define DP_FRGD_BKGD_CLR 0x2E0 +/* 0x2E4 */ +#define DST_X_Y 0x2E8 +#define DST_WIDTH_HEIGHT 0x2EC +#define USR_DST_PITCH 0x2F0 +/* 0x2F4 */ +#define DP_SET_GUI_ENGINE2 0x2F8 +#define DP_SET_GUI_ENGINE 0x2FC +#define CLR_CMP_CLR 0x300 +#define CLR_CMP_MSK 0x304 +#define CLR_CMP_CNTL 0x308 +/* 0x30C */ +#define FIFO_STAT 0x310 +/* 0x314 - 0x31C */ +#define CONTEXT_MSK 0x320 +/* 0x324 */ +/* 0x328 */ +#define CONTEXT_LOAD_CNTL 0x32C +#define GUI_TRAJ_CNTL 0x330 +/* 0x334 */ +#define GUI_STAT 0x338 +/* 0x33C */ +#define S_X_INC2 0x340 +#define TEX_PALETTE_INDEX 0x340 +#define S_Y_INC2 0x344 +#define STW_EXP 0x344 +#define S_XY_INC2 0x348 +#define LOG_MAX_INC 0x348 +#define S_X_INC_START 0x34C +#define S_X_INC 0x34C +#define S_Y_INC 0x350 +/* #define SCALE_Y_PITCH 0x350 */ +/* #define SCALE_PITCH 0x350 */ +#define S_START 0x354 +#define T_X_INC2 0x358 +#define W_X_INC 0x358 +#define T_Y_INC2 0x35C +#define W_Y_INC 0x35C +#define T_XY_INC2 0x360 +#define W_START 0x360 +#define T_X_INC_START 0x364 +#define T_X_INC 0x364 +#define SECONDARY_SCALE_PITCH 0x368 +#define T_Y_INC 0x368 +#define T_START 0x36C +#define TEX_SIZE_PITCH 0x370 +#define TEX_CNTL 0x374 +#define SECONDARY_TEX_OFFSET 0x378 +#define TEX_PAL_WR 0x37C +#define TEX_PALETTE 0x37C +#define SCALE_PITCH_BOTH 0x380 +#define SECONDARY_SCALE_OFF_ACC 0x384 +#define SCALE_OFF_ACC 0x388 +#define SCALE_DST_Y_X 0x38C +/* 0x390 - 0x394 */ +#define COMPOSITE_SHADOW_ID 0x398 +#define SECONDARY_SCALE_X_INC 0x39C +#define SPECULAR_RED_X_INC 0x39C +#define SPECULAR_RED_Y_INC 0x3A0 +#define SECONDARY_SCALE_HACC 0x3A4 +#define SPECULAR_RED_START 0x3A4 +#define SPECULAR_GREEN_X_INC 0x3A8 +#define SPECULAR_GREEN_Y_INC 0x3AC +#define SPECULAR_GREEN_START 0x3B0 +#define SPECULAR_BLUE_X_INC 0x3B4 +#define SPECULAR_BLUE_Y_INC 0x3B8 +#define SPECULAR_BLUE_START 0x3BC +/* #define SCALE_X_INC 0x3C0 */ +#define RED_X_INC 0x3C0 +#define RED_Y_INC 0x3C4 +#define SCALE_HACC 0x3C8 +#define RED_START 0x3C8 +/* #define SCALE_Y_INC 0x3CC */ +#define GREEN_X_INC 0x3CC +#define SECONDARY_SCALE_Y_INC 0x3D0 +#define GREEN_Y_INC 0x3D0 +#define SECONDARY_SCALE_VACC 0x3D4 +#define GREEN_START 0x3D4 +#define SCALE_XUV_INC 0x3D8 +#define BLUE_X_INC 0x3D8 +#define BLUE_Y_INC 0x3DC +#define SCALE_UV_HACC 0x3E0 +#define BLUE_START 0x3E0 +#define Z_X_INC 0x3E4 +#define Z_Y_INC 0x3E8 +#define Z_START 0x3EC +#define ALPHA_X_INC 0x3F0 +#define FOG_X_INC 0x3F0 +#define ALPHA_Y_INC 0x3F4 +#define FOG_Y_INC 0x3F4 +#define ALPHA_START 0x3F8 +#define FOG_START 0x3F8 +/* 0x3FC */ +#define OVERLAY_Y_X_START 0x400 +#define OVERLAY_Y_X_END 0x404 +#define OVERLAY_VIDEO_KEY_CLR 0x408 +#define OVERLAY_VIDEO_KEY_MSK 0x40C +#define OVERLAY_GRAPHICS_KEY_CLR 0x410 +#define OVERLAY_GRAPHICS_KEY_MSK 0x414 +#define OVERLAY_KEY_CNTL 0x418 +/* 0x41C */ +#define OVERLAY_SCALE_INC 0x420 +#define OVERLAY_SCALE_CNTL 0x424 +#define SCALER_HEIGHT_WIDTH 0x428 +#define SCALER_TEST 0x42C +/* 0x430 */ +#define SCALER_BUF0_OFFSET 0x434 +#define SCALER_BUF1_OFFSET 0x438 +#define SCALER_BUF_PITCH 0x43C +#define CAPTURE_START_END 0x440 +#define CAPTURE_X_WIDTH 0x444 +#define VIDEO_FORMAT 0x448 +#define VBI_START_END 0x44C +#define CAPTURE_CONFIG 0x450 +#define TRIG_CNTL 0x454 +#define OVERLAY_EXCLUSIVE_HORZ 0x458 +#define OVERLAY_EXCLUSIVE_VERT 0x45C +#define VBI_WIDTH 0x460 +#define CAPTURE_DEBUG 0x464 +#define VIDEO_SYNC_TEST 0x468 +/* 0x46C */ +#define SNAPSHOT_VH_COUNTS 0x470 +#define SNAPSHOT_F_COUNT 0x474 +#define N_VIF_COUNT 0x478 +#define SNAPSHOT_VIF_COUNT 0x47C +#define BUF0_OFFSET 0x480 +#define CAPTURE_BUF0_OFFSET 0x480 +#define CAPTURE_BUF1_OFFSET 0x484 +#define ONESHOT_BUF_OFFSET 0x488 +#define CAPTURE_BUF_PITCH 0x488 +#define BUF0_PITCH 0x48C +/* 0x490 - 0x494 */ +#define BUF1_OFFSET 0x498 +/* 0x49C - 0x4A0 */ +#define BUF1_PITCH 0x4A4 +/* 0x4A8 */ +#define BUF0_CAP_OFFSET 0x4AC +#define BUF1_CAP_OFFSET 0x4B0 +#define SNAPSHOT2_VH_COUNTS 0x4B0 +#define SNAPSHOT2_F_COUNT 0x4B4 +#define N_VIF2_COUNT 0x4B8 +#define SNAPSHOT2_VIF_COUNT 0x4BC +#define MPP_CONFIG 0x4C0 +#define MPP_STROBE_SEQ 0x4C4 +#define MPP_ADDR 0x4C8 +#define MPP_DATA 0x4CC +#define TVO_CNTL 0x500 +/* 0x504 - 0x540 */ +#define CRT_HORZ_VERT_LOAD 0x544 +#define AGP_BASE 0x548 +#define AGP_CNTL 0x54C +#define SCALER_COLOUR_CNTL 0x550 +#define SCALER_H_COEFF0 0x554 +#define SCALER_H_COEFF1 0x558 +#define SCALER_H_COEFF2 0x55C +#define SCALER_H_COEFF3 0x560 +#define SCALER_H_COEFF4 0x564 +/* 0x568 - 0x56C */ +#define GUI_CMDFIFO_DEBUG 0x570 +#define GUI_CMDFIFO_DATA 0x574 +#define GUI_CNTL 0x578 +/* 0x57C */ +#define BM_FRAME_BUF_OFFSET 0x580 +#define BM_SYSTEM_MEM_ADDR 0x584 +#define BM_COMMAND 0x588 +#define BM_STATUS 0x58C +/* 0x590 - 0x5B4 */ +#define BM_GUI_TABLE 0x5B8 +#define BM_SYSTEM_TABLE 0x5BC +/* 0x5D0 */ +#define SCALER_BUF0_OFFSET_U 0x5D4 +#define SCALER_BUF0_OFFSET_V 0x5D8 +#define SCALER_BUF1_OFFSET_U 0x5DC +#define SCALER_BUF1_OFFSET_V 0x5E0 +/* 0x5E4 - 0x63C */ +#define VERTEX_1_S 0x640 +#define VERTEX_1_T 0x644 +#define VERTEX_1_W 0x648 +#define VERTEX_1_SPEC_ARGB 0x64C +#define VERTEX_1_Z 0x650 +#define VERTEX_1_ARGB 0x654 +#define VERTEX_1_X_Y 0x658 +/* #define ONE_OVER_AREA 0x65C */ +#define VERTEX_2_S 0x660 +#define VERTEX_2_T 0x664 +#define VERTEX_2_W 0x668 +#define VERTEX_2_SPEC_ARGB 0x66C +#define VERTEX_2_Z 0x670 +#define VERTEX_2_ARGB 0x674 +#define VERTEX_2_X_Y 0x678 +/* #define ONE_OVER_AREA 0x67C */ +#define VERTEX_3_S 0x680 +#define VERTEX_3_T 0x684 +#define VERTEX_3_W 0x688 +#define VERTEX_3_SPEC_ARGB 0x68C +#define VERTEX_3_Z 0x690 +#define VERTEX_3_ARGB 0x694 +#define VERTEX_3_X_Y 0x698 +#define ONE_OVER_AREA 0x69C +#define VERTEX_3_SECONDARY_S 0x6A0 +#define VERTEX_3_SECONDARY_T 0x6A4 +#define VERTEX_3_SECONDARY_W 0x6A8 +/* #define VERTEX_1_S 0x6AC */ +/* #define VERTEX_1_T 0x6B0 */ +/* #define VERTEX_1_W 0x6B4 */ +/* #define VERTEX_2_S 0x6B8 */ +/* #define VERTEX_2_T 0x6BC */ +/* #define VERTEX_2_W 0x6C0 */ +/* #define VERTEX_3_S 0x6C4 */ +/* #define VERTEX_3_T 0x6C8 */ +/* #define VERTEX_3_W 0x6CC */ +/* #define VERTEX_1_SPEC_ARGB 0x6D0 */ +/* #define VERTEX_2_SPEC_ARGB 0x6D4 */ +/* #define VERTEX_3_SPEC_ARGB 0x6D8 */ +/* #define VERTEX_1_Z 0x6DC */ +/* #define VERTEX_2_Z 0x6E0 */ +/* #define VERTEX_3_Z 0x6E4 */ +/* #define VERTEX_1_ARGB 0x6E8 */ +/* #define VERTEX_2_ARGB 0x6EC */ +/* #define VERTEX_3_ARGB 0x6F0 */ +/* #define VERTEX_1_X_Y 0x6F4 */ +/* #define VERTEX_2_X_Y 0x6F8 */ +/* #define VERTEX_3_X_Y 0x6FC */ +#define ONE_OVER_AREA_UC 0x700 +#define SETUP_CNTL 0x704 +/* 0x708 - 0x724 */ +#define VERTEX_1_SECONDARY_S 0x728 +#define VERTEX_1_SECONDARY_T 0x72C +#define VERTEX_1_SECONDARY_W 0x730 +#define VERTEX_2_SECONDARY_S 0x734 +#define VERTEX_2_SECONDARY_T 0x738 +#define VERTEX_2_SECONDARY_W 0x73C +/* 0x740 - 0x7FC */ + + +/* HW_DEBUG */ +#define INTER_PRIM_DIS 0x00000040 +#define AUTO_BLKWRT_COLOR_DIS 0x00000100 +#define AUTO_FF_DIS 0x00001000 +#define AUTO_BLKWRT_DIS 0x00002000 + +/* CLOCK_CNTL1 */ +#define PLL_WR_EN 0x02 + +/* CONFIG_CHIP_ID */ +#define CFG_CHIP_TYPE 0x0000FFFF +#define CFG_CHIP_CLASS 0x00FF0000 +#define CFG_CHIP_MAJOR 0x07000000 +#define CFG_CHIP_FND_ID 0x38000000 +#define CFG_CHIP_MINOR 0xC0000000 + +/* CONFIG_STAT0 */ +#define CFG_MEM_TYPE 0x00000007 +#define CFG_MEM_TYPE_SGRAM 0x00000005 + +/* DST_BRES_LNTH */ +#define DRAW_TRAP 0x00008000 +#define LINE_DIS 0x80000000 + +/* DST_CNTL */ +#define DST_X_DIR 0x00000001 +#define DST_Y_DIR 0x00000002 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_POLYGON_EN 0x00000040 +#define DST_24_ROTATION_EN 0x00000080 +#define TRAIL_X_DIR 0x00002000 +#define TRAP_FILL_DIR 0x00004000 + +/* ALPHA_TST_CNTL */ +#define ALPHA_DST_SEL_ZERO 0x00000000 +#define ALPHA_DST_SEL_ONE 0x00000100 +#define ALPHA_DST_SEL_SRCALPHA 0x00000400 +#define ALPHA_DST_SEL_INVSRCALPHA 0x00000500 +#define ALPHA_DST_SEL_DSTALPHA 0x00000600 +#define ALPHA_DST_SEL_INVDSTALPHA 0x00000700 + +/* SRC_CNTL */ +#define SRC_PATTERN_EN 0x00000001 +#define SRC_ROTATION_EN 0x00000002 +#define SRC_LINEAR_EN 0x00000004 +#define SRC_BYTE_ALIGN 0x00000008 +#define SRC_LINE_X_DIR 0x00000010 +#define FAST_FILL_EN 0x00000040 +#define COLOR_REG_WRITE_EN 0x00002000 +#define BLOCK_WRITE_EN 0x00004000 + +/* DP_PIX_WIDTH (GT) */ +#define DST_PIX_WIDTH_MONO 0x00000000 +#define DST_PIX_WIDTH_CI8 0x00000002 +#define DST_PIX_WIDTH_ARGB1555 0x00000003 +#define DST_PIX_WIDTH_RGB565 0x00000004 +#define DST_PIX_WIDTH_RGB888 0x00000005 +#define DST_PIX_WIDTH_ARGB8888 0x00000006 +#define DST_PIX_WIDTH_RGB332 0x00000007 +#define DST_PIX_WIDTH_Y8 0x00000008 +#define DST_PIX_WIDTH_RGB8 0x00000009 +#define DST_PIX_WIDTH_VYUY 0x0000000B +#define DST_PIX_WIDTH_YVYU 0x0000000C +#define DST_PIX_WIDTH_AYUV8888 0x0000000E +#define DST_PIX_WIDTH_ARGB4444 0x0000000F +#define SRC_PIX_WIDTH_MONO 0x00000000 +#define SRC_PIX_WIDTH_CI8 0x00000200 +#define SRC_PIX_WIDTH_ARGB1555 0x00000300 +#define SRC_PIX_WIDTH_RGB565 0x00000400 +#define SRC_PIX_WIDTH_ARGB8888 0x00000600 +#define SRC_PIX_WIDTH_RGB332 0x00000700 +#define SRC_PIX_WIDTH_Y8 0x00000800 +#define SRC_PIX_WIDTH_VYUY 0x00000B00 +#define SRC_PIX_WIDTH_YVYU 0x00000C00 +#define SRC_PIX_WIDTH_AYUV8888 0x00000E00 +#define SRC_PIX_WIDTH_ARGB4444 0x00000F00 +#define SCALE_PIX_WIDTH_CI8 0x20000000 +#define SCALE_PIX_WIDTH_ARGB1555 0x30000000 +#define SCALE_PIX_WIDTH_RGB565 0x40000000 +#define SCALE_PIX_WIDTH_ARGB8888 0x60000000 +#define SCALE_PIX_WIDTH_RGB332 0x70000000 +#define SCALE_PIX_WIDTH_Y8 0x80000000 +#define SCALE_PIX_WIDTH_RGB8 0x90000000 +#define SCALE_PIX_WIDTH_VYUY 0xB0000000 +#define SCALE_PIX_WIDTH_YVYU 0xC0000000 +#define SCALE_PIX_WIDTH_AYUV8888 0xE0000000 +#define SCALE_PIX_WIDTH_ARGB4444 0xF0000000 + +/* DP_PIX_WIDTH (GX/CT/VT) */ +#define DST_PIX_WIDTH_8BPP 0x00000002 +#define DST_PIX_WIDTH_15BPP 0x00000003 +#define DST_PIX_WIDTH_16BPP 0x00000004 +#define DST_PIX_WIDTH_32BPP 0x00000006 +#define SRC_PIX_WIDTH_8BPP 0x00000200 +#define SRC_PIX_WIDTH_15BPP 0x00000300 +#define SRC_PIX_WIDTH_16BPP 0x00000400 +#define SRC_PIX_WIDTH_32BPP 0x00000600 + +/* DP_PIX_WIDTH masks */ +#define DST_PIX_WIDTH 0x0000000F +#define SRC_PIX_WIDTH 0x00000F00 +#define SCALE_PIX_WIDTH 0xF0000000 + +/* DP_MIX */ +#define BKGD_MIX_DST 0x00000003 +#define BKGD_MIX_SRC 0x00000007 +#define FRGD_MIX_DST 0x00030000 +#define FRGD_MIX_SRC 0x00070000 + +/* DP_SRC */ +#define BKGD_SRC_BKGD_CLR 0x00000000 +#define BKGD_SRC_FRGD_CLR 0x00000001 +#define BKGD_SRC_HOST 0x00000002 +#define BKGD_SRC_BLIT 0x00000003 +#define BKGD_SRC_PATTERN 0x00000004 +#define BKGD_SRC_SCALE 0x00000005 +#define FRGD_SRC_BKGD_CLR 0x00000000 +#define FRGD_SRC_FRGD_CLR 0x00000100 +#define FRGD_SRC_HOST 0x00000200 +#define FRGD_SRC_BLIT 0x00000300 +#define FRGD_SRC_PATTERN 0x00000400 +#define FRGD_SRC_SCALE 0x00000500 +#define MONO_SRC_ONE 0x00000000 +#define MONO_SRC_PATTERN 0x00010000 +#define MONO_SRC_HOST 0x00020000 +#define MONO_SRC_BLIT 0x00030000 + +/* CLR_CMP_CNTL */ +#define CLR_CMP_FN_FALSE 0x00000000 +#define CLR_CMP_FN_TRUE 0x00000001 +#define CLR_CMP_FN_NOT_EQUAL 0x00000004 +#define CLR_CMP_FN_EQUAL 0x00000005 +#define CLR_CMP_SRC_DEST 0x00000000 +#define CLR_CMP_SRC_2D 0x01000000 +#define CLR_CMP_SRC_SCALE 0x02000000 + +/* GUI_STAT */ +#define GUI_ACTIVE 0x00000001 + +/* SCALE_3D_CNTL */ +#define SCALE_PIX_EXPAND 0x00000001 +#define SCALE_DITHER 0x00000002 +#define DITHER_EN 0x00000004 +#define DITHER_INIT 0x00000008 +#define ROUND_EN 0x00000010 +#define TEX_CACHE_DIS 0x00000020 +#define SCALE_3D_FCN_NOP 0x00000000 +#define SCALE_3D_FCN_SCALE 0x00000040 +#define SCALE_3D_FCN_TEXTURE 0x00000080 +#define SCALE_3D_FCN_SHADE 0x000000C0 +#define SCALE_PIX_REP 0x00000100 +#define NEAREST_TEX_VIS 0x00000200 +#define TEX_CACHE_SPLIT 0x00000200 +#define APPLE_YUV_MODE 0x00000400 +#define ALPHA_FOG_EN_DIS 0x00000000 +#define ALPHA_FOG_EN_ALPHA 0x00000800 +#define ALPHA_FOG_EN_FOG 0x00001000 +#define COLOR_OVERRIDE 0x00002000 +#define ALPHA_BLND_SAT 0x00002000 +#define RED_DITHER_MAX 0x00004000 +#define SIGNED_DST_CLAMP 0x00008000 +#define ALPHA_BLND_SRC_ZERO 0x00000000 +#define ALPHA_BLND_SRC_ONE 0x00010000 +#define ALPHA_BLND_SRC_DSTCOLOR 0x00020000 +#define ALPHA_BLND_SRC_INVDSTCOLOR 0x00030000 +#define ALPHA_BLND_SRC_SRCALPHA 0x00040000 +#define ALPHA_BLND_SRC_INVSRCALPHA 0x00050000 +#define ALPHA_BLND_SRC_DSTALPHA 0x00060000 +#define ALPHA_BLND_SRC_INVDSTALPHA 0x00070000 +#define ALPHA_BLND_DST_ZERO 0x00000000 +#define ALPHA_BLND_DST_ONE 0x00080000 +#define ALPHA_BLND_DST_SRCCOLOR 0x00100000 +#define ALPHA_BLND_DST_INVSRCCOLOR 0x00180000 +#define ALPHA_BLND_DST_SRCALPHA 0x00200000 +#define ALPHA_BLND_DST_INVSRCALPHA 0x00280000 +#define ALPHA_BLND_DST_DSTALPHA 0x00300000 +#define ALPHA_BLND_DST_INVDSTALPHA 0x00380000 +#define TEX_LIGHT_FCN_REPLACE 0x00000000 +#define TEX_LIGHT_FCN_MODULATE 0x00400000 +#define TEX_LIGHT_FCN_ALPHA_DECAL 0x00800000 +#define MIP_MAP_DISABLE 0x01000000 +#define BILINEAR_TEX_EN 0x02000000 +#define TEX_BLEND_FCN_NEAREST_MIPMAP_NEAREST 0x00000000 +#define TEX_BLEND_FCN_NEAREST_MIPMAP_LINEAR 0x04000000 +#define TEX_BLEND_FCN_LINEAR_MIPMAP_NEAREST 0x08000000 +#define TEX_BLEND_FCN_LINEAR_MIPMAP_LINEAR 0x0C000000 +#define TEX_AMASK_AEN 0x10000000 +#define TEX_AMASK_MODE 0x20000000 +#define TEX_MAP_AEN 0x40000000 +#define SRC_3D_SEL 0x80000000 + +/* TEX_CNTL */ +#define TEX_CACHE_FLUSH 0x00800000 + +/* OVERLAY_Y_X_START */ +#define OVERLAY_LOCK_START 0x80000000 + +/* OVERLAY_Y_X_END */ +#define OVERLAY_LOCK_END 0x80000000 + +/* OVERLAY_KEY_CNTL */ +#define VIDEO_KEY_FN_FALSE 0x00000000 +#define VIDEO_KEY_FN_TRUE 0x00000001 +#define VIDEO_KEY_FN_NOT_EQUAL 0x00000004 +#define VIDEO_KEY_FN_EQUAL 0x00000005 +#define GRAPHICS_KEY_FN_FALSE 0x00000000 +#define GRAPHICS_KEY_FN_TRUE 0x00000010 +#define GRAPHICS_KEY_FN_NOT_EQUAL 0x00000040 +#define GRAPHICS_KEY_FN_EQUAL 0x00000050 +#define OVERLAY_CMP_MIX_OR 0x00000000 +#define OVERLAY_CMP_MIX_AND 0x00000100 + +/* OVERLAY_SCALE_CNTL */ +/* #define SCALE_PIX_EXPAND 0x00000001 */ +#define SCALE_Y2R_TEMP 0x00000002 +#define SCALE_HORZ_MODE 0x00000004 +#define SCALE_VERT_MODE 0x00000008 +#define SCALE_SIGNED_UV 0x00000010 +#define SCALE_GAMMA_SEL 0x00000060 +#define SCALE_BANDWITH 0x04000000 +#define SCALE_DIS_LIMIT 0x08000000 +#define SCALE_CLK_FORCE_ON 0x20000000 +#define OVERLAY_EN 0x40000000 +#define SCALE_EN 0x80000000 + +/* VIDEO_FORMAT */ +#define VIDEO_IN_VYUY422 0x0000000B +#define VIDEO_IN_YVYU422 0x0000000C +#define VIDEO_SIGNED_UV 0x00000010 +#define SCALER_IN_RGB15 0x00030000 +#define SCALER_IN_RGB16 0x00040000 +#define SCALER_IN_RGB32 0x00060000 +#define SCALER_IN_YUV9 0x00090000 +#define SCALER_IN_YUV12 0x000A0000 +#define SCALER_IN_VYUY422 0x000B0000 +#define SCALER_IN_YVYU422 0x000C0000 + +/* CAPTURE_CONFIG */ +#define OVL_BUF_MODE_SINGLE 0x00000000 +#define OVL_BUF_MODE_DOUBLE 0x10000000 +#define OVL_BUF_NEXT_BUF0 0x00000000 +#define OVL_BUF_NEXT_BUF1 0x20000000 + +#endif diff --git a/Source/DirectFB/gfxdrivers/matrox/Makefile.am b/Source/DirectFB/gfxdrivers/matrox/Makefile.am new file mode 100755 index 0000000..ca445ba --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/Makefile.am @@ -0,0 +1,47 @@ +## Makefile.am for DirectFB/src/core/gfxcards/matrox + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +matrox_LTLIBRARIES = libdirectfb_matrox.la + +if BUILD_STATIC +matrox_DATA = $(matrox_LTLIBRARIES:.la=.o) +endif + +matroxdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_matrox_la_SOURCES = \ + matrox.c \ + matrox.h \ + matrox_3d.c \ + matrox_3d.h \ + matrox_bes.c \ + matrox_crtc2.c \ + matrox_maven.c \ + matrox_maven.h \ + matrox_screen_crtc2.c \ + matrox_spic.c \ + matrox_state.c \ + matrox_state.h \ + regs.h \ + mmio.h + +libdirectfb_matrox_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_matrox_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/matrox/Makefile.in b/Source/DirectFB/gfxdrivers/matrox/Makefile.in new file mode 100755 index 0000000..f9a3608 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/Makefile.in @@ -0,0 +1,618 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/matrox +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(matroxdir)" "$(DESTDIR)$(matroxdir)" +matroxLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(matrox_LTLIBRARIES) +libdirectfb_matrox_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_matrox_la_OBJECTS = matrox.lo matrox_3d.lo \ + matrox_bes.lo matrox_crtc2.lo matrox_maven.lo \ + matrox_screen_crtc2.lo matrox_spic.lo matrox_state.lo +libdirectfb_matrox_la_OBJECTS = $(am_libdirectfb_matrox_la_OBJECTS) +libdirectfb_matrox_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_matrox_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_matrox_la_SOURCES) +DIST_SOURCES = $(libdirectfb_matrox_la_SOURCES) +matroxDATA_INSTALL = $(INSTALL_DATA) +DATA = $(matrox_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +matrox_LTLIBRARIES = libdirectfb_matrox.la +@BUILD_STATIC_TRUE@matrox_DATA = $(matrox_LTLIBRARIES:.la=.o) +matroxdir = $(MODULEDIR)/gfxdrivers +libdirectfb_matrox_la_SOURCES = \ + matrox.c \ + matrox.h \ + matrox_3d.c \ + matrox_3d.h \ + matrox_bes.c \ + matrox_crtc2.c \ + matrox_maven.c \ + matrox_maven.h \ + matrox_screen_crtc2.c \ + matrox_spic.c \ + matrox_state.c \ + matrox_state.h \ + regs.h \ + mmio.h + +libdirectfb_matrox_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_matrox_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu gfxdrivers/matrox/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu gfxdrivers/matrox/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-matroxLTLIBRARIES: $(matrox_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(matroxdir)" || $(MKDIR_P) "$(DESTDIR)$(matroxdir)" + @list='$(matrox_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(matroxLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(matroxdir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(matroxLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(matroxdir)/$$f"; \ + else :; fi; \ + done + +uninstall-matroxLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(matrox_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(matroxdir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(matroxdir)/$$p"; \ + done + +clean-matroxLTLIBRARIES: + -test -z "$(matrox_LTLIBRARIES)" || rm -f $(matrox_LTLIBRARIES) + @list='$(matrox_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libdirectfb_matrox.la: $(libdirectfb_matrox_la_OBJECTS) $(libdirectfb_matrox_la_DEPENDENCIES) + $(libdirectfb_matrox_la_LINK) -rpath $(matroxdir) $(libdirectfb_matrox_la_OBJECTS) $(libdirectfb_matrox_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox_3d.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox_bes.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox_crtc2.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox_maven.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/matrox_screen_crtc2.Plo@am__quote@ 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install-matroxLTLIBRARIES install-pdf \ + install-pdf-am install-ps install-ps-am install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-matroxDATA \ + uninstall-matroxLTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox.c b/Source/DirectFB/gfxdrivers/matrox/matrox.c new file mode 100755 index 0000000..d797251 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox.c @@ -0,0 +1,2930 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include + + +DFB_GRAPHICS_DRIVER( matrox ) + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" +#include "matrox_3d.h" +#include "matrox_state.h" + + +static bool matroxFillRectangle ( void *drv, void *dev, DFBRectangle *rect ); +static bool matroxFillRectangle_2P ( void *drv, void *dev, DFBRectangle *rect ); +static bool matroxFillRectangle_3P ( void *drv, void *dev, DFBRectangle *rect ); +static bool matroxFillRectangle_422( void *drv, void *dev, DFBRectangle *rect ); + +static bool matroxBlit2D ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_2P ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_3P ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_422( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_Old( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); + +static bool matroxBlit3D ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit3D_2P ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit3D_3P ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit3D_422( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); + +static bool matroxStretchBlit ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_2P ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_3P ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_422( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); + + +static bool matroxBlit2D_F ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_2P_F ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_3P_F ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_422_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); +static bool matroxBlit2D_Old_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); + +static bool matroxBlit3D_F ( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ); + +static bool matroxStretchBlit_F ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_2P_F ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_3P_F ( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); +static bool matroxStretchBlit_422_F( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ); + + + + +/* Millennium */ + +#define MATROX_2064W_DRAWING_FLAGS (DSDRAW_SRC_PREMULTIPLY) + +#define MATROX_2064W_BLITTING_FLAGS (DSBLIT_NOFX) + +#define MATROX_2064W_DRAWING_FUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE | \ + DFXL_FILLTRIANGLE) + +#define MATROX_2064W_BLITTING_FUNCTIONS (DFXL_BLIT) + + +/* Old cards (Mystique, Millennium II) */ + +#define MATROX_OLD_DRAWING_FLAGS (DSDRAW_SRC_PREMULTIPLY) + +#define MATROX_OLD_BLITTING_FLAGS (DSBLIT_SRC_COLORKEY) + +#define MATROX_OLD_DRAWING_FUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE | \ + DFXL_FILLTRIANGLE) + +#define MATROX_OLD_BLITTING_FUNCTIONS (DFXL_BLIT) + + +/* G100 */ + +#define MATROX_G100_DRAWING_FLAGS (DSDRAW_SRC_PREMULTIPLY) + +#define MATROX_G100_BLITTING_FLAGS (DSBLIT_SRC_COLORKEY | \ + /*DSBLIT_BLEND_ALPHACHANNEL |*/ \ + /*DSBLIT_BLEND_COLORALPHA |*/ \ + DSBLIT_COLORIZE | \ + DSBLIT_SRC_PREMULTCOLOR) + +#define MATROX_G100_DRAWING_FUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE | \ + DFXL_FILLTRIANGLE) + +#define MATROX_G100_BLITTING_FUNCTIONS (DFXL_BLIT | \ + DFXL_STRETCHBLIT) + + +/* G200/G400 */ + +#define MATROX_G200G400_DRAWING_FLAGS (DSDRAW_BLEND | \ + DSDRAW_SRC_PREMULTIPLY) + +#define MATROX_G200G400_BLITTING_FLAGS (DSBLIT_SRC_COLORKEY | \ + DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE | \ + DSBLIT_SRC_PREMULTIPLY | \ + DSBLIT_SRC_PREMULTCOLOR) + +#define MATROX_G200G400_DRAWING_FUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE | \ + DFXL_FILLTRIANGLE) + +#define MATROX_G200G400_BLITTING_FUNCTIONS (DFXL_BLIT | \ + DFXL_STRETCHBLIT | \ + DFXL_TEXTRIANGLES) + + +#define MATROX_USE_TMU(state, accel) \ + ((state)->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE | \ + DSBLIT_SRC_PREMULTIPLY | \ + DSBLIT_SRC_PREMULTCOLOR) || \ + ((state)->destination->config.format != (state)->source->config.format && \ + (state)->destination->config.format != DSPF_I420 && \ + (state)->destination->config.format != DSPF_YV12) || \ + (accel) & (DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES)) + +#define MATROX_USE_3D(state, accel) \ + ((DFB_DRAWING_FUNCTION( accel ) && ((state)->drawingflags & DSDRAW_BLEND)) || \ + (DFB_BLITTING_FUNCTION( accel ) && MATROX_USE_TMU( state, accel ))) + +static void +matroxEngineReset( void *drv, void *dev ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitidle( mdrv, mdev ); + + mga_waitfifo( mdrv, mdev, 11 ); + mga_out32( mmio, 0, TDUALSTAGE0 ); /* multi texture registers */ + mga_out32( mmio, 0, TDUALSTAGE1 ); + mga_out32( mmio, 0, ALPHAXINC ); /* alpha increments */ + mga_out32( mmio, 0, ALPHAYINC ); + mga_out32( mmio, 0, DR6 ); /* red increments */ + mga_out32( mmio, 0, DR7 ); + mga_out32( mmio, 0, DR10 ); /* green increments */ + mga_out32( mmio, 0, DR11 ); + mga_out32( mmio, 0, DR14 ); /* blue increments */ + mga_out32( mmio, 0, DR15 ); + mga_out32( mmio, 0, BCOL ); + + mga_waitfifo( mdrv, mdev, 5 ); + mga_out32( mmio, 0, TMR1 ); + mga_out32( mmio, 0, TMR2 ); + mga_out32( mmio, 0, TMR4 ); + mga_out32( mmio, 0, TMR5 ); + mga_out32( mmio, 0x100000, TMR8 ); + + /* + * Plane write mask is not supported on G100 with SDRAM. + * The chip goes crazy if PLNWT is written. + */ + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG100) { + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, 0xFFFFFFFF, PLNWT ); + } +} + +static DFBResult +matroxEngineSync( void *drv, void *dev ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + mga_waitidle( mdrv, mdev ); + + return DFB_OK; +} + +static void +matroxFlushTextureCache( void *drv, void *dev ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mdrv->mmio_base, 0, TEXORG1 ); +} + +static void +matroxFlushReadCache( void *drv, void *dev ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + + mga_out8( mdrv->mmio_base, 0, CACHEFLUSH ); +} + +static bool +matrox_check_blend( MatroxDeviceData *mdev, + CardState *state ) +{ + switch (state->src_blend) { + case DSBF_SRCCOLOR: + case DSBF_INVSRCCOLOR: + return false; + case DSBF_SRCALPHASAT: + if (!mdev->g550_matrox && state->dst_blend == DSBF_ZERO) + return false; + default: + break; + } + + switch (state->dst_blend) { + case DSBF_DESTCOLOR: + case DSBF_INVDESTCOLOR: + case DSBF_SRCALPHASAT: + return false; + default: + break; + } + + return true; +} + +static void +matrox2064WCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + /* FIXME: 24bit support */ + switch (state->destination->config.format) { + case DSPF_LUT8: + if (DFB_BLITTING_FUNCTION( accel )) + return; + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MATROX_2064W_DRAWING_FLAGS) + return; + + state->accel |= MATROX_2064W_DRAWING_FUNCTIONS; + } + else { + if (state->source->config.format != state->destination->config.format) + return; + + if (state->blittingflags & ~MATROX_2064W_BLITTING_FLAGS) + return; + + state->accel |= MATROX_2064W_BLITTING_FUNCTIONS; + } +} + +static void +matroxOldCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + /* FIXME: 24bit support */ + switch (state->destination->config.format) { + case DSPF_LUT8: + if (DFB_BLITTING_FUNCTION( accel )) + return; + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MATROX_OLD_DRAWING_FLAGS) + return; + + state->accel |= MATROX_OLD_DRAWING_FUNCTIONS; + } + else { + if (state->source->config.format != state->destination->config.format) + return; + + if (state->blittingflags & ~MATROX_OLD_BLITTING_FLAGS) + return; + + state->accel |= MATROX_OLD_BLITTING_FUNCTIONS; + } +} + +static void +matroxG100CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + /* FIXME: 24bit support */ + switch (state->destination->config.format) { + case DSPF_LUT8: + if (DFB_BLITTING_FUNCTION( accel )) + return; + case DSPF_A8: + case DSPF_RGB444: + case DSPF_ARGB4444: + if (DFB_BLITTING_FUNCTION( accel ) && MATROX_USE_TMU( state, accel )) + return; + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MATROX_G100_DRAWING_FLAGS) + return; + + state->accel |= MATROX_G100_DRAWING_FUNCTIONS; + } + else { + if (state->blittingflags & ~MATROX_G100_BLITTING_FLAGS) + return; + + /* using the texture mapping unit? */ + if (MATROX_USE_TMU( state, accel )) { + int max_width = 2048; + + /* TMU has no 32bit support */ + switch (state->source->config.format) { + case DSPF_LUT8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + break; + default: + return; + } + + /* Interleaved source -> pitch must be doubled */ + if ((state->source->config.caps & (DSCAPS_INTERLACED | + DSCAPS_SEPARATED)) == DSCAPS_INTERLACED && + (state->destination->config.caps & DSCAPS_INTERLACED || + state->blittingflags & DSBLIT_DEINTERLACE)) + max_width = 1024; + + /* TMU limits */ + if (state->source->config.size.w < 8 || + state->source->config.size.h < 8 || + state->source->config.size.w > max_width || + state->source->config.size.h > 2048) + return; + + state->accel |= MATROX_G100_BLITTING_FUNCTIONS; + } + else { + /* source and destination formats equal, no stretching is done */ + state->accel |= accel; + } + } +} + +static void +matroxG200CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + /* FIXME: 24bit support */ + switch (state->destination->config.format) { + case DSPF_NV12: + case DSPF_NV21: + if ((accel & DFXL_FILLRECTANGLE && !state->drawingflags) || + (accel & DFXL_BLIT && !state->blittingflags && + state->source->config.format == state->destination->config.format)) + break; + return; + case DSPF_YUY2: + if ((accel & DFXL_FILLRECTANGLE && !state->drawingflags) || + (accel & (DFXL_BLIT | DFXL_STRETCHBLIT) && + !(state->blittingflags & ~DSBLIT_DEINTERLACE) && + state->source->config.format == state->destination->config.format)) + break; + return; + case DSPF_LUT8: + if (DFB_BLITTING_FUNCTION( accel )) + return; + case DSPF_A8: + case DSPF_RGB444: + case DSPF_ARGB4444: + if (MATROX_USE_3D( state, accel )) + return; + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MATROX_G200G400_DRAWING_FLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + !matrox_check_blend( mdev, state )) + return; + + state->accel |= MATROX_G200G400_DRAWING_FUNCTIONS; + } + else { + bool use_tmu = MATROX_USE_TMU( state, accel ); + + switch (state->source->config.format) { + case DSPF_NV12: + case DSPF_NV21: + if (state->destination->config.format != state->source->config.format) + return; + break; + case DSPF_A8: + if (use_tmu) + return; + case DSPF_LUT8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_YUY2: + break; + default: + return; + } + + if (state->blittingflags & ~MATROX_G200G400_BLITTING_FLAGS) + return; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + if (!matrox_check_blend( mdev, state )) + return; + + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY && + (state->src_blend != DSBF_ONE || + (state->dst_blend != DSBF_INVSRCALPHA && + state->dst_blend != DSBF_INVSRCCOLOR))) + return; + } else { + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + } + + if (use_tmu) { + int max_width = 2048; + + /* Interleaved source -> pitch must be doubled */ + if ((state->source->config.caps & (DSCAPS_INTERLACED | + DSCAPS_SEPARATED)) == DSCAPS_INTERLACED && + (state->destination->config.caps & DSCAPS_INTERLACED || + state->blittingflags & DSBLIT_DEINTERLACE) && + state->destination->config.format != DSPF_YUY2) + max_width = 1024; + + if (state->source->config.size.w < 8 || + state->source->config.size.h < 8 || + state->source->config.size.w > max_width || + state->source->config.size.h > 2048) + return; + + state->accel |= MATROX_G200G400_BLITTING_FUNCTIONS; + } + else { + /* source and destination formats equal, no stretching is done */ + state->accel |= accel; + } + } +} + +static void +matroxG400CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + /* FIXME: 24bit support */ + switch (state->destination->config.format) { + case DSPF_I420: + case DSPF_YV12: + if ((accel & DFXL_FILLRECTANGLE && !state->drawingflags) || + (accel & (DFXL_BLIT | DFXL_STRETCHBLIT) && + !(state->blittingflags & ~DSBLIT_DEINTERLACE) && + (state->source->config.format == DSPF_I420 || + state->source->config.format == DSPF_YV12))) + break; + return; + case DSPF_NV12: + case DSPF_NV21: + case DSPF_YUY2: + case DSPF_UYVY: + if ((accel & DFXL_FILLRECTANGLE && !state->drawingflags) || + (accel & (DFXL_BLIT | DFXL_STRETCHBLIT) && + !(state->blittingflags & ~DSBLIT_DEINTERLACE) && + state->source->config.format == state->destination->config.format)) + break; + return; + case DSPF_LUT8: + case DSPF_ALUT44: + if (DFB_BLITTING_FUNCTION( accel )) + return; + case DSPF_A8: + case DSPF_RGB444: + case DSPF_ARGB4444: + if (MATROX_USE_3D( state, accel )) + return; + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~MATROX_G200G400_DRAWING_FLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + !matrox_check_blend( mdev, state )) + return; + + state->accel |= MATROX_G200G400_DRAWING_FUNCTIONS; + } + else { + bool use_tmu = MATROX_USE_TMU( state, accel ); + + switch (state->source->config.format) { + case DSPF_I420: + case DSPF_YV12: + if (state->destination->config.format != DSPF_I420 && + state->destination->config.format != DSPF_YV12) + return; + break; + case DSPF_NV12: + case DSPF_NV21: + if (state->destination->config.format != state->source->config.format) + return; + break; + case DSPF_RGB332: + if (use_tmu) + return; + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + case DSPF_YUY2: + case DSPF_UYVY: + break; + default: + return; + } + + if (state->blittingflags & ~MATROX_G200G400_BLITTING_FLAGS) + return; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + if (!matrox_check_blend( mdev, state )) + return; + + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY && + (state->src_blend != DSBF_ONE || + (state->dst_blend != DSBF_INVSRCALPHA && + state->dst_blend != DSBF_INVSRCCOLOR))) + return; + } else { + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + } + + if (use_tmu) { + int max_width = 2048; + + /* Interleaved source -> pitch must be doubled */ + if ((state->source->config.caps & (DSCAPS_INTERLACED | + DSCAPS_SEPARATED)) == DSCAPS_INTERLACED && + (state->destination->config.caps & DSCAPS_INTERLACED || + state->blittingflags & DSBLIT_DEINTERLACE) && + state->destination->config.format != DSPF_YUY2 && + state->destination->config.format != DSPF_UYVY) + max_width = 1024; + + if (state->source->config.size.w < 8 || + state->source->config.size.h < 8 || + state->source->config.size.w > max_width || + state->source->config.size.h > 2048) + return; + + state->accel |= MATROX_G200G400_BLITTING_FUNCTIONS; + } + else { + /* source and destination formats equal, no stretching is done */ + state->accel |= accel; + } + } +} + +static void +matroxSetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + bool prev_blit_fields = mdev->blit_fields; + + if (state->mod_hw == SMF_ALL) { + mdev->valid = 0; + + /* + * Work around TMU bug(?), under some unclear circumstances + * the TMU's read address (src & dst) gets corrupted (negative offset + * applied to written values) until soft reset occured. + */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG200) + mga_waitidle( mdrv, mdev ); + } + else if (state->mod_hw) { + if (state->mod_hw & SMF_COLOR) + MGA_INVALIDATE( m_drawColor | m_blitColor | m_color ); + + if (state->mod_hw & SMF_CLIP) + MGA_INVALIDATE( m_clip ); + + if (state->mod_hw & SMF_DESTINATION) + MGA_INVALIDATE( m_destination | m_clip | m_color | m_Source | m_source ); + + if (state->mod_hw & SMF_SOURCE) + MGA_INVALIDATE( m_Source | m_source | m_SrcKey | m_srckey | m_blitBlend ); + else if (state->mod_hw & SMF_SRC_COLORKEY) + MGA_INVALIDATE( m_SrcKey | m_srckey ); + + if (state->mod_hw & SMF_DRAWING_FLAGS) + MGA_INVALIDATE( m_drawColor | m_color ); + + if (state->mod_hw & SMF_BLITTING_FLAGS) + MGA_INVALIDATE( m_Source | m_SrcKey | m_blitBlend | m_blitColor ); + + if (state->mod_hw & (SMF_DST_BLEND | SMF_SRC_BLEND)) + MGA_INVALIDATE( m_blitBlend | m_drawBlend ); + } + + switch (accel) { + case DFXL_BLIT: + mdev->blit_deinterlace = state->blittingflags & DSBLIT_DEINTERLACE; + mdev->blit_fields = !mdev->blit_deinterlace && + state->source->config.caps & DSCAPS_INTERLACED && + state->destination->config.caps & DSCAPS_INTERLACED && + (state->source->config.caps & DSCAPS_SEPARATED || + state->destination->config.caps & DSCAPS_SEPARATED); + break; + case DFXL_STRETCHBLIT: + mdev->blit_deinterlace = state->blittingflags & DSBLIT_DEINTERLACE; + mdev->blit_fields = !mdev->blit_deinterlace && + state->source->config.caps & DSCAPS_INTERLACED && + state->destination->config.caps & DSCAPS_INTERLACED; + break; + default: + mdev->blit_deinterlace = 0; + mdev->blit_fields = 0; + } + + if (prev_blit_fields != mdev->blit_fields) + MGA_INVALIDATE( m_destination | m_source | m_Source ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + if (state->drawingflags & DSDRAW_BLEND) { + mdev->draw_blend = 1; + matrox_validate_drawColor( mdrv, mdev, state ); + matrox_validate_drawBlend( mdrv, mdev, state ); + } + else { + mdev->draw_blend = 0; + matrox_validate_color( mdrv, mdev, state ); + } + + switch (state->destination->config.format) { + case DSPF_YUY2: + case DSPF_UYVY: + funcs->FillRectangle = matroxFillRectangle_422; + state->set = DFXL_FILLRECTANGLE; + break; + case DSPF_I420: + case DSPF_YV12: + funcs->FillRectangle = matroxFillRectangle_3P; + state->set = DFXL_FILLRECTANGLE; + break; + case DSPF_NV12: + case DSPF_NV21: + funcs->FillRectangle = matroxFillRectangle_2P; + state->set = DFXL_FILLRECTANGLE; + break; + default: + funcs->FillRectangle = matroxFillRectangle; + state->set = DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE | DFXL_FILLTRIANGLE; + } + break; + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + mdev->blit_src_colorkey = state->blittingflags & DSBLIT_SRC_COLORKEY; + + if (MATROX_USE_TMU( state, accel )) { + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_COLORIZE | + DSBLIT_SRC_PREMULTCOLOR)) + matrox_validate_blitColor( mdrv, mdev, state ); + + switch (state->destination->config.format) { + case DSPF_YUY2: + case DSPF_UYVY: + if (mdev->blit_fields) { + funcs->Blit = NULL; + funcs->StretchBlit = matroxStretchBlit_422_F; + } else { + funcs->Blit = matroxBlit3D_422; + funcs->StretchBlit = matroxStretchBlit_422; + } + state->set = DFXL_BLIT | DFXL_STRETCHBLIT; + break; + case DSPF_I420: + case DSPF_YV12: + if (mdev->blit_fields) { + funcs->Blit = NULL; + funcs->StretchBlit = matroxStretchBlit_3P_F; + } else { + funcs->Blit = matroxBlit3D_3P; + funcs->StretchBlit = matroxStretchBlit_3P; + } + state->set = DFXL_BLIT | DFXL_STRETCHBLIT; + break; + case DSPF_NV12: + case DSPF_NV21: + if (mdev->blit_fields) { + funcs->Blit = NULL; + funcs->StretchBlit = matroxStretchBlit_2P_F; + } else { + funcs->Blit = matroxBlit3D_2P; + funcs->StretchBlit = matroxStretchBlit_2P; + } + state->set = DFXL_BLIT | DFXL_STRETCHBLIT; + break; + default: + if (mdev->blit_fields) { + funcs->Blit = matroxBlit3D_F; + funcs->StretchBlit = matroxStretchBlit_F; + } else { + funcs->Blit = matroxBlit3D; + funcs->StretchBlit = matroxStretchBlit; + } + state->set = DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES; + } + + matrox_validate_blitBlend( mdrv, mdev, state ); + matrox_validate_Source( mdrv, mdev, state ); + + matrox_validate_SrcKey( mdrv, mdev, state ); + } + else { + switch (state->destination->config.format) { + case DSPF_YUY2: + case DSPF_UYVY: + funcs->Blit = mdev->blit_fields ? + matroxBlit2D_422_F : matroxBlit2D_422; + break; + case DSPF_I420: + case DSPF_YV12: + funcs->Blit = mdev->blit_fields ? + matroxBlit2D_3P_F : matroxBlit2D_3P; + break; + case DSPF_NV12: + case DSPF_NV21: + funcs->Blit = mdev->blit_fields ? + matroxBlit2D_2P_F : matroxBlit2D_2P; + break; + default: + if (mdev->old_matrox) + funcs->Blit = mdev->blit_fields ? + matroxBlit2D_Old_F : matroxBlit2D_Old; + else + funcs->Blit = mdev->blit_fields ? + matroxBlit2D_F : matroxBlit2D; + } + + matrox_validate_source( mdrv, mdev, state ); + + if (mdev->blit_src_colorkey) + matrox_validate_srckey( mdrv, mdev, state ); + + state->set = DFXL_BLIT; + } + break; + default: + D_BUG( "unexpected drawing/blitting function!" ); + break; + } + + matrox_validate_destination( mdrv, mdev, state ); + + if (!MGA_IS_VALID( m_clip )) { + mdev->clip = state->clip; + if (state->destination->config.format == DSPF_YUY2 || + state->destination->config.format == DSPF_UYVY) { + mdev->clip.x1 /= 2; + mdev->clip.x2 /= 2; + } + if (mdev->blit_fields) { + mdev->clip.y1 /= 2; + mdev->clip.y2 /= 2; + } + matrox_set_clip( mdrv, mdev, &mdev->clip ); + MGA_VALIDATE( m_clip ); + } + + state->mod_hw = 0; +} + +/******************************************************************************/ + +static void +matrox_fill_rectangle( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRectangle *rect ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitfifo( mdrv, mdev, 3 ); + + if (mdev->draw_blend) + mga_out32( mmio, BOP_COPY | SHFTZERO | SGNZERO | + ARZERO | ATYPE_I | OP_TRAP, DWGCTL ); + else + mga_out32( mmio, TRANSC | BOP_COPY | SHFTZERO | SGNZERO | ARZERO | + SOLID | mdev->atype_blk_rstr | OP_TRAP, DWGCTL ); + + mga_out32( mmio, (RS16(rect->x + rect->w) << 16) | RS16(rect->x), FXBNDRY ); + mga_out32( mmio, (RS16(rect->y) << 16) | RS16(rect->h), YDSTLEN | EXECUTE ); +} + +static bool +matroxFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matrox_fill_rectangle( mdrv, mdev, rect ); + + return true; +} + +static bool +matroxFillRectangle_2P( void *drv, void *dev, DFBRectangle *rect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + matrox_fill_rectangle( mdrv, mdev, rect ); + + rect->x /= 2; + rect->y /= 2; + rect->w = (rect->w + 1) / 2; + rect->h = (rect->h + 1) / 2; + + /* CbCr plane */ + mga_waitfifo( mdrv, mdev, 7 ); + mga_out32( mmio, PW16 | NODITHER, MACCESS ); + mga_out32( mmio, mdev->color[1], FCOL ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 4) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 4) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + matrox_fill_rectangle( mdrv, mdev, rect ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 4 ); + mga_out32( mmio, PW8 | BYPASS332 | NODITHER, MACCESS ); + mga_out32( mmio, mdev->color[0], FCOL ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +static bool +matroxFillRectangle_3P( void *drv, void *dev, DFBRectangle *rect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + matrox_fill_rectangle( mdrv, mdev, rect ); + + rect->x /= 2; + rect->y /= 2; + rect->w = (rect->w + 1) / 2; + rect->h = (rect->h + 1) / 2; + + /* Cb plane */ + mga_waitfifo( mdrv, mdev, 6 ); + mga_out32( mmio, mdev->color[1], FCOL ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 4) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 4) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + matrox_fill_rectangle( mdrv, mdev, rect ); + + /* Cr plane */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->color[2], FCOL ); + mga_out32( mmio, mdev->dst_offset[0][2], DSTORG ); + + matrox_fill_rectangle( mdrv, mdev, rect ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 3 ); + mga_out32( mmio, mdev->color[0], FCOL ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +static bool +matroxFillRectangle_422( void *drv, void *dev, DFBRectangle *rect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + rect->x /= 2; + rect->w = (rect->w + 1) / 2; + + matrox_fill_rectangle( mdrv, mdev, rect ); + + return true; +} + +static bool +matroxDrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitfifo( mdrv, mdev, 6 ); + + if (mdev->draw_blend) + mga_out32( mmio, BLTMOD_BFCOL | BOP_COPY | ATYPE_I | + OP_AUTOLINE_OPEN, DWGCTL ); + else + mga_out32( mmio, BLTMOD_BFCOL | BOP_COPY | SHFTZERO | SOLID | + ATYPE_RSTR | OP_AUTOLINE_OPEN, DWGCTL ); + + mga_out32(mmio, RS16(rect->x) | + (RS16(rect->y) << 16), + XYSTRT); + + mga_out32(mmio, RS16(rect->x + rect->w-1) | (RS16(rect->y) << 16), + XYEND | EXECUTE); + + mga_out32(mmio, RS16(rect->x + rect->w-1) | + (RS16(rect->y + rect->h-1) << 16), + XYEND | EXECUTE); + + mga_out32(mmio, RS16(rect->x) | + (RS16(rect->y + rect->h-1) << 16), + XYEND | EXECUTE); + + mga_out32(mmio, RS16(rect->x) | + (RS16(rect->y) << 16), + XYEND | EXECUTE); + + return true; +} + +static bool +matroxDrawLine( void *drv, void *dev, DFBRegion *line ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitfifo( mdrv, mdev, 3 ); + + if (mdev->draw_blend) + mga_out32( mmio, BLTMOD_BFCOL | BOP_COPY | ATYPE_I | + OP_AUTOLINE_CLOSE, + DWGCTL ); + else + mga_out32( mmio, BLTMOD_BFCOL | BOP_COPY | SHFTZERO | SOLID | + ATYPE_RSTR | OP_AUTOLINE_CLOSE, + DWGCTL ); + + mga_out32( mmio, RS16(line->x1) | (RS16(line->y1) << 16), + XYSTRT ); + + mga_out32( mmio, RS16(line->x2) | (RS16(line->y2) << 16), + XYEND | EXECUTE ); + + return true; +} + +/******************************************************************************/ + +static void +matrox_fill_trapezoid( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + int Xl, int Xr, int X2l, + int X2r, int Y, int dY ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + int dxl = X2l - Xl; + int dxr = ++X2r - ++Xr; + + int dXl = ABS(dxl); + int dXr = ABS(dxr); + + u32 sgn = 0; + + mga_waitfifo( mdrv, mdev, 6 ); + + mga_out32( mmio, dY, AR0 ); + mga_out32( mmio, - dXl, AR1 ); + mga_out32( mmio, - dXl, AR2 ); + mga_out32( mmio, - dXr, AR4 ); + mga_out32( mmio, - dXr, AR5 ); + mga_out32( mmio, dY, AR6 ); + + if (dxl < 0) + sgn |= SDXL; + if (dxr < 0) + sgn |= SDXR; + + mga_waitfifo( mdrv, mdev, 3 ); + + mga_out32( mmio, sgn, SGN ); + mga_out32( mmio, (RS16(Xr) << 16) | RS16(Xl), FXBNDRY ); + mga_out32( mmio, (RS16(Y) << 16) | RS16(dY), YDSTLEN | EXECUTE ); +} + +static bool +matroxFillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitfifo( mdrv, mdev, 1 ); + + if (mdev->draw_blend) + mga_out32( mmio, BOP_COPY | SHFTZERO | ATYPE_I | OP_TRAP, + DWGCTL ); + else + mga_out32( mmio, TRANSC | BOP_COPY | SHFTZERO | + SOLID | mdev->atype_blk_rstr | OP_TRAP, + DWGCTL ); + + dfb_sort_triangle( tri ); + + if (tri->y2 == tri->y3) { + matrox_fill_trapezoid( mdrv, mdev, tri->x1, tri->x1, + MIN( tri->x2, tri->x3 ), MAX( tri->x2, tri->x3 ), + tri->y1, tri->y3 - tri->y1 + 1 ); + } else + if (tri->y1 == tri->y2) { + matrox_fill_trapezoid( mdrv, mdev, + MIN( tri->x1, tri->x2 ), MAX( tri->x1, tri->x2 ), + tri->x3, tri->x3, tri->y1, tri->y3 - tri->y1 + 1 ); + } + else { + int majDx = tri->x3 - tri->x1; + int majDy = tri->y3 - tri->y1; + int topDx = tri->x2 - tri->x1; + int topDy = tri->y2 - tri->y1; + int botDy = tri->y3 - tri->y2; + + int topXperY = (topDx << 20) / topDy; + int X2a = tri->x1 + (((topXperY * topDy) + (1<<19)) >> 20); + + int majXperY = (majDx << 20) / majDy; + int majX2 = tri->x1 + (((majXperY * topDy) + (1<<19)) >> 20); + int majX2a = majX2 - ((majXperY + (1<<19)) >> 20); + + matrox_fill_trapezoid( mdrv, mdev, tri->x1, tri->x1, + MIN( X2a, majX2a ), MAX( X2a, majX2a ), + tri->y1, topDy ); + matrox_fill_trapezoid( mdrv, mdev, + MIN( tri->x2, majX2 ), MAX( tri->x2, majX2 ), + tri->x3, tri->x3, tri->y2, botDy + 1 ); + } + + return true; +} + +/******************************************************************************/ + +static void +matroxDoBlit2D_Old( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + int sx, int sy, + int dx, int dy, + int w, int h, + int pitch, int offset ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 dwgctl = BLTMOD_BFCOL | BOP_COPY | SHFTZERO | ATYPE_RSTR | OP_BITBLT; + u32 start, end; + u32 sgn = 0; + s32 pixelpitch = pitch; + + if (sx < dx) + sgn |= BLIT_LEFT; + if (sy < dy) + sgn |= BLIT_UP; + + if (sgn & BLIT_UP) { + sy += h - 1; + dy += h - 1; + } + + start = sy * pixelpitch + sx + offset; + + w--; + + end = w; + + if (sgn & BLIT_LEFT) { + start += w; + end = -end; + } + + if (sgn & BLIT_UP) + pixelpitch = -pixelpitch; + + if (mdev->blit_src_colorkey) + dwgctl |= TRANSC; + + mga_waitfifo( mdrv, mdev, 7 ); + mga_out32( mmio, dwgctl, DWGCTL ); + mga_out32( mmio, pixelpitch & 0x3FFFFF, AR5 ); + mga_out32( mmio, start & 0xFFFFFF, AR3 ); + mga_out32( mmio, end & 0x3FFFF, AR0 ); + mga_out32( mmio, sgn, SGN ); + mga_out32( mmio, (RS16(dx+w) << 16) | RS16(dx), FXBNDRY ); + mga_out32( mmio, (RS16(dy) << 16) | RS16(h), YDSTLEN | EXECUTE ); +} + +static bool +matroxBlit2D_Old( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxDoBlit2D_Old( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch, + mdev->src_offset[0][0] ); + + return true; +} + +static bool +matroxBlit2D_Old_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = rect->y & 1; + dst_field = dy & 1; + + /* fisrt field */ + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlit2D_Old( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch, + mdev->src_offset[src_field][0] ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlit2D_Old( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch, + mdev->src_offset[!src_field][0] ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + return true; +} + +/******************************************************************************/ + +static void +matroxDoBlit2D( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + int sx, int sy, + int dx, int dy, + int w, int h, + int pitch ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 dwgctl = BLTMOD_BFCOL | BOP_COPY | SHFTZERO | ATYPE_RSTR | OP_BITBLT; + u32 start, end; + u32 sgn = 0; + s32 pixelpitch = pitch; + + if (sx < dx) + sgn |= BLIT_LEFT; + if (sy < dy) + sgn |= BLIT_UP; + + if (sgn & BLIT_UP) { + sy += h - 1; + dy += h - 1; + } + + start = end = sy * pixelpitch + sx; + + w--; + + if (sgn & BLIT_LEFT) + start += w; + else + end += w; + + if (sgn & BLIT_UP) + pixelpitch = -pixelpitch; + + if (mdev->blit_src_colorkey) + dwgctl |= TRANSC; + + mga_waitfifo( mdrv, mdev, 7 ); + mga_out32( mmio, dwgctl, DWGCTL ); + mga_out32( mmio, pixelpitch & 0x3FFFFF, AR5 ); + mga_out32( mmio, start & 0xFFFFFF, AR3 ); + mga_out32( mmio, end & 0x3FFFFF, AR0 ); + mga_out32( mmio, sgn, SGN ); + mga_out32( mmio, (RS16(dx+w) << 16) | RS16(dx), FXBNDRY ); + mga_out32( mmio, (RS16(dy) << 16) | RS16(h), YDSTLEN | EXECUTE ); +} + +static bool +matroxBlit2D( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch ); + + return true; +} + +static bool +matroxBlit2D_2P( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch ); + + rect->x &= ~1; + rect->y /= 2; + rect->w = (rect->w + 1) & ~1; + rect->h = (rect->h + 1) / 2; + dx &= ~1; + dy /= 2; + + /* CbCr plane */ + mga_waitfifo( mdrv, mdev, 4 ); + mga_out32( mmio, mdev->src_offset[0][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 2) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 2) & 0xFFFFFF, YBOT ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 4 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2) & 0xFFFFFF, YBOT ); + + return true; +} + +static bool +matroxBlit2D_3P( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch ); + + rect->x /= 2; + rect->y /= 2; + rect->w = (rect->w + 1) / 2; + rect->h = (rect->h + 1) / 2; + dx /= 2; + dy /= 2; + + /* Cb plane */ + mga_waitfifo( mdrv, mdev, 6 ); + mga_out32( mmio, mdev->src_offset[0][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 4) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 4) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch/2 ); + + /* Cr plane */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[0][2], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][2], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch/2 ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 3 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +static bool +matroxBlit2D_422( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + dx /= 2; + rect->x /= 2; + rect->w = (rect->w + 1) / 2; + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y, + dx, dy, + rect->w, rect->h, + mdev->src_pitch ); + + return true; +} + +static bool +matroxBlit2D_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = rect->y & 1; + dst_field = dy & 1; + + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + return true; +} + +static bool +matroxBlit2D_2P_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = rect->y & 1; + dst_field = dy & 1; + + /* Y plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch ); + + /* Subsampling */ + rect->x &= ~1; + rect->y /= 2; + rect->w = (rect->w + 1) & ~1; + rect->h = (rect->h + 1) / 2; + dx &= ~1; + dy /= 2; + + mga_waitfifo( mdrv, mdev, 4 ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1/2) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2/2) & 0xFFFFFF, YBOT ); + + /* CbCr plane */ + /* First field */ + mga_out32( mmio, mdev->src_offset[src_field][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][1], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][1], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 4 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2) & 0xFFFFFF, YBOT ); + + return true; +} + +static bool +matroxBlit2D_3P_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = rect->y & 1; + dst_field = dy & 1; + + /* Y plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch ); + + /* Subsampling */ + rect->x /= 2; + rect->y /= 2; + rect->w = (rect->w + 1) / 2; + rect->h = (rect->h + 1) / 2; + dx /= 2; + dy /= 2; + + mga_waitfifo( mdrv, mdev, 6 ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y1/2) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y2/2) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + /* Cb plane */ + /* First field */ + mga_out32( mmio, mdev->src_offset[src_field][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][1], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch/2 ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][1], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][1], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch/2 ); + + /* Cr plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][2], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][2], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch/2 ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][2], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][2], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch/2 ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 3 ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +static bool +matroxBlit2D_422_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = rect->y & 1; + dst_field = dy & 1; + + dx /= 2; + rect->x /= 2; + rect->w = (rect->w + 1) / 2; + + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, rect->y/2, + dx, dy/2, + rect->w, (rect->h+1)/2, + mdev->src_pitch ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlit2D( mdrv, mdev, + rect->x, (rect->y+1)/2, + dx, (dy+1)/2, + rect->w, rect->h/2, + mdev->src_pitch ); + + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + return true; +} + +/******************************************************************************/ + +static inline void +matroxDoBlitTMU( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + int sx, int sy, + int dx, int dy, + int sw, int sh, + int dw, int dh, + int w2, int h2, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + s32 startx, starty, incx, incy; + + if (mdev->blit_deinterlace) { + sy /= 2; + sh /= 2; + } + + incx = (sw << (20 - w2)) / dw; + incy = (sh << (20 - h2)) / dh; + + startx = sx << (20 - w2); + starty = sy << (20 - h2); + + if (mdev->blit_deinterlace && !mdev->field) + starty += (0x80000 >> h2); + + mga_waitfifo( mdrv, mdev, 8); + + mga_out32( mmio, BOP_COPY | SHFTZERO | SGNZERO | ARZERO | ATYPE_I | OP_TEXTURE_TRAP, DWGCTL ); + + if (filter) + mga_out32( mmio, (0x10<<21) | MAG_BILIN | MIN_BILIN, TEXFILTER ); + else + mga_out32( mmio, (0x10<<21) | MAG_NRST | MIN_NRST, TEXFILTER ); + + mga_out32( mmio, incx, TMR0 ); + mga_out32( mmio, incy, TMR3 ); + mga_out32( mmio, startx, TMR6 ); + mga_out32( mmio, starty, TMR7 ); + mga_out32( mmio, (RS16(dx+dw) << 16) | RS16(dx), FXBNDRY ); + mga_out32( mmio, (RS16(dy) << 16) | RS16(dh), YDSTLEN | EXECUTE ); +} + +static inline void +matroxBlitTMU( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2, mdev->h2, + filter ); +} + +static inline void +matroxBlitTMU_2P( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + u32 texctl; + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2, mdev->h2, + filter ); + + srect->x /= 2; + srect->y /= 2; + srect->w = (srect->w + 1) / 2; + srect->h = (srect->h + 1) / 2; + drect->x /= 2; + drect->y /= 2; + drect->w = (drect->w + 1) / 2; + drect->h = (drect->h + 1) / 2; + + texctl = mdev->texctl & ~(TPITCHEXT | TFORMAT); + texctl |= (((mdev->src_pitch/2) << 9) & TPITCHEXT) | TW16; + + /* CbCr plane */ + mga_waitfifo( mdrv, mdev, 10 ); + mga_out32( mmio, texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 3) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 3) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->src_offset[0][1], TEXORG ); + + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, PW16 | NODITHER, MACCESS ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 4) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 4) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + /* No filtering since we're not using real RGB16 data */ + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2-1, mdev->h2-1, + false ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 7 ); + mga_out32( mmio, mdev->texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 4) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 4) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + + mga_out32( mmio, mdev->dst_pitch, PITCH ); + mga_out32( mmio, PW8 | BYPASS332 | NODITHER, MACCESS ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); +} + +static inline void +matroxBlitTMU_3P( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + u32 texctl; + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2, mdev->h2, + filter ); + + srect->x /= 2; + srect->y /= 2; + srect->w = (srect->w + 1) / 2; + srect->h = (srect->h + 1) / 2; + drect->x /= 2; + drect->y /= 2; + drect->w = (drect->w + 1) / 2; + drect->h = (drect->h + 1) / 2; + + texctl = mdev->texctl & ~TPITCHEXT; + texctl |= ((mdev->src_pitch/2) << 9) & TPITCHEXT; + + /* Cb plane */ + mga_waitfifo( mdrv, mdev, 9 ); + mga_out32( mmio, texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 3) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 3) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->src_offset[0][1], TEXORG ); + + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][1], DSTORG ); + + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y1 / 4) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * mdev->clip.y2 / 4) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2-1, mdev->h2-1, + filter ); + + /* Cr plane */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[0][2], TEXORG ); + + mga_out32( mmio, mdev->dst_offset[0][2], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y, + drect->x, drect->y, + srect->w, srect->h, + drect->w, drect->h, + mdev->w2-1, mdev->h2-1, + filter ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 6 ); + mga_out32( mmio, mdev->texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 4) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 4) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + + mga_out32( mmio, mdev->dst_pitch, PITCH ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); +} + +static bool +matroxStretchBlit( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxBlitTMU( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxStretchBlit_2P( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxBlitTMU_2P( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxStretchBlit_3P( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxBlitTMU_3P( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxStretchBlit_422( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + srect->x /= 2; + srect->w = (srect->w + 1) / 2; + drect->x /= 2; + drect->w = (drect->w + 1) / 2; + + matroxBlitTMU( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxBlit3D( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + matroxBlitTMU( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool +matroxBlit3D_2P( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + matroxBlitTMU_2P( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool +matroxBlit3D_3P( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + matroxBlitTMU_3P( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static bool +matroxBlit3D_422( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + DFBRectangle drect= { dx, dy, rect->w, rect->h }; + + rect->x /= 2; + rect->w = (rect->w + 1) / 2; + drect.x /= 2; + drect.w = (drect.w + 1) / 2; + + matroxBlitTMU( mdrv, mdev, rect, &drect, mdev->blit_deinterlace ); + + return true; +} + +static void +matroxBlitTMU_F( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRectangle *srect, + DFBRectangle *drect, + bool filter ) +{ + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + + src_field = srect->y & 1; + dst_field = drect->y & 1; + + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2, mdev->h2, filter ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2, mdev->h2, filter ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); +} + +static bool +matroxBlit3D_F( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + DFBRectangle drect = { dx, dy, rect->w, rect->h }; + + matroxBlitTMU_F( mdrv, mdev, rect, &drect, false ); + + return true; +} + +static bool +matroxStretchBlit_F( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + matroxBlitTMU_F( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxStretchBlit_422_F( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + + srect->x /= 2; + srect->w = (srect->w + 1) / 2; + drect->x /= 2; + drect->w = (drect->w + 1) / 2; + + matroxBlitTMU_F( mdrv, mdev, srect, drect, true ); + + return true; +} + +static bool +matroxStretchBlit_2P_F( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + u32 texctl; + + src_field = srect->y & 1; + dst_field = drect->y & 1; + + /* Y plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2, mdev->h2, true ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2, mdev->h2, true ); + + /* Subsampling */ + srect->x /= 2; + srect->y /= 2; + srect->w = (srect->w + 1) / 2; + srect->h = (srect->h + 1) / 2; + drect->x /= 2; + drect->y /= 2; + drect->w = (drect->w + 1) / 2; + drect->h = (drect->h + 1) / 2; + + texctl = mdev->texctl & ~(TPITCHEXT | TFORMAT); + texctl |= (((mdev->src_pitch/2) << 9) & TPITCHEXT) | TW16; + + mga_waitfifo( mdrv, mdev, 10 ); + mga_out32( mmio, texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 3) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 3) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, PW16 | NODITHER, MACCESS ); + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y1/2) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y2/2) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + /* CbCr plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][1], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][1], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][1], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][1], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 7 ); + mga_out32( mmio, mdev->texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 4) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 4) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + mga_out32( mmio, PW8 | BYPASS332 | NODITHER, MACCESS ); + + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +static bool +matroxStretchBlit_3P_F( void *drv, void *dev, + DFBRectangle *srect, DFBRectangle *drect ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + int src_field, dst_field; + u32 texctl; + + src_field = srect->y & 1; + dst_field = drect->y & 1; + + /* Y plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2, mdev->h2, true ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][0], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2, mdev->h2, true ); + + /* Subsampling */ + srect->x /= 2; + srect->y /= 2; + srect->w = (srect->w + 1) / 2; + srect->h = (srect->h + 1) / 2; + drect->x /= 2; + drect->y /= 2; + drect->w = (drect->w + 1) / 2; + drect->h = (drect->h + 1) / 2; + + texctl = mdev->texctl & ~TPITCHEXT; + texctl |= ((mdev->src_pitch/2) << 9) & TPITCHEXT; + + mga_waitfifo( mdrv, mdev, 9 ); + mga_out32( mmio, texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 3) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h/2 - 1) & 0x7ff) << 18) | + (((u32)(3 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 3) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->dst_pitch/2, PITCH ); + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y1/2) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch/2 * mdev->clip.y2/2) & 0xFFFFFF, YBOT ); + mga_out32( mmio, ((mdev->clip.x2/2 & 0x0FFF) << 16) | (mdev->clip.x1/2 & 0x0FFF), CXBNDRY ); + + /* Cb plane */ + /* First field */ + mga_out32( mmio, mdev->src_offset[src_field][1], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][1], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][1], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][1], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Cr plane */ + /* First field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[src_field][2], TEXORG ); + mga_out32( mmio, mdev->dst_offset[dst_field][2], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, srect->y/2, + drect->x, drect->y/2, + srect->w, (srect->h+1)/2, + drect->w, (drect->h+1)/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Second field */ + mga_waitfifo( mdrv, mdev, 2 ); + mga_out32( mmio, mdev->src_offset[!src_field][2], TEXORG ); + mga_out32( mmio, mdev->dst_offset[!dst_field][2], DSTORG ); + + matroxDoBlitTMU( mdrv, mdev, + srect->x, (srect->y+1)/2, + drect->x, (drect->y+1)/2, + srect->w, srect->h/2, + drect->w, drect->h/2, + mdev->w2-1, mdev->h2-1, true ); + + /* Restore registers */ + mga_waitfifo( mdrv, mdev, 6 ); + mga_out32( mmio, mdev->texctl, TEXCTL ); + mga_out32( mmio, ( (((u32)(mdev->w - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 4) & 0x3f) ) ), TEXWIDTH ); + mga_out32( mmio, ( (((u32)(mdev->h - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 4) & 0x3f) ) ), TEXHEIGHT ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + mga_out32( mmio, mdev->dst_offset[0][0], DSTORG ); + + matrox_set_clip( mdrv, mdev, &mdev->clip ); + + return true; +} + +/******************************************************************************/ + +static u32 pci_config_in32( unsigned int bus, + unsigned int slot, + unsigned int func, + u8 reg ) +{ + char filename[512]; + int fd; + u32 val; + + snprintf( filename, 512, + "/proc/bus/pci/%02x/%02x.%x", + bus, slot, func ); + + fd = open( filename, O_RDONLY ); + if (fd < 0) + return 0; + + if (lseek( fd, reg, SEEK_SET ) != reg) { + close( fd ); + return 0; + } + + if (read( fd, &val, 4 ) != 4) { + close( fd ); + return 0; + } + + close( fd ); + +#ifdef WORDS_BIGENDIAN + return ((val & 0xff000000) >> 24) | + ((val & 0x00ff0000) >> 8) | + ((val & 0x0000ff00) << 8) | + ((val & 0x000000ff) << 24); +#else + return val; +#endif +} + +static DFBResult matrox_find_pci_device( MatroxDeviceData *mdev, + unsigned int *bus, + unsigned int *slot, + unsigned int *func ) +{ + unsigned int vendor, device, devfn; + unsigned long addr0, addr1; + char line[512]; + FILE *file; + + file = fopen( "/proc/bus/pci/devices", "r" ); + if (!file) { + D_PERROR( "DirectFB/Matrox: " + "Error opening `/proc/bus/pci/devices'!\n" ); + return errno2result( errno ); + } + + while (fgets( line, 512, file )) { + if (sscanf( line, "%02x%02x\t%04x%04x\t%*x\t%lx\t%lx", + bus, &devfn, &vendor, &device, &addr0, &addr1 ) != 6) + continue; + + if (vendor != PCI_VENDOR_ID_MATROX) + continue; + + *slot = (devfn >> 3) & 0x1F; + *func = devfn & 0x07; + + addr0 &= ~0xFUL; + addr1 &= ~0xFUL; + + switch (device) { + case PCI_DEVICE_ID_MATROX_G550_AGP: + case PCI_DEVICE_ID_MATROX_G400_AGP: + if (addr0 == (mdev->fb.physical & ~0x1FFFFFF)) { + fclose( file ); + return DFB_OK; + } + break; + + case PCI_DEVICE_ID_MATROX_G200_PCI: + case PCI_DEVICE_ID_MATROX_G200_AGP: + case PCI_DEVICE_ID_MATROX_G100_PCI: + case PCI_DEVICE_ID_MATROX_G100_AGP: + case PCI_DEVICE_ID_MATROX_2164W_PCI: + case PCI_DEVICE_ID_MATROX_2164W_AGP: + if (addr0 == mdev->fb.physical) { + fclose( file ); + return DFB_OK; + } + break; + + case PCI_DEVICE_ID_MATROX_1064SG_PCI: + case PCI_DEVICE_ID_MATROX_1064SG_AGP: + if ((pci_config_in32( *bus, *slot, *func, 0x08 ) & 0xFF) > 0x02) { + /* Mystique 220 (1164SG) */ + if (addr0 == mdev->fb.physical) { + fclose( file ); + return DFB_OK; + } + } else { + /* Mystique (1064SG) */ + if (addr1 == mdev->fb.physical) { + fclose( file ); + return DFB_OK; + } + } + break; + + case PCI_DEVICE_ID_MATROX_2064W_PCI: + if (addr1 == mdev->fb.physical) { + fclose( file ); + return DFB_OK; + } + break; + } + } + + D_ERROR( "DirectFB/Matrox: Can't find device in `/proc/bus/pci'!\n" ); + + fclose( file ); + return DFB_INIT; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_MATROX_MGA2064W: /* Matrox 2064W (Millennium) */ + case FB_ACCEL_MATROX_MGA1064SG: /* Matrox 1064SG/1164SG (Mystique) */ + case FB_ACCEL_MATROX_MGA2164W: /* Matrox 2164W (Millennium II) */ + case FB_ACCEL_MATROX_MGA2164W_AGP: /* Matrox 2164W (Millennium II) */ + case FB_ACCEL_MATROX_MGAG100: /* Matrox G100 */ + case FB_ACCEL_MATROX_MGAG200: /* Matrox G200 */ + case FB_ACCEL_MATROX_MGAG400: /* Matrox G400/G450/G550 */ + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Matrox G-Series/Millennium/Mystique" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + info->version.major = 0; + info->version.minor = 7; + + info->driver_data_size = sizeof (MatroxDriverData); + info->device_data_size = sizeof (MatroxDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + MatroxDriverData *mdrv = driver_data; + + mdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!mdrv->mmio_base) + return DFB_IO; + + mdrv->device_data = device_data; + mdrv->maven_fd = -1; + mdrv->accelerator = dfb_gfxcard_get_accelerator( device ); + + switch (mdrv->accelerator) { + case FB_ACCEL_MATROX_MGAG400: + funcs->CheckState = matroxG400CheckState; + break; + + case FB_ACCEL_MATROX_MGAG200: + if (!dfb_config->font_format) + dfb_config->font_format = DSPF_ARGB; + funcs->CheckState = matroxG200CheckState; + break; + + case FB_ACCEL_MATROX_MGAG100: + funcs->CheckState = matroxG100CheckState; + break; + + case FB_ACCEL_MATROX_MGA1064SG: + case FB_ACCEL_MATROX_MGA2164W: + case FB_ACCEL_MATROX_MGA2164W_AGP: + funcs->CheckState = matroxOldCheckState; + break; + + case FB_ACCEL_MATROX_MGA2064W: + funcs->CheckState = matrox2064WCheckState; + break; + } + + funcs->SetState = matroxSetState; + funcs->EngineReset = matroxEngineReset; + funcs->EngineSync = matroxEngineSync; + funcs->FlushTextureCache = matroxFlushTextureCache; + funcs->FlushReadCache = matroxFlushReadCache; + + funcs->DrawRectangle = matroxDrawRectangle; + funcs->DrawLine = matroxDrawLine; + funcs->FillTriangle = matroxFillTriangle; + funcs->TextureTriangles = matroxTextureTriangles; + + /* will be set dynamically: funcs->FillRectangle, funcs->Blit, funcs->StretchBlit */ + + /* Generic CRTC1 support */ + mdrv->primary = dfb_screens_at( DSCID_PRIMARY ); + + /* G200/G400/G450/G550 Backend Scaler Support */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG200 || + mdrv->accelerator == FB_ACCEL_MATROX_MGAG400) + dfb_layers_register( mdrv->primary, driver_data, &matroxBesFuncs ); + + /* G400/G450/G550 CRTC2 support */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG400 && + dfb_config->matrox_crtc2) + { + mdrv->secondary = dfb_screens_register( device, driver_data, + &matroxCrtc2ScreenFuncs ); + + dfb_layers_register( mdrv->secondary, driver_data, &matroxCrtc2Funcs ); + dfb_layers_register( mdrv->secondary, driver_data, &matroxSpicFuncs ); + } + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxDeviceData *mdev = (MatroxDeviceData*) device_data; + volatile u8 *mmio = mdrv->mmio_base; + unsigned int bus, slot, func; + bool g450, g550, sgram = false; + DFBResult ret; + + mdev->fb.physical = dfb_gfxcard_memory_physical( device, 0 ); + + switch (mdrv->accelerator) { + case FB_ACCEL_MATROX_MGAG400: + if ((ret = matrox_find_pci_device( mdev, &bus, &slot, &func ))) + return ret; + + g550 = ((pci_config_in32( bus, slot, func, 0x00 ) >> 16) == PCI_DEVICE_ID_MATROX_G550_AGP); + g450 = ((pci_config_in32( bus, slot, func, 0x08 ) & 0xFF) >= 0x80); + sgram = ((pci_config_in32( bus, slot, func, 0x40 ) & 0x4000) == 0x4000); + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "%s", + g550 ? "G550" : g450 ? "G450" : "G400" ); + mdev->g450_matrox = g450 || g550; + mdev->g550_matrox = g550; + + mdev->fb.offset = mdev->fb.physical & 0x1FFFFFF; + break; + case FB_ACCEL_MATROX_MGAG200: + if ((ret = matrox_find_pci_device( mdev, &bus, &slot, &func ))) + return ret; + + sgram = ((pci_config_in32( bus, slot, func, 0x40 ) & 0x4000) == 0x4000); + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "G200" ); + break; + case FB_ACCEL_MATROX_MGAG100: + mdev->old_matrox = true; + sgram = false; /* FIXME: can we detect this? */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "G100" ); + break; + case FB_ACCEL_MATROX_MGA2064W: + mdev->old_matrox = true; + sgram = true; + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Millennium (2064W)" ); + break; + case FB_ACCEL_MATROX_MGA1064SG: + if ((ret = matrox_find_pci_device( mdev, &bus, &slot, &func ))) + return ret; + + mdev->old_matrox = true; + sgram = ((pci_config_in32( bus, slot, func, 0x40 ) & 0x4000) == 0x4000); + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "%s", + ((pci_config_in32( bus, slot, func, 0x08 ) & 0xFF) > 0x02) ? + "Mystique 220 (1164SG)" : "Mystique (1064SG)" ); + break; + case FB_ACCEL_MATROX_MGA2164W: + case FB_ACCEL_MATROX_MGA2164W_AGP: + mdev->old_matrox = true; + sgram = true; + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Millennium II (2164W)" ); + break; + } + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Matrox" ); + + + /* set hardware capabilities */ + device_info->caps.flags = CCF_CLIPPING; + + switch (mdrv->accelerator) { + case FB_ACCEL_MATROX_MGAG400: + device_info->caps.accel = MATROX_G200G400_DRAWING_FUNCTIONS | + MATROX_G200G400_BLITTING_FUNCTIONS; + device_info->caps.drawing = MATROX_G200G400_DRAWING_FLAGS; + device_info->caps.blitting = MATROX_G200G400_BLITTING_FLAGS; + break; + + case FB_ACCEL_MATROX_MGAG200: + device_info->caps.accel = MATROX_G200G400_DRAWING_FUNCTIONS | + MATROX_G200G400_BLITTING_FUNCTIONS; + device_info->caps.drawing = MATROX_G200G400_DRAWING_FLAGS; + device_info->caps.blitting = MATROX_G200G400_BLITTING_FLAGS; + break; + + case FB_ACCEL_MATROX_MGAG100: + device_info->caps.accel = MATROX_G100_DRAWING_FUNCTIONS | + MATROX_G100_BLITTING_FUNCTIONS; + device_info->caps.drawing = MATROX_G100_DRAWING_FLAGS; + device_info->caps.blitting = MATROX_G100_BLITTING_FLAGS; + break; + + case FB_ACCEL_MATROX_MGA1064SG: + case FB_ACCEL_MATROX_MGA2164W: + case FB_ACCEL_MATROX_MGA2164W_AGP: + device_info->caps.accel = MATROX_OLD_DRAWING_FUNCTIONS | + MATROX_OLD_BLITTING_FUNCTIONS; + device_info->caps.drawing = MATROX_OLD_DRAWING_FLAGS; + device_info->caps.blitting = MATROX_OLD_BLITTING_FLAGS; + break; + + case FB_ACCEL_MATROX_MGA2064W: + device_info->caps.accel = MATROX_2064W_DRAWING_FUNCTIONS | + MATROX_2064W_BLITTING_FUNCTIONS; + device_info->caps.drawing = MATROX_2064W_DRAWING_FLAGS; + device_info->caps.blitting = MATROX_2064W_BLITTING_FLAGS; + break; + } + + /* set hardware limitations */ + device_info->limits.surface_byteoffset_alignment = 128; + device_info->limits.surface_pixelpitch_alignment = 32; + device_info->limits.surface_bytepitch_alignment = 64; + + /* YUY2 / UYVY is handled as 32bit so pixelpitch alignment must be doubled. */ + device_info->limits.surface_pixelpitch_alignment = 64; + + mdev->atype_blk_rstr = (sgram || dfb_config->matrox_sgram) ? ATYPE_BLK : ATYPE_RSTR; + /* + * Pitch must be a multiple of 64 bytes for block write to work. + * SRCORG/DSTORG must be a multiple of 64. + * I420/YV12 subsampling makes the actual requirement 128 bytes. + */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG400) + device_info->limits.surface_bytepitch_alignment = 128; + + /* soft reset to fix eventually corrupted TMU read offset on G200 */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG200) { + u32 ien = mga_in32( mmio, IEN ); + mga_out32( mmio, 1, RST ); + usleep(10); + mga_out32( mmio, 0, RST ); + mga_out32( mmio, ien, IEN ); + } + + if (mdrv->accelerator == FB_ACCEL_MATROX_MGA2064W) + mdev->idle_status = 0; + else + mdev->idle_status = ENDPRDMASTS; + + switch (mdrv->accelerator) { + case FB_ACCEL_MATROX_MGAG100: + case FB_ACCEL_MATROX_MGAG200: + if ((ret = dfb_palette_create( NULL, 256, &mdev->rgb332_palette )) != DFB_OK) + return ret; + dfb_palette_generate_rgb332_map( mdev->rgb332_palette ); + + mdev->tlut_offset = dfb_gfxcard_reserve_memory( device, 2 * 256 ); + } + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxDeviceData *mdev = (MatroxDeviceData*) device_data; + + if (mdev->rgb332_palette) + dfb_palette_unref( mdev->rgb332_palette ); + + /* reset DSTORG as matroxfb does not */ + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mdrv->mmio_base, 0, DSTORG ); + + /* make sure BES registers get updated (besvcnt) */ + mga_out32( mdrv->mmio_base, 0, BESGLOBCTL ); + /* make sure overlay is off */ + mga_out32( mdrv->mmio_base, 0, BESCTL ); + + + D_DEBUG( "DirectFB/Matrox: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/Matrox: %9d matrox_waitfifo calls\n", + mdev->waitfifo_calls ); + D_DEBUG( "DirectFB/Matrox: %9d register writes (matrox_waitfifo sum)\n", + mdev->waitfifo_sum ); + D_DEBUG( "DirectFB/Matrox: %9d FIFO wait cycles (depends on CPU)\n", + mdev->fifo_waitcycles ); + D_DEBUG( "DirectFB/Matrox: %9d IDLE wait cycles (depends on CPU)\n", + mdev->idle_waitcycles ); + D_DEBUG( "DirectFB/Matrox: %9d FIFO space cache hits (depends on CPU)\n", + mdev->fifo_cache_hits ); + D_DEBUG( "DirectFB/Matrox: Conclusion:\n" ); + D_DEBUG( "DirectFB/Matrox: Average register writes/matrox_waitfifo call: %.2f\n", + mdev->waitfifo_sum/(float)(mdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/Matrox: Average wait cycles/matrox_waitfifo call: %.2f\n", + mdev->fifo_waitcycles/(float)(mdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/Matrox: Average fifo space cache hits: %02d%%\n", + (int)(100 * mdev->fifo_cache_hits/(float)(mdev->waitfifo_calls)) ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, mdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox.h b/Source/DirectFB/gfxdrivers/matrox/matrox.h new file mode 100755 index 0000000..70062bf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox.h @@ -0,0 +1,157 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___MATROX_H__ +#define ___MATROX_H__ + +#include + +#include +#include + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_2064W_PCI 0x0519 +#define PCI_DEVICE_ID_MATROX_1064SG_PCI 0x051A +#define PCI_DEVICE_ID_MATROX_2164W_PCI 0x051B +#define PCI_DEVICE_ID_MATROX_1064SG_AGP 0x051E +#define PCI_DEVICE_ID_MATROX_2164W_AGP 0x051F +#define PCI_DEVICE_ID_MATROX_G100_PCI 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400_AGP 0x0525 +#define PCI_DEVICE_ID_MATROX_G550_AGP 0x2527 + +typedef enum { + m_Source = 0x0001, + m_source = 0x0002, + + m_drawColor = 0x0010, + m_blitColor = 0x0020, + m_color = 0x0040, + + m_SrcKey = 0x0100, + m_srckey = 0x0200, + + m_drawBlend = 0x1000, + m_blitBlend = 0x2000, + + m_destination = 0x4000, + m_clip = 0x8000, +} MatroxStateBits; + +#define MGA_VALIDATE(b) (mdev->valid |= (b)) +#define MGA_INVALIDATE(b) (mdev->valid &= ~(b)) +#define MGA_IS_VALID(b) (mdev->valid & (b)) + +typedef struct { + /* Old cards are older than G200/G400, e.g. Mystique or Millennium */ + bool old_matrox; + /* G450/G550 */ + bool g450_matrox; + /* G550 */ + bool g550_matrox; + + /* FIFO Monitoring */ + unsigned int fifo_space; + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; + + /* ATYPE_BLK or ATYPE_RSTR, depending on SGRAM setting */ + u32 atype_blk_rstr; + + /* State handling */ + MatroxStateBits valid; + + /* Stored values */ + int dst_pitch; + int dst_offset[2][3]; + int src_pitch; + int src_offset[2][3]; + int w, h, w2, h2; + u32 color[3]; + + bool draw_blend; + bool blit_src_colorkey; + + bool blit_deinterlace; + bool blit_fields; + int field; + + bool depth_buffer; + + u32 texctl; + + u32 idle_status; + + DFBRegion clip; + + struct { + unsigned long offset; + unsigned long physical; + } fb; + unsigned int tlut_offset; + CorePalette *rgb332_palette; + + bool crtc2_separated; +} MatroxDeviceData; + +typedef struct { + int accelerator; + int maven_fd; + volatile u8 *mmio_base; + + CoreScreen *primary; + CoreScreen *secondary; + + MatroxDeviceData *device_data; +} MatroxDriverData; + + +extern DisplayLayerFuncs matroxBesFuncs; +extern DisplayLayerFuncs matroxCrtc2Funcs; +extern DisplayLayerFuncs matroxSpicFuncs; + +extern ScreenFuncs matroxCrtc2ScreenFuncs; + +static inline int mga_log2( int val ) +{ + register int ret = 0; + + while (val >> ++ret); + + if ((1 << --ret) < val) + ret++; + + return ret; +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_3d.c b/Source/DirectFB/gfxdrivers/matrox/matrox_3d.c new file mode 100755 index 0000000..f3753b0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_3d.c @@ -0,0 +1,627 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include + +#include +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" +#include "matrox_3d.h" + + +#ifdef ARCH_X86 +#define RINT(x) my_rint(x) +#define CEIL(x) my_ceil(x) +#define FLOOR(x) my_floor(x) +#else +#define RINT(x) ((s32)(x)) +#define CEIL(x) ((s32)ceil(x)) +#define FLOOR(x) ((s32)floor(x)) +#endif + +#ifdef ARCH_X86 +static inline long +my_rint(const float x) +{ + register float arg = x; + long result; + __asm__ ("fistl %0" : "=m" (result) : "t" (arg)); + return result; +} + +static inline long +my_ceil(const float x) +{ + register float arg = x; + volatile long value; + volatile short cw, cwtmp; + + __asm__ volatile ("fnstcw %0" : "=m" (cw) : ); + cwtmp = (cw & 0xf3ff) | 0x0800; /* rounding up */ + __asm__ volatile ("fldcw %1\n" + "fistl %0\n" + "fldcw %2" + : "=m" (value) + : "m" (cwtmp), "m" (cw), "t" (arg)); + return value; +} + +static inline long +my_floor(const float x) +{ + register float arg = x; + volatile long value; + volatile short cw, cwtmp; + + __asm__ volatile ("fnstcw %0" : "=m" (cw) : ); + cwtmp = (cw & 0xf3ff) | 0x0400; + __asm__ volatile ("fldcw %1\n" + "fistl %0\n" + "fldcw %2" + : "=m" (value) + : "m" (cwtmp), "m" (cw), "t" (arg)); + return value; +} +#endif + +#define F2COL(x) (RINT(x) & 0x00ffffff) + +#define mgaF1800(x) (((s32) (x)) & 0x0003ffff) +#define mgaF2400(x) (((s32) (x)) & 0x00ffffff) +#define mgaF2200(x) (((s32) (x)) & 0x003fffff) + +#define OUTREG(r,d) do { mga_out32( mmio, d, r ); } while (0) + +#define MGA_S(start,xinc,yinc) \ + do { \ + mga_out32( mmio, start, TMR6 ); \ + mga_out32( mmio, xinc, TMR0 ); \ + mga_out32( mmio, yinc, TMR1 ); \ + } while (0) + +#define MGA_T(start,xinc,yinc) \ + do { \ + mga_out32( mmio, start, TMR7 ); \ + mga_out32( mmio, xinc, TMR2 ); \ + mga_out32( mmio, yinc, TMR3 ); \ + } while (0) + +#define MGA_Q(start,xinc,yinc) \ + do { \ + mga_out32( mmio, start, TMR8 ); \ + mga_out32( mmio, xinc, TMR4 ); \ + mga_out32( mmio, yinc, TMR5 ); \ + } while (0) + + +#define MGA_LSLOPE(dx,dy,sgn,err) \ + do { \ + mga_out32( mmio, mgaF1800(dy), AR0 ); \ + if ((dx) >= 0) { \ + mga_out32( mmio, mgaF2400(-(dx)+(err)), AR1 ); \ + mga_out32( mmio, mgaF1800(-(dx)), AR2 ); \ + sgn &= ~SDXL; \ + } \ + else { \ + mga_out32( mmio, mgaF2400((dx)+(dy)-(err)-1), AR1 ); \ + mga_out32( mmio, mgaF1800(dx), AR2 ); \ + sgn |= SDXL; \ + } \ + } while(0) + + +#define MGA_G400_LSLOPE(dx,dy,sgn,err) \ + do { \ + mga_out32( mmio, mgaF2200(dy), AR0 ); \ + if ((dx) >= 0) { \ + mga_out32( mmio, mgaF2400(-(dx)+(err)), AR1 ); \ + mga_out32( mmio, mgaF2200(-(dx)), AR2); \ + sgn &= ~SDXL; \ + } \ + else { \ + mga_out32( mmio, mgaF2400((dx)+(dy)-(err)-1), AR1 ); \ + mga_out32( mmio, mgaF2200(dx), AR2 ); \ + sgn |= SDXL; \ + } \ + } while(0) + + +#define MGA_RSLOPE(dx,dy,sgn,err) \ + do { \ + mga_out32( mmio, mgaF1800(dy), AR6); \ + if ((dx) >= 0) { \ + mga_out32( mmio, mgaF1800(-(dx)+(err)), AR4 ); \ + mga_out32( mmio, mgaF1800(-(dx)), AR5 ); \ + sgn &= ~SDXR; \ + } \ + else { \ + mga_out32( mmio, mgaF1800((dx)+(dy)-(err)-1), AR4 ); \ + mga_out32( mmio, mgaF1800(dx), AR5 ); \ + sgn |= SDXR; \ + } \ + } while(0) + + +#define MGA_G400_RSLOPE(dx,dy,sgn,err) \ + do { \ + mga_out32( mmio, mgaF2200(dy), AR6 ); \ + if ((dx) >= 0) { \ + mga_out32( mmio, mgaF2200(-(dx)+(err)), AR4 ); \ + mga_out32( mmio, mgaF2200(-(dx)), AR5 ); \ + sgn &= ~SDXR; \ + } \ + else { \ + mga_out32( mmio, mgaF2200((dx)+(dy)-(err)-1), AR4 ); \ + mga_out32( mmio, mgaF2200(dx), AR5); \ + sgn |= SDXR; \ + } \ + } while(0) + + +typedef struct { + DFBVertex *v0, *v1; /* Y(v0) < Y(v1) */ + float dx; /* X(v1) - X(v0) */ + float dy; /* Y(v1) - Y(v0) */ + float dxOOA; /* dx * oneOverArea */ + float dyOOA; /* dy * oneOverArea */ + + float adjx,adjy; /* subpixel offset after rounding to integer */ + int err; /* error term ready for hardware */ + int idx,idy; /* delta-x & delta-y ready for hardware */ + int sx,sy; /* first sample point x,y coord */ + int lines; /* number of lines to be sampled on this edge */ +} EdgeT; + + +static void +texture_triangle( MatroxDriverData *mdrv, MatroxDeviceData *mdev, + DFBVertex *v0, DFBVertex *v1, DFBVertex *v2 ) +{ + EdgeT eMaj, eTop, eBot; + float oneOverArea; + DFBVertex *vMin, *vMid, *vMax; /* Y(vMin)<=Y(vMid)<=Y(vMax) */ + int Shape; /* 1 = Top half, 2 = bottom half, 3 = top+bottom */ +// float bf = mga_bf_sign; + + volatile u8 *mmio = mdrv->mmio_base; + +/* find the order of the 3 vertices along the Y axis */ + { + float y0 = v0->y; + float y1 = v1->y; + float y2 = v2->y; + + if (y0<=y1) { + if (y1<=y2) { + vMin = v0; vMid = v1; vMax = v2; /* y0<=y1<=y2 */ + } + else if (y2<=y0) { + vMin = v2; vMid = v0; vMax = v1; /* y2<=y0<=y1 */ + } + else { + vMin = v0; vMid = v2; vMax = v1; /*bf = -bf;*/ /* y0<=y2<=y1 */ + } + } + else { + if (y0<=y2) { + vMin = v1; vMid = v0; vMax = v2; /*bf = -bf;*/ /* y1<=y0<=y2 */ + } + else if (y2<=y1) { + vMin = v2; vMid = v1; vMax = v0; /*bf = -bf;*/ /* y2<=y1<=y0 */ + } + else { + vMin = v1; vMid = v2; vMax = v0; /* y1<=y2<=y0 */ + } + } + } + +/* vertex/edge relationship */ + eMaj.v0 = vMin; eMaj.v1 = vMax; + eTop.v0 = vMin; eTop.v1 = vMid; + eBot.v0 = vMid; eBot.v1 = vMax; + +/* compute deltas for each edge: vertex[v1] - vertex[v0] */ + eMaj.dx = vMax->x - vMin->x; + eMaj.dy = vMax->y - vMin->y; + eTop.dx = vMid->x - vMin->x; + eTop.dy = vMid->y - vMin->y; + eBot.dx = vMax->x - vMid->x; + eBot.dy = vMax->y - vMid->y; + + +/* compute oneOverArea */ + { + float area = eMaj.dx * eBot.dy - eBot.dx * eMaj.dy; + + /* Do backface culling + */ + //if ( area * bf < 0 || area == 0 ) + //return; + + oneOverArea = 1.0F / area; + } + +/* Edge setup. For a triangle strip these could be reused... */ + { + +#define DELTASCALE 16 /* Scaling factor for idx and idy. Note that idx and + idy are 18 bits signed, so don't choose too big + value. */ + + int ivMax_y; + float temp; + + ivMax_y = CEIL(vMax->y); + eTop.sy = eMaj.sy = CEIL(vMin->y); + eBot.sy = CEIL(vMid->y); + + eMaj.lines = ivMax_y - eMaj.sy; + if (eMaj.lines > 0) { + float dxdy = eMaj.dx / eMaj.dy; + eMaj.adjy = (float) eMaj.sy - vMin->y; + temp = vMin->x + eMaj.adjy*dxdy; + eMaj.sx = CEIL(temp); + eMaj.adjx = (float) eMaj.sx - vMin->x; + if (eMaj.lines == 1) { + eMaj.idy = 1; + eMaj.idx = 0; + eMaj.err = 0; + } + else { + eMaj.idy = RINT(eMaj.dy * DELTASCALE); + eMaj.idx = FLOOR(eMaj.idy * dxdy); + eMaj.err = RINT(((float) eMaj.sx - temp) * (float)eMaj.idy); + } + } + else { + return; /* CULLED */ + } + + Shape = 3; + + eBot.lines = ivMax_y - eBot.sy; + if (eBot.lines > 0) { + float dxdy = eBot.dx / eBot.dy; + eBot.adjy = (float) eBot.sy - vMid->y; + temp = vMid->x + eBot.adjy*dxdy; + eBot.sx = CEIL(temp); + eBot.adjx = (float) eBot.sx - vMid->x; + if (eBot.lines == 1) { + eBot.idy = 1; + eBot.idx = 0; + eBot.err = 0; + } + else { + eBot.idy = RINT(eBot.dy * DELTASCALE); + eBot.idx = FLOOR(eBot.idy * dxdy); + eBot.err = RINT(((float) eBot.sx - temp) * (float)eBot.idy); + } + } + else { + Shape = 1; + } + + eTop.lines = eBot.sy - eTop.sy; + if (eTop.lines > 0) { + float dxdy = eTop.dx / eTop.dy; + eTop.adjy = eMaj.adjy; + temp = vMin->x + eTop.adjy*dxdy; + eTop.sx = CEIL(temp); + eTop.adjx = (float) eTop.sx - vMin->x; + if (eTop.lines == 1) { + eTop.idy = 1; + if (eBot.lines > 0) { + eTop.idx = eBot.sx - eTop.sx; /* needed for bottom half */ + } + else { + eTop.idx = 0; + } + eTop.err = 0; + } + else { + eTop.idy = RINT(eTop.dy * DELTASCALE); + eTop.idx = FLOOR(eTop.idy * dxdy); + eTop.err = RINT(((float) eTop.sx - temp) * (float)eTop.idy); + } + } + else { + Shape = 2; + } + } + + { + int ltor; /* true if scanning left-to-right */ + EdgeT *eLeft, *eRight; + int lines; + DFBVertex *vTL; /* Top left vertex */ + float adjx, adjy; + + /* + * Execute user-supplied setup code + */ +#ifdef SETUP_CODE + SETUP_CODE +#endif + + ltor = (oneOverArea > 0.0F); + + if (Shape == 2) { + /* bottom half triangle */ + if (ltor) { + eLeft = &eMaj; + eRight = &eBot; + } + else { + eLeft = &eBot; + eRight = &eMaj; + } + lines = eBot.lines; + } + else { + /* top half triangle */ + if (ltor) { + eLeft = &eMaj; + eRight = &eTop; + } + else { + eLeft = &eTop; + eRight = &eMaj; + } + lines = eTop.lines; + } + + vTL = eLeft->v0; + adjx = eLeft->adjx; adjy = eLeft->adjy; + + + /* setup derivatives */ +/* compute d?/dx and d?/dy derivatives */ + eBot.dxOOA = eBot.dx * oneOverArea; + eBot.dyOOA = eBot.dy * oneOverArea; + eMaj.dxOOA = eMaj.dx * oneOverArea; + eMaj.dyOOA = eMaj.dy * oneOverArea; + +#define DERIV( DZ, COMP) \ + { \ + float eMaj_DZ, eBot_DZ; \ + eMaj_DZ = vMax->COMP - vMin->COMP; \ + eBot_DZ = vMax->COMP - vMid->COMP; \ + DZ ## dx = eMaj_DZ * eBot.dyOOA - eMaj.dyOOA * eBot_DZ; \ + DZ ## dy = eMaj.dxOOA * eBot_DZ - eMaj_DZ * eBot.dxOOA; \ + } + + if (mdev->depth_buffer) { + float Zstart; + float dzdx, dzdy; + + DERIV(dz, z); + + if (dzdx>65535.0f*(1<<15) || dzdx<-65535.0f*(1<<15)) { + /* probably a sliver triangle */ + dzdx = 0.0; + dzdy = 0.0; + } + + Zstart = vTL->z + dzdx*adjx + dzdy*adjy; + + /* FIXME: 16 bit assumed */ + if (Zstart > 65535.0f*(1 << 15)) { + Zstart = 65535.0f*(1 << 15); + dzdx = 0.0F; + dzdy = 0.0F; + } + + mga_waitfifo( mdrv, mdev, 3 ); + + mga_out32( mmio, RINT(Zstart), DR0 ); + mga_out32( mmio, RINT(dzdx), DR2 ); + mga_out32( mmio, RINT(dzdy), DR3 ); + } + + { + float dsdx, dsdy; + float dtdx, dtdy; + float dvdx, dvdy; + + mga_waitfifo( mdrv, mdev, 9 ); + + DERIV(ds,s); + + MGA_S(RINT( (vTL->s+dsdx*adjx+dsdy*adjy) ), + RINT( dsdx ), RINT( dsdy )); + + DERIV(dt,t); + + MGA_T(RINT( (vTL->t+dtdx*adjx+dtdy*adjy) ), + RINT( dtdx ), RINT( dtdy )); + + DERIV(dv,w); + { + int sq = RINT( (vTL->w+dvdx*adjx+dvdy*adjy) ); + MGA_Q((sq == 0) ? 1 : sq,RINT(dvdx),RINT(dvdy)); + } + } + + { + u32 sgn = 0; + + mga_waitfifo( mdrv, mdev, 9 ); + + /* Draw part #1 */ + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG400) { + MGA_G400_LSLOPE(eLeft->idx,eLeft->idy,sgn,eLeft->err); + MGA_G400_RSLOPE(eRight->idx,eRight->idy,sgn,eRight->err); + } + else { + MGA_LSLOPE(eLeft->idx,eLeft->idy,sgn,eLeft->err); + MGA_RSLOPE(eRight->idx,eRight->idy,sgn,eRight->err); + } + + mga_out32( mmio, sgn, SGN ); + mga_out32( mmio, ((u32)(eLeft->sx) & 0xFFFF) | ((u32)(eRight->sx) << 16), FXBNDRY ); + mga_out32( mmio, lines | ((u32)(eLeft->sy) << 16), YDSTLEN | EXECUTE ); + + if (Shape != 3) { /* has only one half? */ + return; + } + + mga_waitfifo( mdrv, mdev, 6 ); + + /* Draw part #2 */ + if (ltor) { + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG400) + MGA_G400_RSLOPE(eBot.idx,eBot.idy,sgn,eBot.err); + else + MGA_RSLOPE(eBot.idx,eBot.idy,sgn,eBot.err); + + mga_out32( mmio, eBot.sx, FXRIGHT ); + } + else { + sgn |= SGN_BRKLEFT; + mga_out32( mmio, eBot.sx, FXLEFT ); + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG400) + MGA_G400_LSLOPE(eBot.idx,eBot.idy,sgn,eBot.err); + else + MGA_LSLOPE(eBot.idx,eBot.idy,sgn,eBot.err); + + } + + mga_out32( mmio, sgn, SGN ); + mga_out32( mmio, eBot.lines, LEN | EXECUTE ); + } + } +} + +#define INVWMAX 128.0F + +bool +matroxTextureTriangles( void *drv, void *dev, + DFBVertex *vertices, int num, + DFBTriangleFormation formation ) +{ + int i; + MatroxDriverData *mdrv = (MatroxDriverData*) drv; + MatroxDeviceData *mdev = (MatroxDeviceData*) dev; + volatile u8 *mmio = mdrv->mmio_base; + u32 dwgctl; + + float wScale; + +#if 0 + float InvWScale = 1.0f; + float nearVal = 1.0f; + + if (nearVal > 0) { + /* limit InvWScale/wMin in (0,INVWMAX] to avoid over- and underflow. + InvWScale is used by texture setup in mga_tritemp.h */ + int exp2; + + if (frexp(INVWMAX * nearVal,&exp2) != 0) { + if (exp2 >= 2) { + InvWScale = 1 << (exp2-1); + } + else if (exp2 <= 0) { + InvWScale = 1.0 / (1 << (-exp2+1)); + } + } + } +#else +#define InvWScale 128.0f +#endif + + wScale = InvWScale * (float) (1 << 20); + + for (i=0; ix -= 0.5f; + v->y -= 0.5f; + v->z *= (float) (1 << 15) * 65535.0f; + v->w *= wScale; + + v->s *= v->w * (float) mdev->w / (float) (1 << mdev->w2); + v->t *= v->w * (float) mdev->h / (float) (1 << mdev->h2); + } + + if (mdev->depth_buffer) + dwgctl = ATYPE_ZI | ZMODE_ZLTE; + else + dwgctl = ATYPE_I | ZMODE_NOZCMP; + + mga_waitfifo( mdrv, mdev, 2 ); + + mga_out32( mmio, dwgctl | BOP_COPY | SHFTZERO | OP_TEXTURE_TRAP, DWGCTL ); + mga_out32( mmio, (0x10<<21) | MAG_BILIN | MIN_ANISO | FILTER_ALPHA, TEXFILTER ); + + switch (formation) { + case DTTF_LIST: + for (i=0; i, + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___MATROX_3D_H__ +#define ___MATROX_3D_H__ + +bool matroxTextureTriangles( void *drv, void *dev, + DFBVertex *vertices, int num, + DFBTriangleFormation formation ); + +#endif diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_bes.c b/Source/DirectFB/gfxdrivers/matrox/matrox_bes.c new file mode 100755 index 0000000..df1d4ab --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_bes.c @@ -0,0 +1,783 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" + +typedef struct { + CoreLayerRegionConfig config; + + /* Stored registers */ + struct { + /* BES */ + u32 besGLOBCTL; + u32 besA1ORG; + u32 besA2ORG; + u32 besA1CORG; + u32 besA2CORG; + u32 besA1C3ORG; + u32 besA2C3ORG; + u32 besCTL; + + u32 besCTL_field; + + u32 besHCOORD; + u32 besVCOORD; + + u32 besHSRCST; + u32 besHSRCEND; + u32 besHSRCLST; + + u32 besPITCH; + + u32 besV1WGHT; + u32 besV2WGHT; + + u32 besV1SRCLST; + u32 besV2SRCLST; + + u32 besVISCAL; + u32 besHISCAL; + + u8 xKEYOPMODE; + } regs; +} MatroxBesLayerData; + +static bool bes_set_buffer( MatroxDriverData *mdrv, MatroxBesLayerData *mbes, + bool onsync ); +static void bes_set_regs( MatroxDriverData *mdrv, MatroxBesLayerData *mbes ); +static void bes_calc_regs( MatroxDriverData *mdrv, MatroxBesLayerData *mbes, + CoreLayerRegionConfig *config, CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +#define BES_SUPPORTED_OPTIONS (DLOP_DEINTERLACING | DLOP_DST_COLORKEY) + + +/**********************/ + +static int +besLayerDataSize( void ) +{ + return sizeof(MatroxBesLayerData); +} + +static DFBResult +besInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + volatile u8 *mmio = mdrv->mmio_base; + + /* set capabilities and type */ + description->caps = DLCAPS_SCREEN_LOCATION | DLCAPS_SURFACE | + DLCAPS_DEINTERLACING | DLCAPS_DST_COLORKEY; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Matrox Backend Scaler" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + adjustment->flags = DCAF_NONE; + + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) { + description->caps |= DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags |= DCAF_BRIGHTNESS | DCAF_CONTRAST; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + + mga_out32( mmio, 0x80, BESLUMACTL ); + } + + /* make sure BES registers get updated (besvcnt) */ + mga_out32( mmio, 0, BESGLOBCTL ); + /* disable backend scaler */ + mga_out32( mmio, 0, BESCTL ); + + /* set defaults */ + mga_out_dac( mmio, XKEYOPMODE, 0x00 ); /* keying off */ + + mga_out_dac( mmio, XCOLMSK0RED, 0xFF ); /* full mask */ + mga_out_dac( mmio, XCOLMSK0GREEN, 0xFF ); + mga_out_dac( mmio, XCOLMSK0BLUE, 0xFF ); + + mga_out_dac( mmio, XCOLKEY0RED, 0x00 ); /* default to black */ + mga_out_dac( mmio, XCOLKEY0GREEN, 0x00 ); + mga_out_dac( mmio, XCOLKEY0BLUE, 0x00 ); + + return DFB_OK; +} + +static DFBResult +besTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxDeviceData *mdev = mdrv->device_data; + int max_width = mdev->g450_matrox ? 2048 : 1024; + int max_height = 1024; + CoreLayerRegionConfigFlags fail = 0; + + if (config->options & ~BES_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + if (config->surface_caps & ~(DSCAPS_INTERLACED | DSCAPS_SEPARATED)) + fail |= CLRCF_SURFACE_CAPS; + + if (config->options & DLOP_DEINTERLACING) { + /* make sure BESPITCH < 4096 */ + if (mdev->g450_matrox && !(config->surface_caps & DSCAPS_SEPARATED)) + max_width = 2048 - 128; + max_height = 2048; + } else { + if (config->surface_caps & DSCAPS_SEPARATED) + fail |= CLRCF_SURFACE_CAPS; + } + + switch (config->format) { + case DSPF_YUY2: + case DSPF_NV12: + case DSPF_NV21: + break; + + case DSPF_ARGB: + case DSPF_RGB32: + if (!mdev->g450_matrox) + max_width = 512; + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + /* these formats are not supported by G200 */ + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) + break; + default: + fail |= CLRCF_FORMAT; + } + + switch (config->format) { + case DSPF_I420: + case DSPF_YV12: + case DSPF_NV12: + case DSPF_NV21: + if (config->height & 1) + fail |= CLRCF_HEIGHT; + case DSPF_YUY2: + case DSPF_UYVY: + if (config->width & 1) + fail |= CLRCF_WIDTH; + default: + break; + } + + if (config->width > max_width || config->width < 1) + fail |= CLRCF_WIDTH; + + if (config->height > max_height || config->height < 1) + fail |= CLRCF_HEIGHT; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +besSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxBesLayerData *mbes = (MatroxBesLayerData*) layer_data; + volatile u8 *mmio = mdrv->mmio_base; + + /* remember configuration */ + mbes->config = *config; + + /* set main configuration */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | + CLRCF_OPTIONS | CLRCF_DEST | CLRCF_OPACITY | CLRCF_SOURCE)) + { + bes_calc_regs( mdrv, mbes, config, surface, lock ); + bes_set_regs( mdrv, mbes ); + } + + /* set color key */ + if (updated & CLRCF_DSTKEY) { + DFBColorKey key = config->dst_key; + + switch (dfb_primary_layer_pixelformat()) { + case DSPF_RGB555: + case DSPF_ARGB1555: + key.r >>= 3; + key.g >>= 3; + key.b >>= 3; + break; + + case DSPF_RGB16: + key.r >>= 3; + key.g >>= 2; + key.b >>= 3; + break; + + default: + ; + } + + mga_out_dac( mmio, XCOLKEY0RED, key.r ); + mga_out_dac( mmio, XCOLKEY0GREEN, key.g ); + mga_out_dac( mmio, XCOLKEY0BLUE, key.b ); + } + + return DFB_OK; +} + +static DFBResult +besRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + volatile u8 *mmio = mdrv->mmio_base; + + /* make sure BES registers get updated (besvcnt) */ + mga_out32( mmio, 0, BESGLOBCTL ); + /* disable backend scaler */ + mga_out32( mmio, 0, BESCTL ); + + return DFB_OK; +} + +static DFBResult +besFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxBesLayerData *mbes = (MatroxBesLayerData*) layer_data; + bool swap; + + bes_calc_regs( mdrv, mbes, &mbes->config, surface, lock ); + swap = bes_set_buffer( mdrv, mbes, flags & DSFLIP_ONSYNC ); + + dfb_surface_flip( surface, swap ); + + if (flags & DSFLIP_WAIT) + dfb_screen_wait_vsync( mdrv->primary ); + + return DFB_OK; +} + +static DFBResult +besSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + volatile u8 *mmio = mdrv->mmio_base; + + if (mdrv->accelerator == FB_ACCEL_MATROX_MGAG200) + return DFB_UNSUPPORTED; + + mga_out32( mmio, (adj->contrast >> 8) | + ((u8)(((int)adj->brightness >> 8) - 128)) << 16, + BESLUMACTL ); + + return DFB_OK; +} + +static DFBResult +besSetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxBesLayerData *mbes = (MatroxBesLayerData*) layer_data; + + mbes->regs.besCTL_field = field ? 0x2000000 : 0; + + mga_out32( mdrv->mmio_base, + mbes->regs.besCTL | mbes->regs.besCTL_field, BESCTL ); + + return DFB_OK; +} + +DisplayLayerFuncs matroxBesFuncs = { + .LayerDataSize = besLayerDataSize, + .InitLayer = besInitLayer, + + .TestRegion = besTestRegion, + .SetRegion = besSetRegion, + .RemoveRegion = besRemoveRegion, + .FlipRegion = besFlipRegion, + + .SetColorAdjustment = besSetColorAdjustment, + .SetInputField = besSetInputField, +}; + + +/* internal */ + +static void bes_set_regs( MatroxDriverData *mdrv, MatroxBesLayerData *mbes ) +{ + int line = 0; + volatile u8 *mmio = mdrv->mmio_base; + VideoMode *mode = dfb_system_current_mode(); + + if (!mode) { + mode = dfb_system_modes(); + if (!mode) + return; + } + + /* prevent updates */ + line = 0xfff; + mga_out32( mmio, mbes->regs.besGLOBCTL | (line << 16), BESGLOBCTL); + + if (!(mbes->regs.besCTL & 0x4000000)) { + mga_out32( mmio, mbes->regs.besA1ORG, BESA1ORG ); + mga_out32( mmio, mbes->regs.besA2ORG, BESA2ORG ); + mga_out32( mmio, mbes->regs.besA1CORG, BESA1CORG ); + mga_out32( mmio, mbes->regs.besA2CORG, BESA2CORG ); + + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) { + mga_out32( mmio, mbes->regs.besA1C3ORG, BESA1C3ORG ); + mga_out32( mmio, mbes->regs.besA2C3ORG, BESA2C3ORG ); + } + } else { + mga_out32( mmio, mbes->regs.besA1ORG, BESB1ORG ); + mga_out32( mmio, mbes->regs.besA2ORG, BESB2ORG ); + mga_out32( mmio, mbes->regs.besA1CORG, BESB1CORG ); + mga_out32( mmio, mbes->regs.besA2CORG, BESB2CORG ); + + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) { + mga_out32( mmio, mbes->regs.besA1C3ORG, BESB1C3ORG ); + mga_out32( mmio, mbes->regs.besA2C3ORG, BESB2C3ORG ); + } + } + + mga_out32( mmio, mbes->regs.besCTL | mbes->regs.besCTL_field, BESCTL ); + + mga_out32( mmio, mbes->regs.besHCOORD, BESHCOORD ); + mga_out32( mmio, mbes->regs.besVCOORD, BESVCOORD ); + + mga_out32( mmio, mbes->regs.besHSRCST, BESHSRCST ); + mga_out32( mmio, mbes->regs.besHSRCEND, BESHSRCEND ); + mga_out32( mmio, mbes->regs.besHSRCLST, BESHSRCLST ); + + mga_out32( mmio, mbes->regs.besPITCH, BESPITCH ); + + mga_out32( mmio, mbes->regs.besV1WGHT, BESV1WGHT ); + mga_out32( mmio, mbes->regs.besV2WGHT, BESV2WGHT ); + + mga_out32( mmio, mbes->regs.besV1SRCLST, BESV1SRCLST ); + mga_out32( mmio, mbes->regs.besV2SRCLST, BESV2SRCLST ); + + mga_out32( mmio, mbes->regs.besVISCAL, BESVISCAL ); + mga_out32( mmio, mbes->regs.besHISCAL, BESHISCAL ); + + /* allow updates again */ + line = mode->yres; + mga_out32( mmio, mbes->regs.besGLOBCTL | (line << 16), BESGLOBCTL); + + mga_out_dac( mmio, XKEYOPMODE, mbes->regs.xKEYOPMODE ); +} + +static bool bes_set_buffer( MatroxDriverData *mdrv, MatroxBesLayerData *mbes, bool onsync ) +{ + bool ret; + u32 status; + int line; + volatile u8 *mmio = mdrv->mmio_base; + VideoMode *mode = dfb_system_current_mode(); + + if (!mode) { + mode = dfb_system_modes(); + if (!mode) + return false; + } + + /* prevent updates */ + line = 0xfff; + mga_out32( mmio, mbes->regs.besGLOBCTL | (line << 16), BESGLOBCTL); + + status = mga_in32( mmio, BESSTATUS ); + + /* Had the previous flip actually occured? */ + ret = !(status & 0x2) != !(mbes->regs.besCTL & 0x4000000); + + /* + * Pick the next buffer based on what's being displayed right now + * so that it's possible to detect if the flip actually occured + * regardless of how many times the buffers are flipped during one + * displayed frame. + */ + if (status & 0x2) { + mga_out32( mmio, mbes->regs.besA1ORG, BESA1ORG ); + mga_out32( mmio, mbes->regs.besA2ORG, BESA2ORG ); + mga_out32( mmio, mbes->regs.besA1CORG, BESA1CORG ); + mga_out32( mmio, mbes->regs.besA2CORG, BESA2CORG ); + + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) { + mga_out32( mmio, mbes->regs.besA1C3ORG, BESA1C3ORG ); + mga_out32( mmio, mbes->regs.besA2C3ORG, BESA2C3ORG ); + } + + mbes->regs.besCTL &= ~0x4000000; + } else { + mga_out32( mmio, mbes->regs.besA1ORG, BESB1ORG ); + mga_out32( mmio, mbes->regs.besA2ORG, BESB2ORG ); + mga_out32( mmio, mbes->regs.besA1CORG, BESB1CORG ); + mga_out32( mmio, mbes->regs.besA2CORG, BESB2CORG ); + + if (mdrv->accelerator != FB_ACCEL_MATROX_MGAG200) { + mga_out32( mmio, mbes->regs.besA1C3ORG, BESB1C3ORG ); + mga_out32( mmio, mbes->regs.besA2C3ORG, BESB2C3ORG ); + } + + mbes->regs.besCTL |= 0x4000000; + } + + mga_out32( mmio, mbes->regs.besCTL | mbes->regs.besCTL_field, BESCTL ); + + /* allow updates again */ + if (onsync) + line = mode->yres; + else + line = mga_in32( mmio, MGAREG_VCOUNT ) + 48; + mga_out32( mmio, mbes->regs.besGLOBCTL | (line << 16), BESGLOBCTL); + + return ret; +} + +static void bes_calc_regs( MatroxDriverData *mdrv, + MatroxBesLayerData *mbes, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + int cropleft, cropright, croptop, cropbot, croptop_uv; + int pitch, tmp, hzoom, intrep, field_height, field_offset; + DFBRectangle source, dest; + DFBRegion dst; + bool visible; + VideoMode *mode = dfb_system_current_mode(); + + if (!mode) { + mode = dfb_system_modes(); + if (!mode) { + D_BUG( "No current and no default mode" ); + return; + } + } + + source = config->source; + dest = config->dest; + + if (!mdev->g450_matrox && (surface->config.format == DSPF_RGB32 || surface->config.format == DSPF_ARGB)) + dest.w = source.w; + + pitch = lock->pitch; + + field_height = surface->config.size.h; + + if (config->options & DLOP_DEINTERLACING) { + field_height /= 2; + source.y /= 2; + source.h /= 2; + if (!(surface->config.caps & DSCAPS_SEPARATED)) + pitch *= 2; + } else + mbes->regs.besCTL_field = 0; + + /* destination region */ + dst.x1 = dest.x; + dst.y1 = dest.y; + dst.x2 = dest.x + dest.w - 1; + dst.y2 = dest.y + dest.h - 1; + + visible = dfb_region_intersect( &dst, 0, 0, mode->xres - 1, mode->yres - 1 ); + + /* calculate destination cropping */ + cropleft = -dest.x; + croptop = -dest.y; + cropright = dest.x + dest.w - mode->xres; + cropbot = dest.y + dest.h - mode->yres; + + cropleft = cropleft > 0 ? cropleft : 0; + croptop = croptop > 0 ? croptop : 0; + cropright = cropright > 0 ? cropright : 0; + cropbot = cropbot > 0 ? cropbot : 0; + croptop_uv = croptop; + + /* scale crop values to source dimensions */ + if (cropleft) + cropleft = ((u64) (source.w << 16) * cropleft / dest.w) & ~0x3; + if (croptop) + croptop = ((u64) (source.h << 16) * croptop / dest.h) & ~0x3; + if (cropright) + cropright = ((u64) (source.w << 16) * cropright / dest.w) & ~0x3; + if (cropbot) + cropbot = ((u64) (source.h << 16) * cropbot / dest.h) & ~0x3; + if (croptop_uv) + croptop_uv = ((u64) ((source.h/2) << 16) * croptop_uv / dest.h) & ~0x3; + + /* should horizontal zoom be used? */ + if (mdev->g450_matrox) + hzoom = (1000000/mode->pixclock >= 234) ? 1 : 0; + else + hzoom = (1000000/mode->pixclock >= 135) ? 1 : 0; + + /* initialize */ + mbes->regs.besGLOBCTL = 0; + + /* preserve buffer */ + mbes->regs.besCTL &= 0x4000000; + + /* enable/disable depending on opacity */ + if (config->opacity && visible) + mbes->regs.besCTL |= BESEN; + + /* pixel format settings */ + switch (surface->config.format) { + case DSPF_YV12: + mbes->regs.besGLOBCTL |= BESCORDER; + /* fall through */ + + case DSPF_I420: + mbes->regs.besGLOBCTL |= BESPROCAMP | BES3PLANE; + mbes->regs.besCTL |= BESHFEN | BESVFEN | BESCUPS | BES420PL; + break; + + case DSPF_NV21: + mbes->regs.besGLOBCTL |= BESCORDER; + /* fall through */ + + case DSPF_NV12: + mbes->regs.besGLOBCTL |= BESPROCAMP; + mbes->regs.besCTL |= BESHFEN | BESVFEN | BESCUPS | BES420PL; + break; + + case DSPF_UYVY: + mbes->regs.besGLOBCTL |= BESUYVYFMT; + /* fall through */ + + case DSPF_YUY2: + mbes->regs.besGLOBCTL |= BESPROCAMP; + mbes->regs.besCTL |= BESHFEN | BESVFEN | BESCUPS; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + mbes->regs.besGLOBCTL |= BESRGB15; + break; + + case DSPF_RGB16: + mbes->regs.besGLOBCTL |= BESRGB16; + break; + + case DSPF_ARGB: + case DSPF_RGB32: + mbes->regs.besGLOBCTL |= BESRGB32; + break; + + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (surface->config.size.w > 1024) + mbes->regs.besCTL &= ~BESVFEN; + + mbes->regs.besGLOBCTL |= 3*hzoom; + + mbes->regs.besPITCH = pitch / DFB_BYTES_PER_PIXEL(surface->config.format); + + /* buffer offsets */ + + field_offset = lock->pitch; + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 2; + + mbes->regs.besA1ORG = lock->offset + + pitch * (source.y + (croptop >> 16)); + mbes->regs.besA2ORG = mbes->regs.besA1ORG + + field_offset; + + switch (surface->config.format) { + case DSPF_NV12: + case DSPF_NV21: + field_offset = lock->pitch; + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 4; + + mbes->regs.besA1CORG = lock->offset + + surface->config.size.h * lock->pitch + + pitch * (source.y/2 + (croptop_uv >> 16)); + mbes->regs.besA2CORG = mbes->regs.besA1CORG + + field_offset; + break; + + case DSPF_I420: + case DSPF_YV12: + field_offset = lock->pitch / 2; + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 4; + + mbes->regs.besA1CORG = lock->offset + + surface->config.size.h * lock->pitch + + pitch/2 * (source.y/2 + (croptop_uv >> 16)); + mbes->regs.besA2CORG = mbes->regs.besA1CORG + + field_offset; + + mbes->regs.besA1C3ORG = mbes->regs.besA1CORG + + surface->config.size.h/2 * lock->pitch/2; + mbes->regs.besA2C3ORG = mbes->regs.besA1C3ORG + + field_offset; + break; + + default: + ; + } + + mbes->regs.besHCOORD = (dst.x1 << 16) | dst.x2; + mbes->regs.besVCOORD = (dst.y1 << 16) | dst.y2; + + mbes->regs.besHSRCST = (source.x << 16) + cropleft; + mbes->regs.besHSRCEND = ((source.x + source.w - 1) << 16) - cropright; + mbes->regs.besHSRCLST = (surface->config.size.w - 1) << 16; + + /* vertical starting weights */ + tmp = croptop & 0xfffc; + mbes->regs.besV1WGHT = tmp; + if (tmp >= 0x8000) { + tmp = tmp - 0x8000; + /* fields start on the same line */ + if ((source.y + (croptop >> 16)) & 1) + mbes->regs.besCTL |= BESV1SRCSTP | BESV2SRCSTP; + } else { + tmp = 0x10000 | (0x8000 - tmp); + /* fields start on alternate lines */ + if ((source.y + (croptop >> 16)) & 1) + mbes->regs.besCTL |= BESV1SRCSTP; + else + mbes->regs.besCTL |= BESV2SRCSTP; + } + mbes->regs.besV2WGHT = tmp; + + mbes->regs.besV1SRCLST = mbes->regs.besV2SRCLST = + field_height - 1 - source.y - (croptop >> 16); + + /* horizontal scaling */ + if (!mdev->g450_matrox && (surface->config.format == DSPF_RGB32 || surface->config.format == DSPF_ARGB)) { + mbes->regs.besHISCAL = 0x20000 << hzoom; + mbes->regs.besHSRCST *= 2; + mbes->regs.besHSRCEND *= 2; + mbes->regs.besHSRCLST *= 2; + mbes->regs.besPITCH *= 2; + } else { + intrep = ((mbes->regs.besCTL & BESHFEN) || (source.w > dest.w)) ? 1 : 0; + if ((dest.w == source.w) || (dest.w < 2)) + intrep = 0; + tmp = (((source.w - intrep) << 16) / (dest.w - intrep)) << hzoom; + if (tmp >= (32 << 16)) + tmp = (32 << 16) - 1; + mbes->regs.besHISCAL = tmp & 0x001ffffc; + } + + /* vertical scaling */ + intrep = ((mbes->regs.besCTL & BESVFEN) || (source.h > dest.h)) ? 1 : 0; + if ((dest.h == source.h) || (dest.h < 2)) + intrep = 0; + tmp = ((source.h - intrep) << 16) / (dest.h - intrep); + if(tmp >= (32 << 16)) + tmp = (32 << 16) - 1; + mbes->regs.besVISCAL = tmp & 0x001ffffc; + + /* enable color keying? */ + mbes->regs.xKEYOPMODE = (config->options & DLOP_DST_COLORKEY) ? 1 : 0; +} diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_crtc2.c b/Source/DirectFB/gfxdrivers/matrox/matrox_crtc2.c new file mode 100755 index 0000000..36c83a3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_crtc2.c @@ -0,0 +1,751 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" +#include "matrox_maven.h" + +typedef struct { + CoreLayerRegionConfig config; + DFBColorAdjustment adj; + int field; + + /* Stored registers */ + struct { + /* CRTC2 */ + u32 c2CTL; + u32 c2DATACTL; + u32 c2MISC; + u32 c2OFFSET; + + u32 c2HPARAM; + u32 c2VPARAM; + + u32 c2STARTADD0; + u32 c2STARTADD1; + u32 c2PL2STARTADD0; + u32 c2PL2STARTADD1; + u32 c2PL3STARTADD0; + u32 c2PL3STARTADD1; + } regs; + + MatroxMavenData mav; +} MatroxCrtc2LayerData; + +static void crtc2_set_regs ( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ); + +static void crtc2_calc_regs ( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +static void crtc2_calc_buffer ( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +static void crtc2_set_buffer ( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ); + +static DFBResult crtc2_disable_output( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ); + +static DFBResult crtc2_enable_output ( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ); + +#define CRTC2_SUPPORTED_OPTIONS (DLOP_FIELD_PARITY) + +/**********************/ + +static int +crtc2LayerDataSize( void ) +{ + return sizeof(MatroxCrtc2LayerData); +} + +static const DFBColorAdjustment adjustments[2][2] = { + /* G400 */ + { + /* PAL / PAL-60 */ + { + .flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_HUE | DCAF_SATURATION, + .brightness = 0xA800, + .saturation = 0x9500, + .contrast = 0xFF00, + .hue = 0x0000, + }, + /* NTSC */ + { + .flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_HUE | DCAF_SATURATION, + .brightness = 0xB500, + .saturation = 0x8E00, + .contrast = 0xEA00, + .hue = 0x0000, + } + }, + /* G450 / G550 */ + { + /* PAL / PAL-60 */ + { + .flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_HUE | DCAF_SATURATION, + .brightness = 0x9E00, + .saturation = 0xBB00, + .contrast = 0xFF00, + .hue = 0x0000, + }, + /* NTSC */ + { + .flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | DCAF_HUE | DCAF_SATURATION, + .brightness = 0xAA00, + .saturation = 0xAE00, + .contrast = 0xEA00, + .hue = 0x0000, + } + } +}; + +static DFBResult +crtc2InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2LayerData *mcrtc2 = (MatroxCrtc2LayerData*) layer_data; + MatroxDeviceData *mdev = mdrv->device_data; + MatroxMavenData *mav = &mcrtc2->mav; + DFBResult res; + + if ((res = maven_init( mav, mdrv )) != DFB_OK) + return res; + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_FIELD_PARITY | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | + DLCAPS_HUE | DLCAPS_SATURATION | DLCAPS_ALPHA_RAMP; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Matrox CRTC2 Layer" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS | DLCONF_SURFACE_CAPS; + config->width = 720; + config->height = (dfb_config->matrox_tv_std != DSETV_PAL) ? 480 : 576; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + config->surface_caps = DSCAPS_INTERLACED; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + *adjustment = adjustments[mdev->g450_matrox][dfb_config->matrox_tv_std == DSETV_NTSC]; + + /* remember color adjustment */ + mcrtc2->adj = *adjustment; + + return DFB_OK; +} + +static DFBResult +crtc2TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + if (config->options & ~CRTC2_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + if (config->surface_caps & ~(DSCAPS_INTERLACED | DSCAPS_SEPARATED)) + fail |= CLRCF_SURFACE_CAPS; + + switch (config->format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + break; + default: + fail |= CLRCF_FORMAT; + } + + if (config->width != 720) + fail |= CLRCF_WIDTH; + + if (config->height != ((dfb_config->matrox_tv_std != DSETV_PAL) ? 480 : 576)) + fail |= CLRCF_HEIGHT; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +crtc2AddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + return DFB_OK; +} + +static DFBResult +crtc2SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2LayerData *mcrtc2 = (MatroxCrtc2LayerData*) layer_data; + MatroxDeviceData *mdev = mdrv->device_data; + + /* remember configuration */ + mcrtc2->config = *config; + + if (updated & CLRCF_PARITY) + mcrtc2->field = !config->parity; + + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | + CLRCF_SURFACE_CAPS | CLRCF_ALPHA_RAMP | CLRCF_SURFACE)) { + crtc2_calc_regs( mdrv, mcrtc2, config, surface, lock ); + crtc2_calc_buffer( mdrv, mcrtc2, surface, lock ); + + ret = crtc2_enable_output( mdrv, mcrtc2 ); + if (ret) + return ret; + + mdev->crtc2_separated = !!(surface->config.caps & DSCAPS_SEPARATED); + } + + return DFB_OK; +} + +static DFBResult +crtc2RemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2LayerData *mcrtc2 = (MatroxCrtc2LayerData*) layer_data; + + crtc2_disable_output( mdrv, mcrtc2 ); + + return DFB_OK; +} + +static DFBResult +crtc2FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2LayerData *mcrtc2 = (MatroxCrtc2LayerData*) layer_data; + volatile u8 *mmio = mdrv->mmio_base; + + crtc2_calc_buffer( mdrv, mcrtc2, surface, lock ); + + if (mcrtc2->config.options & DLOP_FIELD_PARITY) { + int field = (mga_in32( mmio, C2VCOUNT ) & C2FIELD) ? 1 : 0; + + while (field == mcrtc2->field) { + dfb_screen_wait_vsync( mdrv->secondary ); + + field = (mga_in32( mmio, C2VCOUNT ) & C2FIELD) ? 1 : 0; + } + } + crtc2_set_buffer( mdrv, mcrtc2 ); + + dfb_surface_flip( surface, false ); + + if (flags & DSFLIP_WAIT) + dfb_screen_wait_vsync( mdrv->secondary ); + + return DFB_OK; +} + +static DFBResult +crtc2SetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2LayerData *mcrtc2 = (MatroxCrtc2LayerData*) layer_data; + MatroxMavenData *mav = &mcrtc2->mav; + DFBResult res; + + if ((res = maven_open( mav, mdrv )) != DFB_OK) + return res; + + if (adj->flags & DCAF_HUE) + maven_set_hue( mav, mdrv, + adj->hue >> 8 ); + if (adj->flags & DCAF_SATURATION) + maven_set_saturation( mav, mdrv, + adj->saturation >> 8 ); + if (adj->flags & DCAF_BRIGHTNESS || + adj->flags & DCAF_CONTRAST) + maven_set_bwlevel( mav, mdrv, + adj->brightness >> 8, + adj->contrast >> 8 ); + + maven_close( mav, mdrv ); + + /* remember color adjustment */ + mcrtc2->adj = *adj; + + return DFB_OK; +} + +static DFBResult +crtc2GetCurrentOutputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + int *field ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + + if (!field) + return DFB_INVARG; + + *field = (mga_in32( mdrv->mmio_base, C2VCOUNT ) & C2FIELD) ? 1 : 0; + + return DFB_OK; +} + +DisplayLayerFuncs matroxCrtc2Funcs = { + .LayerDataSize = crtc2LayerDataSize, + .InitLayer = crtc2InitLayer, + + .TestRegion = crtc2TestRegion, + .AddRegion = crtc2AddRegion, + .SetRegion = crtc2SetRegion, + .RemoveRegion = crtc2RemoveRegion, + .FlipRegion = crtc2FlipRegion, + + .SetColorAdjustment = crtc2SetColorAdjustment, + .GetCurrentOutputField = crtc2GetCurrentOutputField, +}; + +/* internal */ + +static void crtc2_set_regs( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mga_out32( mmio, mcrtc2->regs.c2CTL, C2CTL ); + mga_out32( mmio, mcrtc2->regs.c2DATACTL, C2DATACTL ); + mga_out32( mmio, mcrtc2->regs.c2HPARAM, C2HPARAM ); + mga_out32( mmio, 0, C2HSYNC ); + mga_out32( mmio, mcrtc2->regs.c2VPARAM, C2VPARAM ); + mga_out32( mmio, 0, C2VSYNC ); + mga_out32( mmio, mcrtc2->regs.c2OFFSET, C2OFFSET ); + mga_out32( mmio, mcrtc2->regs.c2MISC, C2MISC ); + mga_out32( mmio, 0, C2PRELOAD ); +} + +static void crtc2_calc_regs( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + mcrtc2->regs.c2CTL = 0; + + /* Don't touch sub-picture bits. */ + mcrtc2->regs.c2DATACTL = mga_in32( mdrv->mmio_base, C2DATACTL ); + mcrtc2->regs.c2DATACTL &= C2STATICKEY | C2OFFSETDIVEN | C2STATICKEYEN | C2SUBPICEN; + + if (mdev->g450_matrox) + mcrtc2->regs.c2CTL |= C2PIXCLKSEL_CRISTAL; + else + mcrtc2->regs.c2CTL |= C2PIXCLKSEL_VDOCLK; + + /* + * High priority request level. + * According to G400 specs these values should + * be fixed when CRTC2 is in YUV mode. + */ + /* c2hiprilvl */ + mcrtc2->regs.c2CTL |= 2 << 4; + /* c2maxhipri */ + mcrtc2->regs.c2CTL |= 1 << 8; + + switch (surface->config.format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + mcrtc2->regs.c2DATACTL |= C2DITHEN | C2YFILTEN | C2CBCRFILTEN; + break; + default: + break; + } + + if (dfb_config->matrox_tv_std != DSETV_PAL) + mcrtc2->regs.c2DATACTL |= C2NTSCEN; + + /* pixel format settings */ + switch (surface->config.format) { + case DSPF_I420: + case DSPF_YV12: + mcrtc2->regs.c2CTL |= C2DEPTH_YCBCR420; + break; + + case DSPF_UYVY: + mcrtc2->regs.c2DATACTL |= C2UYVYFMT; + /* fall through */ + + case DSPF_YUY2: + mcrtc2->regs.c2CTL |= C2DEPTH_YCBCR422; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + mcrtc2->regs.c2CTL |= C2DEPTH_15BPP; + break; + + case DSPF_RGB16: + mcrtc2->regs.c2CTL |= C2DEPTH_16BPP; + break; + + case DSPF_RGB32: + case DSPF_ARGB: + mcrtc2->regs.c2CTL |= C2DEPTH_32BPP; + break; + + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (!(surface->config.caps & DSCAPS_INTERLACED)) + mcrtc2->regs.c2CTL |= C2VCBCRSINGLE; + + mcrtc2->regs.c2OFFSET = lock->pitch; + if (!(surface->config.caps & DSCAPS_SEPARATED)) + mcrtc2->regs.c2OFFSET *= 2; + + { + int hdisplay, htotal, vdisplay, vtotal; + + if (dfb_config->matrox_tv_std != DSETV_PAL) { + hdisplay = 720; + htotal = 858; + vdisplay = 480 / 2; + vtotal = 525 / 2; + } else { + hdisplay = 720; + htotal = 864; + vdisplay = 576 / 2; + vtotal = 625 / 2; + } + + mcrtc2->regs.c2HPARAM = ((hdisplay - 8) << 16) | (htotal - 8); + mcrtc2->regs.c2VPARAM = ((vdisplay - 1) << 16) | (vtotal - 1); + + mcrtc2->regs.c2MISC = 0; + /* c2vlinecomp */ + mcrtc2->regs.c2MISC |= (vdisplay + 1) << 16; + } + + /* c2bpp15halpha */ + mcrtc2->regs.c2DATACTL |= config->alpha_ramp[3] << 8; + + /* c2bpp15lalpha */ + mcrtc2->regs.c2DATACTL |= config->alpha_ramp[0] << 16; +} + +static void crtc2_calc_buffer( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + unsigned int field_offset = lock->pitch; + + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 2; + + mcrtc2->regs.c2STARTADD1 = lock->offset; + mcrtc2->regs.c2STARTADD0 = mcrtc2->regs.c2STARTADD1 + field_offset; + + if (surface->config.caps & DSCAPS_INTERLACED) + field_offset = lock->pitch / 2; + else + field_offset = 0; + + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 4; + + switch (surface->config.format) { + case DSPF_I420: + mcrtc2->regs.c2PL2STARTADD1 = mcrtc2->regs.c2STARTADD1 + surface->config.size.h * lock->pitch; + mcrtc2->regs.c2PL2STARTADD0 = mcrtc2->regs.c2PL2STARTADD1 + field_offset; + + mcrtc2->regs.c2PL3STARTADD1 = mcrtc2->regs.c2PL2STARTADD1 + surface->config.size.h/2 * lock->pitch/2; + mcrtc2->regs.c2PL3STARTADD0 = mcrtc2->regs.c2PL3STARTADD1 + field_offset; + break; + case DSPF_YV12: + mcrtc2->regs.c2PL3STARTADD1 = mcrtc2->regs.c2STARTADD1 + surface->config.size.h * lock->pitch; + mcrtc2->regs.c2PL3STARTADD0 = mcrtc2->regs.c2PL3STARTADD1 + field_offset; + + mcrtc2->regs.c2PL2STARTADD1 = mcrtc2->regs.c2PL3STARTADD1 + surface->config.size.h/2 * lock->pitch/2; + mcrtc2->regs.c2PL2STARTADD0 = mcrtc2->regs.c2PL2STARTADD1 + field_offset; + break; + default: + break; + } +} + +static void crtc2_set_buffer( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mga_out32( mmio, mcrtc2->regs.c2STARTADD0, C2STARTADD0 ); + mga_out32( mmio, mcrtc2->regs.c2STARTADD1, C2STARTADD1 ); + mga_out32( mmio, mcrtc2->regs.c2PL2STARTADD0, C2PL2STARTADD0 ); + mga_out32( mmio, mcrtc2->regs.c2PL2STARTADD1, C2PL2STARTADD1 ); + mga_out32( mmio, mcrtc2->regs.c2PL3STARTADD0, C2PL3STARTADD0 ); + mga_out32( mmio, mcrtc2->regs.c2PL3STARTADD1, C2PL3STARTADD1 ); +} + +static void +crtc2OnOff( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2, + int on ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + if (on) + mcrtc2->regs.c2CTL |= C2EN; + else + mcrtc2->regs.c2CTL &= ~C2EN; + mga_out32( mmio, mcrtc2->regs.c2CTL, C2CTL ); + + if (on) + mcrtc2->regs.c2CTL &= ~C2PIXCLKDIS; + else + mcrtc2->regs.c2CTL |= C2PIXCLKDIS; + mga_out32( mmio, mcrtc2->regs.c2CTL, C2CTL ); + + if (!on) { + mcrtc2->regs.c2CTL &= ~C2INTERLACE; + mga_out32( mmio, mcrtc2->regs.c2CTL, C2CTL ); + } +} + +static void crtc2_set_mafc( MatroxDriverData *mdrv, + int on ) +{ + volatile u8 *mmio = mdrv->mmio_base; + u8 val; + + val = mga_in_dac( mmio, XMISCCTRL ); + if (on) { + val &= ~(MFCSEL_MASK | VDOUTSEL_MASK); + val |= MFCSEL_MAFC | VDOUTSEL_CRTC2656; + } else { + val &= ~MFCSEL_MASK; + val |= MFCSEL_DIS; + } + mga_out_dac( mmio, XMISCCTRL, val ); +} + +static DFBResult +crtc2_disable_output( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + MatroxMavenData *mav = &mcrtc2->mav; + DFBResult res; + + if ((res = maven_open( mav, mdrv )) != DFB_OK) + return res; + + maven_disable( mav, mdrv ); + if (!mdev->g450_matrox) + crtc2_set_mafc( mdrv, 0 ); + crtc2OnOff( mdrv, mcrtc2, 0 ); + + maven_close( mav, mdrv ); + + if (mdev->g450_matrox) { + volatile u8 *mmio = mdrv->mmio_base; + u8 val; + + /* Set Rset to 0.7 V */ + val = mga_in_dac( mmio, XGENIOCTRL ); + val &= ~0x40; + mga_out_dac( mmio, XGENIOCTRL, val ); + val = mga_in_dac( mmio, XGENIODATA ); + val &= ~0x40; + mga_out_dac( mmio, XGENIODATA, val ); + + val = mga_in_dac( mmio, XPWRCTRL ); + val &= ~(DAC2PDN | CFIFOPDN); + mga_out_dac( mmio, XPWRCTRL, val ); + + val = mga_in_dac( mmio, XDISPCTRL ); + val &= ~DAC2OUTSEL_MASK; + val |= DAC2OUTSEL_DIS; + mga_out_dac( mmio, XDISPCTRL, val ); + } + + return DFB_OK; +} + +static DFBResult +crtc2_enable_output( MatroxDriverData *mdrv, + MatroxCrtc2LayerData *mcrtc2 ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + MatroxMavenData *mav = &mcrtc2->mav; + volatile u8 *mmio = mdrv->mmio_base; + DFBResult res; + + if ((res = maven_open( mav, mdrv )) != DFB_OK) + return res; + + if (mdev->g450_matrox) { + volatile u8 *mmio = mdrv->mmio_base; + u8 val; + + /* Set Rset to 1.0 V */ + val = mga_in_dac( mmio, XGENIOCTRL ); + val |= 0x40; + mga_out_dac( mmio, XGENIOCTRL, val ); + val = mga_in_dac( mmio, XGENIODATA ); + val &= ~0x40; + mga_out_dac( mmio, XGENIODATA, val ); + + val = mga_in_dac( mmio, XPWRCTRL ); + val |= DAC2PDN | CFIFOPDN; + mga_out_dac( mmio, XPWRCTRL, val ); + + val = mga_in_dac( mmio, XDISPCTRL ); + val &= ~DAC2OUTSEL_MASK; + val |= DAC2OUTSEL_TVE; + mga_out_dac( mmio, XDISPCTRL, val ); + + if (dfb_config->matrox_cable == 1) { + val = mga_in_dac( mmio, XSYNCCTRL ); + val &= ~(DAC2HSOFF | DAC2VSOFF | DAC2HSPOL | DAC2VSPOL); + mga_out_dac( mmio, XSYNCCTRL, val ); + } + } + + maven_disable( mav, mdrv ); + if (!mdev->g450_matrox) + crtc2_set_mafc( mdrv, 0 ); + crtc2OnOff( mdrv, mcrtc2, 0 ); + + crtc2_set_regs( mdrv, mcrtc2 ); + crtc2_set_buffer( mdrv, mcrtc2 ); + + if (!mdev->g450_matrox) + crtc2_set_mafc( mdrv, 1 ); + crtc2OnOff( mdrv, mcrtc2, 1 ); + + maven_set_regs( mav, mdrv, &mcrtc2->config, &mcrtc2->adj ); + + mcrtc2->regs.c2CTL |= C2INTERLACE; + if (mdev->g450_matrox) + mcrtc2->regs.c2CTL |= 0x1000; /* Undocumented bit */ + while ((mga_in32( mmio, C2VCOUNT ) & 0x00000FFF) != 1) + ; + while ((mga_in32( mmio, C2VCOUNT ) & 0x00000FFF) != 0) + ; + mga_out32( mmio, mcrtc2->regs.c2CTL, C2CTL ); + + maven_enable( mav, mdrv ); + + if (!mdev->g450_matrox) { + while ((mga_in32( mmio, C2VCOUNT ) & 0x00000FFF) != 1) + ; + while ((mga_in32( mmio, C2VCOUNT ) & 0x00000FFF) != 0) + ; + maven_sync( mav, mdrv ); + } + + maven_close( mav, mdrv ); + + return DFB_OK; +} diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_maven.c b/Source/DirectFB/gfxdrivers/matrox/matrox_maven.c new file mode 100755 index 0000000..e263864 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_maven.c @@ -0,0 +1,785 @@ +/* + (c) 1998-2001 Petr Vandrovec + + This code originally comes from matroxfb. + Relicensed under the LGPL with the authors permission. + Adapted for CRTC2 ITU-R 656 mode by Ville Syrjala + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +#include + +#include "matrox.h" +#include "regs.h" +#include "mmio.h" +#include "matrox_maven.h" + +#define SYS_CLASS_I2C_DEV "/sys/class/i2c-dev" + +static void +maven_write_byte( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 reg, + u8 val ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + if (mdev->g450_matrox) { + volatile u8 *mmio = mdrv->mmio_base; + + mga_out_dac( mmio, 0x87, reg ); + mga_out_dac( mmio, 0x88, val ); + } else { + union i2c_smbus_data data; + struct i2c_smbus_ioctl_data args; + + data.byte = val; + + args.read_write = I2C_SMBUS_WRITE; + args.command = reg; + args.size = I2C_SMBUS_BYTE_DATA; + args.data = &data; + + ioctl( mdrv->maven_fd, I2C_SMBUS, &args ); + } +} + +static void +maven_write_word( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 reg, + u16 val ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + if (mdev->g450_matrox) { + volatile u8 *mmio = mdrv->mmio_base; + + mga_out_dac( mmio, 0x87, reg ); + mga_out_dac( mmio, 0x88, val ); + mga_out_dac( mmio, 0x87, reg + 1 ); + mga_out_dac( mmio, 0x88, val >> 8 ); + } else { + union i2c_smbus_data data; + struct i2c_smbus_ioctl_data args; + + data.word = val; + + args.read_write = I2C_SMBUS_WRITE; + args.command = reg; + args.size = I2C_SMBUS_WORD_DATA; + args.data = &data; + + ioctl( mdrv->maven_fd, I2C_SMBUS, &args ); + } +} + +#if 0 +/* i2c_smbus_read_byte_data() doesn't work with maven. */ +static int +i2c_read_byte( int fd, u8 addr, u8 reg ) +{ + int ret; + u8 val; + struct i2c_msg msgs[] = { + { addr, I2C_M_REV_DIR_ADDR, sizeof(reg), ® }, + { addr, I2C_M_RD | I2C_M_NOSTART, sizeof(val), &val } + }; + struct i2c_rdwr_ioctl_data data = { + msgs, 2 + }; + + ret = ioctl( fd, I2C_RDWR, &data ); + if (ret < 0) + return ret; + + return val; +} +#endif + +void +maven_disable( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + maven_write_byte( mav, mdrv, 0x3E, 0x01 ); + + if (mdev->g450_matrox) { + maven_write_byte( mav, mdrv, 0x80, 0x00 ); + return; + } + + maven_write_byte( mav, mdrv, 0x82, 0x80 ); + maven_write_byte( mav, mdrv, 0x8C, 0x00 ); + maven_write_byte( mav, mdrv, 0x94, 0xA2 ); + maven_write_word( mav, mdrv, 0x8E, 0x1EFF ); + maven_write_byte( mav, mdrv, 0xC6, 0x01 ); +} + +void +maven_enable( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + bool ntsc = dfb_config->matrox_tv_std != DSETV_PAL; + + if (mdev->g450_matrox) { + if (dfb_config->matrox_cable == 1) + /* SCART RGB */ + maven_write_byte( mav, mdrv, 0x80, ntsc ? 0x43 : 0x41 ); + else + /* Composite / S-Video */ + maven_write_byte( mav, mdrv, 0x80, ntsc ? 0x03 : 0x01 ); + } + else + maven_write_byte( mav, mdrv, 0x82, 0x20 ); + + maven_write_byte( mav, mdrv, 0x3E, 0x00 ); +} + +void +maven_sync( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + if (mdev->g450_matrox) + return; + + maven_write_byte( mav, mdrv, 0xD4, 0x01 ); + maven_write_byte( mav, mdrv, 0xD4, 0x00 ); +} + +#define LR(x) maven_write_byte( mav, mdrv, (x), mav->regs[(x)] ) +#define LRP(x) maven_write_word( mav, mdrv, (x), mav->regs[(x)] | (mav->regs[(x)+1] << 8) ) + +void +maven_set_regs( MatroxMavenData *mav, + MatroxDriverData *mdrv, + CoreLayerRegionConfig *config, + DFBColorAdjustment *adj ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + bool ntsc = dfb_config->matrox_tv_std != DSETV_PAL; + + LR(0x00); + LR(0x01); + LR(0x02); + LR(0x03); + LR(0x04); + LR(0x2C); + LR(0x08); + LR(0x0A); + LR(0x09); + LR(0x29); + LRP(0x31); + LRP(0x17); + LR(0x0B); + LR(0x0C); + LR(0x35); + LRP(0x10); + LRP(0x0E); + LRP(0x1E); + LR(0x20); + LR(0x22); + LR(0x25); + LR(0x34); + + LR(0x33); + LR(0x19); + LR(0x12); + LR(0x3B); + LR(0x13); + LR(0x39); + LR(0x1D); + LR(0x3A); + LR(0x24); + LR(0x14); + LR(0x15); + LR(0x16); + LRP(0x2D); + LRP(0x2F); + LR(0x1A); + LR(0x1B); + LR(0x1C); + LR(0x23); + LR(0x26); + LR(0x28); + LR(0x27); + LR(0x21); + LRP(0x2A); + LR(0x35); + LRP(0x3C); + LR(0x37); + LR(0x38); + + if (mdev->g450_matrox) { + maven_write_word( mav, mdrv, 0x82, ntsc ? 0x0014 : 0x0017 ); + maven_write_word( mav, mdrv, 0x84, 0x0001 ); + } else { + maven_write_byte( mav, mdrv, 0xB3, 0x01 ); + maven_write_byte( mav, mdrv, 0x82, 0xA0 ); + maven_write_byte( mav, mdrv, 0xD3, 0x01 ); + maven_write_byte( mav, mdrv, 0x8C, 0x10 ); + maven_write_byte( mav, mdrv, 0x94, 0xA2 ); + maven_write_byte( mav, mdrv, 0x8D, 0x03 ); + maven_write_byte( mav, mdrv, 0xB9, 0x78 ); + maven_write_byte( mav, mdrv, 0xBF, 0x02 ); + + /* + * Deflicker: 0x00, 0xB1, 0xA2 + * Doesn't work due to: + * - ITU-R BT.656 mode? + * - scaler is not used? + * - something else? + */ + maven_write_byte( mav, mdrv, 0x93, 0x00 ); + } + + maven_set_saturation( mav, mdrv, adj->saturation >> 8 ); + maven_set_hue( mav, mdrv, adj->hue >> 8 ); + maven_set_bwlevel( mav, mdrv, adj->brightness >> 8, + adj->contrast >> 8 ); + + if (!mdev->g450_matrox) { + LR(0x83); + LR(0x84); + LR(0x85); + LR(0x86); + LR(0x87); + LR(0x88); + LR(0x89); + LR(0x8A); + LR(0x8B); + + switch (dfb_config->matrox_cable) { + case 1: + /* SCART RGB */ + maven_write_byte( mav, mdrv, 0xB0, 0x85 ); + break; + case 2: + /* SCART Composite */ + maven_write_byte( mav, mdrv, 0xB0, 0x81 ); + break; + default: + /* Composite / S-Video */ + maven_write_byte( mav, mdrv, 0xB0, 0x80 ); + break; + } + } +} + +void +maven_set_hue( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 hue ) +{ + maven_write_byte( mav, mdrv, 0x25, hue ); +} + +void +maven_set_saturation( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 saturation ) +{ + maven_write_byte( mav, mdrv, 0x20, saturation ); + maven_write_byte( mav, mdrv, 0x22, saturation ); +} + +void +maven_set_bwlevel( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 brightness, + u8 contrast ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + int b, c, bl, wl, wlmax, blmin, range; + bool ntsc = dfb_config->matrox_tv_std == DSETV_NTSC; + + if (mdev->g450_matrox) { + wlmax = ntsc ? 936 : 938; + blmin = ntsc ? 267 : 281; + } else { + wlmax = 786; + blmin = ntsc ? 242 : 255; + } + range = wlmax - blmin - 128; + + b = brightness * range / 255 + blmin; + c = contrast * range / 2 / 255 + 64; + + bl = MAX( b - c, blmin ); + wl = MIN( b + c, wlmax ); + + blmin = ((blmin << 8) & 0x0300) | ((blmin >> 2) & 0x00FF); + bl = ((bl << 8) & 0x0300) | ((bl >> 2) & 0x00FF); + wl = ((wl << 8) & 0x0300) | ((wl >> 2) & 0x00FF); + + maven_write_word( mav, mdrv, 0x10, blmin ); + maven_write_word( mav, mdrv, 0x0E, bl ); + maven_write_word( mav, mdrv, 0x1E, wl ); +} + +DFBResult +maven_open( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + if (mdev->g450_matrox) + return DFB_OK; + + if (mdrv->maven_fd != -1) + D_BUG( "DirectFB/Matrox/Maven: Device already open!\n" ); + + if ((mdrv->maven_fd = open( mav->dev, O_RDWR )) < 0) { + D_PERROR( "DirectFB/Matrox/Maven: Error opening `%s'!\n", + mav->dev ); + mdrv->maven_fd = -1; + return errno2result( errno ); + } + + if (ioctl( mdrv->maven_fd, I2C_SLAVE, mav->address ) < 0) { + D_PERROR( "DirectFB/Matrox/Maven: Error controlling `%s'!\n", + mav->dev ); + close( mdrv->maven_fd ); + mdrv->maven_fd = -1; + return errno2result( errno ); + } + + return DFB_OK; +} + +void +maven_close( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + + if (mdev->g450_matrox) + return; + + if (mdrv->maven_fd == -1) + D_BUG( "DirectFB/Matrox/Maven: Device not open!\n" ); + + close( mdrv->maven_fd ); + mdrv->maven_fd = -1; +} + +DFBResult maven_init( MatroxMavenData *mav, + MatroxDriverData *mdrv ) +{ + MatroxDeviceData *mdev = mdrv->device_data; + char line[512]; + int fd; + FILE *file; + bool found = false; + DIR *dir; + + /* Locate G400 maven /dev/i2c file */ + + /* Try sysfs */ + if (!mdev->g450_matrox && (dir = opendir( SYS_CLASS_I2C_DEV )) != NULL) { + char path[PATH_MAX]; + struct dirent *ent; + + while ((ent = readdir( dir )) != NULL) { + FILE *fp; + + if (!strcmp( ent->d_name, "." )) + continue; + if (!strcmp( ent->d_name, ".." )) + continue; + + snprintf( path, sizeof(path), "%s/%s/name", SYS_CLASS_I2C_DEV, ent->d_name ); + + fp = fopen( path, "r" ); + if (!fp) { + D_PERROR( "DirectFB/Matrox/Maven: Error opening `%s'!\n", path ); + continue; + } + + memset( line, 0, 6 ); + + fread( line, 1, 5, fp ); + if (ferror( fp )) { + D_PERROR( "DirectFB/Matrox/Maven: Error reading `%s'!\n", path ); + fclose( fp ); + continue; + } + + fclose( fp ); + + if (strcmp( line, "MAVEN" )) + continue; + + snprintf( mav->dev, sizeof(mav->dev), "/dev/%s", ent->d_name ); + found = true; + break; + } + if (!ent && errno) + D_PERROR( "DirectFB/Matrox/Maven: Error reading `%s'!\n", SYS_CLASS_I2C_DEV ); + + closedir( dir ); + } + + /* Try /proc/bus/i2c */ + if (!mdev->g450_matrox && !found) { + file = fopen( "/proc/bus/i2c", "r" ); + if (!file) { + D_PERROR( "DirectFB/Matrox/Maven: " + "Error opening `/proc/bus/i2c'!\n" ); + return errno2result( errno ); + } + while (fgets( line, 512, file )) { + if (strstr( line, "MAVEN" )) { + char *p = line; + while (!isspace( *p )) + p++; + *p = '\0'; + direct_snputs( mav->dev, "/dev/", 6 ); + strncat( mav->dev, line, 250 ); + found = true; + break; + } + } + fclose( file ); + } + + if (!mdev->g450_matrox) { + if (!found) { + D_ERROR( "DirectFB/Matrox/Maven: " + "Can't find MAVEN i2c device file!\n" ); + return DFB_UNSUPPORTED; + } + + /* Try to use it */ + if ((fd = open( mav->dev, O_RDWR )) < 0) { + D_PERROR( "DirectFB/Matrox/Maven: Error opening `%s'!\n", + mav->dev ); + return errno2result( errno ); + } + +#if 0 + /* FIXME: This fails for some people */ + /* Check if maven is at address 0x1B (DH board) or 0x1A (DH add-on) */ + if (i2c_read_byte( fd, 0x1B, 0xB2 ) < 0) { + if (i2c_read_byte( fd, 0x1A, 0xB2 ) < 0) { + D_ERROR( "DirectFB/Matrox/Maven: Error reading from maven chip!\n" ); + close( fd ); + return errno2result( errno ); + } else + mav->address = 0x1A; + } else + mav->address = 0x1B; +#else + mav->address = 0x1B; +#endif + + close( fd ); + } + + /* Maven registers */ + { + static const u8 ntscregs[2][0x40] = { + /* G400 */ + { + 0x21, 0xF0, 0x7C, 0x1F, /* 00-03 */ + 0x00, /* 04 */ + 0x00, + 0x00, + 0x00, + 0x7E, /* 08 */ + 0x43, /* 09 */ + 0x7E, /* 0A */ + 0x3D, /* 0B */ + 0x00, /* 0C */ + 0x00, + 0x46, 0x03, /* 0E-0F */ + 0x3C, 0x02, /* 10-11 */ + 0x17, /* 12 */ + 0x21, /* 13 */ + 0x1B, /* 14 */ + 0x1B, /* 15 */ + 0x24, /* 16 */ + 0x83, 0x01, /* 17-18 */ + 0x00, /* 19 */ + 0x0F, /* 1A */ + 0x0F, /* 1B */ + 0x60, /* 1C */ + 0x05, /* 1D */ + 0xC4, 0x02, /* 1E-1F */ + 0x8E, /* 20 */ + 0x04, /* 21 */ + 0x8E, /* 22 */ + 0x01, /* 23 */ + 0x02, /* 24 */ + 0x00, /* 25 */ + 0x0A, /* 26 */ + 0x05, /* 27 */ + 0x00, /* 28 */ + 0x10, /* 29 */ + 0xFF, 0x03, /* 2A-2B */ + 0x18, /* 2C */ + 0x0F, 0x78, /* 2D-2E */ + 0x00, 0x00, /* 2F-30 */ + 0xB4, 0x00, /* 31-32 */ + 0x14, /* 33 */ + 0x02, /* 34 */ + 0x1C, /* 35 */ + 0x00, + 0xA3, /* 37 */ + 0xC8, /* 38 */ + 0x15, /* 39 */ + 0x05, /* 3A */ + 0x15, /* 3B */ + 0x3C, 0x00, /* 3C-3D */ + 0x00, /* 3E */ + 0x00 + }, + /* G450 / G550 */ + { + 0x21, 0xF0, 0x7C, 0x1F, /* 00-03 */ + 0x00, /* 04 */ + 0x00, + 0x00, + 0x00, + 0x7E, /* 08 */ + 0x44, /* 09 */ + 0x76, /* 0A */ + 0x49, /* 0B */ + 0x00, /* 0C */ + 0x00, + 0x4E, 0x03, /* 0E-0F */ + 0x42, 0x03, /* 10-11 */ + 0x17, /* 12 */ + 0x21, /* 13 */ + 0x1B, /* 14 */ + 0x1B, /* 15 */ + 0x24, /* 16 */ + 0x83, 0x01, /* 17-18 */ + 0x00, /* 19 */ + 0x0F, /* 1A */ + 0x0F, /* 1B */ + 0x60, /* 1C */ + 0x05, /* 1D */ + 0xEA, 0x00, /* 1E-1F */ + 0xAE, /* 20 */ + 0x04, /* 21 */ + 0xAE, /* 22 */ + 0x01, /* 23 */ + 0x02, /* 24 */ + 0x00, /* 25 */ + 0x0A, /* 26 */ + 0x05, /* 27 */ + 0x00, /* 28 */ + 0x11, /* 29 */ + 0xFF, 0x03, /* 2A-2B */ + 0x20, /* 2C */ + 0x0F, 0x78, /* 2D-2E */ + 0x00, 0x00, /* 2F-30 */ + 0xB4, 0x00, /* 31-32 */ + 0x14, /* 33 */ + 0x02, /* 34 */ + 0x00, /* 35 */ + 0x00, + 0xBD, /* 37 */ + 0xDA, /* 38 */ + 0x15, /* 39 */ + 0x05, /* 3A */ + 0x15, /* 3B */ + 0x42, 0x03, /* 3C-3D */ + 0x00, /* 3E */ + 0x00 + } + }; + static const u8 palregs[2][0x40] = { + /* G400 */ + { + 0x2A, 0x09, 0x8A, 0xCB, /* 00-03 */ + 0x00, /* 04 */ + 0x00, + 0x00, + 0x00, + 0x7E, /* 08 */ + 0x3C, /* 09 */ + 0x82, /* 0A */ + 0x2E, /* 0B */ + 0x21, /* 0C */ + 0x00, + 0x3F, 0x03, /* 0E-0F */ + 0x3F, 0x03, /* 10-11 */ + 0x1A, /* 12 */ + 0x2A, /* 13 */ + 0x1C, /* 14 */ + 0x3D, /* 15 */ + 0x14, /* 16 */ + 0x9C, 0x01, /* 17-18 */ + 0x00, /* 19 */ + 0xFE, /* 1A */ + 0x7E, /* 1B */ + 0x60, /* 1C */ + 0x05, /* 1D */ + 0xC4, 0x01, /* 1E-1F */ + 0x95, /* 20 */ + 0x07, /* 21 */ + 0x95, /* 22 */ + 0x00, /* 23 */ + 0x00, /* 24 */ + 0x00, /* 25 */ + 0x08, /* 26 */ + 0x04, /* 27 */ + 0x00, /* 28 */ + 0x1A, /* 29 */ + 0x55, 0x01, /* 2A-2B */ + 0x20, /* 2C */ + 0x07, 0x7E, /* 2D-2E */ + 0x02, 0x54, /* 2F-30 */ + 0xB4, 0x00, /* 31-32 */ + 0x14, /* 33 */ + 0x49, /* 34 */ + 0x1D, /* 35 */ + 0x00, + 0xA3, /* 37 */ + 0xC8, /* 38 */ + 0x22, /* 39 */ + 0x02, /* 3A */ + 0x22, /* 3B */ + 0x3F, 0x03, /* 3C-3D */ + 0x00, /* 3E */ + 0x00, + }, + /* G450 / G550 */ + { + 0x2A, 0x09, 0x8A, 0xCB, /* 00-03 */ + 0x00, /* 04 */ + 0x00, + 0x00, + 0x00, + 0x7E, /* 08 */ + 0x3A, /* 09 */ + 0x8A, /* 0A */ + 0x38, /* 0B */ + 0x28, /* 0C */ + 0x00, + 0x46, 0x01, /* 0E-0F */ + 0x46, 0x01, /* 10-11 */ + 0x1A, /* 12 */ + 0x2A, /* 13 */ + 0x1C, /* 14 */ + 0x3D, /* 15 */ + 0x14, /* 16 */ + 0x9C, 0x01, /* 17-18 */ + 0x00, /* 19 */ + 0xFE, /* 1A */ + 0x7E, /* 1B */ + 0x60, /* 1C */ + 0x05, /* 1D */ + 0xEA, 0x00, /* 1E-1F */ + 0xBB, /* 20 */ + 0x07, /* 21 */ + 0xBB, /* 22 */ + 0x00, /* 23 */ + 0x00, /* 24 */ + 0x00, /* 25 */ + 0x08, /* 26 */ + 0x04, /* 27 */ + 0x00, /* 28 */ + 0x1A, /* 29 */ + 0x55, 0x01, /* 2A-2B */ + 0x18, /* 2C */ + 0x07, 0x7E, /* 2D-2E */ + 0x02, 0x54, /* 2F-30 */ + 0xB4, 0x00, /* 31-32 */ + 0x16, /* 33 */ + 0x49, /* 34 */ + 0x00, /* 35 */ + 0x00, + 0xB9, /* 37 */ + 0xDD, /* 38 */ + 0x22, /* 39 */ + 0x02, /* 3A */ + 0x22, /* 3B */ + 0x46, 0x00, /* 3C-3D */ + 0x00, /* 3E */ + 0x00, + } + }; + + if (dfb_config->matrox_tv_std != DSETV_PAL) + direct_memcpy( mav->regs, ntscregs[mdev->g450_matrox], 64 ); + else + direct_memcpy( mav->regs, palregs[mdev->g450_matrox], 64 ); + + if (dfb_config->matrox_tv_std == DSETV_PAL_60) { + mav->regs[0x00] = palregs[mdev->g450_matrox][0x00]; + mav->regs[0x01] = palregs[mdev->g450_matrox][0x01]; + mav->regs[0x02] = palregs[mdev->g450_matrox][0x02]; + mav->regs[0x03] = palregs[mdev->g450_matrox][0x03]; + mav->regs[0x0B] = palregs[mdev->g450_matrox][0x0B]; + mav->regs[0x0C] = palregs[mdev->g450_matrox][0x0C]; + mav->regs[0x0E] = palregs[mdev->g450_matrox][0x0E]; + mav->regs[0x0F] = palregs[mdev->g450_matrox][0x0F]; + mav->regs[0x10] = palregs[mdev->g450_matrox][0x10]; + mav->regs[0x11] = palregs[mdev->g450_matrox][0x11]; + mav->regs[0x1E] = palregs[mdev->g450_matrox][0x1E]; + mav->regs[0x1F] = palregs[mdev->g450_matrox][0x1F]; + mav->regs[0x20] = palregs[mdev->g450_matrox][0x20]; + mav->regs[0x22] = palregs[mdev->g450_matrox][0x22]; + mav->regs[0x25] = palregs[mdev->g450_matrox][0x25]; + mav->regs[0x34] = palregs[mdev->g450_matrox][0x34]; + } + + if (!mdev->g450_matrox) { + /* gamma */ + mav->regs[0x83] = 0x00; + mav->regs[0x84] = 0x00; + mav->regs[0x85] = 0x00; + mav->regs[0x86] = 0x1F; + mav->regs[0x87] = 0x10; + mav->regs[0x88] = 0x10; + mav->regs[0x89] = 0x10; + mav->regs[0x8A] = 0x64; + mav->regs[0x8B] = 0xC8; + } + } + + return DFB_OK; +} diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_maven.h b/Source/DirectFB/gfxdrivers/matrox/matrox_maven.h new file mode 100755 index 0000000..eeeb32d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_maven.h @@ -0,0 +1,64 @@ +/* + (c) 1998-2001 Petr Vandrovec + + This code originally comes from matroxfb. + Relicensed under the LGPL with the authors permission. + Adapted for CRTC2 ITU-R 656 mode by Ville Syrjala + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __MATROX_MAVEN_H__ +#define __MATROX_MAVEN_H__ + +typedef struct { + char dev[256]; + u8 regs[256]; + u8 address; +} MatroxMavenData; + +DFBResult maven_init( MatroxMavenData *mav, + MatroxDriverData *mdrv ); + +DFBResult maven_open( MatroxMavenData *mav, + MatroxDriverData *mdrv ); +void maven_close( MatroxMavenData *mav, + MatroxDriverData *mdrv ); + +void maven_enable( MatroxMavenData *mav, + MatroxDriverData *mdrv ); +void maven_disable( MatroxMavenData *mav, + MatroxDriverData *mdrv ); +void maven_sync( MatroxMavenData *mav, + MatroxDriverData *mdrv ); + +void maven_set_regs( MatroxMavenData *mav, + MatroxDriverData *mdrv, + CoreLayerRegionConfig *config, + DFBColorAdjustment *adj ); + +void maven_set_hue( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 hue ); +void maven_set_saturation( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 saturation ); +void maven_set_bwlevel( MatroxMavenData *mav, + MatroxDriverData *mdrv, + u8 brightness, + u8 contrast ); + +#endif diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_screen_crtc2.c b/Source/DirectFB/gfxdrivers/matrox/matrox_screen_crtc2.c new file mode 100755 index 0000000..f08a58f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_screen_crtc2.c @@ -0,0 +1,279 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include + +#include + +#include +#include +#include +#include + +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" + + +typedef struct { + DFBScreenPowerMode power_mode; +} MatroxCrtc2ScreenData; + +static void crtc2_wait_vsync( MatroxDriverData *mdrv ); + +/**************************************************************************************************/ + +static int +crtc2ScreenDataSize( void ) +{ + return sizeof(MatroxCrtc2ScreenData); +} + +static DFBResult +crtc2InitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + /* Set the screen capabilities. */ + description->caps = DSCCAPS_VSYNC | DSCCAPS_ENCODERS | DSCCAPS_OUTPUTS; + + /* Set the screen name. */ + snprintf( description->name, + DFB_SCREEN_DESC_NAME_LENGTH, "Matrox CRTC2 Screen" ); + + /* Set number of encoders and outputs. */ + description->encoders = 1; + description->outputs = 1; + + return DFB_OK; +} + +/**************************************************************************************************/ + +static DFBResult +crtc2InitEncoder( CoreScreen *screen, + void *driver_data, + void *screen_data, + int encoder, + DFBScreenEncoderDescription *description, + DFBScreenEncoderConfig *config ) +{ + /* Set the encoder capabilities & type. */ + description->caps = DSECAPS_TV_STANDARDS; + description->type = DSET_TV; + + /* Set supported TV standards. */ + description->tv_standards = DSETV_PAL | DSETV_NTSC | DSETV_PAL_60; + + /* Set default configuration. */ + config->flags = DSECONF_TV_STANDARD; + config->tv_standard = dfb_config->matrox_tv_std; + + return DFB_OK; +} + +static DFBResult +crtc2InitOutput( CoreScreen *screen, + void *driver_data, + void *screen_data, + int output, + DFBScreenOutputDescription *description, + DFBScreenOutputConfig *config ) +{ + /* Set the output capabilities. */ + description->caps = DSOCAPS_CONNECTORS | + DSOCAPS_SIGNAL_SEL | DSOCAPS_CONNECTOR_SEL; + + /* Set supported output connectors and signals. */ + description->all_connectors = DSOC_CVBS | DSOC_YC | DSOC_SCART; + description->all_signals = DSOS_CVBS | DSOS_YC | DSOS_RGB; + + /* Set default configuration. */ + config->flags = DSOCONF_SIGNALS | DSOCONF_CONNECTORS; + + switch (dfb_config->matrox_cable) { + case 1: + /* SCART RGB */ + config->out_signals = DSOS_RGB; + config->out_connectors = DSOC_SCART; + break; + case 2: + /* SCART Composite */ + config->out_signals = DSOS_CVBS; + config->out_connectors = DSOC_SCART; + break; + default: + /* Composite / S-Video */ + config->out_signals = DSOS_CVBS | DSOS_YC; + config->out_connectors = DSOC_CVBS | DSOC_YC; + break; + } + + return DFB_OK; +} + +/**************************************************************************************************/ + +static DFBResult +crtc2SetPowerMode( CoreScreen *screen, + void *driver_data, + void *screen_data, + DFBScreenPowerMode mode ) +{ + MatroxCrtc2ScreenData *msc2 = (MatroxCrtc2ScreenData*) screen_data; + + msc2->power_mode = mode; + + return DFB_OK; +} + +static DFBResult +crtc2WaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxCrtc2ScreenData *msc2 = (MatroxCrtc2ScreenData*) screen_data; + + if (msc2->power_mode == DSPM_ON) + crtc2_wait_vsync( mdrv ); + + return DFB_OK; +} + +/**************************************************************************************************/ + +static DFBResult +crtc2TestEncoderConfig( CoreScreen *screen, + void *driver_data, + void *screen_data, + int encoder, + const DFBScreenEncoderConfig *config, + DFBScreenEncoderConfigFlags *failed ) +{ + D_UNIMPLEMENTED(); + + return DFB_UNIMPLEMENTED; +} + +static DFBResult +crtc2SetEncoderConfig( CoreScreen *screen, + void *driver_data, + void *screen_data, + int encoder, + const DFBScreenEncoderConfig *config ) +{ +// D_UNIMPLEMENTED(); + + return DFB_UNIMPLEMENTED; +} + +/**************************************************************************************************/ + +static DFBResult +crtc2TestOutputConfig( CoreScreen *screen, + void *driver_data, + void *screen_data, + int output, + const DFBScreenOutputConfig *config, + DFBScreenOutputConfigFlags *failed ) +{ + D_UNIMPLEMENTED(); + + return DFB_UNIMPLEMENTED; +} + +static DFBResult +crtc2SetOutputConfig( CoreScreen *screen, + void *driver_data, + void *screen_data, + int output, + const DFBScreenOutputConfig *config ) +{ +// D_UNIMPLEMENTED(); + + return DFB_UNIMPLEMENTED; +} + +/**************************************************************************************************/ + +static DFBResult +crtc2GetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + *ret_width = 720; + *ret_height = (dfb_config->matrox_tv_std != DSETV_PAL) ? 480 : 576; + + return DFB_OK; +} + +ScreenFuncs matroxCrtc2ScreenFuncs = { + .ScreenDataSize = crtc2ScreenDataSize, + .InitScreen = crtc2InitScreen, + .InitEncoder = crtc2InitEncoder, + .InitOutput = crtc2InitOutput, + .SetPowerMode = crtc2SetPowerMode, + .WaitVSync = crtc2WaitVSync, + .TestEncoderConfig = crtc2TestEncoderConfig, + .SetEncoderConfig = crtc2SetEncoderConfig, + .TestOutputConfig = crtc2TestOutputConfig, + .SetOutputConfig = crtc2SetOutputConfig, + .GetScreenSize = crtc2GetScreenSize, +}; + +/**************************************************************************************************/ + +static void crtc2_wait_vsync( MatroxDriverData *mdrv ) +{ + int vdisplay = ((dfb_config->matrox_tv_std != DSETV_PAL) ? 480/2 : 576/2) + 1; + +#ifdef FBIO_WAITFORVSYNC + static const int one = 1; + FBDev *dfb_fbdev = dfb_system_data(); + if (ioctl( dfb_fbdev->fd, FBIO_WAITFORVSYNC, &one )) +#endif + while ((int)(mga_in32( mdrv->mmio_base, C2VCOUNT ) & 0x00000FFF) != vdisplay) + ; +} + diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_spic.c b/Source/DirectFB/gfxdrivers/matrox/matrox_spic.c new file mode 100755 index 0000000..cca8392 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_spic.c @@ -0,0 +1,314 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" + +typedef struct { + CoreLayerRegionConfig config; + + /* Stored registers */ + struct { + /* CRTC2 sub picture */ + u32 c2DATACTL; + + u32 c2SPICSTARTADD0; + u32 c2SPICSTARTADD1; + u32 c2SUBPICLUT; + } regs; +} MatroxSpicLayerData; + +static void spic_calc_buffer( MatroxDriverData *mdrv, + MatroxSpicLayerData *mspic, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +static void spic_set_buffer( MatroxDriverData *mdrv, + MatroxSpicLayerData *mspic ); + +#define SPIC_SUPPORTED_OPTIONS (DLOP_ALPHACHANNEL | DLOP_OPACITY) + +/**********************/ + +static int +spicLayerDataSize( void ) +{ + return sizeof(MatroxSpicLayerData); +} + +static DFBResult +spicInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_ALPHACHANNEL | DLCAPS_OPACITY; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Matrox CRTC2 Sub-Picture" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS | DLCONF_SURFACE_CAPS; + + config->width = 720; + config->height = (dfb_config->matrox_tv_std != DSETV_PAL) ? 480 : 576; + config->pixelformat = DSPF_ALUT44; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + config->surface_caps = DSCAPS_INTERLACED; + + return DFB_OK; +} + +static DFBResult +spicTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + if (config->options & ~SPIC_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* Can't have both at the same time */ + if (config->options & DLOP_ALPHACHANNEL && config->options & DLOP_OPACITY) + fail |= CLRCF_OPTIONS; + + switch (config->opacity) { + case 0x00: + case 0xFF: + break; + default: + if (!(config->options & DLOP_OPACITY)) + fail |= CLRCF_OPACITY; + } + + if (config->surface_caps & ~(DSCAPS_INTERLACED | DSCAPS_SEPARATED)) + fail |= CLRCF_SURFACE_CAPS; + + if (config->format != DSPF_ALUT44) + fail |= CLRCF_FORMAT; + + if (config->width != 720) + fail |= CLRCF_WIDTH; + + if (config->surface_caps & DSCAPS_INTERLACED) { + if (config->height != ((dfb_config->matrox_tv_std != DSETV_PAL) ? 480 : 576)) + fail |= CLRCF_HEIGHT; + } else { + if (config->height != ((dfb_config->matrox_tv_std != DSETV_PAL) ? 240 : 288)) + fail |= CLRCF_HEIGHT; + } + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +spicAddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + return DFB_OK; +} + +static DFBResult +spicSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxSpicLayerData *mspic = (MatroxSpicLayerData*) layer_data; + MatroxDeviceData *mdev = mdrv->device_data; + volatile u8 *mmio = mdrv->mmio_base; + + /* remember configuration */ + mspic->config = *config; + + if (updated & CLRCF_PALETTE) { + u8 y, cb, cr; + int i; + + for (i = 0; i < 16; i++) { + RGB_TO_YCBCR( palette->entries[i].r, + palette->entries[i].g, + palette->entries[i].b, + y, cb, cr ); + + mspic->regs.c2SUBPICLUT = (cr << 24) | (cb << 16) | (y << 8) | i; + mga_out32( mmio, mspic->regs.c2SUBPICLUT, C2SUBPICLUT ); + } + } + + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | CLRCF_SURFACE_CAPS | + CLRCF_OPTIONS | CLRCF_OPACITY | CLRCF_SURFACE)) { + spic_calc_buffer( mdrv, mspic, surface, lock ); + spic_set_buffer( mdrv, mspic ); + + mspic->regs.c2DATACTL = mga_in32( mmio, C2DATACTL ); + + if (surface->config.caps & DSCAPS_INTERLACED || mdev->crtc2_separated) + mspic->regs.c2DATACTL &= ~C2OFFSETDIVEN; + else + mspic->regs.c2DATACTL |= C2OFFSETDIVEN; + + if (config->opacity) + mspic->regs.c2DATACTL |= C2SUBPICEN; + else + mspic->regs.c2DATACTL &= ~C2SUBPICEN; + + if (config->options & DLOP_ALPHACHANNEL) + mspic->regs.c2DATACTL &= ~C2STATICKEYEN; + else + mspic->regs.c2DATACTL |= C2STATICKEYEN; + + mspic->regs.c2DATACTL &= ~C2STATICKEY; + mspic->regs.c2DATACTL |= ((config->opacity + 1) << 20) & C2STATICKEY; + + mga_out32( mmio, mspic->regs.c2DATACTL, C2DATACTL); + } + + return DFB_OK; +} + +static DFBResult +spicRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxSpicLayerData *mspic = (MatroxSpicLayerData*) layer_data; + volatile u8 *mmio = mdrv->mmio_base; + + mspic->regs.c2DATACTL = mga_in32( mmio, C2DATACTL ); + + mspic->regs.c2DATACTL &= ~C2SUBPICEN; + + mga_out32( mmio, mspic->regs.c2DATACTL, C2DATACTL ); + + return DFB_OK; +} + +static DFBResult +spicFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + MatroxDriverData *mdrv = (MatroxDriverData*) driver_data; + MatroxSpicLayerData *mspic = (MatroxSpicLayerData*) layer_data; + + spic_calc_buffer( mdrv, mspic, surface, lock ); + spic_set_buffer( mdrv, mspic ); + + dfb_surface_flip( surface, false ); + + return DFB_OK; +} + +DisplayLayerFuncs matroxSpicFuncs = { + .LayerDataSize = spicLayerDataSize, + .InitLayer = spicInitLayer, + + .TestRegion = spicTestRegion, + .AddRegion = spicAddRegion, + .SetRegion = spicSetRegion, + .RemoveRegion = spicRemoveRegion, + .FlipRegion = spicFlipRegion, +}; + +/* internal */ + +static void spic_calc_buffer( MatroxDriverData *mdrv, + MatroxSpicLayerData *mspic, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + unsigned int field_offset = lock->pitch; + + mspic->regs.c2SPICSTARTADD1 = lock->offset; + mspic->regs.c2SPICSTARTADD0 = lock->offset; + + if (surface->config.caps & DSCAPS_SEPARATED) + field_offset *= surface->config.size.h / 2; + + if (surface->config.caps & DSCAPS_INTERLACED) + mspic->regs.c2SPICSTARTADD0 += field_offset; +} + +static void spic_set_buffer( MatroxDriverData *mdrv, + MatroxSpicLayerData *mspic ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mga_out32( mmio, mspic->regs.c2SPICSTARTADD0, C2SPICSTARTADD0 ); + mga_out32( mmio, mspic->regs.c2SPICSTARTADD1, C2SPICSTARTADD1 ); +} diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_state.c b/Source/DirectFB/gfxdrivers/matrox/matrox_state.c new file mode 100755 index 0000000..ceeffa5 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_state.c @@ -0,0 +1,810 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "regs.h" +#include "mmio.h" +#include "matrox.h" + +#include "matrox_state.h" + +#define MGA_KEYMASK(format) ((1 << DFB_COLOR_BITS_PER_PIXEL(format)) - 1) + +static void matrox_calc_offsets( MatroxDeviceData *mdev, + CoreSurface *surface, + CoreSurfaceBufferLock *lock, + bool unit_pixel, + int offset[2][3] ) +{ + int bytes_per_pixel = DFB_BYTES_PER_PIXEL( surface->config.format ); + int pitch; + + if (unit_pixel) { + offset[0][0] = lock->offset / bytes_per_pixel; + pitch = lock->pitch / bytes_per_pixel; + } else { + offset[0][0] = mdev->fb.offset + lock->offset; + pitch = lock->pitch; + } + + switch (surface->config.format) { + case DSPF_NV12: + case DSPF_NV21: + offset[0][1] = offset[0][0] + surface->config.size.h * pitch; + offset[0][2] = 0; + break; + case DSPF_I420: + offset[0][1] = offset[0][0] + surface->config.size.h * pitch; + offset[0][2] = offset[0][1] + surface->config.size.h/2 * pitch/2; + break; + case DSPF_YV12: + offset[0][2] = offset[0][0] + surface->config.size.h * pitch; + offset[0][1] = offset[0][2] + surface->config.size.h/2 * pitch/2; + break; + default: + offset[0][1] = 0; + offset[0][2] = 0; + } + + D_ASSERT( offset[0][0] % 64 == 0 ); + D_ASSERT( offset[0][1] % 64 == 0 ); + D_ASSERT( offset[0][2] % 64 == 0 ); + + if (mdev->blit_fields || mdev->blit_deinterlace) { + if (surface->config.caps & DSCAPS_SEPARATED) { + offset[1][0] = offset[0][0] + surface->config.size.h/2 * pitch; + switch (surface->config.format) { + case DSPF_NV12: + case DSPF_NV21: + offset[1][1] = offset[0][1] + surface->config.size.h/4 * pitch; + offset[1][2] = 0; + break; + case DSPF_I420: + case DSPF_YV12: + offset[1][1] = offset[0][1] + surface->config.size.h/4 * pitch/2; + offset[1][2] = offset[0][2] + surface->config.size.h/4 * pitch/2; + break; + default: + offset[1][1] = 0; + offset[1][2] = 0; + } + } else { + offset[1][0] = offset[0][0] + pitch; + switch (surface->config.format) { + case DSPF_NV12: + case DSPF_NV21: + offset[1][1] = offset[0][1] + pitch; + offset[1][2] = 0; + break; + case DSPF_I420: + case DSPF_YV12: + offset[1][1] = offset[0][1] + pitch/2; + offset[1][2] = offset[0][2] + pitch/2; + break; + default: + offset[1][1] = 0; + offset[1][2] = 0; + } + } + + D_ASSERT( offset[1][0] % 64 == 0 ); + D_ASSERT( offset[1][1] % 64 == 0 ); + D_ASSERT( offset[1][2] % 64 == 0 ); + } +} + +void matrox_validate_destination( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *destination = state->destination; + CoreSurfaceBuffer *depth_buffer = NULL;//destination->depth_buffer; + int bytes_per_pixel = DFB_BYTES_PER_PIXEL( destination->config.format ); + + if (MGA_IS_VALID( m_destination )) + return; + + mdev->dst_pitch = state->dst.pitch / bytes_per_pixel; + + mdev->depth_buffer = depth_buffer != NULL; + + if (destination->config.format == DSPF_YUY2 || destination->config.format == DSPF_UYVY) + mdev->dst_pitch /= 2; + + if (mdev->blit_fields && !(destination->config.caps & DSCAPS_SEPARATED)) + mdev->dst_pitch *= 2; + + D_ASSERT( mdev->dst_pitch % 32 == 0 ); + + matrox_calc_offsets( mdev, destination, &state->dst, mdev->old_matrox, mdev->dst_offset ); + + mga_waitfifo( mdrv, mdev, depth_buffer ? 4 : 3 ); + + mga_out32( mmio, mdev->dst_offset[0][0], mdev->old_matrox ? YDSTORG : DSTORG ); + mga_out32( mmio, mdev->dst_pitch, PITCH ); + +#if 0 + if (depth_buffer) + mga_out32( mmio, depth_buffer->video.offset, ZORG ); +#endif + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_ALUT44: + case DSPF_LUT8: + case DSPF_RGB332: + mga_out32( mmio, PW8, MACCESS ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + mga_out32( mmio, PW16 | DIT555, MACCESS ); + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB16: + mga_out32( mmio, PW16, MACCESS ); + break; + case DSPF_RGB24: + mga_out32( mmio, PW24, MACCESS ); + break; + case DSPF_RGB32: + case DSPF_ARGB: + mga_out32( mmio, PW32, MACCESS ); + break; + case DSPF_I420: + case DSPF_YV12: + case DSPF_NV12: + case DSPF_NV21: + mga_out32( mmio, PW8 | BYPASS332 | NODITHER, MACCESS ); + break; + case DSPF_YUY2: + case DSPF_UYVY: + mga_out32( mmio, PW32 | NODITHER, MACCESS ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + MGA_VALIDATE( m_destination ); +} + +void matrox_set_clip( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRegion *clip ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + mga_waitfifo( mdrv, mdev, 3 ); + + if (mdev->old_matrox) { + mga_out32( mmio, (mdev->dst_offset[0][0] + + mdev->dst_pitch * clip->y1) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_offset[0][0] + + mdev->dst_pitch * clip->y2) & 0xFFFFFF, YBOT ); + } + else { + mga_out32( mmio, (mdev->dst_pitch * clip->y1) & 0xFFFFFF, YTOP ); + mga_out32( mmio, (mdev->dst_pitch * clip->y2) & 0xFFFFFF, YBOT ); + } + + mga_out32( mmio, ((clip->x2 & 0x0FFF) << 16) | (clip->x1 & 0x0FFF), CXBNDRY ); +} + +void matrox_validate_drawColor( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + DFBColor color = state->color; + volatile u8 *mmio = mdrv->mmio_base; + + if (MGA_IS_VALID( m_drawColor )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } + + mga_waitfifo( mdrv, mdev, 4 ); + + mga_out32( mmio, U8_TO_F0915(color.a), ALPHASTART ); + mga_out32( mmio, U8_TO_F0915(color.r), DR4 ); + mga_out32( mmio, U8_TO_F0915(color.g), DR8 ); + mga_out32( mmio, U8_TO_F0915(color.b), DR12 ); + + MGA_VALIDATE( m_drawColor ); + MGA_INVALIDATE( m_blitColor ); + MGA_INVALIDATE( m_blitBlend ); +} + +void matrox_validate_blitColor( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + DFBColor color = state->color; + volatile u8 *mmio = mdrv->mmio_base; + + if (MGA_IS_VALID( m_blitColor )) + return; + + if (state->blittingflags & DSBLIT_COLORIZE) { + if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } + } + else { + if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) + color.r = color.g = color.b = color.a; + else + color.r = color.g = color.b = 0xff; + } + + mga_waitfifo( mdrv, mdev, 4 ); + + mga_out32( mmio, U8_TO_F0915(color.a), ALPHASTART ); + mga_out32( mmio, U8_TO_F0915(color.r), DR4 ); + mga_out32( mmio, U8_TO_F0915(color.g), DR8 ); + mga_out32( mmio, U8_TO_F0915(color.b), DR12 ); + + MGA_VALIDATE( m_blitColor ); + MGA_INVALIDATE( m_drawColor ); + MGA_INVALIDATE( m_blitBlend ); +} + +void matrox_validate_color( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + DFBColor color = state->color; + volatile u8 *mmio = mdrv->mmio_base; + + u32 fcol; + u8 cb, cr; + + if (MGA_IS_VALID( m_color )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = (color.r * (color.a + 1)) >> 8; + color.g = (color.g * (color.a + 1)) >> 8; + color.b = (color.b * (color.a + 1)) >> 8; + } + + switch (state->destination->config.format) { + case DSPF_ALUT44: + fcol = (color.a & 0xF0) | state->color_index; + fcol |= fcol << 8; + fcol |= fcol << 16; + break; + case DSPF_LUT8: + fcol = state->color_index; + fcol |= fcol << 8; + fcol |= fcol << 16; + break; + case DSPF_RGB332: + fcol = PIXEL_RGB332( color.r, + color.g, + color.b ); + fcol |= fcol << 8; + fcol |= fcol << 16; + break; + case DSPF_RGB444: + fcol = PIXEL_RGB444( color.r, + color.g, + color.b ); + fcol |= fcol << 16; + break; + case DSPF_ARGB4444: + fcol = PIXEL_ARGB4444( color.a, + color.r, + color.g, + color.b ); + fcol |= fcol << 16; + break; + case DSPF_RGB555: + fcol = PIXEL_RGB555( color.r, + color.g, + color.b ); + fcol |= fcol << 16; + break; + case DSPF_ARGB1555: + fcol = PIXEL_ARGB1555( color.a, + color.r, + color.g, + color.b ); + fcol |= fcol << 16; + break; + case DSPF_RGB16: + fcol = PIXEL_RGB16( color.r, + color.g, + color.b ); + fcol |= fcol << 16; + break; + case DSPF_RGB24: + fcol = PIXEL_RGB32( color.r, + color.g, + color.b ); + fcol |= fcol << 24; + break; + case DSPF_RGB32: + fcol = PIXEL_RGB32( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB: + fcol = PIXEL_ARGB( color.a, + color.r, + color.g, + color.b ); + break; + case DSPF_A8: + fcol = color.a; + fcol |= fcol << 8; + fcol |= fcol << 16; + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, + color.g, + color.b, + fcol, cb, cr ); + fcol |= fcol << 8; + fcol |= fcol << 16; + mdev->color[0] = fcol; + mdev->color[1] = (cb << 24) | (cb << 16) | (cb << 8) | cb; + mdev->color[2] = (cr << 24) | (cr << 16) | (cr << 8) | cr; + break; + case DSPF_NV12: + RGB_TO_YCBCR( color.r, + color.g, + color.b, + fcol, cb, cr ); + fcol |= fcol << 8; + fcol |= fcol << 16; + mdev->color[0] = fcol; + mdev->color[1] = (cr << 24) | (cb << 16) | (cr << 8) | cb; + break; + case DSPF_NV21: + RGB_TO_YCBCR( color.r, + color.g, + color.b, + fcol, cb, cr ); + fcol |= fcol << 8; + fcol |= fcol << 16; + mdev->color[0] = fcol; + mdev->color[1] = (cb << 24) | (cr << 16) | (cb << 8) | cr; + break; + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, + color.g, + color.b, + fcol, cb, cr ); + fcol = PIXEL_YUY2( fcol, cb, cr ); + break; + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, + color.g, + color.b, + fcol, cb, cr ); + fcol = PIXEL_UYVY( fcol, cb, cr ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + return; + } + + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, fcol, FCOL ); + + MGA_VALIDATE( m_color ); + MGA_INVALIDATE( m_srckey ); +} + +static u32 matroxSourceBlend[] = { + SRC_ZERO, /* DSBF_ZERO */ + SRC_ONE, /* DSBF_ONE */ + 0, /* DSBF_SRCCOLOR */ + 0, /* DSBF_INVSRCCOLOR */ + SRC_ALPHA, /* DSBF_SRCALPHA */ + SRC_ONE_MINUS_SRC_ALPHA, /* DSBF_INVSRCALPHA */ + SRC_DST_ALPHA, /* DSBF_DESTALPHA */ + SRC_ONE_MINUS_DST_ALPHA, /* DSBF_INVDESTALPHA */ + SRC_DST_COLOR, /* DSBF_DESTCOLOR */ + SRC_ONE_MINUS_DST_COLOR, /* DSBF_INVDESTCOLOR */ + SRC_SRC_ALPHA_SATURATE /* DSBF_SRCALPHASAT */ +}; + +static u32 matroxDestBlend[] = { + DST_ZERO, /* DSBF_ZERO */ + DST_ONE, /* DSBF_ONE */ + DST_SRC_COLOR, /* DSBF_SRCCOLOR */ + DST_ONE_MINUS_SRC_COLOR, /* DSBF_INVSRCCOLOR */ + DST_SRC_ALPHA, /* DSBF_SRCALPHA */ + DST_ONE_MINUS_SRC_ALPHA, /* DSBF_INVSRCALPHA */ + DST_DST_ALPHA, /* DSBF_DESTALPHA */ + DST_ONE_MINUS_DST_ALPHA, /* DSBF_INVDESTALPHA */ + 0, /* DSBF_DESTCOLOR */ + 0, /* DSBF_INVDESTCOLOR */ + 0 /* DSBF_SRCALPHASAT */ +}; + +void matrox_validate_drawBlend( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 alphactrl; + + if (MGA_IS_VALID( m_drawBlend )) + return; + + alphactrl = matroxSourceBlend[state->src_blend - 1] | + matroxDestBlend [state->dst_blend - 1] | + ALPHACHANNEL | DIFFUSEDALPHA; + + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, alphactrl, ALPHACTRL ); + + MGA_VALIDATE( m_drawBlend ); + MGA_INVALIDATE( m_blitBlend ); +} + +static u32 matroxAlphaSelect[] = { + 0, + 0, + DIFFUSEDALPHA, + MODULATEDALPHA +}; + +void matrox_validate_blitBlend( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + + u32 alphactrl; + + if (MGA_IS_VALID( m_blitBlend )) + return; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_BLEND_COLORALPHA)) + { + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + /* src_blend == ONE and dst_blend == INVSRCALPHA/INVSRCCOLOR */ + alphactrl = matroxSourceBlend[DSBF_SRCALPHA - 1] | + matroxDestBlend [state->dst_blend - 1] | + VIDEOALPHA; + else + alphactrl = matroxSourceBlend[state->src_blend - 1] | + matroxDestBlend [state->dst_blend - 1] | + ALPHACHANNEL; + + if (state->source->config.format == DSPF_RGB32) { + alphactrl |= DIFFUSEDALPHA; + + if (! (state->blittingflags & DSBLIT_BLEND_COLORALPHA)) { + mga_out32( mmio, U8_TO_F0915(0xff), ALPHASTART ); + MGA_INVALIDATE( m_drawColor | m_blitColor ); + } + } + else + alphactrl |= matroxAlphaSelect [state->blittingflags & 3]; + } + else { + alphactrl = SRC_ONE | DST_ZERO | ALPHACHANNEL; + + if (state->source->config.format == DSPF_RGB32) { + alphactrl |= DIFFUSEDALPHA; + + mga_out32( mmio, U8_TO_F0915(0xff), ALPHASTART ); + MGA_INVALIDATE( m_drawColor | m_blitColor ); + } + } + + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, alphactrl, ALPHACTRL ); + + MGA_VALIDATE( m_blitBlend ); + MGA_INVALIDATE( m_drawBlend ); +} + +static void matrox_tlutload( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CorePalette *palette ) +{ + volatile u8 *mmio = mdrv->mmio_base; + volatile u16 *dst = dfb_gfxcard_memory_virtual( NULL, mdev->tlut_offset ); + unsigned int i; + + for (i = 0; i < palette->num_entries; i++) + *dst++ = PIXEL_RGB16( palette->entries[i].r, + palette->entries[i].g, + palette->entries[i].b ); + + mga_waitfifo( mdrv, mdev, mdev->old_matrox ? 8 : 9 ); + mga_out32( mmio, BLTMOD_BU32RGB | BOP_COPY | SHFTZERO | + SGNZERO | LINEAR | ATYPE_RSTR | OP_BITBLT, DWGCTL ); + mga_out32( mmio, 1024, PITCH ); + if (mdev->old_matrox) { + mga_out32( mmio, mdev->tlut_offset / 2, AR3 ); + mga_out32( mmio, palette->num_entries, AR0 ); + mga_out32( mmio, 0, YDSTORG ); + } + else { + mga_out32( mmio, 0, AR3 ); + mga_out32( mmio, palette->num_entries, AR0 ); + mga_out32( mmio, mdev->fb.offset + mdev->tlut_offset, SRCORG ); + mga_out32( mmio, 0, DSTORG ); + + MGA_INVALIDATE( m_source ); + } + mga_out32( mmio, 0, FXBNDRY ); + mga_out32( mmio, PW16 | TLUTLOAD, MACCESS ); + mga_out32( mmio, palette->num_entries, YDSTLEN | EXECUTE ); + + MGA_INVALIDATE( m_destination ); +} + +void matrox_validate_Source( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *surface = state->source; + int bytes_per_pixel = DFB_BYTES_PER_PIXEL(surface->config.format); + u32 texctl = 0, texctl2 = 0; + + if (MGA_IS_VALID( m_Source )) + return; + + mdev->src_pitch = state->src.pitch / bytes_per_pixel; + mdev->field = surface->field; + mdev->w = surface->config.size.w; + mdev->h = surface->config.size.h; + + if (state->destination->config.format == DSPF_YUY2 || state->destination->config.format == DSPF_UYVY) { + mdev->w /= 2; + mdev->src_pitch /= 2; + } + + if (mdev->blit_deinterlace || mdev->blit_fields) { + mdev->h /= 2; + if (!(surface->config.caps & DSCAPS_SEPARATED)) + mdev->src_pitch *= 2; + } + + D_ASSERT( mdev->src_pitch % 32 == 0 ); + + matrox_calc_offsets( mdev, surface, &state->src, false, mdev->src_offset ); + + if (mdev->blit_deinterlace && mdev->field) { + mdev->src_offset[0][0] = mdev->src_offset[1][0]; + mdev->src_offset[0][1] = mdev->src_offset[1][1]; + mdev->src_offset[0][2] = mdev->src_offset[1][2]; + } + + mdev->w2 = mga_log2( mdev->w ); + mdev->h2 = mga_log2( mdev->h ); + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + texctl = TAMASK; + else + texctl = TAKEY; + + switch (surface->config.format) { + case DSPF_YUY2: + texctl |= (state->destination->config.format == DSPF_YUY2) ? TW32 : TW422; + break; + case DSPF_UYVY: + texctl |= (state->destination->config.format == DSPF_UYVY) ? TW32 : TW422UYVY; + break; + case DSPF_I420: + case DSPF_YV12: + case DSPF_NV12: + case DSPF_NV21: + case DSPF_A8: + texctl |= TW8A; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + texctl |= TW12; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + texctl |= TW15; + break; + case DSPF_RGB16: + texctl |= TW16; + break; + case DSPF_RGB32: + case DSPF_ARGB: + texctl |= TW32; + break; + case DSPF_LUT8: + matrox_tlutload( mdrv, mdev, surface->palette ); + texctl |= TW8; + break; + case DSPF_RGB332: + matrox_tlutload( mdrv, mdev, mdev->rgb332_palette ); + texctl |= TW8; + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + texctl |= ((mdev->src_pitch << 9) & TPITCHEXT) | TPITCHLIN; + + if (1 << mdev->w2 != mdev->w || 1 << mdev->h2 != mdev->h) + texctl |= CLAMPUV; + + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + texctl |= TMODULATE; + else + texctl2 |= DECALDIS; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + texctl |= DECALCKEY | STRANS; + else + texctl2 |= CKSTRANSDIS; + + if (surface->config.format == DSPF_A8) + texctl2 |= IDECAL | DECALDIS; + + mdev->texctl = texctl; + + mga_waitfifo( mdrv, mdev, 5 ); + mga_out32( mmio, texctl, TEXCTL ); + mga_out32( mmio, texctl2, TEXCTL2 ); + + mga_out32( mmio, ( (((u32)(mdev->w - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->w2) & 0x3f) << 9) | + (((u32)(mdev->w2 + 4) & 0x3f) ) ), TEXWIDTH ); + + mga_out32( mmio, ( (((u32)(mdev->h - 1) & 0x7ff) << 18) | + (((u32)(4 - mdev->h2) & 0x3f) << 9) | + (((u32)(mdev->h2 + 4) & 0x3f) ) ), TEXHEIGHT ); + + mga_out32( mmio, mdev->src_offset[0][0], TEXORG ); + + MGA_VALIDATE( m_Source ); +} + +void matrox_validate_source( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *surface = state->source; + int bytes_per_pixel = DFB_BYTES_PER_PIXEL(surface->config.format); + + if (MGA_IS_VALID( m_source )) + return; + + mdev->src_pitch = state->src.pitch / bytes_per_pixel; + + if (state->destination->config.format == DSPF_YUY2 || state->destination->config.format == DSPF_UYVY) + mdev->src_pitch /= 2; + + if (mdev->blit_fields && !(surface->config.caps & DSCAPS_SEPARATED)) + mdev->src_pitch *= 2; + + D_ASSERT( mdev->src_pitch % 32 == 0 ); + + matrox_calc_offsets( mdev, surface, &state->src, mdev->old_matrox, mdev->src_offset ); + + if (!mdev->old_matrox) { + mga_waitfifo( mdrv, mdev, 1 ); + mga_out32( mmio, mdev->src_offset[0][0], SRCORG ); + } + + MGA_VALIDATE( m_source ); +} + +void matrox_validate_SrcKey( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *surface = state->source; + u32 key; + u32 mask; + + if (MGA_IS_VALID( m_SrcKey )) + return; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + mask = MGA_KEYMASK(surface->config.format); + key = state->src_colorkey & mask; + } else { + mask = 0; + key = 0xFFFF; + } + + mga_waitfifo( mdrv, mdev, 2); + + mga_out32( mmio, ((mask & 0xFFFF) << 16) | (key & 0xFFFF), TEXTRANS ); + mga_out32( mmio, (mask & 0xFFFF0000) | (key >> 16), TEXTRANSHIGH ); + + MGA_VALIDATE( m_SrcKey ); +} + +void matrox_validate_srckey( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ) +{ + volatile u8 *mmio = mdrv->mmio_base; + CoreSurface *surface = state->source; + u32 key; + u32 mask; + + if (MGA_IS_VALID( m_srckey )) + return; + + mask = MGA_KEYMASK(surface->config.format); + key = state->src_colorkey & mask; + + switch (DFB_BYTES_PER_PIXEL(state->source->config.format)) { + case 1: + mask |= mask << 8; + key |= key << 8; + case 2: + mask |= mask << 16; + key |= key << 16; + } + + mga_waitfifo( mdrv, mdev, 2); + mga_out32( mmio, mask, BCOL ); + mga_out32( mmio, key, FCOL ); + + MGA_VALIDATE( m_srckey ); + MGA_INVALIDATE( m_color ); +} + diff --git a/Source/DirectFB/gfxdrivers/matrox/matrox_state.h b/Source/DirectFB/gfxdrivers/matrox/matrox_state.h new file mode 100755 index 0000000..160efe0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/matrox_state.h @@ -0,0 +1,70 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef ___MATROX_STATE_H__ +#define ___MATROX_STATE_H__ + +void matrox_validate_destination( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_set_clip( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + DFBRegion *clip ); + +void matrox_validate_drawColor( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_validate_blitColor( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_validate_color( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); + +void matrox_validate_drawBlend( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_validate_blitBlend( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); + +void matrox_validate_Source( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_validate_source( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); + +void matrox_validate_SrcKey( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); +void matrox_validate_srckey( MatroxDriverData *mdrv, + MatroxDeviceData *mdev, + CardState *state ); + +#endif diff --git a/Source/DirectFB/gfxdrivers/matrox/mmio.h b/Source/DirectFB/gfxdrivers/matrox/mmio.h new file mode 100755 index 0000000..d897db6 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/mmio.h @@ -0,0 +1,118 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __MATROX_MMIO_H__ +#define __MATROX_MMIO_H__ + +#include + +#include "matrox.h" + +static inline void +mga_out8(volatile u8 *mmioaddr, u8 value, u32 reg) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static inline void +mga_out32(volatile u8 *mmioaddr, u32 value, u32 reg) +{ +#ifdef __powerpc__ + asm volatile("stwbrx %0,%1,%2;eieio" : : "r"(value), "b"(reg), "r"(mmioaddr) : "memory"); +#else + *((volatile u32*)(mmioaddr+reg)) = value; +#endif +} + +static inline u8 +mga_in8(volatile u8 *mmioaddr, u32 reg) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static inline u32 +mga_in32(volatile u8 *mmioaddr, u32 reg) +{ +#ifdef __powerpc__ + u32 value; + + asm volatile("lwbrx %0,%1,%2;eieio" : "=r"(value) : "b"(reg), "r"(mmioaddr)); + + return value; +#else + return *((volatile u32*)(mmioaddr+reg)); +#endif +} + +/* Wait for idle accelerator and DMA */ +static inline void +mga_waitidle(MatroxDriverData *mdrv, MatroxDeviceData *mdev) +{ + while ((mga_in32(mdrv->mmio_base, STATUS) & (DWGENGSTS | ENDPRDMASTS)) != mdev->idle_status) { + mdev->idle_waitcycles++; + } +} + +/* Wait for fifo space */ +static inline void +mga_waitfifo(MatroxDriverData *mdrv, MatroxDeviceData *mdev, unsigned int space) +{ + mdev->waitfifo_sum += space; + mdev->waitfifo_calls++; + + if (mdev->fifo_space < space) { + do { /* not needed on a G400, + hardware does retries on writing if FIFO is full, + but results in DMA problems */ + mdev->fifo_space = mga_in32(mdrv->mmio_base, FIFOSTATUS) & 0xff; + mdev->fifo_waitcycles++; + } while (mdev->fifo_space < space); + } + else { + mdev->fifo_cache_hits++; + } + + mdev->fifo_space -= space; +} + +static inline void +mga_out_dac( volatile u8 *mmioaddr, u8 reg, u8 val ) +{ + mga_out8( mmioaddr, reg, DAC_INDEX ); + mga_out8( mmioaddr, val, DAC_DATA ); +} + +static inline u8 +mga_in_dac( volatile u8 *mmioaddr, u8 reg ) +{ + mga_out8( mmioaddr, reg, DAC_INDEX ); + return mga_in8( mmioaddr, DAC_DATA ); +} + +#endif + diff --git a/Source/DirectFB/gfxdrivers/matrox/regs.h b/Source/DirectFB/gfxdrivers/matrox/regs.h new file mode 100755 index 0000000..a419b83 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/matrox/regs.h @@ -0,0 +1,454 @@ +#ifndef __MATROX__REGS_H__ +#define __MATROX__REGS_H__ + +#define U8_TO_F0915(x) (((u32) ((x+1) << 15)) & 0x00FFFFFF) + +#define RS16(val) ( (u16)((s16)(val))) +#define RS18(val) (((u32)((s32)(val)))&0x003ffff) +#define RS24(val) (((u32)((s32)(val)))&0x0ffffff) +#define RS27(val) (((u32)((s32)(val)))&0x7ffffff) + +#define DWGSYNC 0x2C4C +#define SYNC_DMA_BUSY 0x8325340 /* just a random number */ + +#define RST 0x1E40 +#define OPMODE 0x1E54 + +#define CACHEFLUSH 0x1FFF + +/* CRTC2 registers */ +#define C2CTL 0x3C10 +# define C2EN 0x00000001 +# define C2PIXCLKSEL_PCICLK 0x00000000 +# define C2PIXCLKSEL_VDOCLK 0x00000002 +# define C2PIXCLKSEL_PIXPLL 0x00000004 +# define C2PIXCLKSEL_VIDPLL 0x00000006 /* SYSPLL on G400 */ +# define C2PIXCLKSEL_VDCLK 0x00004000 /* G450/G550 only */ +# define C2PIXCLKSEL_CRISTAL 0x00004002 /* G450/G550 only */ +# define C2PIXCLKSEL_SYSPLL 0x00004004 /* G450/G550 only */ +# define C2PIXCLKDIS 0x00000008 +# define CRTCDACSEL 0x00100000 +# define C2DEPTH_15BPP 0x00200000 +# define C2DEPTH_16BPP 0x00400000 +# define C2DEPTH_32BPP 0x00800000 +# define C2DEPTH_YCBCR422 0x00A00000 +# define C2DEPTH_YCBCR420 0x00E00000 +# define C2VCBCRSINGLE 0x01000000 +# define C2INTERLACE 0x02000000 +# define C2FIELDLENGTH 0x04000000 +# define C2FIELDPOL 0x08000000 +# define C2VIDRSTMOD_FALLING 0x00000000 +# define C2VIDRSTMOD_RISING 0x10000000 +# define C2VIDRSTMOD_BOTH 0x20000000 +# define C2HPLOADEN 0x40000000 +# define C2VPLOADEN 0x80000000 +#define C2HPARAM 0x3C14 +#define C2HSYNC 0x3C18 +#define C2VPARAM 0x3C1C +#define C2VSYNC 0x3C20 +#define C2PRELOAD 0x3C24 +#define C2STARTADD0 0x3C28 +#define C2STARTADD1 0x3C2C +#define C2PL2STARTADD0 0x3C30 +#define C2PL2STARTADD1 0x3C34 +#define C2PL3STARTADD0 0x3C38 +#define C2PL3STARTADD1 0x3C3C +#define C2OFFSET 0x3C40 +#define C2MISC 0x3C44 +# define C2HSYNCPOL 0x00000100 +# define C2VSYNCPOL 0x00000200 +#define C2VCOUNT 0x3C48 +# define C2FIELD 0x01000000 +#define C2DATACTL 0x3C4C +# define C2DITHEN 0x00000001 +# define C2YFILTEN 0x00000002 +# define C2CBCRFILTEN 0x00000004 +# define C2SUBPICEN 0x00000008 +# define C2NTSCEN 0x00000010 +# define C2STATICKEYEN 0x00000020 +# define C2OFFSETDIVEN 0x00000040 +# define C2UYVYFMT 0x00000080 +# define C2STATICKEY 0x1F000000 +#define C2SUBPICLUT 0x3C50 +#define C2SPICSTARTADD0 0x3C54 +#define C2SPICSTARTADD1 0x3C58 + +/* Backend scaler registers */ +#define BESA1ORG 0x3D00 +#define BESA2ORG 0x3D04 +#define BESB1ORG 0x3D08 +#define BESB2ORG 0x3D0C +#define BESA1CORG 0x3D10 +#define BESA2CORG 0x3D14 +#define BESB1CORG 0x3D18 +#define BESB2CORG 0x3D1C +#define BESA1C3ORG 0x3D60 +#define BESA2C3ORG 0x3D64 +#define BESB1C3ORG 0x3D68 +#define BESB2C3ORG 0x3D6C + +#define BESCTL 0x3D20 +# define BESEN 0x00000001 +# define BESV1SRCSTP 0x00000040 +# define BESV2SRCSTP 0x00000080 +# define BESHFEN 0x00000400 +# define BESVFEN 0x00000800 +# define BESCUPS 0x00010000 +# define BES420PL 0x00020000 + +#define BESGLOBCTL 0x3DC0 +# define BESCORDER 0x00000008 +# define BES3PLANE 0x00000020 +# define BESUYVYFMT 0x00000040 +# define BESPROCAMP 0x00000080 +# define BESRGB15 0x00000100 +# define BESRGB16 0x00000200 +# define BESRGB32 0x00000300 + +#define BESHCOORD 0x3D28 +#define BESHISCAL 0x3D30 +#define BESHSRCEND 0x3D3C +#define BESHSRCLST 0x3D50 +#define BESHSRCST 0x3D38 +#define BESLUMACTL 0x3D40 +#define BESPITCH 0x3D24 +#define BESSTATUS 0x3DC4 +#define BESV1SRCLST 0x3D54 +#define BESV2SRCLST 0x3D58 +#define BESV1WGHT 0x3D48 +#define BESV2WGHT 0x3D4C +#define BESVCOORD 0x3D2C +#define BESVISCAL 0x3D34 + +/* DAC Registers */ +#define DAC_INDEX 0x3C00 +#define DAC_DATA 0x3C0A + +#define MGAREG_VCOUNT 0x1e20 + +/* Alpha registers */ + +#define ALPHASTART 0x2C70 +#define ALPHAXINC 0x2C74 +#define ALPHAYINC 0x2C78 + +#define ALPHACTRL 0x2C7C +#define SRC_ZERO 0x00000000 +#define SRC_ONE 0x00000001 +#define SRC_DST_COLOR 0x00000002 +#define SRC_ONE_MINUS_DST_COLOR 0x00000003 +#define SRC_ALPHA 0x00000004 +#define SRC_ONE_MINUS_SRC_ALPHA 0x00000005 +#define SRC_DST_ALPHA 0x00000006 +#define SRC_ONE_MINUS_DST_ALPHA 0x00000007 +#define SRC_SRC_ALPHA_SATURATE 0x00000008 + +#define DST_ZERO 0x00000000 +#define DST_ONE 0x00000010 +#define DST_SRC_COLOR 0x00000020 +#define DST_ONE_MINUS_SRC_COLOR 0x00000030 +#define DST_SRC_ALPHA 0x00000040 +#define DST_ONE_MINUS_SRC_ALPHA 0x00000050 +#define DST_DST_ALPHA 0x00000060 +#define DST_ONE_MINUS_DST_ALPHA 0x00000070 + +#define ALPHACHANNEL 0x00000100 +#define VIDEOALPHA 0x00000200 + +#define DIFFUSEDALPHA 0x01000000 +#define MODULATEDALPHA 0x02000000 + +/* Texture registers */ + +#define TEXCTL 0x2C30 +#define TEXCTL2 0x2C3C +#define TEXFILTER 0x2C58 +#define TEXWIDTH 0x2C28 +#define TEXHEIGHT 0x2C2C +#define TEXORG 0x2C24 +#define TEXORG1 0x2CA4 +#define TEXORG2 0x2CA8 +#define TEXORG3 0x2CAC +#define TEXORG4 0x2CB0 +#define TEXTRANS 0x2C34 +#define TEXTRANSHIGH 0x2C38 +#define TDUALSTAGE0 0x2CF8 +#define TDUALSTAGE1 0x2CFC + +#define TMR0 0x2C00 +#define TMR1 0x2C04 +#define TMR2 0x2C08 +#define TMR3 0x2C0C +#define TMR4 0x2C10 +#define TMR5 0x2C14 +#define TMR6 0x2C18 +#define TMR7 0x2C1C +#define TMR8 0x2C20 + +#define CUR_XWINDOWS 0x03 + +/* TEXCTL */ +#define TW4 0x00000000 +#define TW8 0x00000001 +#define TW15 0x00000002 +#define TW16 0x00000003 +#define TW12 0x00000004 + +#define TW32 0x00000006 +#define TW8A 0x00000007 +#define TW8AL 0x00000008 +#define TW422 0x0000000A +#define TW422UYVY 0x0000000B + +#define TFORMAT 0x0000000F +#define TPITCHLIN 0x00000100 +#define TPITCHEXT 0x000FFE00 + +#define NOPERSPECTIVE 0x00200000 +#define TAKEY 0x02000000 +#define TAMASK 0x04000000 +#define CLAMPUV 0x18000000 + +#define DECALCKEY 0x01000000 +#define TMODULATE 0x20000000 +#define STRANS 0x40000000 + + +/* TEXTCTL2 */ +#define IDECAL 0x00000002 +#define DECALDIS 0x00000004 +#define CKSTRANSDIS 0x00000010 + + +/* TEXFILTER */ +#define MIN_NRST 0x00000000 +#define MIN_BILIN 0x00000002 +#define MIN_ANISO 0x0000000D +#define MAG_NRST 0x00000000 +#define MAG_BILIN 0x00000020 +#define FILTER_ALPHA 0x00100000 + +/* SGN */ +#define SGN_BRKLEFT 0x00000100 + +#define DSTORG 0x2cb8 +#define SRCORG 0x2cb4 + +#define MACCESS 0x1C04 +# define PW8 0x00000000 +# define PW16 0x00000001 +# define PW32 0x00000002 +# define PW24 0x00000003 +# define ZW16 0x00000000 +# define ZW32 0x00000008 +# define ZW15 0x00000010 +# define ZW24 0x00000018 +# define BYPASS332 0x10000000 +# define TLUTLOAD 0x20000000 +# define NODITHER 0x40000000 +# define DIT555 0x80000000 + + +#define EXECUTE 0x100 /* or with register to execute a programmed + accel command */ + +#define DWGCTL 0x1C00 /* Drawing control */ + /* opcod - Operation code */ +# define OP_LINE_OPEN 0x00 +# define OP_AUTOLINE_OPEN 0x01 +# define OP_LINE_CLOSE 0x02 +# define OP_AUTOLINE_CLOSE 0x03 +# define OP_TRAP 0x04 +# define OP_TRAP_ILOAD 0x05 +# define OP_TEXTURE_TRAP 0x06 +# define OP_ILOAD_HIQH 0x07 +# define OP_BITBLT 0x08 +# define OP_ILOAD 0x09 +# define OP_IDUMP 0x0A +# define OP_FBITBLT 0x0C +# define OP_ILOAD_SCALE 0x0D +# define OP_ILOAD_HIQHV 0x0E +# define OP_ILOAD_FILTER 0x0F + + /* atype - Access type */ +# define ATYPE_RPL 0x00 +# define ATYPE_RSTR 0x10 +# define ATYPE_ZI 0x30 +# define ATYPE_BLK 0x40 +# define ATYPE_I 0x70 + + /* Flag */ +# define LINEAR 0x80 +# define NOCLIP (1<<31) +# define TRANSC (1<<30) + + /* zmode - Z drawing mode */ +# define ZMODE_NOZCMP 0x000 +# define ZMODE_ZE 0x200 +# define ZMODE_ZNE 0x300 +# define ZMODE_ZLT 0x400 +# define ZMODE_ZLTE 0x500 +# define ZMODE_ZGT 0x600 +# define ZMODE_ZGTE 0x700 + + /* Flags */ +# define SOLID 0x0800 +# define ARZERO 0x1000 +# define SGNZERO 0x2000 +# define SHFTZERO 0x4000 + + /* bop - Boolean operation */ +# define BOP_CLEAR 0x00000 +# define BOP_NOR 0x10000 +# define BOP_COPYINV 0x30000 +# define BOP_INVERT 0x50000 +# define BOP_XOR 0x60000 +# define BOP_NAND 0x70000 +# define BOP_AND 0x80000 +# define BOP_EQUIV 0x90000 +# define BOP_NOOP 0xA0000 +# define BOP_IMP 0xB0000 +# define BOP_COPY 0xC0000 +# define BOP_OR 0xE0000 +# define BOP_SET 0xF0000 + + /* bltmod - Blit mode selection */ +# define BLTMOD_BMONOLEF 0x00000000 +# define BLTMOD_BMONOWF 0x08000000 +# define BLTMOD_BPLAN 0x02000000 +# define BLTMOD_BFCOL 0x04000000 +# define BLTMOD_BUYUV 0x1C000000 +# define BLTMOD_BU32BGR 0x06000000 +# define BLTMOD_BU32RGB 0x0E000000 +# define BLTMOD_BU24BGR 0x16000000 +# define BLTMOD_BU24RGB 0x1E000000 + +#define ZORG 0x1C0C +#define PAT0 0x1C10 +#define PAT1 0x1C14 +#define PLNWT 0x1C1C +#define BCOL 0x1C20 +#define FCOL 0x1C24 +#define SRC0 0x1C30 +#define SRC1 0x1C34 +#define SRC2 0x1C38 +#define SRC3 0x1C3C +#define XYSTRT 0x1C40 +#define XYEND 0x1C44 +#define SHIFT 0x1C50 +#define DMAPAD 0x1C54 +#define SGN 0x1C58 +#define LEN 0x1C5C +#define AR0 0x1C60 +#define AR1 0x1C64 +#define AR2 0x1C68 +#define AR3 0x1C6C +#define AR4 0x1C70 +#define AR5 0x1C74 +#define AR6 0x1C78 +#define CXBNDRY 0x1C80 +#define FXBNDRY 0x1C84 +#define YDSTLEN 0x1C88 +#define PITCH 0x1C8C +#define YDST 0x1C90 +#define YDSTORG 0x1C94 +#define YTOP 0x1C98 +#define YBOT 0x1C9C +#define CXLEFT 0x1CA0 +#define CXRIGHT 0x1CA4 +#define FXLEFT 0x1CA8 +#define FXRIGHT 0x1CAC +#define XDST 0x1CB0 +#define DR0 0x1CC0 +#define DR2 0x1CC8 +#define DR3 0x1CCC +#define DR4 0x1CD0 +#define DR6 0x1CD8 +#define DR7 0x1CDC +#define DR8 0x1CE0 +#define WO 0x1CE4 +#define DR10 0x1CE8 +#define DR11 0x1CEC +#define DR12 0x1CF0 +#define DR14 0x1CF8 +#define DR15 0x1CFC + +#define FIFOSTATUS 0x1E10 + +#define STATUS 0x1E14 +# define DWGENGSTS 0x10000 +# define ENDPRDMASTS 0x20000 + +#define IEN 0x1E1C + +#define BLIT_LEFT 1 +#define BLIT_UP 4 + + +#define SDXL 0x0002 +#define SDXR 0x0020 + + +/* DAC registers */ + +#define XMISCCTRL 0x1E +# define DACPDN 0x01 +# define MFCSEL_MAFC 0x02 +# define MFCSEL_PANELLINK 0x04 +# define MFCSEL_DIS 0x06 +# define MFCSEL_MASK 0x06 +# define VGA8DAC 0x08 +# define RAMCS 0x10 +# define VDOUTSEL_MAFC12 0x00 +# define VDOUTSEL_BYPASS656 0x40 +# define VDOUTSEL_CRTC2RGB 0x80 +# define VDOUTSEL_CRTC2656 0xC0 +# define VDOUTSEL_MASK 0xE0 + +#define XGENIOCTRL 0x2A +#define XGENIODATA 0x2B + +#define XKEYOPMODE 0x51 + +#define XCOLMSK0RED 0x52 +#define XCOLMSK0GREEN 0x53 +#define XCOLMSK0BLUE 0x54 + +#define XCOLKEY0RED 0x55 +#define XCOLKEY0GREEN 0x56 +#define XCOLKEY0BLUE 0x57 + +#define XDISPCTRL 0x8A +# define DAC1OUTSEL_DIS 0x00 +# define DAC1OUTSEL_EN 0x01 +# define DAC1OUTSEL_MASK 0x01 +# define DAC2OUTSEL_DIS 0x00 +# define DAC2OUTSEL_CRTC1 0x04 +# define DAC2OUTSEL_CRTC2 0x08 +# define DAC2OUTSEL_TVE 0x0C +# define DAC2OUTSEL_MASK 0x0C +# define PANOUTSEL_DIS 0x00 +# define PANOUTSEL_CRTC1 0x20 +# define PANOUTSEL_CRTC2RGB 0x40 +# define PANOUTSEL_CRTC2656 0x60 +# define PANOUTSEL_MASK 0x60 + +#define XSYNCCTRL 0x8B +# define DAC1HSOFF 0x01 +# define DAC1VSOFF 0x02 +# define DAC1HSPOL 0x04 +# define DAC1VSPOL 0x08 +# define DAC2HSOFF 0x10 +# define DAC2VSOFF 0x20 +# define DAC2HSPOL 0x40 +# define DAC2VSPOL 0x80 + +#define XPWRCTRL 0xA0 +# define DAC2PDN 0x01 +# define VIDPLLPDN 0x02 +# define PANPDN 0x04 +# define RFIFOPDN 0x08 +# define CFIFOPDN 0x10 + +#endif + diff --git a/Source/DirectFB/gfxdrivers/neomagic/Makefile.am b/Source/DirectFB/gfxdrivers/neomagic/Makefile.am new file mode 100755 index 0000000..24a850f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/Makefile.am @@ -0,0 +1,35 @@ +## Makefile.am for DirectFB/gfxdrivers/neomagic + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src + +neomagic_LTLIBRARIES = libdirectfb_neomagic.la + +if BUILD_STATIC +neomagic_DATA = $(neomagic_LTLIBRARIES:.la=.o) +endif + +neomagicdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_neomagic_la_SOURCES = \ + neomagic.c \ + neomagic.h \ + neo_overlay.c \ + neo2200.c + +libdirectfb_neomagic_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_neomagic_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/neomagic/Makefile.in b/Source/DirectFB/gfxdrivers/neomagic/Makefile.in new file mode 100755 index 0000000..1613ab6 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/Makefile.in @@ -0,0 +1,601 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/neomagic +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(neomagicdir)" \ + "$(DESTDIR)$(neomagicdir)" +neomagicLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(neomagic_LTLIBRARIES) +libdirectfb_neomagic_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_neomagic_la_OBJECTS = neomagic.lo neo_overlay.lo \ + neo2200.lo +libdirectfb_neomagic_la_OBJECTS = \ + $(am_libdirectfb_neomagic_la_OBJECTS) +libdirectfb_neomagic_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_neomagic_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_neomagic_la_SOURCES) +DIST_SOURCES = $(libdirectfb_neomagic_la_SOURCES) +neomagicDATA_INSTALL = $(INSTALL_DATA) +DATA = $(neomagic_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src + +neomagic_LTLIBRARIES = libdirectfb_neomagic.la +@BUILD_STATIC_TRUE@neomagic_DATA = $(neomagic_LTLIBRARIES:.la=.o) +neomagicdir = $(MODULEDIR)/gfxdrivers +libdirectfb_neomagic_la_SOURCES = \ + neomagic.c \ + neomagic.h \ + neo_overlay.c \ + neo2200.c + +libdirectfb_neomagic_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_neomagic_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu gfxdrivers/neomagic/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu gfxdrivers/neomagic/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-neomagicLTLIBRARIES: $(neomagic_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(neomagicdir)" || $(MKDIR_P) "$(DESTDIR)$(neomagicdir)" + @list='$(neomagic_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(neomagicLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(neomagicdir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(neomagicLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(neomagicdir)/$$f"; \ + else :; fi; \ + done + +uninstall-neomagicLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(neomagic_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(neomagicdir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) 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maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-neomagicDATA \ + uninstall-neomagicLTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/neomagic/neo2200.c b/Source/DirectFB/gfxdrivers/neomagic/neo2200.c new file mode 100755 index 0000000..4ac54ac --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/neo2200.c @@ -0,0 +1,570 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "neomagic.h" + +typedef volatile struct { + u32 bltStat; + u32 bltCntl; + u32 xpColor; + u32 fgColor; + u32 bgColor; + u32 pitch; + u32 clipLT; + u32 clipRB; + u32 srcBitOffset; + u32 srcStart; + u32 reserved0; + u32 dstStart; + u32 xyExt; + + u32 reserved1[19]; + + u32 pageCntl; + u32 pageBase; + u32 postBase; + u32 postPtr; + u32 dataPtr; +} Neo2200; + +typedef struct { + NeoDeviceData neo; + + int dstOrg; + int dstPitch; + int dstPixelWidth; + + int srcOrg; + int srcPitch; + int srcPixelWidth; + + u32 bltCntl; + + bool src_dst_equal; + + /* state validation */ + int n_bltMode_dst; + int n_src; + int n_fgColor; + int n_xpColor; +} Neo2200DeviceData; + +typedef struct { + NeoDriverData neo; + + Neo2200 *neo2200; +} Neo2200DriverData; + + +static inline void neo2200_waitidle( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev ) +{ + while (ndrv->neo2200->bltStat & 1) + ndev->neo.idle_waitcycles++; +} + +static inline void neo2200_waitfifo( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev, + int requested_fifo_space ) +{ + ndev->neo.waitfifo_calls++; + ndev->neo.waitfifo_sum += requested_fifo_space; + + /* FIXME: does not work + if (neo_fifo_space < requested_fifo_space) + { + neo_fifo_waitcycles++; + + while (1) + { + neo_fifo_space = (neo2200->bltStat >> 8); + if (neo_fifo_space >= requested_fifo_space) + break; + } + } + else + { + neo_fifo_cache_hits++; + } + + neo_fifo_space -= requested_fifo_space; + */ + + neo2200_waitidle( ndrv, ndev ); +} + + + +static inline void neo2200_validate_bltMode_dst( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev, + CoreSurface *dst, + CoreSurfaceBufferLock *lock ) +{ + int bltMode = 0; + + if (ndev->n_bltMode_dst) + return; + + switch (dst->config.format) + { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_RGB332: + bltMode |= NEO_MODE1_DEPTH8; + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_YUY2: + bltMode |= NEO_MODE1_DEPTH16; + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + ndev->dstOrg = lock->offset; + ndev->dstPitch = lock->pitch; + ndev->dstPixelWidth = DFB_BYTES_PER_PIXEL(dst->config.format); + + + neo2200_waitfifo( ndrv, ndev, 2 ); + + ndrv->neo2200->bltStat = bltMode << 16; + ndrv->neo2200->pitch = (ndev->dstPitch << 16) | (ndev->srcPitch & 0xffff); + + + ndev->n_bltMode_dst = 1; +} + +static inline void neo2200_validate_src( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev, + CoreSurface *src, + CoreSurfaceBufferLock *lock ) +{ + if (ndev->n_src) + return; + + ndev->srcOrg = lock->offset; + ndev->srcPitch = lock->pitch; + ndev->srcPixelWidth = DFB_BYTES_PER_PIXEL(src->config.format); + + neo2200_waitfifo( ndrv, ndev, 1 ); + ndrv->neo2200->pitch = (ndev->dstPitch << 16) | (ndev->srcPitch & 0xffff); + + ndev->n_src = 1; +} + +static inline void neo2200_validate_fgColor( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev, + CardState *state ) +{ + if (ndev->n_fgColor) + return; + + neo2200_waitfifo( ndrv, ndev, 1 ); + + switch (state->destination->config.format) + { + case DSPF_A8: + ndrv->neo2200->fgColor = state->color.a; + break; + case DSPF_LUT8: + ndrv->neo2200->fgColor = state->color_index; + break; + case DSPF_RGB332: + ndrv->neo2200->fgColor = PIXEL_RGB332( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_ARGB1555: + ndrv->neo2200->fgColor = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB16: + ndrv->neo2200->fgColor = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + ndev->n_fgColor = 1; +} + +static inline void neo2200_validate_xpColor( Neo2200DriverData *ndrv, + Neo2200DeviceData *ndev, + CardState *state ) +{ + if (ndev->n_xpColor) + return; + + neo2200_waitfifo( ndrv, ndev, 1 ); + + ndrv->neo2200->xpColor = state->src_colorkey; + + ndev->n_xpColor = 1; +} + + +/* required implementations */ + +static DFBResult neo2200EngineSync( void *drv, void *dev ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) drv; + Neo2200DeviceData *ndev = (Neo2200DeviceData*) dev; + + neo2200_waitidle( ndrv, ndev ); + + return DFB_OK; +} + +#define NEO_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_NOFX) + +#define NEO_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE) + +#define NEO_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY) + +#define NEO_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT) + +static void neo2200CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) + { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_RGB16: + break; + case DSPF_YUY2: + if (accel == DFXL_BLIT) + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION(accel)) + { + /* if the function is supported and there are no other + drawing flags than the supported */ + if (!(accel & ~NEO_SUPPORTED_DRAWINGFUNCTIONS) && + !(state->drawingflags & ~NEO_SUPPORTED_DRAWINGFLAGS)) + state->accel |= accel; + } + else + { + /* if the function is supported, there are no other + blitting flags than the supported, the source and + destination formats are the same and the source and dest. + are different due to a blitting bug */ + if (!(accel & ~NEO_SUPPORTED_BLITTINGFUNCTIONS) && + !(state->blittingflags & ~NEO_SUPPORTED_BLITTINGFLAGS) && + state->source->config.format == state->destination->config.format) + state->accel |= accel; + } +} + +static void neo2200SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) drv; + Neo2200DeviceData *ndev = (Neo2200DeviceData*) dev; + + if (state->mod_hw & SMF_DESTINATION) + ndev->n_fgColor = ndev->n_bltMode_dst = 0; + else if (state->mod_hw & SMF_COLOR) + ndev->n_fgColor = 0; + + if (state->mod_hw & SMF_SOURCE) + ndev->n_src = 0; + + if (state->mod_hw & SMF_SRC_COLORKEY) + ndev->n_xpColor = 0; + + neo2200_validate_bltMode_dst( ndrv, ndev, state->destination, &state->dst ); + + switch (accel) { + case DFXL_BLIT: + neo2200_validate_src( ndrv, ndev, state->source, &state->src ); + + ndev->src_dst_equal = (state->src.buffer == + state->dst.buffer); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + ndev->bltCntl = NEO_BC0_SRC_TRANS; + neo2200_validate_xpColor( ndrv, ndev, state ); + } + else + ndev->bltCntl = 0; + + state->set |= DFXL_BLIT; + break; + + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + neo2200_validate_fgColor( ndrv, ndev, state ); + + state->set |= DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE; + break; + + default: + D_BUG( "unexpected drawing/blitting function!" ); + break; + } + + state->mod_hw = 0; +} + +static bool neo2200FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) drv; + Neo2200DeviceData *ndev = (Neo2200DeviceData*) dev; + Neo2200 *neo2200 = ndrv->neo2200; + + neo2200_waitfifo( ndrv, ndev, 3 ); + + /* set blt control */ + neo2200->bltCntl = NEO_BC3_FIFO_EN | + NEO_BC0_SRC_IS_FG | + NEO_BC3_SKIP_MAPPING | 0x0c0000; + + neo2200->dstStart = ndev->dstOrg + + (rect->y * ndev->dstPitch) + + (rect->x * ndev->dstPixelWidth); + + neo2200->xyExt = (rect->h << 16) | (rect->w & 0xffff); + + return true; +} + +static bool neo2200DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) drv; + Neo2200DeviceData *ndev = (Neo2200DeviceData*) dev; + Neo2200 *neo2200 = ndrv->neo2200; + + u32 dst = ndev->dstOrg + + (rect->y * ndev->dstPitch) + + (rect->x * ndev->dstPixelWidth); + + neo2200_waitfifo( ndrv, ndev, 3 ); + + /* set blt control */ + neo2200->bltCntl = NEO_BC3_FIFO_EN | + NEO_BC0_SRC_IS_FG | + NEO_BC3_SKIP_MAPPING | 0x0c0000; + + neo2200->dstStart = dst; + neo2200->xyExt = (1 << 16) | (rect->w & 0xffff); + + + dst += (rect->h - 1) * ndev->dstPitch; + neo2200_waitfifo( ndrv, ndev, 2 ); + neo2200->dstStart = dst; + neo2200->xyExt = (1 << 16) | (rect->w & 0xffff); + + + dst -= (rect->h - 2) * ndev->dstPitch; + neo2200_waitfifo( ndrv, ndev, 2 ); + neo2200->dstStart = dst; + neo2200->xyExt = ((rect->h - 2) << 16) | 1; + + + dst += (rect->w - 1) * ndev->dstPixelWidth; + neo2200_waitfifo( ndrv, ndev, 2 ); + neo2200->dstStart = dst; + neo2200->xyExt = ((rect->h - 2) << 16) | 1; + + return true; +} + +static bool neo2200Blit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) drv; + Neo2200DeviceData *ndev = (Neo2200DeviceData*) dev; + Neo2200 *neo2200 = ndrv->neo2200; + + u32 src_start, dst_start; + u32 bltCntl = ndev->bltCntl; + +// fprintf(stderr, "blit: %d, %d (%dx%d) -> %d, %d\n", +// rect->x, rect->y, rect->w, rect->h, dx, dy); + +/* if (rect->x < dx) { + //rect->x += rect->w - 1; + //dx += rect->w - 1; + + bltCntl |= NEO_BC0_X_DEC; + } + + if (rect->y < dy) { + //rect->y += rect->h - 1; + //dy += rect->h - 1; + + bltCntl |= NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC; + } +*/ + /* ARGH, the above code for the blitting direction doesn't work. */ + if (ndev->src_dst_equal && (rect->x < dx || rect->y < dy)) + return false; + + src_start = rect->y * ndev->srcPitch + rect->x * ndev->srcPixelWidth; + dst_start = dy * ndev->dstPitch + dx * ndev->dstPixelWidth; + + neo2200_waitfifo( ndrv, ndev, 4 ); + + /* set blt control */ + neo2200->bltCntl = bltCntl | + NEO_BC3_FIFO_EN | + NEO_BC3_SKIP_MAPPING | 0x0c0000; + + /* set start addresses */ + neo2200->srcStart = ndev->srcOrg + src_start; + neo2200->dstStart = ndev->dstOrg + dst_start; + + /* set size */ + neo2200->xyExt = (rect->h << 16) | (rect->w & 0xffff); + + return true; +} + + + +void +neo2200_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (Neo2200DriverData); + info->device_data_size = sizeof (Neo2200DeviceData); +} + +DFBResult +neo2200_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ) +{ + Neo2200DriverData *ndrv = (Neo2200DriverData*) driver_data; + + ndrv->neo2200 = (Neo2200*) ndrv->neo.mmio_base; + + funcs->CheckState = neo2200CheckState; + funcs->SetState = neo2200SetState; + funcs->EngineSync = neo2200EngineSync; + + funcs->FillRectangle = neo2200FillRectangle; + funcs->DrawRectangle = neo2200DrawRectangle; + // funcs->DrawLine = neoDrawLine2D; + funcs->Blit = neo2200Blit; + // funcs->StretchBlit = neoStretchBlit; + + /* overlay support */ + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &neoOverlayFuncs ); + return DFB_OK; +} + +DFBResult +neo2200_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "2200/2230/2360/2380" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "NeoMagic" ); + + + device_info->caps.flags = 0; + device_info->caps.accel = NEO_SUPPORTED_DRAWINGFUNCTIONS | + NEO_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NEO_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NEO_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + return DFB_OK; +} + +void +neo2200_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +void +neo2200_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} + diff --git a/Source/DirectFB/gfxdrivers/neomagic/neo_overlay.c b/Source/DirectFB/gfxdrivers/neomagic/neo_overlay.c new file mode 100755 index 0000000..b0d4c42 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/neo_overlay.c @@ -0,0 +1,349 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include + +#include +#include +#include + +#include "neomagic.h" + +typedef struct { + CoreLayerRegionConfig config; + + /* overlay registers */ + struct { + u32 OFFSET; + u16 PITCH; + u16 X1; + u16 X2; + u16 Y1; + u16 Y2; + u16 HSCALE; + u16 VSCALE; + u8 CONTROL; + } regs; +} NeoOverlayLayerData; + +static void ovl_set_regs ( NeoDriverData *ndrv, + NeoOverlayLayerData *novl ); +static void ovl_calc_regs( NeoDriverData *ndrv, + NeoOverlayLayerData *novl, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); + +#define NEO_OVERLAY_SUPPORTED_OPTIONS (DLOP_NONE) + +/**********************/ + +static int +ovlLayerDataSize( void ) +{ + return sizeof(NeoOverlayLayerData); +} + +static DFBResult +ovlInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *default_config, + DFBColorAdjustment *default_adj ) +{ + /* set capabilities and type */ + description->caps = DLCAPS_SCREEN_LOCATION | DLCAPS_SURFACE | + DLCAPS_BRIGHTNESS; + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "NeoMagic Overlay" ); + + /* fill out the default configuration */ + default_config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + default_config->width = 640; + default_config->height = 480; + default_config->pixelformat = DSPF_YUY2; + default_config->buffermode = DLBM_FRONTONLY; + default_config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + default_adj->flags = DCAF_BRIGHTNESS; + default_adj->brightness = 0x8000; + + /* FIXME: use mmio */ + if (iopl(3) < 0) { + D_PERROR( "NeoMagic/Overlay: Could not change I/O permission level!\n" ); + return DFB_UNSUPPORTED; + } + + neo_unlock(); + + /* reset overlay */ + OUTGR(0xb0, 0x00); + + /* reset brightness */ + OUTGR(0xc4, 0x00); + + /* disable capture */ + OUTGR(0x0a, 0x21); + OUTSR(0x08, 0xa0); + OUTGR(0x0a, 0x01); + + neo_lock(); + + return DFB_OK; +} + + +static void +ovlOnOff( NeoDriverData *ndrv, + NeoOverlayLayerData *novl, + int on ) +{ + /* set/clear enable bit */ + if (on) + novl->regs.CONTROL = 0x01; + else + novl->regs.CONTROL = 0x00; + + /* FIXME: use mmio */ + if (iopl(3) < 0) { + D_PERROR( "NeoMagic/Overlay: Could not change I/O permission level!\n" ); + return; + } + + /* write back to card */ + neo_unlock(); + OUTGR(0xb0, novl->regs.CONTROL); + neo_lock(); +} + +static DFBResult +ovlTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + /* check for unsupported options */ + if (config->options & ~NEO_OVERLAY_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* check pixel format */ + switch (config->format) { + case DSPF_YUY2: + break; + + default: + fail |= CLRCF_FORMAT; + } + + /* check width */ + if (config->width > 1024 || config->width < 160) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 1024 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ovlSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + NeoDriverData *ndrv = (NeoDriverData*) driver_data; + NeoOverlayLayerData *novl = (NeoOverlayLayerData*) layer_data; + + /* remember configuration */ + novl->config = *config; + + ovl_calc_regs( ndrv, novl, config, surface, lock ); + ovl_set_regs( ndrv, novl ); + + /* enable overlay */ + ovlOnOff( ndrv, novl, config->opacity ); + + return DFB_OK; +} + +static DFBResult +ovlRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + NeoDriverData *ndrv = (NeoDriverData*) driver_data; + NeoOverlayLayerData *novl = (NeoOverlayLayerData*) layer_data; + + /* disable overlay */ + ovlOnOff( ndrv, novl, 0 ); + + return DFB_OK; +} + +static DFBResult +ovlFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + NeoDriverData *ndrv = (NeoDriverData*) driver_data; + NeoOverlayLayerData *novl = (NeoOverlayLayerData*) layer_data; +#if 0 + bool onsync = (flags & DSFLIP_WAITFORSYNC); + + if (onsync) + dfb_fbdev_wait_vsync(); +#endif + + dfb_surface_flip( surface, false ); + + ovl_calc_regs( ndrv, novl, &novl->config, surface, lock ); + ovl_set_regs( ndrv, novl ); + + return DFB_OK; +} + +static DFBResult +ovlSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + /* FIXME: use mmio */ + if (iopl(3) < 0) { + D_PERROR( "NeoMagic/Overlay: Could not change I/O permission level!\n" ); + return DFB_UNSUPPORTED; + } + + neo_unlock(); + OUTGR(0xc4, (signed char)((adj->brightness >> 8) -128)); + neo_lock(); + + return DFB_OK; +} + + +DisplayLayerFuncs neoOverlayFuncs = { + .LayerDataSize = ovlLayerDataSize, + .InitLayer = ovlInitLayer, + .SetRegion = ovlSetRegion, + .RemoveRegion = ovlRemoveRegion, + .TestRegion = ovlTestRegion, + .FlipRegion = ovlFlipRegion, + .SetColorAdjustment = ovlSetColorAdjustment, +}; + + +/* internal */ + +static void ovl_set_regs( NeoDriverData *ndrv, NeoOverlayLayerData *novl ) +{ + /* FIXME: use mmio */ + if (iopl(3) < 0) { + D_PERROR( "NeoMagic/Overlay: Could not change I/O permission level!\n" ); + return; + } + + neo_unlock(); + + OUTGR(0xb1, ((novl->regs.X2 >> 4) & 0xf0) | (novl->regs.X1 >> 8)); + OUTGR(0xb2, novl->regs.X1); + OUTGR(0xb3, novl->regs.X2); + OUTGR(0xb4, ((novl->regs.Y2 >> 4) & 0xf0) | (novl->regs.Y1 >> 8)); + OUTGR(0xb5, novl->regs.Y1); + OUTGR(0xb6, novl->regs.Y2); + OUTGR(0xb7, novl->regs.OFFSET >> 16); + OUTGR(0xb8, novl->regs.OFFSET >> 8); + OUTGR(0xb9, novl->regs.OFFSET); + OUTGR(0xba, novl->regs.PITCH >> 8); + OUTGR(0xbb, novl->regs.PITCH); + OUTGR(0xbc, 0x2e); /* Neo2160: 0x4f */ + OUTGR(0xbd, 0x02); + OUTGR(0xbe, 0x00); + OUTGR(0xbf, 0x02); + + OUTGR(0xc0, novl->regs.HSCALE >> 8); + OUTGR(0xc1, novl->regs.HSCALE); + OUTGR(0xc2, novl->regs.VSCALE >> 8); + OUTGR(0xc3, novl->regs.VSCALE); + + neo_lock(); +} + +static void ovl_calc_regs( NeoDriverData *ndrv, + NeoOverlayLayerData *novl, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + /* fill register struct */ + novl->regs.X1 = config->dest.x; + novl->regs.X2 = config->dest.x + config->dest.w - 1; + + novl->regs.Y1 = config->dest.y; + novl->regs.Y2 = config->dest.y + config->dest.h - 1; + + novl->regs.OFFSET = lock->offset; + novl->regs.PITCH = lock->pitch; + + novl->regs.HSCALE = (surface->config.size.w << 12) / (config->dest.w + 1); + novl->regs.VSCALE = (surface->config.size.h << 12) / (config->dest.h + 1); +} + diff --git a/Source/DirectFB/gfxdrivers/neomagic/neomagic.c b/Source/DirectFB/gfxdrivers/neomagic/neomagic.c new file mode 100755 index 0000000..7eee15f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/neomagic.c @@ -0,0 +1,223 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include + + +DFB_GRAPHICS_DRIVER( neomagic ) + +#include "neomagic.h" + +/* for fifo/performance monitoring */ +//unsigned int neo_fifo_space = 0; + + + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "NeoMagic Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + info->version.major = 0; + info->version.minor = 0; + + info->driver_data_size = sizeof (NeoDriverData); + info->device_data_size = sizeof (NeoDeviceData); + + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + neo2200_get_info( device, info ); + break; + } +} + + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + NeoDriverData *ndrv = (NeoDriverData*) driver_data; + + ndrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!ndrv->mmio_base) + return DFB_IO; + + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + return neo2200_init_driver( device, funcs, driver_data ); + } + + return DFB_BUG; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + /* use polling for syncing, artefacts occur otherwise */ + dfb_config->pollvsync_after = 1; + + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + return neo2200_init_device( device, device_info, + driver_data, device_data ); + } + + return DFB_BUG; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + NeoDeviceData *ndev = (NeoDeviceData*) device_data; + + (void) ndev; + + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + neo2200_close_device( device, driver_data, device_data ); + } + + D_DEBUG( "DirectFB/NEO: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/NEO: %9d neo_waitfifo calls\n", + ndev->waitfifo_calls ); + D_DEBUG( "DirectFB/NEO: %9d register writes (neo_waitfifo sum)\n", + ndev->waitfifo_sum ); + D_DEBUG( "DirectFB/NEO: %9d FIFO wait cycles (depends on CPU)\n", + ndev->fifo_waitcycles ); + D_DEBUG( "DirectFB/NEO: %9d IDLE wait cycles (depends on CPU)\n", + ndev->idle_waitcycles ); + D_DEBUG( "DirectFB/NEO: %9d FIFO space cache hits(depends on CPU)\n", + ndev->fifo_cache_hits ); + D_DEBUG( "DirectFB/NEO: Conclusion:\n" ); + D_DEBUG( "DirectFB/NEO: Average register writes/neo_waitfifo" + "call:%.2f\n", + ndev->waitfifo_sum/(float)(ndev->waitfifo_calls) ); + D_DEBUG( "DirectFB/NEO: Average wait cycles/neo_waitfifo call:" + " %.2f\n", + ndev->fifo_waitcycles/(float)(ndev->waitfifo_calls) ); + D_DEBUG( "DirectFB/NEO: Average fifo space cache hits: %02d%%\n", + (int)(100 * ndev->fifo_cache_hits/ + (float)(ndev->waitfifo_calls)) ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + NeoDriverData *ndrv = (NeoDriverData*) driver_data; + + switch (dfb_gfxcard_get_accelerator( device )) { + /* no support for other NeoMagic cards yet */ + case 95: /* NM2200 */ + case 96: /* NM2230 */ + case 97: /* NM2360 */ + case 98: /* NM2380 */ + neo2200_close_driver( device, driver_data ); + } + + dfb_gfxcard_unmap_mmio( device, ndrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/neomagic/neomagic.h b/Source/DirectFB/gfxdrivers/neomagic/neomagic.h new file mode 100755 index 0000000..d388faf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/neomagic/neomagic.h @@ -0,0 +1,147 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NEOMAGIC_H__ +#define __NEOMAGIC_H__ + +#include +#include + +#include +#include + +typedef struct { + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; +} NeoDeviceData; + +typedef struct { + volatile u8 *mmio_base; +} NeoDriverData; + +extern DisplayLayerFuncs neoOverlayFuncs; + +void +neo2200_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ); + +DFBResult +neo2200_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ); + +DFBResult +neo2200_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ); + +void +neo2200_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ); + +void +neo2200_close_driver( CoreGraphicsDevice *device, + void *driver_data ); + + +#define NEO_BS0_BLT_BUSY 0x00000001 +#define NEO_BS0_FIFO_AVAIL 0x00000002 +#define NEO_BS0_FIFO_PEND 0x00000004 + +#define NEO_BC0_DST_Y_DEC 0x00000001 +#define NEO_BC0_X_DEC 0x00000002 +#define NEO_BC0_SRC_TRANS 0x00000004 +#define NEO_BC0_SRC_IS_FG 0x00000008 +#define NEO_BC0_SRC_Y_DEC 0x00000010 +#define NEO_BC0_FILL_PAT 0x00000020 +#define NEO_BC0_SRC_MONO 0x00000040 +#define NEO_BC0_SYS_TO_VID 0x00000080 + +#define NEO_BC1_DEPTH8 0x00000100 +#define NEO_BC1_DEPTH16 0x00000200 +#define NEO_BC1_X_320 0x00000400 +#define NEO_BC1_X_640 0x00000800 +#define NEO_BC1_X_800 0x00000c00 +#define NEO_BC1_X_1024 0x00001000 +#define NEO_BC1_X_1152 0x00001400 +#define NEO_BC1_X_1280 0x00001800 +#define NEO_BC1_X_1600 0x00001c00 +#define NEO_BC1_DST_TRANS 0x00002000 +#define NEO_BC1_MSTR_BLT 0x00004000 +#define NEO_BC1_FILTER_Z 0x00008000 + +#define NEO_BC2_WR_TR_DST 0x00800000 + +#define NEO_BC3_SRC_XY_ADDR 0x01000000 +#define NEO_BC3_DST_XY_ADDR 0x02000000 +#define NEO_BC3_CLIP_ON 0x04000000 +#define NEO_BC3_FIFO_EN 0x08000000 +#define NEO_BC3_BLT_ON_ADDR 0x10000000 +#define NEO_BC3_SKIP_MAPPING 0x80000000 + +#define NEO_MODE1_DEPTH8 0x0100 +#define NEO_MODE1_DEPTH16 0x0200 +#define NEO_MODE1_DEPTH24 0x0300 +#define NEO_MODE1_X_320 0x0400 +#define NEO_MODE1_X_640 0x0800 +#define NEO_MODE1_X_800 0x0c00 +#define NEO_MODE1_X_1024 0x1000 +#define NEO_MODE1_X_1152 0x1400 +#define NEO_MODE1_X_1280 0x1800 +#define NEO_MODE1_X_1600 0x1c00 +#define NEO_MODE1_BLT_ON_ADDR 0x2000 + + +static inline void OUTGR (u8 index, u8 data) +{ + outb (index, 0x3ce); + outb (data, 0x3cf); +} + +static inline void OUTSR (u8 index, u8 data) +{ + outb (index, 0x3c4); + outb (data, 0x3c5); +} + +static inline void neo_lock( void ) +{ + OUTGR(0x09, 0x00); +} + +static inline void neo_unlock( void ) +{ + OUTGR(0x09, 0x26); +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/nsc/Makefile.am b/Source/DirectFB/gfxdrivers/nsc/Makefile.am new file mode 100755 index 0000000..95b0d7d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/Makefile.am @@ -0,0 +1,40 @@ +## Makefile.am for DirectFB/gfxdrivers/nsc + +SUBDIRS = include + +INCLUDES = \ + -I/usr/src/linux/drivers/video/nsc \ + -I/usr/src/linux/drivers/video/nsc/gfx \ + -I/usr/src/linux/drivers/video/nsc/panel \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/gfxdrivers/nsc/include + +nsc_LTLIBRARIES = libdirectfb_nsc.la + +if BUILD_STATIC +nsc_DATA = $(nsc_LTLIBRARIES:.la=.o) +endif + +nscdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_nsc_la_SOURCES = \ + nsc.c \ + nsc_galfns.c + +libdirectfb_nsc_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_nsc_la_LIBADD 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all all-am check check-am clean clean-generic clean-libtool \ + distclean distclean-generic distclean-libtool distdir dvi \ + dvi-am html html-am info info-am install install-am \ + install-data install-data-am install-dvi install-dvi-am \ + install-exec install-exec-am install-html install-html-am \ + install-info install-info-am install-man install-pdf \ + install-pdf-am install-ps install-ps-am install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-generic \ + mostlyclean-libtool pdf pdf-am ps ps-am uninstall uninstall-am + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/nsc/include/gfx_regs.h b/Source/DirectFB/gfxdrivers/nsc/include/gfx_regs.h new file mode 100755 index 0000000..059ce47 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/include/gfx_regs.h @@ -0,0 +1,1733 @@ +/* + * $Workfile: gfx_regs.h $ + * + * This header file contains the graphics register definitions. + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + + +/*----------------------------------*/ +/* FIRST GENERATION GRAPHICS UNIT */ +/*----------------------------------*/ + +#define GP_DST_XCOOR 0x8100 /* x destination origin */ +#define GP_DST_YCOOR 0x8102 /* y destination origin */ +#define GP_WIDTH 0x8104 /* pixel width */ +#define GP_HEIGHT 0x8106 /* pixel height */ +#define GP_SRC_XCOOR 0x8108 /* x source origin */ +#define GP_SRC_YCOOR 0x810A /* y source origin */ + +#define GP_VECTOR_LENGTH 0x8104 /* vector length */ +#define GP_INIT_ERROR 0x8106 /* vector initial error */ +#define GP_AXIAL_ERROR 0x8108 /* axial error increment */ +#define GP_DIAG_ERROR 0x810A /* diagonal error increment */ + +#define GP_SRC_COLOR_0 0x810C /* source color 0 */ +#define GP_SRC_COLOR_1 0x810E /* source color 1 */ +#define GP_PAT_COLOR_0 0x8110 /* pattern color 0 */ +#define GP_PAT_COLOR_1 0x8112 /* pattern color 1 */ +#define GP_PAT_COLOR_2 0x8114 /* pattern color 2 */ +#define GP_PAT_COLOR_3 0x8116 /* pattern color 3 */ +#define GP_PAT_DATA_0 0x8120 /* bits 31:0 of pattern */ +#define GP_PAT_DATA_1 0x8124 /* bits 63:32 of pattern */ +#define GP_PAT_DATA_2 0x8128 /* bits 95:64 of pattern */ +#define GP_PAT_DATA_3 0x812C /* bits 127:96 of pattern */ + +#define GP_VGA_WRITE 0x8140 /* VGA write path control */ +#define GP_VGA_READ 0x8144 /* VGA read path control */ + +#define GP_RASTER_MODE 0x8200 /* raster operation */ +#define GP_VECTOR_MODE 0x8204 /* vector mode register */ +#define GP_BLIT_MODE 0x8208 /* blit mode register */ +#define GP_BLIT_STATUS 0x820C /* blit status register */ + +#define GP_VGA_BASE 0x8210 /* VGA memory offset (x64K) */ +#define GP_VGA_LATCH 0x8214 /* VGA display latch */ + +/* "GP_VECTOR_MODE" BIT DEFINITIONS */ + +#define VM_X_MAJOR 0x0000 /* X major vector */ +#define VM_Y_MAJOR 0x0001 /* Y major vector */ +#define VM_MAJOR_INC 0x0002 /* positive major axis step */ +#define VM_MINOR_INC 0x0004 /* positive minor axis step */ +#define VM_READ_DST_FB 0x0008 /* read destination data */ + +/* "GP_RASTER_MODE" BIT DEFINITIONS */ + +#define RM_PAT_DISABLE 0x0000 /* pattern is disabled */ +#define RM_PAT_MONO 0x0100 /* 1BPP pattern expansion */ +#define RM_PAT_DITHER 0x0200 /* 2BPP pattern expansion */ +#define RM_PAT_COLOR 0x0300 /* 8BPP or 16BPP pattern */ +#define RM_PAT_MASK 0x0300 /* mask for pattern mode */ +#define RM_PAT_TRANSPARENT 0x0400 /* transparent 1BPP pattern */ +#define RM_SRC_TRANSPARENT 0x0800 /* transparent 1BPP source */ + +/* "GP_BLIT_STATUS" BIT DEFINITIONS */ + +#define BS_BLIT_BUSY 0x0001 /* blit engine is busy */ +#define BS_PIPELINE_BUSY 0x0002 /* graphics pipeline is busy*/ +#define BS_BLIT_PENDING 0x0004 /* blit pending */ +#define BC_FLUSH 0x0080 /* flush pipeline requests */ +#define BC_8BPP 0x0000 /* 8BPP mode */ +#define BC_16BPP 0x0100 /* 16BPP mode */ +#define BC_FB_WIDTH_1024 0x0000 /* framebuffer width = 1024 */ +#define BC_FB_WIDTH_2048 0x0200 /* framebuffer width = 2048 */ +#define BC_FB_WIDTH_4096 0x0400 /* framebuffer width = 4096 */ + +/* "GP_BLIT_MODE" BIT DEFINITIONS */ + +#define BM_READ_SRC_NONE 0x0000 /* source foreground color */ +#define BM_READ_SRC_FB 0x0001 /* read source from FB */ +#define BM_READ_SRC_BB0 0x0002 /* read source from BB0 */ +#define BM_READ_SRC_BB1 0x0003 /* read source from BB1 */ +#define BM_READ_SRC_MASK 0x0003 /* read source mask */ + +#define BM_READ_DST_NONE 0x0000 /* no destination data */ +#define BM_READ_DST_BB0 0x0008 /* destination from BB0 */ +#define BM_READ_DST_BB1 0x000C /* destination from BB1 */ +#define BM_READ_DST_FB0 0x0010 /* dest from FB (store BB0) */ +#define BM_READ_DST_FB1 0x0014 /* dest from FB (store BB1) */ +#define BM_READ_DST_MASK 0x001C /* read destination mask */ + +#define BM_WRITE_FB 0x0000 /* write to framebuffer */ +#define BM_WRITE_MEM 0x0020 /* write to memory */ +#define BM_WRITE_MASK 0x0020 /* write mask */ + +#define BM_SOURCE_COLOR 0x0000 /* source is 8BPP or 16BPP */ +#define BM_SOURCE_EXPAND 0x0040 /* source is 1BPP */ +#define BM_SOURCE_TEXT 0x00C0 /* source is 1BPP text */ +#define BM_SOURCE_MASK 0x00C0 /* source mask */ + +#define BM_REVERSE_Y 0x0100 /* reverse Y direction */ + +/*---------------------------------------*/ +/* FIRST GENERATION DISPLAY CONTROLLER */ +/*---------------------------------------*/ + +#define DC_UNLOCK 0x8300 /* lock register */ +#define DC_GENERAL_CFG 0x8304 /* config registers... */ +#define DC_TIMING_CFG 0x8308 +#define DC_OUTPUT_CFG 0x830C + +#define DC_FB_ST_OFFSET 0x8310 /* framebuffer start offset */ +#define DC_CB_ST_OFFSET 0x8314 /* compression start offset */ +#define DC_CURS_ST_OFFSET 0x8318 /* cursor start offset */ +#define DC_ICON_ST_OFFSET 0x831C /* icon start offset */ +#define DC_VID_ST_OFFSET 0x8320 /* video start offset */ +#define DC_LINE_DELTA 0x8324 /* fb and cb skip counts */ +#define DC_BUF_SIZE 0x8328 /* fb and cb line size */ + +#define DC_H_TIMING_1 0x8330 /* horizontal timing... */ +#define DC_H_TIMING_2 0x8334 +#define DC_H_TIMING_3 0x8338 +#define DC_FP_H_TIMING 0x833C + +#define DC_V_TIMING_1 0x8340 /* vertical timing... */ +#define DC_V_TIMING_2 0x8344 +#define DC_V_TIMING_3 0x8348 +#define DC_FP_V_TIMING 0x834C + +#define DC_CURSOR_X 0x8350 /* cursor x position */ +#define DC_ICON_X 0x8354 /* HACK - 1.3 definition */ +#define DC_V_LINE_CNT 0x8354 /* vertical line counter */ +#define DC_CURSOR_Y 0x8358 /* cursor y position */ +#define DC_ICON_Y 0x835C /* HACK - 1.3 definition */ +#define DC_SS_LINE_CMP 0x835C /* line compare value */ +#define DC_CURSOR_COLOR 0x8360 /* cursor colors */ +#define DC_ICON_COLOR 0x8364 /* icon colors */ +#define DC_BORDER_COLOR 0x8368 /* border color */ +#define DC_PAL_ADDRESS 0x8370 /* palette address */ +#define DC_PAL_DATA 0x8374 /* palette data */ +#define DC_DFIFO_DIAG 0x8378 /* display FIFO diagnostic */ +#define DC_CFIFO_DIAG 0x837C /* compression FIF0 diagnostic */ + +/* PALETTE LOCATIONS */ + +#define PAL_CURSOR_COLOR_0 0x100 +#define PAL_CURSOR_COLOR_1 0x101 +#define PAL_ICON_COLOR_0 0x102 +#define PAL_ICON_COLOR_1 0x103 +#define PAL_OVERSCAN_COLOR 0x104 + +/* UNLOCK VALUE */ + +#define DC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* "DC_GENERAL_CFG" BIT DEFINITIONS */ + +#define DC_GCFG_DFLE 0x00000001 /* display FIFO load enable */ +#define DC_GCFG_CURE 0x00000002 /* cursor enable */ +#define DC_GCFG_VCLK_DIV 0x00000004 /* vid clock divisor */ +#define DC_GCFG_PLNO 0x00000004 /* planar offset LSB */ +#define DC_GCFG_PPC 0x00000008 /* pixel pan compatibility */ +#define DC_GCFG_CMPE 0x00000010 /* compression enable */ +#define DC_GCFG_DECE 0x00000020 /* decompression enable */ +#define DC_GCFG_DCLK_MASK 0x000000C0 /* dotclock multiplier */ +#define DC_GCFG_DCLK_POS 6 /* dotclock multiplier */ +#define DC_GCFG_DFHPSL_MASK 0x00000F00 /* FIFO high-priority start */ +#define DC_GCFG_DFHPSL_POS 8 /* FIFO high-priority start */ +#define DC_GCFG_DFHPEL_MASK 0x0000F000 /* FIFO high-priority end */ +#define DC_GCFG_DFHPEL_POS 12 /* FIFO high-priority end */ +#define DC_GCFG_CIM_MASK 0x00030000 /* compressor insert mode */ +#define DC_GCFG_CIM_POS 16 /* compressor insert mode */ +#define DC_GCFG_FDTY 0x00040000 /* frame dirty mode */ +#define DC_GCFG_RTPM 0x00080000 /* real-time perf. monitor */ +#define DC_GCFG_DAC_RS_MASK 0x00700000 /* DAC register selects */ +#define DC_GCFG_DAC_RS_POS 20 /* DAC register selects */ +#define DC_GCFG_CKWR 0x00800000 /* clock write */ +#define DC_GCFG_LDBL 0x01000000 /* line double */ +#define DC_GCFG_DIAG 0x02000000 /* FIFO diagnostic mode */ +#define DC_GCFG_CH4S 0x04000000 /* sparse refresh mode */ +#define DC_GCFG_SSLC 0x08000000 /* enable line compare */ +#define DC_GCFG_VIDE 0x10000000 /* video enable */ +#define DC_GCFG_DFCK 0x20000000 /* divide flat-panel clock - rev 2.3 down */ +#define DC_GCFG_VRDY 0x20000000 /* video port speed - rev 2.4 up */ +#define DC_GCFG_DPCK 0x40000000 /* divide pixel clock */ +#define DC_GCFG_DDCK 0x80000000 /* divide dot clock */ + +/* "DC_TIMING_CFG" BIT DEFINITIONS */ + +#define DC_TCFG_FPPE 0x00000001 /* flat-panel power enable */ +#define DC_TCFG_HSYE 0x00000002 /* horizontal sync enable */ +#define DC_TCFG_VSYE 0x00000004 /* vertical sync enable */ +#define DC_TCFG_BLKE 0x00000008 /* blank enable */ +#define DC_TCFG_DDCK 0x00000010 /* DDC clock */ +#define DC_TCFG_TGEN 0x00000020 /* timing generator enable */ +#define DC_TCFG_VIEN 0x00000040 /* vertical interrupt enable*/ +#define DC_TCFG_BLNK 0x00000080 /* blink enable */ +#define DC_TCFG_CHSP 0x00000100 /* horizontal sync polarity */ +#define DC_TCFG_CVSP 0x00000200 /* vertical sync polarity */ +#define DC_TCFG_FHSP 0x00000400 /* panel horz sync polarity */ +#define DC_TCFG_FVSP 0x00000800 /* panel vert sync polarity */ +#define DC_TCFG_FCEN 0x00001000 /* flat-panel centering */ +#define DC_TCFG_CDCE 0x00002000 /* HACK - 1.3 definition */ +#define DC_TCFG_PLNR 0x00002000 /* planar mode enable */ +#define DC_TCFG_INTL 0x00004000 /* interlace scan */ +#define DC_TCFG_PXDB 0x00008000 /* pixel double */ +#define DC_TCFG_BKRT 0x00010000 /* blink rate */ +#define DC_TCFG_PSD_MASK 0x000E0000 /* power sequence delay */ +#define DC_TCFG_PSD_POS 17 /* power sequence delay */ +#define DC_TCFG_DDCI 0x08000000 /* DDC input (RO) */ +#define DC_TCFG_SENS 0x10000000 /* monitor sense (RO) */ +#define DC_TCFG_DNA 0x20000000 /* display not active (RO) */ +#define DC_TCFG_VNA 0x40000000 /* vertical not active (RO) */ +#define DC_TCFG_VINT 0x80000000 /* vertical interrupt (RO) */ + +/* "DC_OUTPUT_CFG" BIT DEFINITIONS */ + +#define DC_OCFG_8BPP 0x00000001 /* 8/16 bpp select */ +#define DC_OCFG_555 0x00000002 /* 16 bpp format */ +#define DC_OCFG_PCKE 0x00000004 /* PCLK enable */ +#define DC_OCFG_FRME 0x00000008 /* frame rate mod enable */ +#define DC_OCFG_DITE 0x00000010 /* dither enable */ +#define DC_OCFG_2PXE 0x00000020 /* 2 pixel enable */ +#define DC_OCFG_2XCK 0x00000040 /* 2 x pixel clock */ +#define DC_OCFG_2IND 0x00000080 /* 2 index enable */ +#define DC_OCFG_34ADD 0x00000100 /* 3- or 4-bit add */ +#define DC_OCFG_FRMS 0x00000200 /* frame rate mod select */ +#define DC_OCFG_CKSL 0x00000400 /* clock select */ +#define DC_OCFG_PRMP 0x00000800 /* palette re-map */ +#define DC_OCFG_PDEL 0x00001000 /* panel data enable low */ +#define DC_OCFG_PDEH 0x00002000 /* panel data enable high */ +#define DC_OCFG_CFRW 0x00004000 /* comp line buffer r/w sel */ +#define DC_OCFG_DIAG 0x00008000 /* comp line buffer diag */ + +#define MC_MEM_CNTRL1 0x00008400 +#define MC_DR_ADD 0x00008418 +#define MC_DR_ACC 0x0000841C + +/* MC_MEM_CNTRL1 BIT DEFINITIONS */ + +#define MC_XBUSARB 0x00000008 /* 0 = GP priority < CPU priority */ + /* 1 = GP priority = CPU priority */ + /* GXm databook V2.0 is wrong ! */ +/*----------*/ +/* CS5530 */ +/*----------*/ + +/* CS5530 REGISTER DEFINITIONS */ + +#define CS5530_VIDEO_CONFIG 0x0000 +#define CS5530_DISPLAY_CONFIG 0x0004 +#define CS5530_VIDEO_X_POS 0x0008 +#define CS5530_VIDEO_Y_POS 0x000C +#define CS5530_VIDEO_SCALE 0x0010 +#define CS5530_VIDEO_COLOR_KEY 0x0014 +#define CS5530_VIDEO_COLOR_MASK 0x0018 +#define CS5530_PALETTE_ADDRESS 0x001C +#define CS5530_PALETTE_DATA 0x0020 +#define CS5530_DOT_CLK_CONFIG 0x0024 +#define CS5530_CRCSIG_TFT_TV 0x0028 + +/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define CS5530_VCFG_VID_EN 0x00000001 +#define CS5530_VCFG_VID_REG_UPDATE 0x00000002 +#define CS5530_VCFG_VID_INP_FORMAT 0x0000000C +#define CS5530_VCFG_8_BIT_4_2_0 0x00000004 +#define CS5530_VCFG_16_BIT_4_2_0 0x00000008 +#define CS5530_VCFG_GV_SEL 0x00000010 +#define CS5530_VCFG_CSC_BYPASS 0x00000020 +#define CS5530_VCFG_X_FILTER_EN 0x00000040 +#define CS5530_VCFG_Y_FILTER_EN 0x00000080 +#define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define CS5530_VCFG_INIT_READ_MASK 0x01FF0000 +#define CS5530_VCFG_EARLY_VID_RDY 0x02000000 +#define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000 +#define CS5530_VCFG_4_2_0_MODE 0x10000000 +#define CS5530_VCFG_16_BIT_EN 0x20000000 +#define CS5530_VCFG_HIGH_SPD_INT 0x40000000 + +/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define CS5530_DCFG_DIS_EN 0x00000001 +#define CS5530_DCFG_HSYNC_EN 0x00000002 +#define CS5530_DCFG_VSYNC_EN 0x00000004 +#define CS5530_DCFG_DAC_BL_EN 0x00000008 +#define CS5530_DCFG_DAC_PWDNX 0x00000020 +#define CS5530_DCFG_FP_PWR_EN 0x00000040 +#define CS5530_DCFG_FP_DATA_EN 0x00000080 +#define CS5530_DCFG_CRT_HSYNC_POL 0x00000100 +#define CS5530_DCFG_CRT_VSYNC_POL 0x00000200 +#define CS5530_DCFG_FP_HSYNC_POL 0x00000400 +#define CS5530_DCFG_FP_VSYNC_POL 0x00000800 +#define CS5530_DCFG_XGA_FP 0x00001000 +#define CS5530_DCFG_FP_DITH_EN 0x00002000 +#define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define CS5530_DCFG_VG_CK 0x00100000 +#define CS5530_DCFG_GV_PAL_BYP 0x00200000 +#define CS5530_DCFG_DDC_SCL 0x00400000 +#define CS5530_DCFG_DDC_SDA 0x00800000 +#define CS5530_DCFG_DDC_OE 0x01000000 +#define CS5530_DCFG_16_BIT_EN 0x02000000 + + +/*----------*/ +/* SC1200 */ +/*----------*/ + +/* SC1200 VIDEO REGISTER DEFINITIONS */ + +#define SC1200_VIDEO_CONFIG 0x000 +#define SC1200_DISPLAY_CONFIG 0x004 +#define SC1200_VIDEO_X_POS 0x008 +#define SC1200_VIDEO_Y_POS 0x00C +#define SC1200_VIDEO_UPSCALE 0x010 +#define SC1200_VIDEO_COLOR_KEY 0x014 +#define SC1200_VIDEO_COLOR_MASK 0x018 +#define SC1200_PALETTE_ADDRESS 0x01C +#define SC1200_PALETTE_DATA 0x020 +#define SC1200_VID_MISC 0x028 +#define SC1200_VID_CLOCK_SELECT 0x02C +#define SC1200_VIDEO_DOWNSCALER_CONTROL 0x03C +#define SC1200_VIDEO_DOWNSCALER_COEFFICIENTS 0x40 +#define SC1200_VID_CRC 0x044 +#define SC1200_DEVICE_ID 0x048 +#define SC1200_VID_ALPHA_CONTROL 0x04C +#define SC1200_CURSOR_COLOR_KEY 0x050 +#define SC1200_CURSOR_COLOR_MASK 0x054 +#define SC1200_CURSOR_COLOR_1 0x058 +#define SC1200_CURSOR_COLOR_2 0x05C +#define SC1200_ALPHA_XPOS_1 0x060 +#define SC1200_ALPHA_YPOS_1 0x064 +#define SC1200_ALPHA_COLOR_1 0x068 +#define SC1200_ALPHA_CONTROL_1 0x06C +#define SC1200_ALPHA_XPOS_2 0x070 +#define SC1200_ALPHA_YPOS_2 0x074 +#define SC1200_ALPHA_COLOR_2 0x078 +#define SC1200_ALPHA_CONTROL_2 0x07C +#define SC1200_ALPHA_XPOS_3 0x080 +#define SC1200_ALPHA_YPOS_3 0x084 +#define SC1200_ALPHA_COLOR_3 0x088 +#define SC1200_ALPHA_CONTROL_3 0x08C +#define SC1200_VIDEO_REQUEST 0x090 +#define SC1200_ALPHA_WATCH 0x094 +#define SC1200_VIDEO_DISPLAY_MODE 0x400 +#define SC1200_VIDEO_ODD_VBI_LINE_ENABLE 0x40C +#define SC1200_VIDEO_EVEN_VBI_LINE_ENABLE 0x410 +#define SC1200_VIDEO_VBI_HORIZ_CONTROL 0x414 +#define SC1200_VIDEO_ODD_VBI_TOTAL_COUNT 0x418 +#define SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT 0x41C +#define SC1200_GENLOCK 0x420 +#define SC1200_GENLOCK_DELAY 0x424 +#define SC1200_TVOUT_HORZ_TIM 0x800 +#define SC1200_TVOUT_HORZ_SYNC 0x804 +#define SC1200_TVOUT_VERT_SYNC 0x808 +#define SC1200_TVOUT_LINE_END 0x80C +#define SC1200_TVOUT_VERT_DOWNSCALE 0x810 /* REV. A & B */ +#define SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE 0x810 /* REV. C */ +#define SC1200_TVOUT_HORZ_SCALING 0x814 +#define SC1200_TVOUT_DEBUG 0x818 +#define SC1200_TVENC_TIM_CTRL_1 0xC00 +#define SC1200_TVENC_TIM_CTRL_2 0xC04 +#define SC1200_TVENC_TIM_CTRL_3 0xC08 +#define SC1200_TVENC_SUB_FREQ 0xC0C +#define SC1200_TVENC_DISP_POS 0xC10 +#define SC1200_TVENC_DISP_SIZE 0xC14 +#define SC1200_TVENC_CC_DATA 0xC18 +#define SC1200_TVENC_EDS_DATA 0xC1C +#define SC1200_TVENC_CGMS_DATA 0xC20 +#define SC1200_TVENC_WSS_DATA 0xC24 +#define SC1200_TVENC_CC_CONTROL 0xC28 +#define SC1200_TVENC_DAC_CONTROL 0xC2C +#define SC1200_TVENC_MV_CONTROL 0xC30 + +/* "SC1200_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define SC1200_VCFG_VID_EN 0x00000001 +#define SC1200_VCFG_VID_INP_FORMAT 0x0000000C +#define SC1200_VCFG_UYVY_FORMAT 0x00000000 +#define SC1200_VCFG_Y2YU_FORMAT 0x00000004 +#define SC1200_VCFG_YUYV_FORMAT 0x00000008 +#define SC1200_VCFG_YVYU_FORMAT 0x0000000C +#define SC1200_VCFG_X_FILTER_EN 0x00000040 +#define SC1200_VCFG_Y_FILTER_EN 0x00000080 +#define SC1200_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define SC1200_VCFG_INIT_READ_MASK 0x01FF0000 +#define SC1200_VCFG_LINE_SIZE_UPPER 0x08000000 +#define SC1200_VCFG_4_2_0_MODE 0x10000000 + +/* "SC1200_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define SC1200_DCFG_DIS_EN 0x00000001 +#define SC1200_DCFG_HSYNC_EN 0x00000002 +#define SC1200_DCFG_VSYNC_EN 0x00000004 +#define SC1200_DCFG_DAC_BL_EN 0x00000008 +#define SC1200_DCFG_FP_PWR_EN 0x00000040 +#define SC1200_DCFG_FP_DATA_EN 0x00000080 +#define SC1200_DCFG_CRT_HSYNC_POL 0x00000100 +#define SC1200_DCFG_CRT_VSYNC_POL 0x00000200 +#define SC1200_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define SC1200_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define SC1200_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define SC1200_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define SC1200_DCFG_VG_CK 0x00100000 +#define SC1200_DCFG_GV_PAL_BYP 0x00200000 +#define SC1200_DCFG_DDC_SCL 0x00400000 +#define SC1200_DCFG_DDC_SDA 0x00800000 +#define SC1200_DCFG_DDC_OE 0x01000000 + +/* "SC1200_VID_MISC" BIT DEFINITIONS */ + +#define SC1200_GAMMA_BYPASS_BOTH 0x00000001 +#define SC1200_DAC_POWER_DOWN 0x00000400 +#define SC1200_ANALOG_POWER_DOWN 0x00000800 +#define SC1200_PLL_POWER_NORMAL 0x00001000 + +/* "SC1200_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ + +#define SC1200_VIDEO_DOWNSCALE_ENABLE 0x00000001 +#define SC1200_VIDEO_DOWNSCALE_FACTOR_POS 1 +#define SC1200_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E +#define SC1200_VIDEO_DOWNSCALE_TYPE_A 0x00000000 +#define SC1200_VIDEO_DOWNSCALE_TYPE_B 0x00000040 +#define SC1200_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 + +/* "SC1200_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ + +#define SC1200_VIDEO_DOWNSCALER_COEF1_POS 0 +#define SC1200_VIDEO_DOWNSCALER_COEF2_POS 8 +#define SC1200_VIDEO_DOWNSCALER_COEF3_POS 16 +#define SC1200_VIDEO_DOWNSCALER_COEF4_POS 24 +#define SC1200_VIDEO_DOWNSCALER_COEF_MASK 0xF + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL (REGISTER 0x4C) */ + +#define SC1200_VERTICAL_SCALER_SHIFT_MASK 0x00000007 +#define SC1200_VERTICAL_SCALER_SHIFT_INIT 0x00000004 +#define SC1200_VERTICAL_SCALER_SHIFT_EN 0x00000010 +#define SC1200_TOP_LINE_IN_ODD 0x00000040 +#define SC1200_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define SC1200_VIDEO_IS_INTERLACED 0x00000200 +#define SC1200_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define SC1200_CSC_GFX_RGB_TO_YUV 0x00000800 +#define SC1200_VIDEO_INPUT_IS_RGB 0x00002000 +#define SC1200_VIDEO_LINE_OFFSET_ODD 0x00001000 +#define SC1200_ALPHA1_PRIORITY_POS 16 +#define SC1200_ALPHA1_PRIORITY_MASK 0x00030000 +#define SC1200_ALPHA2_PRIORITY_POS 18 +#define SC1200_ALPHA2_PRIORITY_MASK 0x000C0000 +#define SC1200_ALPHA3_PRIORITY_POS 20 +#define SC1200_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS (REGISTER 0x50) */ + +#define SC1200_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define SC1200_CURSOR_COLOR_BITS 23 +#define SC1200_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define SC1200_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define SC1200_ACTRL_WIN_ENABLE 0x00010000 +#define SC1200_ACTRL_LOAD_ALPHA 0x00020000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define SC1200_VIDEO_Y_REQUEST_POS 0 +#define SC1200_VIDEO_X_REQUEST_POS 16 +#define SC1200_VIDEO_REQUEST_MASK 0x00000FFF + +/* VIDEO DISPLAY MODE (REGISTER 0x400) */ + +#define SC1200_VIDEO_SOURCE_MASK 0x00000003 +#define SC1200_VIDEO_SOURCE_GX1 0x00000000 +#define SC1200_VIDEO_SOURCE_DVIP 0x00000002 +#define SC1200_VBI_SOURCE_MASK 0x00000004 +#define SC1200_VBI_SOURCE_DVIP 0x00000000 +#define SC1200_VBI_SOURCE_GX1 0x00000004 + +/* ODD/EVEN VBI LINE ENABLE (REGISTERS 0x40C, 0x410) */ + +#define SC1200_VIDEO_VBI_LINE_ENABLE_MASK 0x00FFFFFC +#define SC1200_VIDEO_ALL_ACTIVE_IS_VBI 0x01000000 +#define SC1200_VIDEO_VBI_LINE_OFFSET_POS 25 +#define SC1200_VIDEO_VBI_LINE_OFFSET_MASK 0x3E000000 + +/* ODD/EVEN VBI TOTAL COUNT (REGISTERS 0x418, 0x41C) */ + +#define SC1200_VIDEO_VBI_TOTAL_COUNT_MASK 0x000FFFFF + +/* GENLOCK BIT DEFINITIONS */ + +#define SC1200_GENLOCK_SINGLE_ENABLE 0x00000001 +#define SC1200_GENLOCK_FIELD_SYNC_ENABLE 0x00000001 +#define SC1200_GENLOCK_CONTINUOUS_ENABLE 0x00000002 +#define SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE 0x00000004 +#define SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE 0x00000008 +#define SC1200_GENLOCK_TIMEOUT_ENABLE 0x00000010 +#define SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD 0x00000020 +#define SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY 0x00000040 +#define SC1200_GENLOCK_TVENC_RESET_ENABLE 0x00000080 +#define SC1200_GENLOCK_SYNC_TO_TVENC 0x00000100 +#define SC1200_GENLOCK_DELAY_MASK 0x001FFFFF + +/* TVOUT HORIZONTAL PRE ENCODER SCALE BIT DEFINITIONS */ + +#define SC1200_TVOUT_YC_DELAY_MASK 0x00C00000 +#define SC1200_TVOUT_YC_DELAY_NONE 0x00000000 +#define SC1200_TVOUT_Y_DELAY_ONE_PIXEL 0x00400000 +#define SC1200_TVOUT_C_DELAY_ONE_PIXEL 0x00800000 +#define SC1200_TVOUT_C_DELAY_TWO_PIXELS 0x00C00000 + +/* TVOUT HORIZONTAL SCALING/CONTROL BIT DEFINITIONS */ + +#define SC1200_TVOUT_FLICKER_FILTER_MASK 0x60000000 +#define SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH 0x00000000 +#define SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF 0x20000000 +#define SC1200_TVOUT_FLICKER_FILTER_DISABLED 0x40000000 +#define SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK 0x0F000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD 0x00000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD 0x02000000 +#define SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD 0x05000000 +#define SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD 0x07000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD 0x0E000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_ODD_FIELDS 0x08000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_EVEN_FIELDS 0x0A000000 + +/* TVOUT DEBUG BIT DEFINITIONS */ + +#define SC1200_TVOUT_FIELD_STATUS_EVEN 0x00000040 +#define SC1200_TVOUT_FIELD_STATUS_TV 0x00000080 +#define SC1200_TVOUT_CRT_VSYNC_STATUS_TRAILING 0x00000100 +#define SC1200_TVOUT_FIELD_STATUS_INVERT 0x00000200 +#define SC1200_TVOUT_CONVERTER_INTERPOLATION 0x00000400 + +/* TVENC TIMING/CONTROL 1 BIT DEFINITIONS (REGISTER 0xC00) */ + +#define SC1200_TVENC_VPHASE_MASK 0x001FF800 +#define SC1200_TVENC_VPHASE_POS 11 +#define SC1200_TVENC_SUB_CARRIER_RESET_MASK 0x30000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_NEVER 0x00000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES 0x10000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES 0x20000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES 0x30000000 +#define SC1200_TVENC_VIDEO_TIMING_ENABLE 0x80000000 + +/* TVENC TIMING/CONTROL 2 BIT DEFINITIONS (REGISTER 0xC04) */ + +#define SC1200_TVENC_OUTPUT_YCBCR 0x40000000 +#define SC1200_TVENC_CFS_MASK 0x00030000 +#define SC1200_TVENC_CFS_BYPASS 0x00000000 +#define SC1200_TVENC_CFS_CVBS 0x00020000 +#define SC1200_TVENC_CFS_SVIDEO 0x00030000 + +/* TVENC TIMING/CONTROL 3 BIT DEFINITIONS (REGISTER 0xC08) */ + +#define SC1200_TVENC_CS 0x00000001 +#define SC1200_TVENC_SYNCMODE_MASK 0x00000006 +#define SC1200_TVENC_SYNC_ON_GREEN 0x00000002 +#define SC1200_TVENC_SYNC_ON_CVBS 0x00000004 +#define SC1200_TVENC_CM 0x00000008 + +/* TVENC DAC CONTROL BIT DEFINITIONS (REGISTER 0xC2C) */ +#define SC1200_TVENC_TRIM_MASK 0x00000007 +#define SC1200_TVENC_POWER_DOWN 0x00000020 + +/* TVENC MV CONTROL BIT DEFINITIONS (REGISTER 0xC30) */ +#define SC1200_TVENC_MV_ENABLE 0xBE + +/* SC1200 VIP REGISTER DEFINITIONS */ + +#define SC1200_VIP_CONFIG 0x00000000 +#define SC1200_VIP_CONTROL 0x00000004 +#define SC1200_VIP_STATUS 0x00000008 +#define SC1200_VIP_CURRENT_LINE 0x00000010 +#define SC1200_VIP_LINE_TARGET 0x00000014 +#define SC1200_ODD_DIRECT_VBI_LINE_ENABLE 0x00000018 +#define SC1200_EVEN_DIRECT_VBI_LINE_ENABLE 0x0000001C +#define SC1200_VIP_ODD_BASE 0x00000020 +#define SC1200_VIP_EVEN_BASE 0x00000024 +#define SC1200_VIP_PITCH 0x00000028 +#define SC1200_VBI_ODD_BASE 0x00000040 +#define SC1200_VBI_EVEN_BASE 0x00000044 +#define SC1200_VBI_PITCH 0x00000048 + +/* "SC1200_VIP_CONFIG" BIT DEFINITIONS */ + +#define SC1200_VIP_MODE_MASK 0x00000003 +#define SC1200_VIP_MODE_C 0x00000002 +#define SC1200_VBI_ANCILLARY_TO_MEMORY 0x000C0000 +#define SC1200_VBI_TASK_A_TO_MEMORY 0x00140000 +#define SC1200_VBI_TASK_B_TO_MEMORY 0x00240000 +#define SC1200_VIP_BUS_REQUEST_THRESHOLD 0x00400000 + +/* "SC1200_VIP_CONTROL" BIT DEFINITIONS */ + +#define SC1200_CAPTURE_RUN_MODE_MASK 0x00000003 +#define SC1200_CAPTURE_RUN_MODE_STOP_LINE 0x00000000 +#define SC1200_CAPTURE_RUN_MODE_STOP_FIELD 0x00000001 +#define SC1200_CAPTURE_RUN_MODE_START 0x00000003 +#define SC1200_VIP_DATA_CAPTURE_EN 0x00000100 +#define SC1200_VIP_VBI_CAPTURE_EN 0x00000200 +#define SC1200_VIP_VBI_FIELD_INTERRUPT_EN 0x00010000 + +/* "SC1200_VIP_STATUS" BIT DEFINITIONS */ + +#define SC1200_VIP_CURRENT_FIELD_ODD 0x01000000 +#define SC1200_VIP_BASE_NOT_UPDATED 0x00200000 +#define SC1200_VIP_FIFO_OVERFLOW 0x00100000 +#define SC1200_VIP_CLEAR_LINE_INT 0x00020000 +#define SC1200_VIP_CLEAR_FIELD_INT 0x00010000 +#define SC1200_VBI_DATA_CAPTURE_ACTIVE 0x00000200 +#define SC1200_VIDEO_DATA_CAPTURE_ACTIVE 0x00000100 + +/* "SC1200_VIP_CURRENT_LINE" BIT DEFINITIONS */ + +#define SC1200_VIP_CURRENT_LINE_MASK 0x000003FF + +/* "SC1200_VIP_LINE_TARGET" BIT DEFINITIONS */ + +#define SC1200_VIP_LAST_LINE_MASK 0x03FF0000 + +/* "SC1200_VIP_PITCH" BIT DEFINITION */ + +#define SC1200_VIP_PITCH_MASK 0x0000FFFC + +/* "SC1200_VBI_PITCH" BIT DEFINITION */ + +#define SC1200_VBI_PITCH_MASK 0x0000FFFC + +/* SC1200 DIRECT VBI LINE ENABLE BIT DEFINITION */ + +#define SC1200_DIRECT_VBI_LINE_ENABLE_MASK 0x00FFFFFF + +/* SC1200 CONFIGURATION BLOCK */ + +#define SC1200_CB_BASE_ADDR 0x9000 +#define SC1200_CB_WDTO 0x0000 +#define SC1200_CB_WDCNFG 0x0002 +#define SC1200_CB_WDSTS 0x0004 +#define SC1200_CB_TMVALUE 0x0008 +#define SC1200_CB_TMCNFG 0x000D +#define SC1200_CB_PMR 0x0030 +#define SC1200_CB_MCR 0x0034 +#define SC1200_CB_INTSEL 0x0038 +#define SC1200_CB_PID 0x003C +#define SC1200_CB_REV 0x003D + +/* SC1200 HIGH RESOLUTION TIMER CONFIGURATION REGISTER BITS */ + +#define SC1200_TMCLKSEL_27MHZ 0x2 + +/*---------------------------------*/ +/* PHILIPS SAA7114 VIDEO DECODER */ +/*---------------------------------*/ + +#define SAA7114_CHIPADDR 0x42 + +/* VIDEO DECODER REGISTER DEFINITIONS */ + +#define SAA7114_ANALOG_INPUT_CTRL1 0x02 +#define SAA7114_LUMINANCE_CONTROL 0x09 +#define SAA7114_BRIGHTNESS 0x0A +#define SAA7114_CONTRAST 0x0B +#define SAA7114_SATURATION 0x0C +#define SAA7114_HUE 0x0D +#define SAA7114_STATUS 0x1F +#define SAA7114_IPORT_CONTROL 0x86 + +/* TASK A REGISTER DEFINITIONS */ + +#define SAA7114_TASK_A_HORZ_OUTPUT_LO 0x9C +#define SAA7114_TASK_A_HORZ_OUTPUT_HI 0x9D +#define SAA7114_TASK_A_HSCALE_LUMA_LO 0xA8 +#define SAA7114_TASK_A_HSCALE_LUMA_HI 0xA9 +#define SAA7114_TASK_A_HSCALE_CHROMA_LO 0xAC +#define SAA7114_TASK_A_HSCALE_CHROMA_HI 0xAD + +/* TASK B REGISTER DEFINITIONS */ + +#define SAA7114_HORZ_OFFSET_LO 0xC4 +#define SAA7114_HORZ_OFFSET_HI 0xC5 +#define SAA7114_HORZ_INPUT_LO 0xC6 +#define SAA7114_HORZ_INPUT_HI 0xC7 +#define SAA7114_VERT_OFFSET_LO 0xC8 +#define SAA7114_VERT_OFFSET_HI 0xC9 +#define SAA7114_VERT_INPUT_LO 0xCA +#define SAA7114_VERT_INPUT_HI 0xCB +#define SAA7114_HORZ_OUTPUT_LO 0xCC +#define SAA7114_HORZ_OUTPUT_HI 0xCD +#define SAA7114_VERT_OUTPUT_LO 0xCE +#define SAA7114_VERT_OUTPUT_HI 0xCF +#define SAA7114_HORZ_PRESCALER 0xD0 +#define SAA7114_HORZ_ACL 0xD1 +#define SAA7114_HORZ_FIR_PREFILTER 0xD2 +#define SAA7114_FILTER_CONTRAST 0xD5 +#define SAA7114_FILTER_SATURATION 0xD6 +#define SAA7114_HSCALE_LUMA_LO 0xD8 +#define SAA7114_HSCALE_LUMA_HI 0xD9 +#define SAA7114_HSCALE_CHROMA_LO 0xDC +#define SAA7114_HSCALE_CHROMA_HI 0xDD +#define SAA7114_VSCALE_LUMA_LO 0xE0 +#define SAA7114_VSCALE_LUMA_HI 0xE1 +#define SAA7114_VSCALE_CHROMA_LO 0xE2 +#define SAA7114_VSCALE_CHROMA_HI 0xE3 +#define SAA7114_VSCALE_CONTROL 0xE4 +#define SAA7114_VSCALE_CHROMA_OFFS0 0xE8 +#define SAA7114_VSCALE_CHROMA_OFFS1 0xE9 +#define SAA7114_VSCALE_CHROMA_OFFS2 0xEA +#define SAA7114_VSCALE_CHROMA_OFFS3 0xEB +#define SAA7114_VSCALE_LUMINA_OFFS0 0xEC +#define SAA7114_VSCALE_LUMINA_OFFS1 0xED +#define SAA7114_VSCALE_LUMINA_OFFS2 0xEE +#define SAA7114_VSCALE_LUMINA_OFFS3 0xEF + + +/* Still need to determine PHO value (common phase offset) */ +#define SAA7114_VSCALE_PHO 0x00 + + +/*----------------------------------------------*/ +/* SECOND GENERATION GRAPHICS UNIT (REDCLOUD) */ +/*----------------------------------------------*/ + +#define MGP_DST_OFFSET 0x0000 /* dst address */ +#define MGP_SRC_OFFSET 0x0004 /* src address */ +#define MGP_VEC_ERR 0x0004 /* vector diag/axial errors */ +#define MGP_STRIDE 0x0008 /* src and dst strides */ +#define MGP_WID_HEIGHT 0x000C /* width and height of BLT */ +#define MGP_VEC_LEN 0x000C /* vector length/init error */ +#define MGP_SRC_COLOR_FG 0x0010 /* src mono data fgcolor */ +#define MGP_SRC_COLOR_BG 0x0014 /* src mono data bkcolor */ +#define MGP_PAT_COLOR_0 0x0018 /* pattern color 0 */ +#define MGP_PAT_COLOR_1 0x001C /* pattern color 1 */ +#define MGP_PAT_COLOR_2 0x0020 /* pattern color 2 */ +#define MGP_PAT_COLOR_3 0x0024 /* pattern color 3 */ +#define MGP_PAT_COLOR_4 0x0028 /* pattern color 4 */ +#define MGP_PAT_COLOR_5 0x002C /* pattern color 5 */ +#define MGP_PAT_DATA_0 0x0030 /* pattern data 0 */ +#define MGP_PAT_DATA_1 0x0034 /* pattern data 1 */ +#define MGP_RASTER_MODE 0x0038 /* raster operation */ +#define MGP_VECTOR_MODE 0x003C /* render vector */ +#define MGP_BLT_MODE 0x0040 /* render BLT */ +#define MGP_BLT_STATUS 0x0044 /* BLT status register */ +#define MGP_RESET 0x0044 /* reset register (write) */ +#define MGP_HST_SOURCE 0x0048 /* host src data (bitmap) */ +#define MGP_BASE_OFFSET 0x004C /* base render offset */ + +/* MGP_RASTER_MODE DEFINITIONS */ + +#define MGP_RM_BPPFMT_332 0x00000000 /* 8 BPP, 3:3:2 */ +#define MGP_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */ +#define MGP_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */ +#define MGP_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */ +#define MGP_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */ +#define MGP_RM_ALPHA_EN_MASK 0x00C00000 /* Alpha enable */ +#define MGP_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */ +#define MGP_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */ +#define MGP_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */ +#define MGP_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */ +#define MGP_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */ +#define MGP_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */ +#define MGP_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */ +#define MGP_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */ +#define MGP_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */ +#define MGP_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */ +#define MGP_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */ +#define MGP_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */ +#define MGP_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */ +#define MGP_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */ +#define MGP_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */ +#define MGP_RM_PAT_FLAGS 0x00000700 /* pattern related bits */ +#define MGP_RM_PAT_MONO 0x00000100 /* monochrome pattern */ +#define MGP_RM_PAT_COLOR 0x00000200 /* color pattern */ +#define MGP_RM_PAT_TRANS 0x00000400 /* pattern transparency */ +#define MGP_RM_SRC_TRANS 0x00000800 /* source transparency */ + +/* MGP_VECTOR_MODE DEFINITIONS */ + +#define MGP_VM_DST_REQ 0x00000008 /* dst data required */ +#define MGP_VM_THROTTLE 0x00000010 /* sync to VBLANK */ + +/* MGP_BLT_MODE DEFINITIONS */ + +#define MGP_BM_SRC_FB 0x00000001 /* src = frame buffer */ +#define MGP_BM_SRC_HOST 0x00000002 /* src = host register */ +#define MGP_BM_DST_REQ 0x00000004 /* dst data required */ +#define MGP_BM_SRC_MONO 0x00000040 /* monochrome source data */ +#define MGP_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */ +#define MGP_BM_NEG_YDIR 0x00000100 /* negative Y direction */ +#define MGP_BM_NEG_XDIR 0x00000200 /* negative X direction */ +#define MGP_BM_THROTTLE 0x00000400 /* sync to VBLANK */ + +/* MGP_BLT_STATUS DEFINITIONS */ + +#define MGP_BS_BLT_BUSY 0x00000001 /* GP is not idle */ +#define MGP_BS_BLT_PENDING 0x00000004 /* second BLT is pending */ +#define MGP_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */ + +/* ALPHA BLENDING MODES */ + +#define ALPHA_MODE_BLEND 0x00000000 + +/*---------------------------------------------------*/ +/* SECOND GENERATION DISPLAY CONTROLLER (REDCLOUD) */ +/*---------------------------------------------------*/ + +#define MDC_UNLOCK 0x00000000 /* Unlock register */ +#define MDC_GENERAL_CFG 0x00000004 /* Config registers */ +#define MDC_DISPLAY_CFG 0x00000008 +#define MDC_GFX_SCL 0x0000000C /* Graphics scaling */ + +#define MDC_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ +#define MDC_CB_ST_OFFSET 0x00000014 /* Compression start offset */ +#define MDC_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ +#define MDC_ICON_ST_OFFSET 0x0000001C /* Icon buffer start offset */ +#define MDC_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ +#define MDC_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ +#define MDC_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ +#define MDC_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ +#define MDC_GFX_PITCH 0x00000034 /* FB and DB skip counts */ +#define MDC_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ + +#define MDC_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ +#define MDC_H_BLANK_TIMING 0x00000044 +#define MDC_H_SYNC_TIMING 0x00000048 +#define MDC_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ +#define MDC_V_BLANK_TIMING 0x00000054 +#define MDC_V_SYNC_TIMING 0x00000058 + +#define MDC_CURSOR_X 0x00000060 /* Cursor X position */ +#define MDC_CURSOR_Y 0x00000064 /* Cursor Y Position */ +#define MDC_ICON_X 0x00000068 /* Icon X Position */ +#define MDC_LINE_CNT_STATUS 0x0000006C /* Icon Y Position */ + +#define MDC_PAL_ADDRESS 0x00000070 /* Palette Address */ +#define MDC_PAL_DATA 0x00000074 /* Palette Data */ +#define MDC_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ +#define MDC_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ + +#define MDC_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ + +#define MDC_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ +#define MDC_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ +#define MDC_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ + +/* UNLOCK VALUE */ + +#define MDC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* VG MBUS DEVICE SMI MSR FIELDS */ + +#define MDC_VG_BL_MASK 0x00000001 +#define MDC_MISC_MASK 0x00000002 +#define MDC_ISR0_MASK 0x00000004 +#define MDC_VGA_BL_MASK 0x00000008 +#define MDC_CRTCIO_MSK 0x00000010 +#define MDC_VG_BLANK_SMI 0x00000001 +#define MDC_MISC_SMI 0x00000002 +#define MDC_ISR0_SMI 0x00000004 +#define MDC_VGA_BLANK_SMI 0x00000008 +#define MDC_CRTCIO_SMI 0x00000010 + +/* MDC_GENERAL_CFG BIT FIELDS */ + +#define MDC_GCFG_DBUG 0x80000000 +#define MDC_GCFG_DBSL 0x40000000 +#define MDC_GCFG_CFRW 0x20000000 +#define MDC_GCFG_DIAG 0x10000000 +#define MDC_GCFG_GXRFS4 0x08000000 +#define MDC_GCFG_SGFR 0x04000000 +#define MDC_GCFG_SGRE 0x02000000 +#define MDC_GCFG_SIGE 0x01000000 +#define MDC_GCFG_YUVM 0x00100000 +#define MDC_GCFG_VDSE 0x00080000 +#define MDC_GCFG_VGAFT 0x00040000 +#define MDC_GCFG_FDTY 0x00020000 +#define MDC_GCFG_STFM 0x00010000 +#define MDC_GCFG_DFHPEL_MASK 0x0000F000 +#define MDC_GCFG_DFHPSL_MASK 0x00000F00 +#define MDC_GCFG_VGAE 0x00000080 +#define MDC_GCFG_DECE 0x00000040 +#define MDC_GCFG_CMPE 0x00000020 +#define MDC_GCFG_VIDE 0x00000008 +#define MDC_GCFG_ICNE 0x00000004 +#define MDC_GCFG_CURE 0x00000002 +#define MDC_GCFG_DFLE 0x00000001 + +/* MDC_DISPLAY_CFG BIT FIELDS */ + +#define MDC_DCFG_A20M 0x80000000 +#define MDC_DCFG_A18M 0x40000000 +#define MDC_DCFG_VISL 0x08000000 +#define MDC_DCFG_FRLK 0x04000000 +#define MDC_DCFG_PALB 0x02000000 +#define MDC_DCFG_PIX_PAN_MASK 0x00F00000 +#define MDC_DCFG_DCEN 0x00080000 +#define MDC_DCFG_16BPP_MODE_MASK 0x00000C00 +#define MDC_DCFG_16BPP 0x00000000 +#define MDC_DCFG_15BPP 0x00000400 +#define MDC_DCFG_12BPP 0x00000800 +#define MDC_DCFG_DISP_MODE_MASK 0x00000300 +#define MDC_DCFG_DISP_MODE_8BPP 0x00000000 +#define MDC_DCFG_DISP_MODE_16BPP 0x00000100 +#define MDC_DCFG_DISP_MODE_24BPP 0x00000200 +#define MDC_DCFG_SCLE 0x00000080 +#define MDC_DCFG_TRUP 0x00000040 +#define MDC_DCFG_VIEN 0x00000020 +#define MDC_DCFG_VDEN 0x00000010 +#define MDC_DCFG_GDEN 0x00000008 +#define MDC_DCFG_VCKE 0x00000004 +#define MDC_DCFG_PCKE 0x00000002 +#define MDC_DCFG_TGEN 0x00000001 + +/* MDC_LINE_CNT BIT FIELDS */ + +#define MDC_LNCNT_DNA 0x80000000 +#define MDC_LNCNT_VNA 0x40000000 +#define MDC_LNCNT_VSA 0x20000000 +#define MDC_LNCNT_VINT 0x10000000 +#define MDC_LNCNT_FLIP 0x08000000 +#define MDC_LNCNT_V_LINE_CNT 0x07FF0000 +#define MDC_LNCNT_VFLIP 0x00008000 +#define MDC_LNCNT_SIGC 0x00004000 +#define MDC_LNCNT_SS_LINE_CMP 0x000007FF + +/* MDC_FB_ST_OFFSET BIT FIELDS */ + +#define MDC_FB_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_CB_ST_OFFSET BIT FIELDS */ + +#define MDC_CB_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_CURS_ST_OFFSET BIT FIELDS */ + +#define MDC_CURS_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_ICON_ST_OFFSET BIT FIELDS */ + +#define MDC_ICON_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_Y_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_U_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_U_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_V_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_V_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_LINE_SIZE BIT FIELDS */ + +#define MDC_LINE_SIZE_VLS_MASK 0xFF000000 +#define MDC_LINE_SIZE_CBLS_MASK 0x007F0000 +#define MDC_LINE_SIZE_FBLS_MASK 0x000007FF + +/* MDC_GFX_PITCH BIT FIELDS */ + +#define MDC_GFX_PITCH_CBP_MASK 0xFFFF0000 +#define MDC_GFX_PITCH_FBP_MASK 0x0000FFFF + +/* MDC_VID_YUV_PITCH BIT FIELDS */ + +#define MDC_YUV_PITCH_UVP_MASK 0xFFFF0000 +#define MDC_YUV_PITCH_YBP_MASK 0x0000FFFF + +/* MDC_H_ACTIVE_TIMING BIT FIELDS */ + +#define MDC_HAT_HT_MASK 0x0FF80000 +#define MDC_HAT_HA_MASK 0x00000FF8 + +/* MDC_H_BLANK_TIMING BIT FIELDS */ + +#define MDC_HBT_HBE_MASK 0x0FF80000 +#define MDC_HBT_HBS_MASK 0x00000FF8 + +/* MDC_H_SYNC_TIMING BIT FIELDS */ + +#define MDC_HST_HSE_MASK 0x0FF80000 +#define MDC_HST_HSS_MASK 0x00000FF8 + +/* MDC_V_ACTIVE_TIMING BIT FIELDS */ + +#define MDC_VAT_VT_MASK 0x07FF0000 +#define MDC_VAT_VA_MASK 0x000007FF + +/* MDC_V_BLANK_TIMING BIT FIELDS */ + +#define MDC_VBT_VBE_MASK 0x07FF0000 +#define MDC_VBT_VBS_MASK 0x000007FF + +/* MDC_V_SYNC_TIMING BIT FIELDS */ + +#define MDC_VST_VSE_MASK 0x07FF0000 +#define MDC_VST_VSS_MASK 0x000007FF + +/* MDC_DV_CTL BIT DEFINITIONS */ + +#define MDC_DV_LINE_SIZE_MASK 0x00000C00 +#define MDC_DV_LINE_SIZE_1024 0x00000000 +#define MDC_DV_LINE_SIZE_2048 0x00000400 +#define MDC_DV_LINE_SIZE_4096 0x00000800 +#define MDC_DV_LINE_SIZE_8192 0x00000C00 + +/* VGA DEFINITIONS */ + +#define MDC_SEQUENCER_INDEX 0x03C4 +#define MDC_SEQUENCER_DATA 0x03C5 +#define MDC_SEQUENCER_RESET 0x00 +#define MDC_SEQUENCER_CLK_MODE 0x01 + +#define MDC_RESET_VGA_DISP_ENABLE 0x03 +#define MDC_CLK_MODE_SCREEN_OFF 0x20 + + +/*---------------------------------------------------*/ +/* REDCLOUD DISPLAY FILTER */ +/*---------------------------------------------------*/ + +/* RCDF VIDEO REGISTER DEFINITIONS */ + +#define RCDF_VIDEO_CONFIG 0x000 +#define RCDF_DISPLAY_CONFIG 0x008 +#define RCDF_VIDEO_X_POS 0x010 +#define RCDF_VIDEO_Y_POS 0x018 +#define RCDF_VIDEO_SCALE 0x020 +#define RCDF_VIDEO_COLOR_KEY 0x028 +#define RCDF_VIDEO_COLOR_MASK 0x030 +#define RCDF_PALETTE_ADDRESS 0x038 +#define RCDF_PALETTE_DATA 0x040 +#define RCDF_VID_MISC 0x050 +#define RCDF_VID_CLOCK_SELECT 0x058 +#define RCDF_VIDEO_DOWNSCALER_CONTROL 0x078 +#define RCDF_VIDEO_DOWNSCALER_COEFFICIENTS 0x080 +#define RCDF_VID_CRC 0x088 +#define RCDF_VID_CRC32 0x090 +#define RCDF_VID_ALPHA_CONTROL 0x098 +#define RCDF_CURSOR_COLOR_KEY 0x0A0 +#define RCDF_CURSOR_COLOR_MASK 0x0A8 +#define RCDF_CURSOR_COLOR_1 0x0B0 +#define RCDF_CURSOR_COLOR_2 0x0B8 +#define RCDF_ALPHA_XPOS_1 0x0C0 +#define RCDF_ALPHA_YPOS_1 0x0C8 +#define RCDF_ALPHA_COLOR_1 0x0D0 +#define RCDF_ALPHA_CONTROL_1 0x0D8 +#define RCDF_ALPHA_XPOS_2 0x0E0 +#define RCDF_ALPHA_YPOS_2 0x0E8 +#define RCDF_ALPHA_COLOR_2 0x0F0 +#define RCDF_ALPHA_CONTROL_2 0x0F8 +#define RCDF_ALPHA_XPOS_3 0x100 +#define RCDF_ALPHA_YPOS_3 0x108 +#define RCDF_ALPHA_COLOR_3 0x110 +#define RCDF_ALPHA_CONTROL_3 0x118 +#define RCDF_VIDEO_REQUEST 0x120 +#define RCDF_ALPHA_WATCH 0x128 +#define RCDF_VIDEO_TEST_MODE 0x210 +#define RCDF_POWER_MANAGEMENT 0x410 + +/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */ + +#define RCDF_PM_PANEL_POWER_ON 0x01000000 + +/* DISPLAY FILTER MSRS */ + +#define RCDF_MBD_MSR_DIAG_DF 0x2010 +#define RCDF_DIAG_32BIT_CRC 0x80000000 + +/* "RCDF_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define RCDF_VCFG_VID_EN 0x00000001 +#define RCDF_VCFG_VID_INP_FORMAT 0x0000000C +#define RCDF_VCFG_X_FILTER_EN 0x00000040 +#define RCDF_VCFG_Y_FILTER_EN 0x00000080 +#define RCDF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define RCDF_VCFG_INIT_READ_MASK 0x01FF0000 +#define RCDF_VCFG_LINE_SIZE_UPPER 0x08000000 +#define RCDF_VCFG_4_2_0_MODE 0x10000000 +#define RCDF_VCFG_UYVY_FORMAT 0x00000000 +#define RCDF_VCFG_Y2YU_FORMAT 0x00000004 +#define RCDF_VCFG_YUYV_FORMAT 0x00000008 +#define RCDF_VCFG_YVYU_FORMAT 0x0000000C + +/* "RCDF_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define RCDF_DCFG_DIS_EN 0x00000001 +#define RCDF_DCFG_HSYNC_EN 0x00000002 +#define RCDF_DCFG_VSYNC_EN 0x00000004 +#define RCDF_DCFG_DAC_BL_EN 0x00000008 +#define RCDF_DCFG_FP_PWR_EN 0x00000040 +#define RCDF_DCFG_FP_DATA_EN 0x00000080 +#define RCDF_DCFG_CRT_HSYNC_POL 0x00000100 +#define RCDF_DCFG_CRT_VSYNC_POL 0x00000200 +#define RCDF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define RCDF_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define RCDF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define RCDF_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define RCDF_DCFG_VG_CK 0x00100000 +#define RCDF_DCFG_GV_PAL_BYP 0x00200000 +#define RCDF_DAC_VREF 0x04000000 +#define RCDF_FP_ON_STATUS 0x08000000 + +/* "RCDF_VID_MISC" BIT DEFINITIONS */ + +#define RCDF_GAMMA_BYPASS_BOTH 0x00000001 +#define RCDF_DAC_POWER_DOWN 0x00000400 +#define RCDF_ANALOG_POWER_DOWN 0x00000800 + +/* "RCDF_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ + +#define RCDF_VIDEO_DOWNSCALE_ENABLE 0x00000001 +#define RCDF_VIDEO_DOWNSCALE_FACTOR_POS 1 +#define RCDF_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E +#define RCDF_VIDEO_DOWNSCALE_TYPE_A 0x00000000 +#define RCDF_VIDEO_DOWNSCALE_TYPE_B 0x00000040 +#define RCDF_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 + +/* "RCDF_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ + +#define RCDF_VIDEO_DOWNSCALER_COEF1_POS 0 +#define RCDF_VIDEO_DOWNSCALER_COEF2_POS 8 +#define RCDF_VIDEO_DOWNSCALER_COEF3_POS 16 +#define RCDF_VIDEO_DOWNSCALER_COEF4_POS 24 +#define RCDF_VIDEO_DOWNSCALER_COEF_MASK 0xF + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL */ + +#define RCDF_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define RCDF_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define RCDF_VIDEO_INPUT_IS_RGB 0x00002000 +#define RCDF_ALPHA1_PRIORITY_POS 16 +#define RCDF_ALPHA1_PRIORITY_MASK 0x00030000 +#define RCDF_ALPHA2_PRIORITY_POS 18 +#define RCDF_ALPHA2_PRIORITY_MASK 0x000C0000 +#define RCDF_ALPHA3_PRIORITY_POS 20 +#define RCDF_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS */ + +#define RCDF_CURSOR_COLOR_KEY_ENABLE 0x20000000 +#define RCDF_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define RCDF_CURSOR_COLOR_BITS 23 +#define RCDF_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define RCDF_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define RCDF_ACTRL_WIN_ENABLE 0x00010000 +#define RCDF_ACTRL_LOAD_ALPHA 0x00020000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define RCDF_VIDEO_Y_REQUEST_POS 0 +#define RCDF_VIDEO_X_REQUEST_POS 16 +#define RCDF_VIDEO_REQUEST_MASK 0x000007FF + +/* GEODELINK DEVICE MSR REGISTER SUMMARY */ + +#define MBD_MSR_CAP 0x2000 /* Device Capabilities */ +#define MBD_MSR_CONFIG 0x2001 /* Device Master Configuration Register */ +#define MBD_MSR_SMI 0x2002 /* MBus Device SMI Register */ +#define MBD_MSR_ERROR 0x2003 /* MBus Device Error */ +#define MBD_MSR_PM 0x2004 /* MBus Device Power Management Register */ +#define MBD_MSR_DIAG 0x2005 /* Mbus Device Diagnostic Register */ + +/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */ + +#define RCDF_MBD_DIAG_SEL0 0x00007FFF /* Lower 32-bits of Diag Bus Select */ +#define RCDF_MBD_DIAG_EN0 0x00008000 /* Enable for lower 32-bits of diag bus */ +#define RCDF_MBD_DIAG_SEL1 0x7FFF0000 /* Upper 32-bits of Diag Bus Select */ +#define RCDF_MBD_DIAG_EN1 0x80000000 /* Enable for upper 32-bits of diag bus */ + +/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */ + +#define RCDF_CONFIG_FMT_MASK 0x00000038 /* Output Format */ +#define RCDF_CONFIG_FMT_CRT 0x00000000 +#define RCDF_CONFIG_FMT_FP 0x00000008 + +/* MCP MSR DEFINITIONS */ + +#define MCP_CLKOFF 0x0010 +#define MCP_CLKACTIVE 0x0011 +#define MCP_CLKDISABLE 0x0012 +#define MCP_CLK4ACK 0x0013 +#define MCP_SYS_RSTPLL 0x0014 +#define MCP_DOTPLL 0x0015 +#define MCP_DBGCLKCTL 0x0016 +#define MCP_RC_REVID 0x0017 +#define MCP_SETM0CTL 0x0040 +#define MCP_SETN0CTL 0x0048 +#define MCP_CMPVAL0 0x0050 +#define MCP_CMPMASK0 0x0051 +#define MCP_REGA 0x0058 +#define MCP_REGB 0x0059 +#define MCP_REGAMASK 0x005A +#define MCP_REGAVAL 0x005B +#define MCP_REGBMASK 0x005C +#define MCP_REGBVAL 0x005D +#define MCP_FIFOCTL 0x005E +#define MCP_DIAGCTL 0x005F +#define MCP_H0CTL 0x0060 +#define MCP_XSTATE 0x0066 +#define MCP_YSTATE 0x0067 +#define MCP_ACTION0 0x0068 + +/* MCP_SYS_RSTPLL DEFINITIONS */ + +#define MCP_DOTPOSTDIV3 0x00000008 +#define MCP_DOTPREMULT2 0x00000004 +#define MCP_DOTPREDIV2 0x00000002 + +/* MCP MBD_MSR_DIAG DEFINITIONS */ + +#define MCP_MBD_DIAG_SEL0 0x00000007 +#define MCP_MBD_DIAG_EN0 0x00008000 +#define MCP_MBD_DIAG_SEL1 0x00070000 +#define MCP_MBD_DIAG_EN1 0x80000000 + +/* MCP_DOTPLL DEFINITIONS */ + +#define MCP_DOTPLL_P 0x00000003 +#define MCP_DOTPLL_N 0x000001FC +#define MCP_DOTPLL_M 0x00001E00 +#define MCP_DOTPLL_LOCK 0x02000000 +#define MCP_DOTPLL_BYPASS 0x00008000 + + +/*---------------------------------------------------*/ +/* THIRD GENERATION DISPLAY CONTROLLER (CASTLE) */ +/*---------------------------------------------------*/ + +#define DC3_UNLOCK 0x00000000 /* Unlock register */ +#define DC3_GENERAL_CFG 0x00000004 /* Config registers */ +#define DC3_DISPLAY_CFG 0x00000008 + +#define DC3_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ +#define DC3_CB_ST_OFFSET 0x00000014 /* Compression start offset */ +#define DC3_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ +#define DC3_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ +#define DC3_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ +#define DC3_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ +#define DC3_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ +#define DC3_GFX_PITCH 0x00000034 /* FB and DB skip counts */ +#define DC3_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ + +#define DC3_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ +#define DC3_H_BLANK_TIMING 0x00000044 +#define DC3_H_SYNC_TIMING 0x00000048 +#define DC3_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ +#define DC3_V_BLANK_TIMING 0x00000054 +#define DC3_V_SYNC_TIMING 0x00000058 + +#define DC3_CURSOR_X 0x00000060 /* Cursor X position */ +#define DC3_CURSOR_Y 0x00000064 /* Cursor Y Position */ +#define DC3_LINE_CNT_STATUS 0x0000006C /* Icon Y Position */ + +#define DC3_PAL_ADDRESS 0x00000070 /* Palette Address */ +#define DC3_PAL_DATA 0x00000074 /* Palette Data */ +#define DC3_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ +#define DC3_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ + +#define DC3_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ + +#define DC3_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ +#define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ +#define DC3_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ + +#define DC3_COLOR_KEY 0x000000B8 /* Graphics color key */ +#define DC3_COLOR_MASK 0x000000BC /* Graphics color key mask */ + +/* UNLOCK VALUE */ + +#define DC3_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* VG MBUS DEVICE SMI MSR FIELDS */ + +#define DC3_VG_BL_MASK 0x00000001 +#define DC3_MISC_MASK 0x00000002 +#define DC3_ISR0_MASK 0x00000004 +#define DC3_VGA_BL_MASK 0x00000008 +#define DC3_CRTCIO_MSK 0x00000010 +#define DC3_VG_BLANK_SMI 0x00000001 +#define DC3_MISC_SMI 0x00000002 +#define DC3_ISR0_SMI 0x00000004 +#define DC3_VGA_BLANK_SMI 0x00000008 +#define DC3_CRTCIO_SMI 0x00000010 + +/* DC3_GENERAL_CFG BIT FIELDS */ + +#define DC3_GCFG_DBUG 0x80000000 +#define DC3_GCFG_DBSL 0x40000000 +#define DC3_GCFG_CFRW 0x20000000 +#define DC3_GCFG_DIAG 0x10000000 +#define DC3_GCFG_GXRFS4 0x08000000 +#define DC3_GCFG_SGFR 0x04000000 +#define DC3_GCFG_SGRE 0x02000000 +#define DC3_GCFG_SIGE 0x01000000 +#define DC3_GCFG_YUVM 0x00100000 +#define DC3_GCFG_VDSE 0x00080000 +#define DC3_GCFG_VGAFT 0x00040000 +#define DC3_GCFG_FDTY 0x00020000 +#define DC3_GCFG_STFM 0x00010000 +#define DC3_GCFG_DFHPEL_MASK 0x0000F000 +#define DC3_GCFG_DFHPSL_MASK 0x00000F00 +#define DC3_GCFG_VGAE 0x00000080 +#define DC3_GCFG_DECE 0x00000040 +#define DC3_GCFG_CMPE 0x00000020 +#define DC3_GCFG_VIDE 0x00000008 +#define DC3_GCFG_ICNE 0x00000004 +#define DC3_GCFG_CURE 0x00000002 +#define DC3_GCFG_DFLE 0x00000001 + +/* DC3_DISPLAY_CFG BIT FIELDS */ + +#define DC3_DCFG_A20M 0x80000000 +#define DC3_DCFG_A18M 0x40000000 +#define DC3_DCFG_VISL 0x08000000 +#define DC3_DCFG_FRLK 0x04000000 +#define DC3_DCFG_PALB 0x02000000 +#define DC3_DCFG_PIX_PAN_MASK 0x00F00000 +#define DC3_DCFG_DCEN 0x00080000 +#define DC3_DCFG_16BPP_MODE_MASK 0x00000C00 +#define DC3_DCFG_16BPP 0x00000000 +#define DC3_DCFG_15BPP 0x00000400 +#define DC3_DCFG_12BPP 0x00000800 +#define DC3_DCFG_DISP_MODE_MASK 0x00000300 +#define DC3_DCFG_DISP_MODE_8BPP 0x00000000 +#define DC3_DCFG_DISP_MODE_16BPP 0x00000100 +#define DC3_DCFG_DISP_MODE_24BPP 0x00000200 +#define DC3_DCFG_SCLE 0x00000080 +#define DC3_DCFG_TRUP 0x00000040 +#define DC3_DCFG_VIEN 0x00000020 +#define DC3_DCFG_VDEN 0x00000010 +#define DC3_DCFG_GDEN 0x00000008 +#define DC3_DCFG_VCKE 0x00000004 +#define DC3_DCFG_PCKE 0x00000002 +#define DC3_DCFG_TGEN 0x00000001 + +/* DC3_LINE_CNT BIT FIELDS */ + +#define DC3_LNCNT_DNA 0x80000000 +#define DC3_LNCNT_VNA 0x40000000 +#define DC3_LNCNT_VSA 0x20000000 +#define DC3_LNCNT_VINT 0x10000000 +#define DC3_LNCNT_FLIP 0x08000000 +#define DC3_LNCNT_V_LINE_CNT 0x07FF0000 +#define DC3_LNCNT_VFLIP 0x00008000 +#define DC3_LNCNT_SIGC 0x00004000 +#define DC3_LNCNT_SS_LINE_CMP 0x000007FF + +/* DC3_FB_ST_OFFSET BIT FIELDS */ + +#define DC3_FB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CB_ST_OFFSET BIT FIELDS */ + +#define DC3_CB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CURS_ST_OFFSET BIT FIELDS */ + +#define DC3_CURS_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_ICON_ST_OFFSET BIT FIELDS */ + +#define DC3_ICON_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_Y_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_U_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_U_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_V_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_V_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_LINE_SIZE BIT FIELDS */ + +#define DC3_LINE_SIZE_VLS_MASK 0x3FF00000 +#define DC3_LINE_SIZE_CBLS_MASK 0x0007F000 +#define DC3_LINE_SIZE_FBLS_MASK 0x000003FF +#define DC3_LINE_SIZE_CB_SHIFT 12 +#define DC3_LINE_SIZE_VB_SHIFT 20 + +/* DC3_GFX_PITCH BIT FIELDS */ + +#define DC3_GFX_PITCH_CBP_MASK 0xFFFF0000 +#define DC3_GFX_PITCH_FBP_MASK 0x0000FFFF + +/* DC3_VID_YUV_PITCH BIT FIELDS */ + +#define DC3_YUV_PITCH_UVP_MASK 0xFFFF0000 +#define DC3_YUV_PITCH_YBP_MASK 0x0000FFFF + +/* DC3_H_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_HAT_HT_MASK 0x0FF80000 +#define DC3_HAT_HA_MASK 0x00000FF8 + +/* DC3_H_BLANK_TIMING BIT FIELDS */ + +#define DC3_HBT_HBE_MASK 0x0FF80000 +#define DC3_HBT_HBS_MASK 0x00000FF8 + +/* DC3_H_SYNC_TIMING BIT FIELDS */ + +#define DC3_HST_HSE_MASK 0x0FF80000 +#define DC3_HST_HSS_MASK 0x00000FF8 + +/* DC3_V_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_VAT_VT_MASK 0x07FF0000 +#define DC3_VAT_VA_MASK 0x000007FF + +/* DC3_V_BLANK_TIMING BIT FIELDS */ + +#define DC3_VBT_VBE_MASK 0x07FF0000 +#define DC3_VBT_VBS_MASK 0x000007FF + +/* DC3_V_SYNC_TIMING BIT FIELDS */ + +#define DC3_VST_VSE_MASK 0x07FF0000 +#define DC3_VST_VSS_MASK 0x000007FF + +/* DC3_DV_CTL BIT DEFINITIONS */ + +#define DC3_DV_LINE_SIZE_MASK 0x00000C00 +#define DC3_DV_LINE_SIZE_1024 0x00000000 +#define DC3_DV_LINE_SIZE_2048 0x00000400 +#define DC3_DV_LINE_SIZE_4096 0x00000800 +#define DC3_DV_LINE_SIZE_8192 0x00000C00 + +#define DC3_CLR_KEY_DATA_MASK 0x00FFFFFF +#define DC3_CLR_KEY_ENABLE 0x01000000 +#define DC3_CLR_KEY_INVERT 0x02000000 + +/* VGA DEFINITIONS */ + +#define DC3_SEQUENCER_INDEX 0x03C4 +#define DC3_SEQUENCER_DATA 0x03C5 +#define DC3_SEQUENCER_RESET 0x00 +#define DC3_SEQUENCER_CLK_MODE 0x01 + +#define DC3_RESET_VGA_DISP_ENABLE 0x03 +#define DC3_CLK_MODE_SCREEN_OFF 0x20 + +/*---------------------------------------------------*/ +/* CASTLE DISPLAY FILTER */ +/*---------------------------------------------------*/ + +/* CASTLE VIDEO REGISTER DEFINITIONS */ + +#define CASTLE_VIDEO_CONFIG 0x000 +#define CASTLE_DISPLAY_CONFIG 0x008 +#define CASTLE_VIDEO_X_POS 0x010 +#define CASTLE_VIDEO_Y_POS 0x018 +#define CASTLE_VIDEO_COLOR_KEY 0x028 +#define CASTLE_VIDEO_COLOR_MASK 0x030 +#define CASTLE_PALETTE_ADDRESS 0x038 +#define CASTLE_PALETTE_DATA 0x040 +#define CASTLE_VID_MISC 0x050 +#define CASTLE_VID_CLOCK_SELECT 0x058 +#define CASTLE_VIDEO_YSCALE 0x060 +#define CASTLE_VIDEO_XSCALE 0x068 +#define CASTLE_VIDEO_DOWNSCALER_CONTROL 0x078 +#define CASTLE_VID_CRC 0x088 +#define CASTLE_VID_CRC32 0x090 +#define CASTLE_VID_ALPHA_CONTROL 0x098 +#define CASTLE_CURSOR_COLOR_KEY 0x0A0 +#define CASTLE_CURSOR_COLOR_MASK 0x0A8 +#define CASTLE_CURSOR_COLOR_1 0x0B0 +#define CASTLE_CURSOR_COLOR_2 0x0B8 +#define CASTLE_ALPHA_XPOS_1 0x0C0 +#define CASTLE_ALPHA_YPOS_1 0x0C8 +#define CASTLE_ALPHA_COLOR_1 0x0D0 +#define CASTLE_ALPHA_CONTROL_1 0x0D8 +#define CASTLE_ALPHA_XPOS_2 0x0E0 +#define CASTLE_ALPHA_YPOS_2 0x0E8 +#define CASTLE_ALPHA_COLOR_2 0x0F0 +#define CASTLE_ALPHA_CONTROL_2 0x0F8 +#define CASTLE_ALPHA_XPOS_3 0x100 +#define CASTLE_ALPHA_YPOS_3 0x108 +#define CASTLE_ALPHA_COLOR_3 0x110 +#define CASTLE_ALPHA_CONTROL_3 0x118 +#define CASTLE_VIDEO_REQUEST 0x120 +#define CASTLE_ALPHA_WATCH 0x128 +#define CASTLE_VIDEO_TEST_MODE 0x210 +#define CASTLE_POWER_MANAGEMENT 0x410 + +/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */ + +#define CASTLE_PM_PANEL_POWER_ON 0x01000000 + +/* DISPLAY FILTER MSRS */ + +#define CASTLE_MBD_MSR_DIAG_DF 0x2010 +#define CASTLE_DIAG_32BIT_CRC 0x80000000 + +/* "CASTLE_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define CASTLE_VCFG_VID_EN 0x00000001 +#define CASTLE_VCFG_VID_INP_FORMAT 0x0000000C +#define CASTLE_VCFG_SCALER_BYPASS 0x00000020 +#define CASTLE_VCFG_X_FILTER_EN 0x00000040 +#define CASTLE_VCFG_Y_FILTER_EN 0x00000080 +#define CASTLE_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define CASTLE_VCFG_INIT_READ_MASK 0x01FF0000 +#define CASTLE_VCFG_LINE_SIZE_UPPER 0x08000000 +#define CASTLE_VCFG_4_2_0_MODE 0x10000000 +#define CASTLE_VCFG_UYVY_FORMAT 0x00000000 +#define CASTLE_VCFG_Y2YU_FORMAT 0x00000004 +#define CASTLE_VCFG_YUYV_FORMAT 0x00000008 +#define CASTLE_VCFG_YVYU_FORMAT 0x0000000C + +/* "CASTLE_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define CASTLE_DCFG_DIS_EN 0x00000001 +#define CASTLE_DCFG_HSYNC_EN 0x00000002 +#define CASTLE_DCFG_VSYNC_EN 0x00000004 +#define CASTLE_DCFG_DAC_BL_EN 0x00000008 +#define CASTLE_DCFG_FP_PWR_EN 0x00000040 +#define CASTLE_DCFG_FP_DATA_EN 0x00000080 +#define CASTLE_DCFG_CRT_HSYNC_POL 0x00000100 +#define CASTLE_DCFG_CRT_VSYNC_POL 0x00000200 +#define CASTLE_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define CASTLE_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define CASTLE_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define CASTLE_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define CASTLE_DCFG_VG_CK 0x00100000 +#define CASTLE_DCFG_GV_PAL_BYP 0x00200000 +#define CASTLE_DAC_VREF 0x04000000 +#define CASTLE_FP_ON_STATUS 0x08000000 + +/* "CASTLE_VID_MISC" BIT DEFINITIONS */ + +#define CASTLE_GAMMA_BYPASS_BOTH 0x00000001 +#define CASTLE_DAC_POWER_DOWN 0x00000400 +#define CASTLE_ANALOG_POWER_DOWN 0x00000800 + +/* "CASTLE_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ + +#define CASTLE_VIDEO_DOWNSCALE_ENABLE 0x00000001 +#define CASTLE_VIDEO_DOWNSCALE_FACTOR_POS 1 +#define CASTLE_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E +#define CASTLE_VIDEO_DOWNSCALE_TYPE_A 0x00000000 +#define CASTLE_VIDEO_DOWNSCALE_TYPE_B 0x00000040 +#define CASTLE_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 + +/* "CASTLE_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ + +#define CASTLE_VIDEO_DOWNSCALER_COEF1_POS 0 +#define CASTLE_VIDEO_DOWNSCALER_COEF2_POS 8 +#define CASTLE_VIDEO_DOWNSCALER_COEF3_POS 16 +#define CASTLE_VIDEO_DOWNSCALER_COEF4_POS 24 +#define CASTLE_VIDEO_DOWNSCALER_COEF_MASK 0xF + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL */ + +#define CASTLE_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define CASTLE_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define CASTLE_VIDEO_INPUT_IS_RGB 0x00002000 +#define CASTLE_ALPHA1_PRIORITY_POS 16 +#define CASTLE_ALPHA1_PRIORITY_MASK 0x00030000 +#define CASTLE_ALPHA2_PRIORITY_POS 18 +#define CASTLE_ALPHA2_PRIORITY_MASK 0x000C0000 +#define CASTLE_ALPHA3_PRIORITY_POS 20 +#define CASTLE_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS */ + +#define CASTLE_CURSOR_COLOR_KEY_ENABLE 0x20000000 +#define CASTLE_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define CASTLE_CURSOR_COLOR_BITS 23 +#define CASTLE_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define CASTLE_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define CASTLE_ACTRL_WIN_ENABLE 0x00010000 +#define CASTLE_ACTRL_LOAD_ALPHA 0x00020000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define CASTLE_VIDEO_Y_REQUEST_POS 0 +#define CASTLE_VIDEO_X_REQUEST_POS 16 +#define CASTLE_VIDEO_REQUEST_MASK 0x000007FF + +/* END OF FILE */ + diff --git a/Source/DirectFB/gfxdrivers/nsc/include/gfx_type.h b/Source/DirectFB/gfxdrivers/nsc/include/gfx_type.h new file mode 100755 index 0000000..71be2d9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/include/gfx_type.h @@ -0,0 +1,426 @@ +/* + * $Workfile: gfx_type.h $ + * + * This header file defines the pneumonics used when calling Durango routines. + * This file is automatically included by gfx_rtns.h + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + + +#ifndef _gfx_type_h +#define _gfx_type_h + +/* MSR DEFINITIONS */ + +typedef enum DevStatus { FOUND, NOT_KNOWN, REQ_NOT_FOUND, REQ_NOT_INSTALLED } DEV_STATUS; + +typedef struct msr { + DEV_STATUS Present; /* Node enumeration status */ + unsigned char Id; /* Device ID (from MSR specs) */ + unsigned long Address; /* Address - 32-bit MBus address at which 'Id' is found */ +} MSR; + +typedef struct mValue { + unsigned long high; + unsigned long low; +} Q_WORD; + +typedef struct mbusNode { + unsigned long address; + unsigned int deviceId; + unsigned int claimed; +} MBUS_NODE; + +/* MSR ARRAY INDEXES */ +/* These are indexes into the array of MBus devices. These */ +/* should not be confused with the class codes at MSR register */ +/* 0x2000. */ + +#define RC_ID_MBIU0 0x00 +#define RC_ID_MBIU1 0x01 +#define RC_ID_MCP 0x02 +#define RC_ID_MPCI 0x03 +#define RC_ID_MC 0x04 +#define RC_ID_GP 0x05 +#define RC_ID_VG 0x06 +#define RC_ID_DF 0x07 +#define RC_ID_FG 0x08 +#define RC_ID_VA 0x09 +#define CP_ID_MBIU 0x0A +#define CP_ID_MPCI 0x0B +#define CP_ID_USB2 0x0C +#define CP_ID_ATAC 0x0D +#define CP_ID_MDD 0x0E +#define CP_ID_ACC 0x0F +#define CP_ID_USB1 0x10 +#define CP_ID_MCP 0x11 + +/* MBUS DEVICE CLASS CODES */ +/* These are the device ids for the known Redcloud MBus devices. */ + +#define RC_CC_MBIU 0x01 +#define RC_CC_MCP 0x02 +#define RC_CC_MPCI 0x05 +#define RC_CC_MC 0x20 +#define RC_CC_GP 0x3D +#define RC_CC_VG 0x3E +#define RC_CC_DF 0x3F +#define RC_CC_FG 0xF0 +#define RC_CC_VA 0x86 +#define CP_CC_MBIU 0x01 +#define CP_CC_MPCI 0x05 +#define CP_CC_USB2 0x42 +#define CP_CC_ATAC 0x47 +#define CP_CC_MDD 0xDF +#define CP_CC_ACC 0x33 +#define CP_CC_USB1 0x42 +#define CP_CC_MCP 0x02 + +/* VAIL AND MBIUS ARE AT KNOWN ADDRESSES */ +/* We can initialize the addresses of these devices in advance, */ +/* as their location should never change. */ + +#define RC_MB0_MBIU0 0x10000000 +#define RC_MB0_MBIU1 0x40000000 +#define CP_MB0_MBIU0 0x51010000 +#define RC_MB0_CPU 0x00000000 +#define FAKE_ADDRESS 0xFFFFFFFF + +/* MSR PORT DESCRIPTORS */ + +#define NOT_POPULATED 0 +#define NOT_INSTALLED 0xFFFE +#define REFLECTIVE 0xFFFF + +/* CRC DATA SOURCES */ + +#define CRC_SOURCE_GFX_DATA 0x00 +#define CRC_SOURCE_CRT_RGB 0x01 +#define CRC_SOURCE_FP_DATA 0x02 + + +/* TV DEFINITIONS */ + +typedef enum TVStandardType { + TV_STANDARD_NTSC = 1, + TV_STANDARD_PAL +} TVStandardType; + +typedef enum GfxOnTVType { + GFX_ON_TV_SQUARE_PIXELS = 1, + GFX_ON_TV_NO_SCALING +} GfxOnTVType; + +#define CRT_DISABLE 0x00 +#define CRT_ENABLE 0x01 +#define CRT_STANDBY 0x02 +#define CRT_SUSPEND 0x03 + +#define TV_OUTPUT_COMPOSITE 0x01 +#define TV_OUTPUT_S_VIDEO 0x02 +#define TV_OUTPUT_YUV 0x03 +#define TV_OUTPUT_SCART 0x04 + +#define TV_FLICKER_FILTER_NONE 0x01 +#define TV_FLICKER_FILTER_NORMAL 0x02 +#define TV_FLICKER_FILTER_INTERLACED 0x03 + +#define TV_YC_DELAY_NONE 0x01 +#define TV_Y_DELAY_ONE_PIXEL 0x02 +#define TV_C_DELAY_ONE_PIXEL 0x03 +#define TV_C_DELAY_TWO_PIXELS 0x04 + +#define TV_SUB_CARRIER_RESET_NEVER 0x01 +#define TV_SUB_CARRIER_RESET_EVERY_TWO_LINES 0x02 +#define TV_SUB_CARRIER_RESET_EVERY_TWO_FRAMES 0x03 +#define TV_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES 0x04 + +#define TVENC_RESET_EVERY_ODD_FIELD 0x01 +#define TVENC_RESET_EVERY_EVEN_FIELD 0x02 +#define TVENC_RESET_NEXT_ODD_FIELD 0x03 +#define TVENC_RESET_NEXT_EVEN_FIELD 0x04 +#define TVENC_RESET_EVERY_FIELD 0x05 +#define TVENC_RESET_EVERY_X_ODD_FIELDS 0x06 +#define TVENC_RESET_EVERY_X_EVEN_FIELDS 0x07 + +/* VBI FORMATS */ + +#define VBI_FORMAT_VIDEO 0x1 +#define VBI_FORMAT_RAW 0x2 +#define VBI_FORMAT_CC 0x4 +#define VBI_FORMAT_NABTS 0x8 + +/* VIDEO DEFINITIONS */ + +#define VIDEO_FORMAT_UYVY 0x0 +#define VIDEO_FORMAT_Y2YU 0x1 +#define VIDEO_FORMAT_YUYV 0x2 +#define VIDEO_FORMAT_YVYU 0x3 +#define VIDEO_FORMAT_Y0Y1Y2Y3 0x4 +#define VIDEO_FORMAT_Y3Y2Y1Y0 0x5 +#define VIDEO_FORMAT_Y1Y0Y3Y2 0x6 +#define VIDEO_FORMAT_Y1Y2Y3Y0 0x7 +#define VIDEO_FORMAT_RGB 0x8 +#define VIDEO_FORMAT_P2M_P2L_P1M_P1L 0x9 +#define VIDEO_FORMAT_P1M_P1L_P2M_P2L 0xA +#define VIDEO_FORMAT_P1M_P2L_P2M_P1L 0xB + +#define VIDEO_DOWNSCALE_KEEP_1_OF 0x1 +#define VIDEO_DOWNSCALE_DROP_1_OF 0x2 + +typedef enum VideoSourceType { /* The source from which the video processor shows full screen video */ + VIDEO_SOURCE_MEMORY = 1, + VIDEO_SOURCE_DVIP +} VideoSourceType; + +typedef enum VbiSourceType { /* The source from which the video processor takes VBI */ + VBI_SOURCE_MEMORY = 1, + VBI_SOURCE_DVIP +} VbiSourceType; + +/* GENLOCK DEFINITIONS */ + +#define GENLOCK_SINGLE 0x001 +#define GENLOCK_FIELD_SYNC 0x001 +#define GENLOCK_CONTINUOUS 0x002 +#define GENLOCK_SYNCED_EDGE_FALLING 0x004 +#define GENLOCK_SYNCING_EDGE_FALLING 0x008 +#define GENLOCK_TIMEOUT 0x010 +#define GENLOCK_TVENC_RESET_EVEN_FIELD 0x020 +#define GENLOCK_TVENC_RESET_BEFORE_DELAY 0x040 +#define GENLOCK_TVENC_RESET 0x080 +#define GENLOCK_SYNC_TO_TVENC 0x100 + +/* VIP DEFINITIONS */ + +#define VIP_MODE_C 0x1 + +#define VIP_CAPTURE_STOP_LINE 0x1 +#define VIP_CAPTURE_STOP_FIELD 0x2 +#define VIP_CAPTURE_START_FIELD 0x4 + +#define VBI_ANCILLARY 0x1 +#define VBI_TASK_A 0x2 +#define VBI_TASK_B 0x4 + +/* VGA STRUCTURE */ + +#define GFX_STD_CRTC_REGS 25 +#define GFX_EXT_CRTC_REGS 16 + +#define GFX_VGA_FLAG_MISC_OUTPUT 0x00000001 +#define GFX_VGA_FLAG_STD_CRTC 0x00000002 +#define GFX_VGA_FLAG_EXT_CRTC 0x00000004 + +/* FS450 TV Standard flags */ + +#define GFX_TV_STANDARD_NTSC_M 0x0001 +#define GFX_TV_STANDARD_NTSC_M_J 0x0002 +#define GFX_TV_STANDARD_PAL_B 0x0004 +#define GFX_TV_STANDARD_PAL_D 0x0008 +#define GFX_TV_STANDARD_PAL_H 0x0010 +#define GFX_TV_STANDARD_PAL_I 0x0020 +#define GFX_TV_STANDARD_PAL_M 0x0040 +#define GFX_TV_STANDARD_PAL_N 0x0080 +#define GFX_TV_STANDARD_PAL_G 0x0100 + +/* FS450 VGA Mode flags */ + +#define GFX_VGA_MODE_UNKNOWN 0 +#define GFX_VGA_MODE_640X480 0x0001 +#define GFX_VGA_MODE_720X487 0x0002 +#define GFX_VGA_MODE_720X576 0x0004 +#define GFX_VGA_MODE_800X600 0x0008 +#define GFX_VGA_MODE_1024X768 0x0010 + +/* FS450 TVout mode flags */ + +#define GFX_TVOUT_MODE_CVBS 0x0001 +#define GFX_TVOUT_MODE_YC 0x0002 +#define GFX_TVOUT_MODE_RGB 0x0004 +#define GFX_TVOUT_MODE_CVBS_YC (GFX_TVOUT_MODE_CVBS | GFX_TVOUT_MODE_YC) + +/* FS450 Luma and Chroma Filters */ + +#define GFX_LUMA_FILTER 0x0001 +#define GFX_CHROMA_FILTER 0x0002 + +/* APS Trigger Bits */ + +#define GFX_APS_TRIGGER_OFF 0 +#define GFX_APS_TRIGGER_AGC_ONLY 1 +#define GFX_APS_TRIGGER_AGC_2_LINE 2 +#define GFX_APS_TRIGGER_AGC_4_LINE 3 + +typedef struct { + int xsize; + int ysize; + int hz; + int clock; + unsigned char miscOutput; + unsigned char stdCRTCregs[GFX_STD_CRTC_REGS]; + unsigned char extCRTCregs[GFX_EXT_CRTC_REGS]; +} gfx_vga_struct; + +/* POSSIBLE STATUS VALUES */ + +#define GFX_STATUS_UNSUPPORTED (-3) +#define GFX_STATUS_BAD_PARAMETER (-2) +#define GFX_STATUS_ERROR (-1) +#define GFX_STATUS_OK 0 + +/* CPU AND VIDEO TYPES */ + +#define GFX_CPU_GXLV 1 +#define GFX_CPU_SC1200 2 +#define GFX_CPU_REDCLOUD 3 +#define GFX_CPU_PYRAMID 0x20801 + + +#define GFX_VID_CS5530 1 +#define GFX_VID_SC1200 2 +#define GFX_VID_REDCLOUD 3 + +/* CHIP NAME AND REVISION */ + +typedef enum ChipType { + CHIP_NOT_DETECTED, + SC1200_REV_A, + SC1200_REV_B1_B2, + SC1200_REV_B3, + SC1200_REV_C1, + SC1200_REV_D1, + SC1200_REV_D1_1, + SC1200_REV_D2_MVD, /* Macrovision disabled */ + SC1200_REV_D2_MVE, /* Macrovision enabled */ + SC1200_FUTURE_REV +} ChipType; + +#endif /* !_gfx_type_h */ diff --git a/Source/DirectFB/gfxdrivers/nsc/include/nsc_galproto.h b/Source/DirectFB/gfxdrivers/nsc/include/nsc_galproto.h new file mode 100755 index 0000000..67266cc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/include/nsc_galproto.h @@ -0,0 +1,1987 @@ +/* + * $Workfile: nsc_galproto.h $ + * $Revision: 1.3 $ + * + * File Contents: This file contains the main functions of the Geode + * frame buffer device drivers GAL function prototypes and + * data structures. + * + * Project: Geode Frame buffer device driver + * + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + +#ifndef __GALPROTO_SEP_20_2000 +#define __GALPROTO_SEP_20_2000 + +/* durango reg definitions and type's */ +#include +#include + +/* Panel related definition */ +#include + +typedef int SWORD; +typedef unsigned int DWORD; +typedef unsigned short WORD; +typedef unsigned char CHAR; +typedef unsigned char BOOLEAN; +typedef unsigned int *PDWORD; + +/***************************************/ +/* Applications/User mode drivers use this ioctl to + * send a graphics device request to the frame buffer + * driver + */ +#define FBIOGAL_API 0x4700 + +/* + * Applications must sign the I/O packet with this value + */ + +#define FBGAL_SIGNATURE 0xC0C0BABE + +/* + * Version is a 16:16 fixed value + * Current version is 1.0000 + */ + +#define FBGAL_VERSION 0x10000 + +/* + * Definitions for Graphics Subfunctions + * + */ + +typedef enum GALFN_CODES +{ +/* General Adapter level functions */ + GALFN_GETADAPTERINFO = 0, + GALFN_SETSOFTVGASTATE, + GALFN_GETSOFTVGASTATE, + GALFN_WAITUNTILIDLE, + GALFN_WAITVERTICALBLANK, + GALFN_SETCRTENABLE, + GALFN_WRITEREG, + GALFN_READREG, + +/* Change/Get Display hardware state */ + + GALFN_ISDISPLAYMODESUPPORTED, + GALFN_SETDISPLAYMODE, + GALFN_GETDISPLAYMODE, + GALFN_SETBPP, + GALFN_SETDISPLAYBPP, + GALFN_GETDISPLAYBPP, + GALFN_SETDISPLAYPITCH, + GALFN_GETDISPLAYPITCH, + GALFN_SETDISPLAYOFFSET, + GALFN_GETDISPLAYOFFSET, + GALFN_DOTCLKTOREFRESH, + GALFN_GETDISPLAYTIMINGS, + GALFN_SETDISPLAYTIMINGS, + GALFN_SETPALETTE, + GALFN_GETPALETTE, + GALFN_SETPALETTE_ENTRY, + GALFN_GETPALETTE_ENTRY, + GALFN_SETFIXEDTIMINGS, + +/* Hardware cursor funtions */ + + GALFN_SETCURSORENABLE, + GALFN_GETCURSORENABLE, + GALFN_SETCURSORPOSITION, + GALFN_GETCURSORPOSITION, + GALFN_SETCURSORCOLORS, + GALFN_GETCURSORCOLORS, + GALFN_SETCURSORSHAPE, + GALFN_SETCURSORSHAPE_RCLD, + +/* grafix rendering funtions */ + GALFN_SETSOLIDPATTERN, + GALFN_SETRASTEROPERATION, + GALFN_SETSOLIDSOURCE, + GALFN_PATTERNFILL, + GALFN_SETMONOSOURCE, + GALFN_SETMONOPATTERN, + GALFN_SCREENTOSCREENBLT, + GALFN_SCREENTOSCREENXBLT, + GALFN_BRESENHAMLINE, + GALFN_COLOR_PATTERNFILL, + GALFN_COLOR_BITMAP_TO_SCREEN_BLT, + GALFN_COLOR_BITMAP_TO_SCREEN_XBLT, + GALFN_MONO_BITMAP_TO_SCREEN_BLT, + GALFN_TEXT_BLT, + +/* VGA Support functions */ + + GALFN_VGAMODESWITCH, + GALFN_VGACLEARCRTEXT, + GALFN_VGASETPITCH, + GALFN_VGARESTORE, + GALFN_VGASAVE, + GALFN_VGASETMODE, + +/* Compression functions */ + GALFN_SETCOMPRESSIONSTATE, + GALFN_GETCOMPRESSIONSTATE, + GALFN_SETCOMPRESSIONPARAMS, + GALFN_GETCOMPRESSIONPARAMS, + +/* Panel Support functions */ + + GALFN_PNLSETPARAMS, + GALFN_PNLGETPARAMS, + GALFN_PNLINITPANEL, + GALFN_PNLSAVESTATE, + GALFN_PNLRESTORESTATE, + GALFN_PNLPOWERUP, + GALFN_PNLPOWERDOWN, + GALFN_PNLBIOSENABLE, + GALFN_PNLBIOSINFO, + GALFN_ENABLEPANNING, + +/* TV Support functions */ + + GALFN_SETTVPARAMS, + GALFN_GETTVPARAMS, + GALFN_SETTVTIMING, + GALFN_GETTVTIMING, + GALFN_SETENABLE, + GALFN_GETENABLE, + GALFN_ISTVMODESUPPORTED, + +/* Video Support functions */ + + GALFN_SETVIDEOENABLE, + GALFN_SETVIDEOFORMAT, + GALFN_SETVIDEOSIZE, + GALFN_SETVIDEOOFFSET, + GALFN_SETVIDEOWINDOW, + GALFN_SETVIDEOSCALE, + GALFN_SETVIDEOFILTER, + GALFN_SETVIDEOCOLORKEY, + GALFN_SETVIDEODOWNSCALEENABLE, + GALFN_SETVIDEODOWNSCALECONFIG, + GALFN_SETVIDEODOWNSCALECOEFF, + GALFN_SETVIDEOSOURCE, + GALFN_SETVIDEOINTERLACED, + GALFN_SETVIDEOCURSOR, + GALFN_SETVIDEOREQUEST, + GALFN_SETALPHAENABLE, + GALFN_SETALPHAWINDOW, + GALFN_SETALPHAVALUE, + GALFN_SETALPHAPRIORITY, + GALFN_SETALPHACOLOR, + GALFN_SETALPHAREGION, + GALFN_SETVIDEOOUTSIDEALPHA, + GALFN_SETVIDEOPALETTE, + GALFN_GETVIDEOINFO, + GALFN_SETVIDEOCOLORSPACE, + +/* VIP Supported functions */ + + GALFN_SETVIPENABLE, + GALFN_SETVIPCAPTURERUNMODE, + GALFN_SETVIPBASE, + GALFN_SETVIPPITCH, + GALFN_SETVIPMODE, + GALFN_SETVIPBRTH, + GALFN_SETVIPLASTLINE, + GALFN_TESTVIPODDFIELD, + GALFN_TESTVIPBASESUPDATED, + GALFN_SETVBIENABLE, + GALFN_SETVBIMODE, + GALFN_SETVBIBASE, + GALFN_SETVBIPITCH, + GALFN_SETVBIDIRECT, + GALFN_SETVBIINTERRUPT, + GALFN_SETGENLOCKENABLE, + GALFN_SETTOPLINEINODD, + GALFN_SETGENLOCKDELAY, + GALFN_SETMACROVISIONENABLE, + + GALFN_GETVIPENABLE, + GALFN_GETVIPBASE, + GALFN_GETVIPPITCH, + GALFN_GETVIPMODE, + GALFN_GETVIPBRTH, + GALFN_GETVIPLINE, + GALFN_GETVBIENABLE, + GALFN_GETVBIBASE, + GALFN_GETVBIPITCH, + GALFN_GETVBIMODE, + GALFN_GETVBIDIRECT, + GALFN_GETVBIINTERRUPT, + GALFN_TESTVIPFIFOOVERFLOW, + +/* Second generation rendering routines */ + + GALFN_SETICONENABLE, + GALFN_SETICONCOLORS, + GALFN_SETICONPOSITION, + GALFN_SETICONSHAPE64, + + GALFN_SETSOURCESTRIDE, + GALFN_SETDESTINATIONSTRIDE, + GALFN_SETSOURCETRANSPARENCY, + GALFN_SETPATTERNORIGIN, + GALFN_GFX2SETALPHAMODE, + GALFN_GFX2SETALPHAVALUE, + GALFN_GFX2PATTERNFILL, + GALFN_GFX2COLORPATTERNFILL, + GALFN_GFX2SCREENTOSCREENBLT, + GALFN_GFX2MONOEXPANDBLT, + GALFN_GFX2COLORBMPTOSCRBLT, + GALFN_GFX2MONOBMPTOSCRBLT, + GALFN_GFX2TEXTBLT, + GALFN_GFX2BRESENHAMLINE, + GALFN_GFX2SYNCTOVBLANK, + +/* Change/Get Video routines */ + + GALFN_SETCOLORSPACEYUV, + GALFN_SETVIDEOYUVPITCH, + GALFN_SETVIDEOYUVOFFSETS, + GALFN_SETVIDEOLEFTCROP, + GALFN_SETVIDEOVERTICALDOWNSCALE, + GALFN_SETVBISOURCE, + GALFN_SETVBILINES, + GALFN_SETVBITOTAL, + GALFN_SETVSCALEROFFSET, + + GALFN_GETVBISOURCE, + GALFN_GETVBILINES, + GALFN_GETVBITOTAL, + GALFN_GETVSCALEROFFSET, + GALFN_GETVIDEOINTERLACED, + GALFN_GETCOLORSPACEYUV, + GALFN_GETGENLOCKENABLE, + GALFN_GETGENLOCKDELAY, + GALFN_GETVIDEOCURSOR, + GALFN_READCRC, + GALFN_READWINDOWCRC, + GALFN_GETMACROVISIONENABLE, + GALFN_GETALPHAENABLE, + GALFN_GETALPHASIZE, + GALFN_GETALPHAVALUE, + GALFN_GETALPHAPRIORITY, + GALFN_GETALPHACOLOR, + GALFN_GETVIDEOYUVPITCH, + GALFN_GETVIDEOYUVOFFSETS, + +/* Additional VGA Support functions */ + + GALFN_VGATESTPCI, + GALFN_VGAGETPCICOMMAND, + GALFN_VGASEQRESET, + GALFN_VGASETGRAPHICSBITS, + +/* This is last function supported. + * If you want to define ioctl function. + * You should define before this function. + * Update that the lastfunction supported to new value. + */ + GALFN_LASTFUNCTION_SUPPORTED +} +GALFN_CODES; + +/* end of GAL function list */ + +#define GAL_HEADER\ + DWORD dwSignature; /* Sign all structs with FBGAL_SIGNATURE */\ + DWORD dwSize; /* Size of struct for that subfunction */\ + DWORD dwVersion; /* Current version of the API */\ + DWORD dwSubfunction; /* GAL subfunction */\ + DWORD dwReturnValue; /* Return value from subfunction */ + +/* + * #define GALFN_PNLPOWERUP + * #define GALFN_PNLPOWERDOWN + */ +typedef struct __GAL_BASE +{ +GAL_HEADER} +GAL_BASE, *PGAL_BASE; + +/* + * #define GALFN_GETADAPTERINFO + */ +typedef struct __GAL_GETADAPTERINFO +{ + GAL_HEADER DWORD dwCPUVersion; + DWORD dwCPUType; + DWORD dwFrameBufferBase; + DWORD dwFrameBufferSize; + DWORD dwGfxRegisterBase; + DWORD dwGpsRegisterBase; + DWORD dwVidRegisterBase; + DWORD dwVipRegisterBase; + DWORD dwVideoVersion; + DWORD dwMaxSupportedPixelClock; + +} +GAL_ADAPTERINFO, *PGAL_ADAPTERINFO; + +#define GAL_SOFTVGASTATE_ENABLE 1 +#define GAL_SOFTVGASTATE_DISABLE 0 +/* + * #define GALFN_SOFTVGASTATE + */ +typedef struct __GAL_SOFTVGASTATE +{ + GAL_HEADER BOOLEAN bSoftVgaEnable; + +} +GAL_SOFTVGASTATE, *PGAL_SOFTVGASTATE; + +/* + * #define GALFN_WAITUNTILIDLE + */ +typedef struct __GAL_WAITUNTILIDLE +{ +GAL_HEADER} +GAL_WAITUNTILIDLE, *PGAL_WAITUNTILIDLE; + +/* + * #define GALFN_WAITVERTICALBLANK + */ +typedef struct __GAL_WAITVERTICALBLANK +{ +GAL_HEADER} +GAL_WAITVERTICALBLANK, *PGAL_WAITVERTICALBLANK; + +#define GAL_REG 0x1 +#define GAL_VID 0x2 +#define GAL_VIP 0x4 +/* + * #define GALFN_WRITEREG + * #define GALFN_READREG + */ +typedef struct __GAL_HWACCESS +{ + GAL_HEADER DWORD dwType; + DWORD dwOffset; + DWORD dwValue; + DWORD dwByteCount; + +} +GAL_HWACCESS, *PGAL_HWACCESS; + +/* + * #define GALFN_ISDISPLAYMODESUPPORTED + * #define GALFN_SETDISPLAYMODE + * #define GALFN_GETDISPLAYMODE + */ +typedef struct __GAL_DISPLAYMODE +{ + GAL_HEADER WORD wXres; + WORD wYres; + WORD wBpp; + WORD wRefresh; + DWORD dwSupported; + +} +GAL_DISPLAYMODE, *PGAL_DISPLAYMODE; + +/* + * #define GALFN_SETBPP + * #define GALFN_GETBPP + * #define GALFN_SETPITCH + * #define GALFN_GETPITCH + * #define GALFN_SETOFFSET + * #define GALFN_GETOFFSET + */ +typedef struct __GAL_DISPLAYPARAMS +{ + GAL_HEADER DWORD dwOffset; + WORD wBpp; + WORD wPitch; + +} +GAL_DISPLAYPARAMS, *PGAL_DISPLAYPARAMS; + +/* + * #define GALFN_DOTCLKTOREFRESH + */ +typedef struct __GAL_DOTCLKTOREFRESH +{ + GAL_HEADER DWORD dwDotClock; + WORD wXres; + WORD wYres; + WORD wBpp; + WORD wRefreshRate; + +} +GAL_DOTCLKTOREFRESH, *PGAL_DOTCLKTOREFRESH; + +/* + * #define GALFN_GETDISPLAYTIMINGS + * #define GALFN_SETDISPLAYTIMINGS + */ +typedef struct __GAL_DISPLAYTIMING +{ + GAL_HEADER DWORD dwDotClock; + WORD wPitch; + WORD wBpp; + WORD wHTotal; + WORD wHActive; + WORD wHSyncStart; + WORD wHSyncEnd; + WORD wHBlankStart; + WORD wHBlankEnd; + WORD wVTotal; + WORD wVActive; + WORD wVSyncStart; + WORD wVSyncEnd; + WORD wVBlankStart; + WORD wVBlankEnd; + WORD wPolarity; + +} +GAL_DISPLAYTIMING, *PGAL_DISPLAYTIMING; + +/* + * #define GALFN_SETPALETTE_ENTRY + * #define GALFN_GETPALETTE_ENTRY + */ +typedef struct __GAL_PALETTE_ENTRY +{ + GAL_HEADER DWORD dwIndex; + DWORD dwPalette; +} +GAL_PALETTE_ENTRY, *PGAL_PALETTE_ENTRY; + +/* + * #define GALFN_SETPALETTE + * #define GALFN_GETPALETTE + */ +typedef struct __GAL_PALETTE +{ + GAL_HEADER DWORD dwColors[256]; +} +GAL_PALETTE, *PGAL_PALETTE; + +/* + * #define GALFN_COMPRESSIONSTATE + */ +typedef struct __GAL_COMPRESSIONSTATE +{ + GAL_HEADER BOOLEAN bCompressionState; +} +GAL_COMPRESSIONSTATE, *PGAL_COMPRESSIONSTATE; + +#define GAL_COMPRESSION_ENABLE 1 +#define GAL_COMPRESSION_DISABLE 0 + +#define GAL_COMPRESSION_OFFSET 1 +#define GAL_COMPRESSION_PITCH 2 +#define GAL_COMPRESSION_SIZE 4 +#define GAL_COMPRESSION_ALL 7 + +/* + * #define GALFN_COMPRESSIONPARAMS + */ +typedef struct __GAL_COMPRESSIONPARAMS +{ + GAL_HEADER DWORD dwFlags; + DWORD dwCompOffset; + WORD dwCompPitch; + WORD dwCompSize; +} +GAL_COMPRESSIONPARAMS, *PGAL_COMPRESSIONPARAMS; + +#define GAL_SETCURSORENABLE_ENABLE 1 +#define GAL_SETCURSORENABLE_DISABLE 0 +/* + * #define GALFN_CURSORENABLE + */ +typedef struct __GAL_CURSORENABLE +{ + GAL_HEADER BOOLEAN bCursorEnable; +} +GAL_CURSORENABLE, *PGAL_CURSORENABLE; + +/* + * #define GALFN_CURSORPOSITION + */ +typedef struct __GAL_CURSORPOSITION +{ + GAL_HEADER DWORD dwMemOffset; + WORD wXPos; + WORD wYPos; + WORD wXHot; + WORD wYHot; +} +GAL_CURSORPOSITION, *PGAL_CURSORPOSITION; + +/* + * #define GALFN_SETCURSORSHAPE + */ +typedef struct __GAL_SETCURSORSHAPE +{ + GAL_HEADER DWORD dwMemOffset; + DWORD dwAndMask[32]; /* Most gfx hardware support only 32x32 */ + DWORD dwXorMask[32]; +} +GAL_SETCURSORSHAPE, *PGAL_SETCURSORSHAPE; + +/* + * #define GALFN_SETCURSORCOLORS + */ +typedef struct __GAL_CURSORCOLORS +{ + GAL_HEADER DWORD dwBgColor; + DWORD dwFgColor; +} +GAL_CURSORCOLORS, *PGAL_CURSORCOLORS; + +/* + * #define GALFN_SETSOLIDPATTERN + */ +typedef struct __GAL_SETSOLIDPATTERN +{ + GAL_HEADER DWORD dwColor; +} +GAL_SETSOLIDPATTERN, *PGAL_SETSOLIDPATTERN; + +/* + * #define GALFN_SETRASTEROPERATION + */ +typedef struct __GAL_SETRASTEROPERATION +{ + GAL_HEADER CHAR cRop; +} +GAL_RASTEROPERATION, *PGAL_RASTEROPERATION; + +/* + * #define GALFN_SETSOLIDSOURCE + */ +typedef struct __GAL_SETSOLIDSOURCE +{ + GAL_HEADER DWORD dwColor; +} +GAL_SETSOLIDSOURCE, *PGAL_SETSOLIDSOURCE; + +/* + * #define GALFN_PATTERNFILL + */ +typedef struct __GAL_PATTERNFILL +{ + GAL_HEADER WORD wXPos; + WORD wYPos; + WORD wWidth; + WORD wHeight; +} +GAL_PATTERNFILL, *PGAL_PATTERNFILL; + +/* + * #define GALFN_SETMONOSOURCE + */ +typedef struct __GAL_SETMONOSOURCE +{ + GAL_HEADER DWORD dwBgColor; + DWORD dwFgColor; + CHAR cTransparency; +} +GAL_SETMONOSOURCE, *PGAL_SETMONOSOURCE; + +/* + * #define GALFN_SETMONOPATTERN + */ +typedef struct __GAL_SETMONOPATTERN +{ + GAL_HEADER DWORD dwBgColor; + DWORD dwFgColor; + DWORD dwData0; + DWORD dwData1; + CHAR cTransparency; +} +GAL_SETMONOPATTERN, *PGAL_SETMONOPATTERN; + +/* + * #define GALFN_SCREENTOSCREENBLT + */ +typedef struct __GAL_SCREENTOSCREENBLT +{ + GAL_HEADER WORD wXStart; + WORD wYStart; + WORD wXEnd; + WORD wYEnd; + WORD wWidth; + WORD wHeight; +} +GAL_SCREENTOSCREENBLT, *PGAL_SCREENTOSCREENBLT; + +/* + * #define GALFN_SCREENTOSCREENXBLT + */ +typedef struct __GAL_SCREENTOSCREENXBLT +{ + GAL_HEADER WORD wXStart; + WORD wYStart; + WORD wXEnd; + WORD wYEnd; + WORD wWidth; + WORD wHeight; + DWORD dwColor; +} +GAL_SCREENTOSCREENXBLT, *PGAL_SCREENTOSCREENXBLT; + +/* + * #define GALFN_BRESENHAMLINE + */ +typedef struct __GAL_BRESENHAMLINE +{ + GAL_HEADER WORD wX1; + WORD wY1; + WORD wLength; + WORD wErr; + WORD wE1; + WORD wE2; + WORD wFlags; +} +GAL_BRESENHAMLINE, *PGAL_BRESENHAMLINE; + +/* + * #define GALFN_COLOR_PATTERNFILL + */ +typedef struct __GAL_COLOR_PATTERNFILL +{ + GAL_HEADER WORD wDsty; + WORD wDstx; + WORD wWidth; + WORD wHeight; + DWORD dwPattern; +} +GAL_COLOR_PATTERNFILL, *PGAL_COLOR_PATTERNFILL; + +/* + * #define GALFN_COLOR_BITMAP_TO_SCREEN_BLT + */ +typedef struct __GAL_COLOR_BITMAP_TO_SCREEN_BLT +{ + GAL_HEADER WORD wSrcx; + WORD wSrcy; + WORD wDstx; + WORD wDsty; + WORD wWidth; + WORD wHeight; + DWORD dwData; + WORD wPitch; +} +GAL_COLOR_BITMAP_TO_SCREEN_BLT, *PGAL_COLOR_BITMAP_TO_SCREEN_BLT; + +/* + * #define GALFN_COLOR_BITMAP_TO_SCREEN_XBLT + */ +typedef struct __GAL_COLOR_BITMAP_TO_SCREEN_XBLT +{ + GAL_HEADER WORD wSrcx; + WORD wSrcy; + WORD wDstx; + WORD wDsty; + WORD wWidth; + WORD wHeight; + DWORD dwData; + WORD wPitch; + DWORD dwColor; +} +GAL_COLOR_BITMAP_TO_SCREEN_XBLT, *PGAL_COLOR_BITMAP_TO_SCREEN_XBLT; + +/* + * #define GALFN_MONO_BITMAP_TO_SCREEN_BLT + */ +typedef struct __GAL_MONO_BITMAP_TO_SCREEN_BLT +{ + GAL_HEADER WORD wSrcx; + WORD wSrcy; + WORD wDstx; + WORD wDsty; + WORD wWidth; + WORD wHeight; + DWORD dwData; + WORD wPitch; +} +GAL_MONO_BITMAP_TO_SCREEN_BLT, *PGAL_MONO_BITMAP_TO_SCREEN_BLT; + +/* + * #define GALFN_TEXT_BLT + */ +typedef struct __GAL_TEXT_BLT +{ + GAL_HEADER WORD wDstx; + WORD wDsty; + WORD wWidth; + WORD wHeight; + DWORD dwData; +} +GAL_TEXT_BLT, *PGAL_TEXT_BLT; + + /* + * * #define GALFN_VGAMODESWITCH + * * #define GALFN_VGACLEARCRTEXT + * * #define GALFN_VGASETPITCH + * * #define GALFN_VGARESTORE + * * #define GALFN_VGASAVE + * * #define GALFN_VGASETMODE + */ + +typedef struct __GAL_VGAREGS +{ + int xsize; + int ysize; + int hz; + int clock; + unsigned char miscOutput; + unsigned char stdCRTCregs[GFX_STD_CRTC_REGS]; + unsigned char extCRTCregs[GFX_EXT_CRTC_REGS]; +} +GAL_VGAREGS, *PGAL_VGAREGS; + +typedef struct __GAL_VGAMODEDATA +{ + GAL_HEADER DWORD dwFlags; /* Flags for this subfunction */ + GAL_VGAREGS sVgaRegs; /* CRT+SEQ+SEQ register data block */ + WORD wXres; + WORD wYres; + WORD wBpp; + WORD wRefresh; +} +GAL_VGAMODEDATA, *PGAL_VGAMODEDATA; + +typedef struct __GAL_VGATESTPCI +{ + GAL_HEADER SWORD softvga; +} +GAL_VGATESTPCI, *PGAL_VGATESTPCI; + +typedef struct __GAL_VGAGETPCICOMMAND +{ + GAL_HEADER unsigned char value; +} +GAL_VGAGETPCICOMMAND, *PGAL_VGAGETPCICOMMAND; + +typedef struct __GAL_VGASEQRESET +{ + GAL_HEADER SWORD reset; + SWORD statusok; +} +GAL_VGASEQRESET, *PGAL_VGASEQRESET; + +typedef struct __GAL_VGASETGRAPHICSBITS +{ + GAL_HEADER SWORD statusok; +} +GAL_VGASETGRAPHICSBITS, *PGAL_VGASETGRAPHICSBITS; + +/******** Panel Support functions *********************/ +/* +* #define GALFN_PNLSETPARAMS +* #define GALFN_PNLGETPARAMS +* #define GALFN_PNLINITPANEL +* #define GALFN_PNLSAVESTATE +* #define GALFN_PNLRESTORESTATE +*/ +typedef struct __GAL_PNLPARAMS +{ + GAL_HEADER Pnl_PanelParams PanelParams; +} +GAL_PNLPARAMS, *PGAL_PNLPARAMS; + +/* +* #define GALFN_PNLBIOSENABLE +* #define GALFN_PNLBIOSINFO +*/ +typedef struct __GAL_PNLBIOS +{ + GAL_HEADER int state; + int XRes; + int YRes; + int Bpp; + int Freq; +} +GAL_PNLBIOS, *PGAL_PNLBIOS; + +typedef struct __GAL_ENABLEPANNING +{ + GAL_HEADER int x; + int y; +} +GAL_ENABLEPANNING, *PGAL_ENABLEPANNING; + +/* + * #define GALFN_SETCRTENABLE + * #define GALFN_GETCRTENABLE + */ +typedef struct __GAL_CRTENABLE +{ + GAL_HEADER WORD wCrtEnable; +} +GAL_CRTENABLE, *PGAL_CRTENABLE; + +#define GAL_TVSTATE 0x01 +#define GAL_TVOUTPUT 0x02 +#define GAL_TVFORMAT 0x04 +#define GAL_TVRESOLUTION 0x08 +#define GAL_TVALL 0x0F +/* + * #define GALFN_SETTVPARAMS + * #define GALFN_GETTVPARAMS + * #define GALFN_SETENABLE + * #define GALFN_GETENABLE + * #define GALFN_ISTVMODESUPPORTED + */ +typedef struct __GAL_TVPARAMS +{ + GAL_HEADER DWORD dwFlags; + WORD wWidth; + WORD wHeight; + WORD wStandard; + WORD wType; + WORD wOutput; + WORD wResolution; + BOOLEAN bState; + +} +GAL_TVPARAMS, *PGAL_TVPARAMS; + +/* + * #define GALFN_SETTVTIMING + * #define GALFN_GETTVTIMING + */ +typedef struct __GAL_TVTIMING +{ + GAL_HEADER DWORD dwFlags; /* not used currently */ + unsigned long HorzTim; + unsigned long HorzSync; + unsigned long VertSync; + unsigned long LineEnd; + unsigned long VertDownscale; + unsigned long HorzScaling; + unsigned long TimCtrl1; + unsigned long TimCtrl2; + unsigned long Subfreq; + unsigned long DispPos; + unsigned long DispSize; + unsigned long Debug; + unsigned long DacCtrl; + unsigned long DotClock; +} +GAL_TVTIMING, *PGAL_TVTIMING; + +/******** Video Support functions *********************/ + +typedef struct __GAL_SETVIDEOENABLE +{ + GAL_HEADER BOOLEAN enable; +} +GAL_VIDEOENABLE, *PGAL_VIDEOENABLE; + +typedef struct __GAL_SETVIDEOFORMAT +{ + GAL_HEADER int format; +} +GAL_VIDEOFORMAT, *PGAL_VIDEOFORMAT; + +typedef struct __GAL_SETVIDEOSIZE +{ + GAL_HEADER unsigned short width; + unsigned short height; +} +GAL_VIDEOSIZE, *PGAL_VIDEOSIZE; + +typedef struct __GAL_SETVIDEOOFFSET +{ + GAL_HEADER unsigned long offset; +} +GAL_VIDEOOFFSET, *PGAL_VIDEOOFFSET; + +typedef struct __GAL_SETVIDEOWINDOW +{ + GAL_HEADER short x; + short y; + short w; + short h; +} +GAL_VIDEOWINDOW, *PGAL_VIDEOWINDOW; + +typedef struct __GAL_SETVIDEOSCALE +{ + GAL_HEADER unsigned short srcw; + unsigned short srch; + unsigned short dstw; + unsigned short dsth; +} +GAL_VIDEOSCALE, *PGAL_VIDEOSCALE; + +typedef struct __GAL_SETVIDEOFILTER +{ + GAL_HEADER int xfilter; + int yfilter; +} +GAL_VIDEOFILTER, *PGAL_VIDEOFILTER; + +typedef struct __GAL_SETVIDEOCOLORKEY +{ + GAL_HEADER unsigned long key; + unsigned long mask; + int bluescreen; +} +GAL_VIDEOCOLORKEY, *PGAL_VIDEOCOLORKEY; + +typedef struct __GAL_SETVIDEODOWNSCALEENABLE +{ + GAL_HEADER int enable; +} +GAL_VIDEODOWNSCALEENABLE, *PGAL_VIDEODOWNSCALEENABLE; + +typedef struct __GAL_SETVIDEODOWNSCALECONFIG +{ + GAL_HEADER unsigned short type; + unsigned short m; +} +GAL_VIDEODOWNSCALECONFIG, *PGAL_VIDEODOWNSCALECONFIG; + +typedef struct __GAL_SETVIDEODOWNSCALECOEFF +{ + GAL_HEADER unsigned short coef1; + unsigned short coef2; + unsigned short coef3; + unsigned short coef4; +} +GAL_VIDEODOWNSCALECOEFF, *PGAL_VIDEODOWNSCALECOEFF; + +#define GAL_VIDEO_SOURCE_MEMORY 0x0 +#define GAL_VIDEO_SOURCE_DVIP 0x1 +typedef struct __GAL_SETVIDEOSOURCE +{ + GAL_HEADER int source; +} +GAL_VIDEOSOURCE, *PGAL_VIDEOSOURCE; + +typedef struct __GAL_SETVIDEOINTERLACED +{ + GAL_HEADER int enable; +} +GAL_SETVIDEOINTERLACED, *PGAL_SETVIDEOINTERLACED; + +typedef struct __GAL_GETVIDEOINTERLACED +{ + GAL_HEADER int interlaced; +} +GAL_GETVIDEOINTERLACED, *PGAL_GETVIDEOINTERLACED; + +typedef struct __GAL_COLORSPACEYUV +{ + GAL_HEADER int colorspace; +} +GAL_COLORSPACEYUV, *PGAL_COLORSPACEYUV; + +typedef struct __GAL_SETGENLOCKENABLE +{ + GAL_HEADER int enable; +} +GAL_GENLOCKENABLE, *PGAL_GENLOCKENABLE; + +typedef struct __GAL_SETGENLOCKDELAY +{ + GAL_HEADER int delay; +} +GAL_GENLOCKDELAY, *PGAL_GENLOCKDELAY; + +typedef struct __GAL_SETTOPLINEINODD +{ + GAL_HEADER int enable; +} +GAL_TOPLINEINODD, *PGAL_TOPLINEINODD; + +typedef struct __GAL_SETVIDEOCURSOR +{ + GAL_HEADER unsigned long key; + unsigned long mask; + unsigned short select_color2; + unsigned long color1; + unsigned long color2; +} +GAL_VIDEOCURSOR, *PGAL_VIDEOCURSOR; + +typedef struct __GAL_READCRC +{ + GAL_HEADER DWORD crc; +} +GAL_READCRC, *PGAL_READCRC; + +typedef struct __GAL_READWINDOWCRC +{ + GAL_HEADER SWORD source; + WORD x; + WORD y; + WORD width; + WORD height; + SWORD crc32; + DWORD crc; +} +GAL_READWINDOWCRC, *PGAL_READWINDOWCRC; + +typedef struct __GAL_GETALPHASIZE +{ + GAL_HEADER WORD * x; + WORD *y; + WORD *width; + WORD *height; +} +GAL_ALPHASIZE, *PGAL_ALPHASIZE; + +typedef struct __GAL_SETMACROVISIONENABLE +{ + GAL_HEADER SWORD enable; +} +GAL_MACROVISIONENABLE, *PGAL_MACROVISIONENABLE; + +typedef struct __GAL_SETVIDEOREQUEST +{ + GAL_HEADER short x; + short y; +} +GAL_VIDEOREQUEST, *PGAL_VIDEOREQUEST; + +typedef struct __GAL_ALPHAENABLE +{ + GAL_HEADER int enable; +} +GAL_ALPHAENABLE, *PGAL_ALPHAENABLE; + +typedef struct __GAL_SETALPHAWINDOW +{ + GAL_HEADER short x; + short y; + unsigned short width; + unsigned short height; +} +GAL_ALPHAWINDOW, *PGAL_ALPHAWINDOW; + +typedef struct __GAL_ALPHAVALUE +{ + GAL_HEADER unsigned char alpha; + char delta; +} +GAL_ALPHAVALUE, *PGAL_ALPHAVALUE; + +typedef struct __GAL_ALPHAPRIORITY +{ + GAL_HEADER int priority; +} +GAL_ALPHAPRIORITY, *PGAL_ALPHAPRIORITY; + +typedef struct __GAL_ALPHACOLOR +{ + GAL_HEADER unsigned long color; +} +GAL_ALPHACOLOR, *PGAL_ALPHACOLOR; + +typedef struct __GAL_SETALPHAREGION +{ + GAL_HEADER int region; +} +GAL_ALPHAREGION, *PGAL_ALPHAREGION; + +typedef struct __GAL_SETVIDEOOUTSIDEALPHA +{ + GAL_HEADER int enable; +} +GAL_VIDEOOUTSIDEALPHA, *PGAL_VIDEOOUTSIDEALPHA; + +typedef struct __GAL_SETVIDEOPALETTE +{ + GAL_HEADER int identity; + unsigned long palette[256]; +} +GAL_VIDEOPALETTE, *PGAL_VIDEOPALETTE; + +typedef struct __GAL_VIDEOINFO +{ + GAL_HEADER int enable; + int format; + int filter; + + unsigned long src_size; + unsigned long dst_size; + unsigned long line_size; + unsigned long xclip; + unsigned long offset; + unsigned long scale; + unsigned long position; + + int color_key_src; + unsigned long color_key; + unsigned long color_key_mask; + + int downscale_enable; + + unsigned short downscale_type; + + unsigned short downscale_mask; + unsigned short downscale_coef1; + unsigned short downscale_coef2; + unsigned short downscale_coef3; + unsigned short downscale_coef4; +} +GAL_VIDEOINFO, *PGAL_VIDEOINFO; + +/* ICON related data strucures */ +typedef struct __GAL_SETICONENABLE +{ + GAL_HEADER SWORD enable; +} +GAL_ICONENABLE, *PGAL_ICONENABLE; + +typedef struct __GAL_SETICONCOLORS +{ + GAL_HEADER DWORD color0; + DWORD color1; + DWORD color2; +} +GAL_ICONCOLORS, *PGAL_ICONCOLORS; + +typedef struct __GAL_SETICONPOSITION +{ + GAL_HEADER DWORD memoffset; + WORD xpos; +} +GAL_ICONPOSITION, *PGAL_ICONPOSITION; + +typedef struct __GAL_SETICONSHAPE64 +{ + GAL_HEADER DWORD memoffset; + DWORD *andmask; + DWORD *xormask; + DWORD lines; +} +GAL_ICONSHAPE64, *PGAL_ICONSHAPE64; + +/* VIP related data strucures */ + +typedef struct __GAL_SETVIPENABLE +{ + GAL_HEADER SWORD enable; +} +GAL_VIPENABLE, *PGAL_VIPENABLE; + +typedef struct __GAL_SETVIPCAPTURERUNMODE +{ + GAL_HEADER SWORD mode; +} +GAL_VIPCAPTURERUNMODE, *PGAL_VIPCAPTURERUNMODE; + +typedef struct __GAL_SETVIPBASE +{ + GAL_HEADER DWORD even; + DWORD odd; + DWORD address; +} +GAL_VIPBASE, *PGAL_VIPBASE; + +typedef struct __GAL_SETVIPPITCH +{ + GAL_HEADER DWORD pitch; +} +GAL_VIPPITCH, *PGAL_VIPPITCH; + +typedef struct __GAL_SETVIPMODE +{ + GAL_HEADER SWORD mode; +} +GAL_VIPMODE, *PGAL_VIPMODE; + +typedef struct __GAL_SETVIPBUS_RTH +{ + GAL_HEADER SWORD enable; +} +GAL_VIPBUS_RTH, *PGAL_VIPBUS_RTH; + +typedef struct __GAL_SETVIPLASTLINE +{ + GAL_HEADER SWORD last_line; +} +GAL_VIPLASTLINE, *PGAL_VIPLASTLINE; + +typedef struct __GAL_TESTVIPODDFIELD +{ + GAL_HEADER SWORD status; +} +GAL_TESTVIPODDFIELD, *PGAL_TESTVIPODDFIELD; + +typedef struct __GAL_TESTVIPBASESUPDATED +{ + GAL_HEADER SWORD status; +} +GAL_TESTVIPBASESUPDATED, *PGAL_TESTVIPBASESUPDATED; + +typedef struct __GAL_TESTVIPFIFOOVERFLOW +{ + GAL_HEADER SWORD status; +} +GAL_TESTVIPOVERFLOW, *PGAL_TESTVIPOVERFLOW; + +typedef struct __GAL_GETVIPLINE +{ + GAL_HEADER SWORD status; +} +GAL_VIPLINE, *PGAL_VIPLINE; + +/* VBI related data strucures */ + +typedef struct __GAL_VBIENABLE +{ + GAL_HEADER SWORD enable; +} +GAL_VBIENABLE, *PGAL_VBIENABLE; + +typedef struct __GAL_VBIBASE +{ + GAL_HEADER DWORD even; + DWORD odd; + DWORD address; +} +GAL_VBIBASE, *PGAL_VBIBASE; + +typedef struct __GAL_VBIPITCH +{ + GAL_HEADER DWORD pitch; +} +GAL_VBIPITCH, *PGAL_VBIPITCH; + +typedef struct __GAL_VBIMODE +{ + GAL_HEADER SWORD mode; +} +GAL_VBIMODE, *PGAL_VBIMODE; + +typedef struct __GAL_SETVBIDIRECT +{ + GAL_HEADER DWORD even_lines; + DWORD odd_lines; +} +GAL_SETVBIDIRECT, *PGAL_SETVBIDIRECT; + +typedef struct __GAL_GETVBIDIRECT +{ + GAL_HEADER SWORD odd; + DWORD direct_lines; +} +GAL_GETVBIDIRECT, *PGAL_GETVBIDIRECT; + +typedef struct __GAL_VBIINTERRUPT +{ + GAL_HEADER SWORD enable; +} +GAL_VBIINTERRUPT, *PGAL_VBIINTERRUPT; + +/* Second generation rendering routines data structures */ + +typedef struct __GAL_SETSTRIDE +{ + GAL_HEADER WORD stride; +} +GAL_STRIDE, *PGAL_STRIDE; + +typedef struct __GAL_SETPATTERNORIGIN +{ + GAL_HEADER int x; + int y; +} +GAL_PATTERNORIGIN, *PGAL_PATTERNORIGIN; + +typedef struct __GAL_SETSOURCETRANSPARENCY +{ + GAL_HEADER DWORD color; + DWORD mask; +} +GAL_SOURCETRANSPARENCY, *PGAL_SOURCETRANSPARENCY; + +typedef struct __GAL_GFX2SETALPHAMODE +{ + GAL_HEADER SWORD mode; +} +GAL_GFX2ALPHAMODE, *PGAL_GFX2ALPHAMODE; + +typedef struct __GAL_GFX2SETALPHAVALUE +{ + GAL_HEADER CHAR value; +} +GAL_GFX2ALPHAVALUE, *PGAL_GFX2ALPHAVALUE; + +typedef struct __GAL_GFX2PATTERNFILL +{ + GAL_HEADER DWORD dstoffset; + WORD width; + WORD height; +} +GAL_GFX2PATTERNFILL, *PGAL_GFX2PATTERNFILL; + +typedef struct __GAL_GFX2COLORPATTERNFILL +{ + GAL_HEADER DWORD dstoffset; + WORD width; + WORD height; + DWORD pattern; +} +GAL_GFX2COLORPATTERNFILL, *PGAL_GFX2COLORPATTERNFILL; + +typedef struct __GAL_GFX2SCREENTOSCREENBLT +{ + GAL_HEADER DWORD srcoffset; + DWORD dstoffset; + WORD width; + WORD height; + SWORD flags; +} +GAL_GFX2SCREENTOSCREENBLT, *PGAL_GFX2SCREENTOSCREENBLT; + +typedef struct __GAL_GFX2MONOEXPANDBLT +{ + GAL_HEADER unsigned long srcbase; + WORD srcx; + WORD srcy; + DWORD dstoffset; + WORD width; + WORD height; + WORD byte_packed; +} +GAL_GFX2MONOEXPANDBLT, *PGAL_GFX2MONOEXPANDBLT; + +typedef struct __GAL_GFX2COLORBMPTOSCRBLT +{ + GAL_HEADER WORD srcx; + WORD srcy; + DWORD dstoffset; + WORD width; + WORD height; + DWORD data; + WORD pitch; +} +GAL_GFX2COLORBMPTOSCRBLT, *PGAL_GFX2COLORBMPTOSCRBLT; + +typedef struct __GAL_GFX2MONOBMPTOSCRBLT +{ + GAL_HEADER WORD srcbase; + WORD srcx; + WORD srcy; + DWORD dstoffset; + WORD width; + WORD height; + DWORD data; + WORD pitch; +} +GAL_GFX2MONOBMPTOSCRBLT, *PGAL_GFX2MONOBMPTOSCRBLT; + +typedef struct __GAL_GFX2TEXTBLT +{ + GAL_HEADER DWORD dstoffset; + WORD width; + WORD height; + DWORD data; +} +GAL_GFX2TEXTBLT, *PGAL_GFX2TEXTBLT; + +typedef struct __GAL_GFX2BRESENHAMLINE +{ + GAL_HEADER DWORD dstoffset; + WORD length; + WORD initerr; + WORD axialerr; + WORD diagerr; + WORD flags; +} +GAL_GFX2BRESENHAMLINE, *PGAL_GFX2BRESENHAMLINE; + +typedef struct __GAL_GFX2SYNCTOVBLANK +{ +GAL_HEADER} +GAL_GFX2SYNCTOVBLANK, *PGAL_GFX2SYNCTOVBLANK; + +/* + GALFN_SETVIDEOYUVPITCH + */ +typedef struct _GAL_SETVIDEOYUVPITCH +{ + GAL_HEADER unsigned long y_pitch; + unsigned long uv_pitch; +} +GAL_VIDEOYUVPITCH, *PGAL_VIDEOYUVPITCH; + +/* + GALFN_SETVIDEOYUVOFFSETS +*/ +typedef struct _GAL_VIDEOYUVOFFSETS +{ + GAL_HEADER unsigned long dwYoffset; + unsigned long dwUoffset; + unsigned long dwVoffset; +} +GAL_VIDEOYUVOFFSETS, *PGAL_VIDEOYUVOFFSETS; + +typedef struct __GAL_SETVIDEOLEFTCROP +{ + GAL_HEADER WORD x; + SWORD status; +} +GAL_VIDEOLEFTCROP, *PGAL_VIDEOLEFTCROP; + +typedef struct __GAL_SETVIDEOVERTICALDOWNSCALE +{ + GAL_HEADER WORD srch; + WORD dsth; + SWORD status; +} +GAL_VIDEOVERTICALDOWNSCALE, *PGAL_VIDEOVERTICALDOWNSCALE; + +typedef struct __GAL_VBISOURCE +{ + GAL_HEADER VideoSourceType source; + SWORD status; +} +GAL_VBISOURCE, *PGAL_VBISOURCE; + +typedef struct __GAL_VBILINES +{ + GAL_HEADER DWORD even; + DWORD odd; + SWORD status; + DWORD lines; +} +GAL_VBILINES, *PGAL_VBILINES; + +typedef struct __GAL_VBITOTAL +{ + GAL_HEADER DWORD even; + DWORD odd; + SWORD status; + DWORD total; +} +GAL_VBITOTAL, *PGAL_VBITOTAL; + +typedef struct __GAL_VSCALEROFFSET +{ + GAL_HEADER char offset; + SWORD status; +} +GAL_VSCALEROFFSET, *PGAL_VSCALEROFFSET; + +/* MSR data strucures */ + +typedef struct __GAL_IDMSRDEVICE +{ + GAL_HEADER MSR * pDev; + DWORD address; + DEV_STATUS dev_status; +} +GAL_IDMSRDEVICE, *PGAL_IDMSRDEVICE; + +typedef struct __GAL_GETMSRDEVADDRESS +{ + GAL_HEADER WORD device; + unsigned long address; + DEV_STATUS dev_status; +} +GAL_GETMSRDEVADDRESS, *PGAL_GETMSRDEVADDRESS; + +typedef struct __GAL_GETMBUSIDATADDRESS +{ + GAL_HEADER unsigned int device; + unsigned long address; + DEV_STATUS dev_status; +} +GAL_GETMBUSIDATADDRESS, *PGAL_GETMBUSIDATADDRESS; + +/* Gal device function's prototye declarations */ + +/** Init **********************************************************/ +BOOLEAN Gal_initialize_interface(void); +BOOLEAN Gal_cleanup_interface(void); +BOOLEAN Gal_get_adapter_info(PGAL_ADAPTERINFO pAdapterInfo); +BOOLEAN Gal_set_softvga_state(BOOLEAN); +BOOLEAN Gal_get_softvga_state(int *bState); +BOOLEAN Gal_set_crt_enable(int); +BOOLEAN Gal_wait_until_idle(void); +BOOLEAN Gal_wait_vertical_blank(void); +BOOLEAN Gal_write_register(int type, unsigned long offset, + unsigned long value, int size); + +BOOLEAN Gal_read_register(int type, unsigned long offset, + unsigned long *value, int size); +/** Display Engine ******************************************************/ +BOOLEAN Gal_is_display_mode_supported(int xres, int yres, int bpp, int hz, + int *supported); +BOOLEAN Gal_set_display_mode(int xres, int yres, int bpp, int hz); +BOOLEAN Gal_get_display_mode(int *xres, int *yres, int *bpp, int *hz); +BOOLEAN Gal_set_bpp(unsigned short bpp); +BOOLEAN Gal_set_display_bpp(unsigned short bpp); +BOOLEAN Gal_get_display_bpp(unsigned short *bpp); +BOOLEAN Gal_set_display_pitch(unsigned short pitch); +BOOLEAN Gal_get_display_pitch(unsigned short *pitch); +BOOLEAN Gal_set_display_offset(unsigned long offset); +BOOLEAN Gal_get_display_offset(unsigned long *offset); +BOOLEAN Gal_get_refreshrate_from_dotclock(int xres, int yres, int bpp, + int *hz, unsigned long frequency); +BOOLEAN Gal_get_display_timing(PGAL_DISPLAYTIMING pDisplayTiming); +BOOLEAN Gal_set_display_timing(PGAL_DISPLAYTIMING pDisplayTiming); +BOOLEAN Gal_set_fixed_timings(int pnlXres, int pnlYres, int totXres, + int totYres, int bpp); +BOOLEAN Gal_set_display_palette_entry(unsigned long index, + unsigned long palette); +BOOLEAN Gal_get_display_palette_entry(unsigned long index, + unsigned long *palette); +BOOLEAN Gal_set_display_palette(PGAL_PALETTE); +BOOLEAN Gal_get_display_palette(PGAL_PALETTE); +BOOLEAN Gal_set_cursor_enable(int enable); +BOOLEAN Gal_get_cursor_enable(int *enable); +BOOLEAN Gal_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor); +BOOLEAN Gal_get_cursor_colors(unsigned long *bkcolor, unsigned long *fgcolor); +BOOLEAN Gal_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, + unsigned short yhotspot); +BOOLEAN Gal_get_cursor_position(unsigned long *memoffset, + unsigned short *xpos, unsigned short *ypos, + unsigned short *xhotspot, + unsigned short *yhotspot); +BOOLEAN Gal_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, + unsigned long *xormask); + +BOOLEAN Gal_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, + unsigned long *xormask); + +/** Render ********************************************************/ +BOOLEAN Gal_set_solid_pattern(unsigned long color); + +BOOLEAN Gal_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned char transparency); +BOOLEAN Gal_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, + unsigned char transparency); + +BOOLEAN Gal_set_raster_operation(unsigned char rop); + +BOOLEAN Gal_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height); + +BOOLEAN Gal_set_solid_source(unsigned long color); + +BOOLEAN Gal_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height); + +BOOLEAN Gal_screen_to_screen_xblt(unsigned short srcx, + unsigned short srcy, + unsigned short dstx, + unsigned short dsty, + unsigned short width, + unsigned short height, unsigned long color); + +BOOLEAN Gal_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); + +BOOLEAN Gal_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, + unsigned long pattern); + +BOOLEAN Gal_color_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned short dstx, + unsigned short dsty, + unsigned short width, + unsigned short height, + unsigned long data, long pitch); + +BOOLEAN Gal_color_bitmap_to_screen_xblt(unsigned short srcx, + unsigned short srcy, + unsigned short dstx, + unsigned short dsty, + unsigned short width, + unsigned short height, + unsigned long data, long pitch, + unsigned long color); + +BOOLEAN Gal_mono_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned short dstx, + unsigned short dsty, + unsigned short width, + unsigned short height, + unsigned long data, short pitch); + +BOOLEAN Gal_text_blt(unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned long data); + +/** Compression*******************************************************/ +BOOLEAN Gal_set_compression_enable(BOOLEAN); +BOOLEAN Gal_get_compression_enable(int *flag); +BOOLEAN Gal_set_compression_parameters(unsigned long flags, + unsigned long offset, + unsigned short pitch, + unsigned short size); +BOOLEAN Gal_get_compression_parameters(unsigned long flags, + unsigned long *offset, + unsigned short *pitch, + unsigned short *size); + +/** VGA **********************************************************/ +BOOLEAN Gal_vga_mode_switch(int active); +BOOLEAN Gal_vga_clear_extended(void); +BOOLEAN Gal_vga_pitch(PGAL_VGAMODEDATA pvregs, unsigned short pitch); +BOOLEAN Gal_vga_restore(PGAL_VGAMODEDATA pvregs); +BOOLEAN Gal_vga_save(PGAL_VGAMODEDATA pvregs); +BOOLEAN Gal_vga_mode(PGAL_VGAMODEDATA pvregs); +BOOLEAN Gal_vga_test_pci(int *softvga); +BOOLEAN Gal_vga_get_pci_command(unsigned char *value); +BOOLEAN Gal_vga_seq_reset(int reset); +BOOLEAN Gal_vga_set_graphics_bits(void); + +/** Panel **********************************************************/ +BOOLEAN Gal_pnl_set_params(unsigned long flags, PPnl_PanelParams pParam); +BOOLEAN Gal_pnl_get_params(unsigned long flags, PPnl_PanelParams pParam); +BOOLEAN Gal_pnl_init(PPnl_PanelParams pParam); +BOOLEAN Gal_pnl_save(void); +BOOLEAN Gal_pnl_restore(void); +BOOLEAN Gal_pnl_powerup(void); +BOOLEAN Gal_pnl_powerdown(void); +BOOLEAN Gal_enable_panning(int x, int y); +BOOLEAN Gal_pnl_enabled_in_bios(int *state); +BOOLEAN Gal_pnl_info_from_bios(int *xres, int *yres, int *bpp, int *hz); + +/** TV **********************************************************/ +BOOLEAN Gal_tv_set_params(unsigned long flags, PGAL_TVPARAMS pTV); +BOOLEAN Gal_tv_get_params(unsigned long flags, PGAL_TVPARAMS pTV); +BOOLEAN Gal_tv_set_timings(unsigned long flags, PGAL_TVTIMING pTV); +BOOLEAN Gal_tv_get_timings(unsigned long flags, PGAL_TVTIMING pTV); +BOOLEAN Gal_set_tv_enable(int bState); +BOOLEAN Gal_get_tv_enable(unsigned int *bState); +BOOLEAN Gal_is_tv_mode_supported(unsigned long flags, PGAL_TVPARAMS pTV, + int *bState); + +/** Video **********************************************************/ +BOOLEAN Gal_set_video_enable(int enable); +BOOLEAN Gal_set_video_format(int format); +BOOLEAN Gal_set_video_size(unsigned short width, unsigned short height); +BOOLEAN Gal_set_video_offset(unsigned long offset); +BOOLEAN Gal_set_video_yuv_offsets(unsigned long yoffset, + unsigned long uoffset, + unsigned long voffset); +BOOLEAN Gal_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch); + +BOOLEAN Gal_set_video_window(short x, short y, short w, short h); +BOOLEAN Gal_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +BOOLEAN Gal_set_video_filter(int xfilter, int yfilter); +BOOLEAN Gal_set_video_color_key(unsigned long key, + unsigned long mask, int bluescreen); +BOOLEAN Gal_set_video_downscale_enable(int enable); +BOOLEAN Gal_set_video_downscale_config(unsigned short type, unsigned short m); +BOOLEAN Gal_set_video_downscale_coefficients(unsigned short coef1, + unsigned short coef2, + unsigned short coef3, + unsigned short coef4); +BOOLEAN Gal_set_video_source(int source); +BOOLEAN Gal_set_video_interlaced(int enable); +BOOLEAN Gal_get_video_interlaced(int *interlaced); +BOOLEAN Gal_set_color_space_YUV(int enable); +BOOLEAN Gal_get_color_space_YUV(int *colorspace); +BOOLEAN Gal_set_video_cursor(unsigned long key, + unsigned long mask, + unsigned short select_color2, + unsigned long color1, unsigned long color2); +BOOLEAN Gal_get_video_cursor(unsigned long *key, + unsigned long *mask, + unsigned short *select_color2, + unsigned long *color1, unsigned long *color2); +BOOLEAN Gal_set_video_request(short x, short y); +BOOLEAN Gal_set_alpha_enable(int enable); +BOOLEAN Gal_get_alpha_enable(int *enable); +BOOLEAN Gal_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height); + +BOOLEAN Gal_set_video_request(short x, short y); +BOOLEAN Gal_set_alpha_window(short x, short y, + unsigned short width, unsigned short height); +BOOLEAN Gal_set_alpha_value(unsigned char alpha, char delta); +BOOLEAN Gal_get_alpha_value(unsigned char *alpha, char *delta); +BOOLEAN Gal_set_alpha_priority(int priority); +BOOLEAN Gal_get_alpha_priority(int *priority); +BOOLEAN Gal_set_alpha_color(unsigned long color); +BOOLEAN Gal_get_alpha_color(unsigned long *color); +BOOLEAN Gal_select_alpha_region(int region); +BOOLEAN Gal_set_video_outside_alpha(int enable); +BOOLEAN Gal_set_video_palette(unsigned long *palette); + +/* Icon related prototypes */ + +BOOLEAN Gal_set_icon_enable(int enable); +BOOLEAN Gal_set_icon_colors(unsigned long color0, unsigned long color1, + unsigned long color2); + +BOOLEAN Gal_set_icon_position(unsigned long memoffset, unsigned short xpos); +BOOLEAN Gal_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned int lines); + +/* Icon related prototypes */ + +BOOLEAN Gal_set_vip_enable(int enable); +BOOLEAN Gal_get_vip_enable(int *enable); +BOOLEAN Gal_set_vip_capture_run_mode(int mode); +BOOLEAN Gal_set_vip_base(unsigned long even, unsigned long odd); +BOOLEAN Gal_get_vip_base(unsigned long *address, int odd); +BOOLEAN Gal_set_vip_pitch(unsigned long pitch); +BOOLEAN Gal_get_vip_pitch(unsigned long *pitch); +BOOLEAN Gal_set_vip_mode(int mode); +BOOLEAN Gal_get_vip_mode(int *mode); +BOOLEAN Gal_set_vbi_enable(int enable); +BOOLEAN Gal_get_vbi_enable(int *enable); +BOOLEAN Gal_set_vbi_mode(int mode); +BOOLEAN Gal_get_vbi_mode(int *mode); +BOOLEAN Gal_set_vbi_base(unsigned long even, unsigned long odd); +BOOLEAN Gal_get_vbi_base(unsigned long *address, int odd); +BOOLEAN Gal_set_vbi_pitch(unsigned long pitch); +BOOLEAN Gal_get_vbi_pitch(unsigned long *pitch); +BOOLEAN Gal_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines); +BOOLEAN Gal_get_vbi_direct(int odd, unsigned long *vbi_direct); +BOOLEAN Gal_set_vbi_interrupt(int enable); +BOOLEAN Gal_get_vbi_interrupt(int *enable); +BOOLEAN Gal_set_vip_bus_request_threshold_high(int enable); +BOOLEAN Gal_get_vip_bus_request_threshold_high(int *enable); +BOOLEAN Gal_set_vip_last_line(int last_line); +BOOLEAN Gal_test_vip_odd_field(int *status); +BOOLEAN Gal_test_vip_bases_updated(int *status); +BOOLEAN Gal_test_vip_fifo_overflow(int *status); +BOOLEAN Gal_get_vip_line(int *status); + +/* Second generation rendering routines */ + +BOOLEAN Gal_set_source_stride(unsigned short stride); +BOOLEAN Gal_set_destination_stride(unsigned short stride); +BOOLEAN Gal_set_source_transparency(unsigned long color, unsigned long mask); +BOOLEAN Gal2_set_source_transparency(unsigned long color, unsigned long mask); +BOOLEAN Gal2_set_source_stride(unsigned short stride); +BOOLEAN Gal2_set_destination_stride(unsigned short stride); +BOOLEAN Gal2_set_pattern_origin(int x, int y); +BOOLEAN Gal2_set_alpha_mode(int mode); +BOOLEAN Gal2_set_alpha_value(unsigned char value); +BOOLEAN Gal2_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height); +BOOLEAN Gal2_color_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned long pattern); +BOOLEAN Gal2_screen_to_screen_blt(unsigned long srcoffset, + unsigned long dstoffset, + unsigned short width, unsigned short height, + int flags); + +BOOLEAN Gal2_mono_expand_blt(unsigned long srcbase, unsigned short srcx, + unsigned short srcy, unsigned long dstoffset, + unsigned short width, unsigned short height, + int byte_packed); + +BOOLEAN Gal2_color_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned long dstoffset, + unsigned short width, + unsigned short height, + unsigned char *data, + unsigned short pitch); +BOOLEAN Gal2_mono_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned long dstoffset, + unsigned short width, + unsigned short height, + unsigned char *data, + unsigned short pitch); + +BOOLEAN Gal2_text_blt(unsigned long dstoffset, + unsigned short width, + unsigned short height, unsigned long data); +BOOLEAN Gal2_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +BOOLEAN Gal2_sync_to_vblank(void); + +/* Video routines */ + +BOOLEAN Gal_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch); +BOOLEAN Gal_get_video_yuv_pitch(unsigned long *ypitch, + unsigned long *uvpitch); + +BOOLEAN Gal_set_video_yuv_offsets(unsigned long yoffset, + unsigned long uoffset, + unsigned long voffset); +BOOLEAN Gal_get_video_yuv_offsets(unsigned long *yoffset, + unsigned long *uoffset, + unsigned long *voffset); + +BOOLEAN Gal_set_video_left_crop(unsigned short x); +BOOLEAN Gal_set_video_vertical_downscale(unsigned short srch, + unsigned short dsth); + +BOOLEAN Gal_set_vbi_source(VbiSourceType source); +BOOLEAN Gal_get_vbi_source(VbiSourceType * source); + +BOOLEAN Gal_set_vbi_lines(unsigned long even, unsigned long odd); +BOOLEAN Gal_get_vbi_lines(int odd, unsigned long *lines); + +BOOLEAN Gal_set_vbi_total(unsigned long even, unsigned long odd); +BOOLEAN Gal_get_vbi_total(int odd, unsigned long *total); + +BOOLEAN Gal_set_vertical_scaler_offset(char offset); +BOOLEAN Gal_get_vertical_scaler_offset(char *offset); +BOOLEAN Gal_get_genlock_enable(int *enable); +BOOLEAN Gal_set_genlock_enable(int flags); +BOOLEAN Gal_get_genlock_delay(unsigned long *delay); +BOOLEAN Gal_set_genlock_delay(unsigned long delay); +BOOLEAN Gal_set_top_line_in_odd(int enable); + +BOOLEAN Gal_read_crc(unsigned long *crc); +BOOLEAN Gal_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, + int crc32, unsigned long *crc); + +BOOLEAN Gal_set_macrovision_enable(int enable); +BOOLEAN Gal_get_macrovision_enable(int *enable); + +/* MSR routines */ + +BOOLEAN Gal_id_msr_dev_address(MSR * pDev, unsigned long address); +BOOLEAN Gal_get_msr_dev_address(unsigned int device, unsigned long *address); + +#endif diff --git a/Source/DirectFB/gfxdrivers/nsc/include/pnl_defs.h b/Source/DirectFB/gfxdrivers/nsc/include/pnl_defs.h new file mode 100755 index 0000000..62de7bb --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/include/pnl_defs.h @@ -0,0 +1,201 @@ +/* + * $Workfile: pnl_defs.h $ + * + * File Contents: This file contains definitions of the Geode + * frame buffer panel data structures. + * + * SubModule: Geode FlatPanel library + * + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + +#ifndef _pnl_defs_h +#define _pnl_defs_h + +typedef enum +{ + MARMOT_PLATFORM = 0, + UNICORN_PLATFORM, + CENTAURUS_PLATFORM, + ARIES_PLATFORM, + CARMEL_PLATFORM, + HYDRA_PLATFORM, + DORADO_PLATFORM, + DRACO_PLATFORM, + REDCLOUD_PLATFORM, + OTHER_PLATFORM +} +SYS_BOARD; + +#define PNL_9210 0x01 +#define PNL_9211_A 0x02 +#define PNL_9211_C 0x04 +#define PNL_UNKNOWN_CHIP 0x08 + +#define PNL_TFT 0x01 +#define PNL_SSTN 0x02 +#define PNL_DSTN 0x04 +#define PNL_TWOP 0x08 +#define PNL_UNKNOWN_PANEL 0x10 + +#define PNL_MONO_PANEL 0x01 +#define PNL_COLOR_PANEL 0x02 +#define PNL_UNKNOWN_COLOR 0x08 + +#define PNL_PANELPRESENT 0x01 +#define PNL_PLATFORM 0x02 +#define PNL_PANELCHIP 0x04 +#define PNL_PANELSTAT 0x08 +#define PNL_OVERRIDE_STAT 0x10 +#define PNL_OVERRIDE_ALL 0x1F + +typedef struct _Pnl_PanelStat_ +{ + int Type; + int XRes; + int YRes; + int Depth; + int MonoColor; +} +Pnl_PanelStat; + +typedef struct _Pnl_Params_ +{ + unsigned long Flags; + int PanelPresent; + int Platform; + int PanelChip; + Pnl_PanelStat PanelStat; +} +Pnl_PanelParams, *PPnl_PanelParams; + +#endif /* _pnl_defs_h */ + +/* END OF FILE */ diff --git a/Source/DirectFB/gfxdrivers/nsc/nsc.c b/Source/DirectFB/gfxdrivers/nsc/nsc.c new file mode 100755 index 0000000..f0a0d72 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/nsc.c @@ -0,0 +1,592 @@ +/* + * $Workfile: $ + * $Revision: 1.16 $ + * + * File Contents: This file contains the main functions of the NSC DFB. + * + * Project: NSC Direct Frame buffer device driver + * + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "nsc_galproto.h" + +#define NSC_ACCEL 1 + +#define GP_VECTOR_DEST_DATA 0x8 +#define GP_VECTOR_MINOR_AXIS_POS 0x4 +#define GP_VECTOR_MAJOR_AXIS_POS 0x2 +#define GP_VECTOR_Y_MAJOR 0x1 + +#define GFX_CPU_REDCLOUD 3 + +#define GX_SUPPORTED_DRAWINGFLAGS DSDRAW_NOFX + +#define GX_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE) + +#define GX_SUPPORTED_BLITTINGFUNCTIONS DFXL_BLIT + +#define GX_SUPPORTED_BLITTINGFLAGS DSBLIT_SRC_COLORKEY + +DFB_GRAPHICS_DRIVER(nsc) + +typedef struct +{ + unsigned long Color; + unsigned long src_offset; + unsigned long dst_offset; + unsigned long src_pitch; + unsigned long dst_pitch; + unsigned long src_colorkey; + int v_srcColorkey; +}NSCDeviceData; + +typedef struct +{ + unsigned int cpu_version; + int cpu; +}NSCDriverData; + +static GAL_ADAPTERINFO sAdapterInfo; + +static bool nscDrawLine(void *drv, void *dev, DFBRegion *line); +static bool nscFillRectangle(void *drv, void *dev, DFBRectangle *rect); +static bool nscDrawRectangle(void *drv, void *dev, DFBRectangle *rect); +static bool nscBlit(void *drv, void *dev, DFBRectangle *rect, int dx, int dy); +static bool nscBlitGu1(void *drv, void *dev, DFBRectangle *rect, int dx, int dy); + +static DFBResult gxEngineSync(void *drv, void *dev) +{ + Gal_wait_until_idle(); + + return DFB_OK; +} + +static inline void +nsc_validate_srcColorkey(NSCDriverData *gxdrv, + NSCDeviceData *gxdev, CardState *state) +{ + if (gxdev->v_srcColorkey) + return; + gxdev->src_colorkey = state->src_colorkey; + gxdev->v_srcColorkey = 1; +} + +static void +gxCheckState(void *drv, + void *dev, CardState *state, DFBAccelerationMask accel) +{ +#if NSC_ACCEL + NSCDriverData *gxdrv = (NSCDriverData *) drv; + NSCDeviceData *gxdev = (NSCDeviceData *) dev; + + if(state->destination->config.format != DSPF_RGB16) + return; + + if (DFB_BLITTING_FUNCTION(accel)) { + + if(state->source->config.format != DSPF_RGB16) + return; + if (gxdrv->cpu) { + /* GU2 - if there are no other blitting flags than the supported + * and the source and destination formats are the same + */ + if (!(state->blittingflags & ~GX_SUPPORTED_BLITTINGFLAGS) && + state->source && state->source->config.format != DSPF_RGB24) { + state->accel |= GX_SUPPORTED_BLITTINGFUNCTIONS; + } + } else{ + /* GU1 - source width must match frame buffer strid + */ + if(state->source) { + int src_pitch = 0; + int dst_pitch = 0; + + if(state->source) { + src_pitch = state->source->config.size.w * DFB_BYTES_PER_PIXEL(state->source->config.format); + } + + if (state->modified & SMF_DESTINATION) { + if(state->destination && state->dst.buffer) + dst_pitch = state->dst.pitch; + } + if(dst_pitch == 0) { + dst_pitch = gxdev->dst_pitch; + } + + if(src_pitch == dst_pitch && state->source) { + state->accel |= GX_SUPPORTED_BLITTINGFUNCTIONS; + } + } + } + } else { + /* if there are no other drawing flags than the supported */ + if (!(state->drawingflags & ~GX_SUPPORTED_DRAWINGFLAGS)) { + state->accel |= GX_SUPPORTED_DRAWINGFUNCTIONS; + } + } +#endif /* NSC_ACCEL */ +} + +static void +gxSetState(void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel) +{ + NSCDriverData *gxdrv = (NSCDriverData *) drv; + NSCDeviceData *gxdev = (NSCDeviceData *) dev; + + if (state->mod_hw & SMF_SRC_COLORKEY) + gxdev->v_srcColorkey = 0; + + switch (accel) { + case DFXL_BLIT: + state->set |= DFXL_BLIT; + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + nsc_validate_srcColorkey(gxdrv, gxdev, state); + break; + + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + state->set |= DFXL_FILLRECTANGLE | DFXL_DRAWLINE | DFXL_DRAWRECTANGLE; + break; + + default: + D_BUG("unexpected drawing/blitting function"); + break; + } + + if (state->mod_hw & SMF_DESTINATION) { + + /* set offset & pitch */ + + gxdev->dst_offset = state->dst.offset; + gxdev->dst_pitch = state->dst.pitch; + } + + if (state->mod_hw & SMF_SOURCE && state->source) { + + gxdev->src_offset = state->src.offset; + gxdev->src_pitch = state->src.pitch; + } + + if (state->mod_hw & (SMF_DESTINATION | SMF_COLOR)) { + switch (state->destination->config.format) { + case DSPF_A8: + gxdev->Color = state->color.a; + break; + case DSPF_ARGB1555: + gxdev->Color = + PIXEL_ARGB1555(state->color.a, state->color.r, + state->color.g, state->color.b); + break; + case DSPF_RGB16: + gxdev->Color = + PIXEL_RGB16(state->color.r, state->color.g, state->color.b); + break; + + default: + D_BUG("unexpected pixelformat"); + break; + } + } + + state->mod_hw = 0; +} + +static bool +nscDrawLine(void *drv, void *dev, DFBRegion *line) +{ + long dx, dy, adx, ady; + short majorErr; + unsigned short destData; + NSCDeviceData *gxdev = (NSCDeviceData *) dev; + int yoffset; + + destData = 0; /* Value will be 0x8 (or) 0 */ + dx = line->x2 - line->x1; /* delta values */ + dy = line->y2 - line->y1; + adx = ABS(dx); + ady = ABS(dy); + yoffset = gxdev->dst_offset / gxdev->dst_pitch; + + /* Canonical Bresenham stepper. + * * We use hardware to draw the pixels to take care of alu modes + * * and whatnot. + */ + Gal_set_raster_operation(0xF0); + Gal_set_solid_pattern(gxdev->Color); + if (adx >= ady) { + unsigned short vectorMode; + + vectorMode = destData; + if (dy >= 0) + vectorMode |= GP_VECTOR_MINOR_AXIS_POS; + if (dx >= 0) + vectorMode |= GP_VECTOR_MAJOR_AXIS_POS; + majorErr = (short)(ady << 1); + + Gal_bresenham_line((short)line->x1, + (short)line->y1 + yoffset, + (short)adx, + (short)(majorErr - adx), + (short)majorErr, + (short)(majorErr - (adx << 1)), vectorMode); + } else { + unsigned short vectorMode; + + vectorMode = destData | GP_VECTOR_Y_MAJOR; + + if (dx >= 0) + vectorMode |= GP_VECTOR_MINOR_AXIS_POS; + if (dy >= 0) + vectorMode |= GP_VECTOR_MAJOR_AXIS_POS; + majorErr = (short)(adx << 1); + Gal_bresenham_line((short)line->x1, + (short)line->y1 + yoffset, + (short)ady, + (short)(majorErr - ady), + (short)majorErr, + (short)(majorErr - (ady << 1)), vectorMode); + } + + return true; +} + +static bool +nscFillRectangle(void *drv, void *dev, DFBRectangle *rect) +{ + NSCDeviceData *gxdev = (NSCDeviceData *) dev; + int yoffset; + + Gal_set_raster_operation(0xF0); + Gal_set_solid_pattern(gxdev->Color); + + yoffset = gxdev->dst_offset / gxdev->dst_pitch; + Gal_pattern_fill(rect->x, rect->y + yoffset, rect->w, rect->h); + + return true; +} + +static bool +nscDrawRectangle(void *drv, void *dev, DFBRectangle *rect) +{ + NSCDeviceData *gxdev = (NSCDeviceData *) dev; + int yoffset; + + Gal_set_raster_operation(0xF0); + Gal_set_solid_pattern(gxdev->Color); + + yoffset = gxdev->dst_offset / gxdev->dst_pitch; + + Gal_pattern_fill(rect->x, rect->y + yoffset, rect->w, 1); + Gal_pattern_fill(rect->x, ((rect->y + yoffset + rect->h) - 1), rect->w, 1); + Gal_pattern_fill(rect->x, (rect->y + yoffset + 1), 1, (rect->h - 2)); + Gal_pattern_fill(((rect->x + rect->w) - 1), + (rect->y + yoffset + 1), 1, (rect->h - 2)); + + return true; +} + +static bool +nscBlit(void *drv, void *dev, DFBRectangle * rect, int dx, int dy) +{ + NSCDeviceData *nscdev = (NSCDeviceData *) dev; + unsigned long soffset = (rect->x * nscdev->src_pitch) + (rect->y * 2); + unsigned long doffset = (dy * nscdev->dst_pitch) + (dx * 2); + + Gal_set_solid_pattern(nscdev->Color); + if (nscdev->v_srcColorkey) { + Gal2_set_source_transparency(nscdev->src_colorkey, 0xFFFF); + } + Gal_set_raster_operation(0xCC); + Gal2_set_source_stride((unsigned short)nscdev->src_pitch); + Gal2_set_destination_stride(nscdev->dst_pitch); + Gal2_screen_to_screen_blt(nscdev->src_offset + soffset, + nscdev->dst_offset + doffset, + (unsigned short)rect->w, + (unsigned short)rect->h, 1); + + return true; +} + +static bool +nscBlitGu1(void *drv, void *dev, DFBRectangle * rect, int dx, int dy) +{ + int result, yoff; + + NSCDeviceData *nscdev = (NSCDeviceData *) dev; + + Gal_set_solid_pattern(nscdev->Color); + if (nscdev->v_srcColorkey) { +//FIXME Gal_set_source_transparency(nscdev->src_colorkey, 0xFFFF); + } +#if 0 + printf("rect x %d y %d w %d h %d dx %d dy %d src_off %x dst_off %x src pitch %x dst pitch %x\n", + rect->x, rect->y, rect->w, rect->h, dx, dy, + nscdev->src_offset, nscdev->dst_offset, + nscdev->src_pitch, nscdev->dst_pitch); +#endif + + Gal_set_raster_operation(0xCC); + + yoff = nscdev->src_offset / nscdev->src_pitch; + result = Gal_screen_to_screen_blt(rect->x, rect->y + yoff, dx, dy, + (unsigned short)rect->w, + (unsigned short)rect->h); + + return true; +} + +/* exported symbols */ + +static int +driver_probe(CoreGraphicsDevice *device) +{ + Gal_initialize_interface(); + if(!Gal_get_adapter_info(&sAdapterInfo)) + return 0; + + return sAdapterInfo.dwFrameBufferBase == dfb_gfxcard_memory_physical( device, 0 ); +} + +static void +driver_get_info(CoreGraphicsDevice *device, GraphicsDriverInfo *info) +{ + /* fill driver info structure */ + snprintf(info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, "NSC GX1 and GX2 Driver"); + snprintf(info->vendor, DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, "NSC"); + + info->version.major = 1; + info->version.minor = 1; + info->driver_data_size = sizeof(NSCDriverData); + info->device_data_size = sizeof(NSCDeviceData); +} + +static DFBResult +driver_init_driver(CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core) +{ + NSCDriverData *gxdrv = (NSCDriverData *) driver_data; + + Gal_set_compression_enable(0); + + gxdrv->cpu_version = sAdapterInfo.dwCPUVersion; + gxdrv->cpu = 0; + if ((gxdrv->cpu_version & 0xFF) == GFX_CPU_REDCLOUD) { + gxdrv->cpu = 1; + } + D_DEBUG("CPU is GX%d", gxdrv->cpu); + +#if NSC_ACCEL + funcs->CheckState = gxCheckState; + funcs->SetState = gxSetState; + funcs->EngineSync = gxEngineSync; + funcs->FillRectangle = nscFillRectangle; + funcs->DrawLine = nscDrawLine; + funcs->DrawRectangle = nscDrawRectangle; + funcs->DrawLine = nscDrawLine; + if (gxdrv->cpu) { + funcs->Blit = nscBlit; + } else { + funcs->Blit = nscBlitGu1; + } +#endif /* NSC_ACCEL */ + + /*dfb_config->pollvsync_after = 1;*/ + + return DFB_OK; +} + +static DFBResult +driver_init_device(CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, void *device_data) +{ + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "NSC GX1/GX2 driver version"); + snprintf(device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "nsc"); + printf("Dependent NSC Kernel FrameBuffer driver version is 2.7.7 or later\n"); + device_info->caps.flags = CCF_NOTRIEMU; + device_info->caps.accel = GX_SUPPORTED_DRAWINGFUNCTIONS; + device_info->caps.drawing = GX_SUPPORTED_DRAWINGFLAGS; + device_info->caps.accel |= GX_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.blitting = GX_SUPPORTED_BLITTINGFLAGS; + return DFB_OK; +} + +static void +driver_close_device(CoreGraphicsDevice * device, + void *driver_data, void *device_data) +{ + NSCDeviceData *gxdev = (NSCDeviceData *) device_data; + + (void)gxdev; + D_DEBUG("DirectFB/nsc: 5"); +} + +static void +driver_close_driver(CoreGraphicsDevice *device, void *driver_data) +{ + D_DEBUG("DirectFB/nsc: 6"); +} diff --git a/Source/DirectFB/gfxdrivers/nsc/nsc_galfns.c b/Source/DirectFB/gfxdrivers/nsc/nsc_galfns.c new file mode 100755 index 0000000..42a9b44 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nsc/nsc_galfns.c @@ -0,0 +1,4905 @@ +/* + * $Workfile: nsc_galfns.c $ + * $Revision: 1.13 $ + * $Author: dok $ + * + * File Contents: This file contains the main functions of the Geode + * frame buffer device drivers GAL function definitions. + * + * Project: Geode Frame buffer device driver + * + */ + +/* NSC_LIC_ALTERNATIVE_PREAMBLE + * + * Revision 1.0 + * + * National Semiconductor Alternative GPL-BSD License + * + * National Semiconductor Corporation licenses this software + * ("Software"): + * + * National Xfree frame buffer driver + * + * under one of the two following licenses, depending on how the + * Software is received by the Licensee. + * + * If this Software is received as part of the Linux Framebuffer or + * other GPL licensed software, then the GPL license designated + * NSC_LIC_GPL applies to this Software; in all other circumstances + * then the BSD-style license designated NSC_LIC_BSD shall apply. + * + * END_NSC_LIC_ALTERNATIVE_PREAMBLE */ + +/* NSC_LIC_BSD + * + * National Semiconductor Corporation Open Source License for + * + * National Xfree frame buffer driver + * + * (BSD License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * * Neither the name of the National Semiconductor Corporation nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * END_NSC_LIC_BSD */ + +/* NSC_LIC_GPL + * + * National Semiconductor Corporation Gnu General Public License for + * + * National Xfree frame buffer driver + * + * (GPL License with Export Notice) + * + * Copyright (c) 1999-2001 + * National Semiconductor Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted under the terms of the GNU General + * Public License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version + * + * In addition to the terms of the GNU General Public License, neither + * the name of the National Semiconductor Corporation nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE, + * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. See the GNU General Public License for more details. + * + * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF + * YOUR JURISDICTION. It is licensee's responsibility to comply with + * any export regulations applicable in licensee's jurisdiction. Under + * CURRENT (2001) U.S. export regulations this software + * is eligible for export from the U.S. and can be downloaded by or + * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed + * destinations which include Cuba, Iraq, Libya, North Korea, Iran, + * Syria, Sudan, Afghanistan and any other country to which the U.S. + * has embargoed goods and services. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * END_NSC_LIC_GPL */ + +#include + +#ifndef XFree86LOADER +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include + +static FBDev *dfb_fbdev = NULL; + +#include "nsc_galproto.h" + +/* + * Compile time constants + */ +#define FBDEV_NAME "/dev/nscgal" + +/* + * Cool Macros to access the structures + */ +#define INIT_GAL(x) \ + (x)->dwSignature = FBGAL_SIGNATURE;\ + (x)->dwSize = sizeof(*x);\ + (x)->dwVersion = FBGAL_VERSION; + +#if 0 +/*------------------------------------------------------------------------ + * create_devicenode + * + * Description: This function creates nscgal device node in the device + * directory. + * parameters : none + * + * return: '0' was return on creating the galdevice node. + *----------------------------------------------------------------------*/ +static int +create_devicenode(void) +{ + +#if 1 + FILE *pfdevices; + char line[200], devname[200]; + int majdev; + + /* remove fails if device is open */ + remove("/dev/nscgal"); + + if ((pfdevices = fopen("/proc/devices", "r"))) { + while (fgets(line, sizeof(line), pfdevices)) { + if (sscanf(line, "%d%*[ \t]%s", &majdev, devname) == 2) { + if (strstr(devname, "nscgal")) + mknod("/dev/nscgal", S_IFCHR | S_IRUSR | S_IWUSR, + makedev(majdev, 0)); + } + } + fclose(pfdevices); + } + return 1; +#endif + +} +#endif + +/*------------------------------------------------------------------------ + * Gal_initialize_interface + * + * Description: This function intializes the nscgal device . + * parameters : none + * + * return: '1' was returned on intialization of the galdevice + * otherwise '0' was returned on failure. + *----------------------------------------------------------------------*/ +BOOLEAN +Gal_initialize_interface(void) +{ +/* create_devicenode(); */ + dfb_fbdev = dfb_system_data(); + + return 1; +} + +/*------------------------------------------------------------------------ + * Gal_cleanup_interface + * + * Description: This function closes the nscgal device . + * parameters : none + * + * return: '1' was returned on closing the galdevice. + *----------------------------------------------------------------------*/ +BOOLEAN +Gal_cleanup_interface(void) +{ + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_write_register + * + * Description: This function writes the data to the hardware register + * of the nscgal device . + * parameters: + * type: It specifies the hardware access type. + * offset: It specifies the offset address the register to be accessed. + * value: It specifies the data value to be written into the register. + * size: It specifies the size of the data to be written. + * + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_write_register(int type, unsigned long offset, unsigned long value, + int size) +{ + GAL_HWACCESS hwAccess; + + INIT_GAL(&hwAccess); + hwAccess.dwSubfunction = GALFN_WRITEREG; + hwAccess.dwType = type; + hwAccess.dwOffset = offset; + hwAccess.dwValue = value; + hwAccess.dwByteCount = size; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &hwAccess)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_read_register + * + * Description: This function reads the data from the hardware register + * of the nscgal device . + * parameters: + * type: It specifies the hardware access type. + * offset: It specifies the offset address of the register to be accessed. + * value: It specifies the pointer to hold the data to be read from + * the gal hardware register. + * size: It specifies the size of the data to be read + * + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_read_register(int type, unsigned long offset, unsigned long *value, + int size) +{ + GAL_HWACCESS hwAccess; + + INIT_GAL(&hwAccess); + hwAccess.dwSubfunction = GALFN_READREG; + hwAccess.dwType = type; + hwAccess.dwOffset = offset; + hwAccess.dwByteCount = size; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &hwAccess)) + return 0; + else { + *value = hwAccess.dwValue; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_get_adapter_info + * + * Description: This function gets the adapter information of the + * nscgal device . + * parameters: + *pAdapterInfo: It specifies the adapter information structure. + * + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_adapter_info(PGAL_ADAPTERINFO pAdapterInfo) +{ + INIT_GAL(pAdapterInfo); + + pAdapterInfo->dwSubfunction = GALFN_GETADAPTERINFO; + + if (!dfb_fbdev || ioctl(dfb_fbdev->fd, FBIOGAL_API, pAdapterInfo)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_softvga_state + * + * Description: This function sets the softvga state of the platform device . + * parameters: + * bEnable: It specifies the softvga state enable state. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_softvga_state(BOOLEAN bEnable) +{ + GAL_SOFTVGASTATE sSoftVgaState; + + INIT_GAL(&sSoftVgaState); + sSoftVgaState.dwSubfunction = GALFN_SETSOFTVGASTATE; + sSoftVgaState.bSoftVgaEnable = bEnable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSoftVgaState)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_softvga_state + * + * Description: This function gets the softvga state of the platform device . + * parameters: + * bEnable: get the softvga state. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_softvga_state(int *bState) +{ + GAL_SOFTVGASTATE sSoftVgaState; + + INIT_GAL(&sSoftVgaState); + sSoftVgaState.dwSubfunction = GALFN_GETSOFTVGASTATE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSoftVgaState)) + return 0; + else { + *bState = sSoftVgaState.bSoftVgaEnable; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_vga_test_pci + * + * Description: This function tests the vga pci. + * parameters: + * softvga: It is pointer to the softvga state. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_test_pci(int *softvga) +{ + GAL_VGATESTPCI sVgatestpci; + + INIT_GAL(&sVgatestpci); + sVgatestpci.dwSubfunction = GALFN_GETSOFTVGASTATE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgatestpci)) + return 0; + else { + *softvga = sVgatestpci.softvga; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_vga_get_pci_command + * + * Description: This function gets the vga pci command. + * parameters: + * value: It is pointer to pci command value. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_get_pci_command(unsigned char *value) +{ + GAL_VGAGETPCICOMMAND sVgagetpcicommand; + + INIT_GAL(&sVgagetpcicommand); + sVgagetpcicommand.dwSubfunction = GALFN_VGAGETPCICOMMAND; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgagetpcicommand)) + return 0; + else { + *value = sVgagetpcicommand.value; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_vga_seq_reset + * + * Description: This function resets the vga seq. + * parameters: + * reset: It gives the reset value. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_seq_reset(int reset) +{ + GAL_VGASEQRESET sVgaseqreset; + + INIT_GAL(&sVgaseqreset); + sVgaseqreset.dwSubfunction = GALFN_VGASEQRESET; + sVgaseqreset.reset = reset; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgaseqreset)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_vga_set_graphics_bits + * + * Description: This function resets the vga seq. + * parameters: None. + * + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_set_graphics_bits(void) +{ + GAL_VGASETGRAPHICSBITS sVgasetgraphics; + + INIT_GAL(&sVgasetgraphics); + sVgasetgraphics.dwSubfunction = GALFN_VGASETGRAPHICSBITS; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgasetgraphics)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_crt_enable + * + * Description: This function sets the crt state of the device . + * parameters: + * crtState: It specifies the crt state of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_crt_enable(int crtEnable) +{ + GAL_CRTENABLE sCrtEnable; + + INIT_GAL(&sCrtEnable); + sCrtEnable.dwSubfunction = GALFN_SETCRTENABLE; + sCrtEnable.wCrtEnable = crtEnable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCrtEnable)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_is_display_mode_supported + * + * Description: This function checks the display mode is supported or not. + * parameters: + * xres: It specifies x co-ordinate resolution. + * Yres: It specifies y co-ordinate resolution. + * bpp: It specifies the bits per pixel (8/16 bits). + * hz: It specifies the frequency of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_is_display_mode_supported(int xres, int yres, int bpp, int hz, + int *supported) +{ + GAL_DISPLAYMODE sDisplayMode; + + *supported = 0; + INIT_GAL(&sDisplayMode); + sDisplayMode.dwSubfunction = GALFN_ISDISPLAYMODESUPPORTED; + sDisplayMode.wXres = xres; + sDisplayMode.wYres = yres; + sDisplayMode.wBpp = bpp; + sDisplayMode.wRefresh = hz; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayMode)) + return 0; + else { + *supported = sDisplayMode.dwSupported; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_mode + * + * Description: This function sets the display mode of the galdevice. + * parameters: + * xres: It specifies x co-ordinate resolution. + * Yres: It specifies y co-ordinate resolution. + * bpp: It specifies the bits per pixel (8/16 bits). + * hz: It specifies the frequency of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_mode(int xres, int yres, int bpp, int hz) +{ + GAL_DISPLAYMODE sDisplayMode; + + INIT_GAL(&sDisplayMode); + sDisplayMode.dwSubfunction = GALFN_SETDISPLAYMODE; + sDisplayMode.wXres = xres; + sDisplayMode.wYres = yres; + sDisplayMode.wBpp = bpp; + sDisplayMode.wRefresh = hz; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayMode)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_mode + * + * Description: This function gets the display mode of the galdevice. + * parameters: + * xres: It specifies x co-ordinate resolution. + * Yres: It specifies y co-ordinate resolution. + * bpp: It specifies the bits per pixel (8/16 bits). + * hz: It specifies the frequency of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +{ + GAL_DISPLAYMODE sDisplayMode; + + INIT_GAL(&sDisplayMode); + sDisplayMode.dwSubfunction = GALFN_GETDISPLAYMODE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayMode)) + return 0; + else { + *xres = sDisplayMode.wXres; + *yres = sDisplayMode.wYres; + *bpp = sDisplayMode.wBpp; + *hz = sDisplayMode.wRefresh; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_bpp + * + * Description: This function sets the number bits per pixel in the display + * mode of the galdevice. + * parameters: + * bpp: It specifies the bits per pixel (8/16 bits). + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_bpp(unsigned short bpp) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_SETDISPLAYBPP; + sDisplayParams.wBpp = bpp; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_set_bpp + * + * Description: This function sets the number bits per pixel in the display + * mode of the galdevice. + * parameters: + * bpp: It specifies the bits per pixel (8/16 bits). + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_bpp(unsigned short bpp) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_SETBPP; + sDisplayParams.wBpp = bpp; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_bpp + * + * Description: This function gets the number bits per pixel in the display + * mode of the galdevice. + * parameters: + * bpp: It specifies the bits per pixel (8/16 bits). + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_bpp(unsigned short *bpp) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_GETDISPLAYBPP; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else { + *bpp = sDisplayParams.wBpp; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_pitch + * + * Description: This function sets the display pitch of the galdevice. + * parameters: + * pitch: It specifies pitch of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_pitch(unsigned short pitch) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_SETDISPLAYPITCH; + sDisplayParams.wPitch = pitch; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_pitch + * + * Description: This function gets the display pitch of the galdevice. + * parameters: + * pitch: It specifies pitch of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_pitch(unsigned short *pitch) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_GETDISPLAYPITCH; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else { + *pitch = sDisplayParams.wPitch; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_offset + * + * Description: This function sets the offset of display parameters. + * parameters: + * offset: It specifies the offset address of display parameters. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_offset(unsigned long offset) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_SETDISPLAYOFFSET; + sDisplayParams.dwOffset = offset; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_offset + * + * Description: This function gets the offset of display parameters. + * parameters: + * offset: It specifies the offset address of display parameters. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_offset(unsigned long *offset) +{ + GAL_DISPLAYPARAMS sDisplayParams; + + INIT_GAL(&sDisplayParams); + sDisplayParams.dwSubfunction = GALFN_GETDISPLAYOFFSET; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDisplayParams)) + return 0; + else { + *offset = sDisplayParams.dwOffset; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_get_refreshrate_from_dotclock + * + * Description: This function gets the refreshrate from dotclock. + * parameters: + * xres: It specifies x co-ordinate resolution. + * Yres: It specifies y co-ordinate resolution. + * bpp: It specifies the bits per pixel (8/16 bits). + * hz: It is a pointer which holds the refresh rate of the display. + * frequency: It spcifies the frequency of the dotclock. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_refreshrate_from_dotclock(int xres, int yres, int bpp, int *hz, + unsigned long frequency) +{ + GAL_DOTCLKTOREFRESH sDclkToRefresh; + + INIT_GAL(&sDclkToRefresh); + sDclkToRefresh.dwSubfunction = GALFN_DOTCLKTOREFRESH; + sDclkToRefresh.wXres = xres; + sDclkToRefresh.wYres = yres; + sDclkToRefresh.wBpp = bpp; + sDclkToRefresh.dwDotClock = frequency; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sDclkToRefresh)) + return 0; + else { + *hz = sDclkToRefresh.wRefreshRate; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_timing + * + * Description: This function gets the display timing from galdevice. + * parameters: + * pDisplayTiming: It specifies the display timing of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_timing(PGAL_DISPLAYTIMING pDisplayTiming) +{ + INIT_GAL(pDisplayTiming); + pDisplayTiming->dwSubfunction = GALFN_GETDISPLAYTIMINGS; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pDisplayTiming)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_timing + * + * Description: This function sets the display timing of the galdevice. + * parameters: + * pDisplayTiming: It specifies the display timing of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_timing(PGAL_DISPLAYTIMING pDisplayTiming) +{ + INIT_GAL(pDisplayTiming); + pDisplayTiming->dwSubfunction = GALFN_SETDISPLAYTIMINGS; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pDisplayTiming)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_set_fixed_timings + * + * Description: This function sets the fixed display timings of the + * galdevice. + * parameters: + * pnlXres: It specifies the panel X resolution. + * pnlYres: It specifies the panel Y resolution. + * totXres: It specifies the total X resolution. + * totYres: It specifies the total Y resolution. + * bpp: It specifies the bits per pixel (8/16 bits). + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_fixed_timings(int pnlXres, int pnlYres, int totXres, + int totYres, int bpp) +{ + GAL_DISPLAYTIMING DisplayTiming; + + INIT_GAL(&DisplayTiming); + DisplayTiming.dwSubfunction = GALFN_SETFIXEDTIMINGS; + DisplayTiming.wHActive = pnlXres; /* panel Xres */ + DisplayTiming.wVActive = pnlYres; /* panel Yres */ + DisplayTiming.wHTotal = totXres; /* Total Xres */ + DisplayTiming.wVTotal = totYres; /* Total Yres */ + DisplayTiming.wBpp = bpp; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &DisplayTiming)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_palette_entry + * + * Description: This function sets the display palette entry of the + * galdevice. + * parameters: + * index: It specifies the palette index, + * palette: It specifies the palette of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_palette_entry(unsigned long index, unsigned long palette) +{ + GAL_PALETTE_ENTRY sPalette; + + INIT_GAL(&sPalette); + sPalette.dwSubfunction = GALFN_SETPALETTE_ENTRY; + sPalette.dwIndex = index; + sPalette.dwPalette = palette; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sPalette)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_palette_entry + * + * Description: This function gets the display palette entry of the + * galdevice. + * parameters: + * index: It specifies the palette index, + * palette: It is a pointer to the palette of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_palette_entry(unsigned long index, unsigned long *palette) +{ + GAL_PALETTE_ENTRY sPalette; + + INIT_GAL(&sPalette); + sPalette.dwSubfunction = GALFN_GETPALETTE_ENTRY; + sPalette.dwIndex = index; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sPalette)) + return 0; + else { + *palette = sPalette.dwPalette; + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_set_display_palette_entry + * + * Description: This function sets the display palette entry of the + * galdevice. + * parameters: + * pPalette: It specifies the palette structure of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_display_palette(PGAL_PALETTE pPalette) +{ + INIT_GAL(pPalette); + pPalette->dwSubfunction = GALFN_SETPALETTE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pPalette)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_get_display_palette_entry + * + * Description: This function gets the display palette entry of the + * galdevice. + * parameters: + * pPalette: It specifies the palette structure of the galdevice. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_display_palette(PGAL_PALETTE pPalette) +{ + INIT_GAL(pPalette); + pPalette->dwSubfunction = GALFN_GETPALETTE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pPalette)) + return 0; + else { + return 1; + } +} + +/*--------------------------------------------------------------------------- + * Gal_wait_until_idle + * + * Description: This function waits until the graphics engine is idle. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_wait_until_idle(void) +{ + GAL_WAITUNTILIDLE sWaitIdle; + + INIT_GAL(&sWaitIdle); + sWaitIdle.dwSubfunction = GALFN_WAITUNTILIDLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sWaitIdle)) + return 0; + else + return 1; +} + +/*--------------------------------------------------------------------------- + * Gal_wait_vertical_blank + * + * Description: This function wait until start of vertical blank. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_wait_vertical_blank(void) +{ + GAL_WAITVERTICALBLANK sWaitVerticalBlank; + + INIT_GAL(&sWaitVerticalBlank); + sWaitVerticalBlank.dwSubfunction = GALFN_WAITVERTICALBLANK; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sWaitVerticalBlank)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_cursor_enable + * + * Description: This function enable or disable the hardware cursor. + * parameters: + * enable: This specifies the enable value of the cursor. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_cursor_enable(int enable) +{ + GAL_CURSORENABLE sCursorEnable; + + INIT_GAL(&sCursorEnable); + sCursorEnable.dwSubfunction = GALFN_SETCURSORENABLE; + sCursorEnable.bCursorEnable = enable ? 1 : 0; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorEnable)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_cursor_position + * + * Description: This function sets the position of the cursor. + * parameters: + * memoffset: It specifies the memory offset of the cursor position. + * xpos: It specifies the X co-ordinate position of the cursor. + * ypos: It specifies the Y co-ordinate position of the cursor. + * xhotspot: It specifies the X hotspot location for current cursor shape. + * yhotspot: It specifies the Y hotspot location for current cursor shape. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +{ + GAL_CURSORPOSITION sCursorPos; + + INIT_GAL(&sCursorPos); + sCursorPos.dwSubfunction = GALFN_SETCURSORPOSITION; + sCursorPos.dwMemOffset = memoffset; + sCursorPos.wXPos = xpos; + sCursorPos.wYPos = ypos; + sCursorPos.wXHot = xhotspot; + sCursorPos.wYHot = yhotspot; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorPos)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_cursor_position + * + * Description: This function gets the cursor position. + * parameters: + * memoffset: It points the memory offset of the cursor position. + * xpos: It points the X co-ordinate position of the cursor. + * ypos: It points the Y co-ordinate position of the cursor. + * xhotspot: It points the X hotspot location for current cursor shape. + * yhotspot: It points the Y hotspot location for current cursor shape. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_cursor_position(unsigned long *memoffset, + unsigned short *xpos, unsigned short *ypos, + unsigned short *xhotspot, unsigned short *yhotspot) +{ + GAL_CURSORPOSITION sCursorPos; + + INIT_GAL(&sCursorPos); + sCursorPos.dwSubfunction = GALFN_GETCURSORPOSITION; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorPos)) + return 0; + else { + *memoffset = sCursorPos.dwMemOffset; + *xpos = sCursorPos.wXPos; + *ypos = sCursorPos.wYPos; + *xhotspot = sCursorPos.wXHot; + *yhotspot = sCursorPos.wYHot; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_cursor_shape32 + * + * Description: This function loads 32x32 cursor pattern. + * parameters: + * memoffset: It specifies the graphics memory offset for cursor shape. + * andmask: It is a pointer to 32 DWORD of AND data. + * xormask: It is a pointer to 32 DWORD of XOR data. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +{ + GAL_SETCURSORSHAPE sCursorShape; + + INIT_GAL(&sCursorShape); + sCursorShape.dwSubfunction = GALFN_SETCURSORSHAPE; + sCursorShape.dwMemOffset = memoffset; + + direct_memcpy(sCursorShape.dwAndMask, andmask, sizeof(sCursorShape.dwAndMask)); + + direct_memcpy(sCursorShape.dwXorMask, xormask, sizeof(sCursorShape.dwXorMask)); + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorShape)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_cursor_shape64 + * + * Description: This function loads 64x64 cursor pattern. + * parameters: + * memoffset: It specifies the graphics memory offset for cursor shape. + * andmask: It is a pointer to 64 DWORD of AND data. + * xormask: It is a pointer to 64 DWORD of XOR data. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ BOOLEAN +Gal_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +{ + GAL_SETCURSORSHAPE sCursorShape; + + INIT_GAL(&sCursorShape); + sCursorShape.dwSubfunction = GALFN_SETCURSORSHAPE_RCLD; + sCursorShape.dwMemOffset = memoffset; + + direct_memcpy(sCursorShape.dwAndMask, andmask, sizeof(sCursorShape.dwAndMask)); + + direct_memcpy(sCursorShape.dwXorMask, xormask, sizeof(sCursorShape.dwXorMask)); + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorShape)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_cursor_colors + * + * Description: This function sets the colors of the hardware cursor. + * parameters: + * bkcolor:It specifies the RGB value for the background color. + * fgcolor:It specifies the RGB value for the foreground color. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +{ + GAL_CURSORCOLORS sCursorColor; + + INIT_GAL(&sCursorColor); + sCursorColor.dwSubfunction = GALFN_SETCURSORCOLORS; + sCursorColor.dwBgColor = bkcolor; + sCursorColor.dwFgColor = fgcolor; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorColor)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_cursor_colors + * + * Description: This function gets the colors of the hardware cursor. + * parameters: + * bkcolor:It points the RGB value for the background color. + * fgcolor:It points the RGB value for the foreground color. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_cursor_colors(unsigned long *bkcolor, unsigned long *fgcolor) +{ + GAL_CURSORCOLORS sCursorColor; + + INIT_GAL(&sCursorColor); + sCursorColor.dwSubfunction = GALFN_GETCURSORCOLORS; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCursorColor)) + return 0; + else { + *bkcolor = sCursorColor.dwBgColor; + *fgcolor = sCursorColor.dwFgColor; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_solid_pattern + * + * Description: This function sets a solid pattern color for future rendering. + * parameters: + * color: It specifies the pattern color in proper format for current + * display mode. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_solid_pattern(unsigned long color) +{ + GAL_SETSOLIDPATTERN sSetSoildPat; + + INIT_GAL(&sSetSoildPat); + sSetSoildPat.dwSubfunction = GALFN_SETSOLIDPATTERN; + sSetSoildPat.dwColor = color; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetSoildPat)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_solid_source + * + * Description: This function specifies a constant source data value for + * raster operations that use both pattern + * and source data. + * parameters: + * color: It specifies the source color. + * return: '1' was returned on success otherwise '0' was returned. + *-------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_solid_source(unsigned long color) +{ + GAL_SETSOLIDSOURCE sSetSolidSrc; + + INIT_GAL(&sSetSolidSrc); + sSetSolidSrc.dwSubfunction = GALFN_SETSOLIDSOURCE; + sSetSolidSrc.dwColor = color; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetSolidSrc)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_mono_source + * + * Description: + * parameters: + * bkcolor: It specifies the background color. + * fgcolor: It specifies the foreground color. + *transparency: It specifies the transparency flag. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned char transparency) +{ + GAL_SETMONOSOURCE sSetMonoSrc; + + INIT_GAL(&sSetMonoSrc); + sSetMonoSrc.dwSubfunction = GALFN_SETMONOSOURCE; + sSetMonoSrc.dwFgColor = fgcolor; + sSetMonoSrc.dwBgColor = bgcolor; + sSetMonoSrc.cTransparency = transparency; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetMonoSrc)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_mono_pattern + * + * Description: This function specifies an 8x8 monochrome pattern + * used in future rendering operations. + * parameters: + * bkcolor: It specifies the background color. + * fgcolor: It specifies the foreground color. + * data0: It specifies the bits of 8x8 monochrome pattern. + * data1: It specifies the bits of 8x8 monochrome pattern. + *transparency: It specifies the transparency flag. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, + unsigned char transparency) +{ + GAL_SETMONOPATTERN sSetMonoPat; + + INIT_GAL(&sSetMonoPat); + sSetMonoPat.dwSubfunction = GALFN_SETMONOPATTERN; + sSetMonoPat.dwFgColor = fgcolor; + sSetMonoPat.dwBgColor = bgcolor; + sSetMonoPat.dwData0 = data0; + sSetMonoPat.dwData1 = data1; + sSetMonoPat.cTransparency = transparency; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetMonoPat)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_raster_operation + * + * Description: This function specifies the raster operation for + * future rendering. + * parameters: + * rop: It specifies the ternary raster operation + * (pattern/source/destination). + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_raster_operation(unsigned char rop) +{ + GAL_RASTEROPERATION sSetRop; + + INIT_GAL(&sSetRop); + sSetRop.dwSubfunction = GALFN_SETRASTEROPERATION; + sSetRop.cRop = rop; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetRop)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_pattern_fill + * + * Description: This function renders pattern data to a rectangular + * region. + * parameters: + * x: It specifies the screen X position, in pixels. + * y: It specifies the screen Y position, in pixels. + * width: It specifies the width of rectangle, in pixels. + * height: It specifies the height of rectangle, in pixels. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +{ + GAL_PATTERNFILL sPatternFill; + + INIT_GAL(&sPatternFill); + sPatternFill.dwSubfunction = GALFN_PATTERNFILL; + sPatternFill.wXPos = x; + sPatternFill.wYPos = y; + sPatternFill.wWidth = width; + sPatternFill.wHeight = height; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sPatternFill)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_screen_to_screen_blt + * + * Description: This function is used to perform a screen to screen + * BLT operation. + * parameters: + * srcx: It specifies the source X position. + * srcy: It specifies the source Y position. + * dstx: It specifies the destination X position. + * dsty: It specifies the destination Y position. + * width: It specifies the width of BLT, in pixels. + * height: It specifies the height of BLT, in pixels. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height) +{ + GAL_SCREENTOSCREENBLT sScreenBlt; + + INIT_GAL(&sScreenBlt); + sScreenBlt.dwSubfunction = GALFN_SCREENTOSCREENBLT; + sScreenBlt.wXStart = srcx; + sScreenBlt.wYStart = srcy; + sScreenBlt.wXEnd = dstx; + sScreenBlt.wYEnd = dsty; + sScreenBlt.wWidth = width; + sScreenBlt.wHeight = height; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sScreenBlt)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_screen_to_screen_xblt + * + * Description: This function is used to perform a screen to screen + * BLT operation using a transparency color. + * parameters: + * srcx: It specifies the source X position. + * srcy: It specifies the source Y position. + * dstx: It specifies the destination X position. + * dsty: It specifies the destination Y position. + * width: It specifies the width of BLT, in pixels. + * height: It specifies the height of BLT, in pixels. + * color: It specifies the transparency color. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned long color) +{ + GAL_SCREENTOSCREENXBLT sScreenXBlt; + + INIT_GAL(&sScreenXBlt); + sScreenXBlt.dwSubfunction = GALFN_SCREENTOSCREENXBLT; + sScreenXBlt.wXStart = srcx; + sScreenXBlt.wYStart = srcy; + sScreenXBlt.wXEnd = dstx; + sScreenXBlt.wYEnd = dsty; + sScreenXBlt.wWidth = width; + sScreenXBlt.wHeight = height; + sScreenXBlt.dwColor = color; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sScreenXBlt)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_bresenham_line + * + * Description: This function is used to draw a single pixel line + * using the specified Bresenham parameters. + * parameters: + * x: It specifies the starting X position. + * y: It specifies the starting Y position. + * length: It specifies the length of the vector, in pixels. + * initerr: It specifies the Bresenham initial error term. + * axialerr: It specifies the Bresenham axial error term + * (moving in major direction only). + * diagerr: It specifies Bresenham diagonal error term + * (moving in major and minor direction. + * flags: It specifies the flag. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +{ + GAL_BRESENHAMLINE sBresenhamLine; + + INIT_GAL(&sBresenhamLine); + sBresenhamLine.dwSubfunction = GALFN_BRESENHAMLINE; + sBresenhamLine.wX1 = x; + sBresenhamLine.wY1 = y; + sBresenhamLine.wLength = length; + sBresenhamLine.wErr = initerr; + sBresenhamLine.wE1 = axialerr; + sBresenhamLine.wE2 = diagerr; + sBresenhamLine.wFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sBresenhamLine)) + return 0; + else + return 1; +} + +BOOLEAN +Gal_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, + unsigned long pattern) +{ + GAL_COLOR_PATTERNFILL sColorPat; + + INIT_GAL(&sColorPat); + sColorPat.dwSubfunction = GALFN_COLOR_PATTERNFILL; + sColorPat.wDstx = x; + sColorPat.wDsty = y; + sColorPat.wWidth = width; + sColorPat.wHeight = height; + sColorPat.dwPattern = pattern; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sColorPat)) + return 0; + else + return 1; +} + +BOOLEAN +Gal_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned long data, long pitch) +{ + GAL_COLOR_BITMAP_TO_SCREEN_BLT sBmp2Scr; + + INIT_GAL(&sBmp2Scr); + sBmp2Scr.dwSubfunction = GALFN_COLOR_BITMAP_TO_SCREEN_BLT; + sBmp2Scr.wSrcx = srcx; + sBmp2Scr.wSrcy = srcy; + sBmp2Scr.wDstx = dstx; + sBmp2Scr.wDsty = dsty; + sBmp2Scr.wWidth = width; + sBmp2Scr.wHeight = height; + sBmp2Scr.dwData = data; + sBmp2Scr.wPitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sBmp2Scr)) + return 0; + else + return 1; +} + +BOOLEAN +Gal_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned long data, long pitch, + unsigned long color) +{ + GAL_COLOR_BITMAP_TO_SCREEN_XBLT sBmp2Scr; + + INIT_GAL(&sBmp2Scr); + sBmp2Scr.dwSubfunction = GALFN_COLOR_BITMAP_TO_SCREEN_XBLT; + sBmp2Scr.wSrcx = srcx; + sBmp2Scr.wSrcy = srcy; + sBmp2Scr.wDstx = dstx; + sBmp2Scr.wDsty = dsty; + sBmp2Scr.wWidth = width; + sBmp2Scr.wHeight = height; + sBmp2Scr.dwData = data; + sBmp2Scr.wPitch = pitch; + sBmp2Scr.dwColor = color; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sBmp2Scr)) + return 0; + else + return 1; +} + +BOOLEAN +Gal_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned long data, short pitch) +{ + GAL_MONO_BITMAP_TO_SCREEN_BLT sBmp2Scr; + + INIT_GAL(&sBmp2Scr); + sBmp2Scr.dwSubfunction = GALFN_MONO_BITMAP_TO_SCREEN_BLT; + sBmp2Scr.wSrcx = srcx; + sBmp2Scr.wSrcy = srcy; + sBmp2Scr.wDstx = dstx; + sBmp2Scr.wDsty = dsty; + sBmp2Scr.wWidth = width; + sBmp2Scr.wHeight = height; + sBmp2Scr.dwData = data; + sBmp2Scr.wPitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sBmp2Scr)) + return 0; + else + return 1; +} + +BOOLEAN +Gal_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long data) +{ + GAL_TEXT_BLT sTextBlt; + + INIT_GAL(&sTextBlt); + sTextBlt.dwSubfunction = GALFN_TEXT_BLT; + sTextBlt.wDstx = dstx; + sTextBlt.wDsty = dsty; + sTextBlt.wWidth = width; + sTextBlt.wHeight = height; + sTextBlt.dwData = data; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sTextBlt)) + return 0; + else + return 1; +} + +/*------------------------------------------------------------------------ + * Gal_set_compression_enable + * + * Description: This function enables or disables display + * compression. + * parameters: + * bCompressionState: It specifies the display compression state. + * return: '1' was returned on success otherwise + * '0' was returned. + *----------------------------------------------------------------------*/ +BOOLEAN +Gal_set_compression_enable(BOOLEAN bCompressionState) +{ + GAL_COMPRESSIONSTATE sCompState; + + INIT_GAL(&sCompState); + sCompState.dwSubfunction = GALFN_SETCOMPRESSIONSTATE; + sCompState.bCompressionState = bCompressionState; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCompState)) + return 0; + else + return 1; +} + +/*------------------------------------------------------------------------ + * Gal_get_compression_enable + * + * Description: This function gets the compression state. + * + * parameters: + * bCompressionState: gets the display compression state. + * return: '1' was returned on success otherwise + * '0' was returned. + *----------------------------------------------------------------------*/ +BOOLEAN +Gal_get_compression_enable(int *bCompressionState) +{ + GAL_COMPRESSIONSTATE sCompState; + + INIT_GAL(&sCompState); + sCompState.dwSubfunction = GALFN_GETCOMPRESSIONSTATE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCompState)) + return 0; + else { + *bCompressionState = sCompState.bCompressionState; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_compression_parameters + * + * Description: This function sets the compression parameters of the + * frame buffer device. + * parameters: + * flags: It specifies the flag. + * offset: It specifies the base offset in graphics memory for the + * compression buffer. + * pitch: It specifies the pitch of compression buffer, in bytes. + * size: It specifies the maximum line size of the compression buffer + * in bytes. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_compression_parameters(unsigned long flags, + unsigned long offset, unsigned short pitch, + unsigned short size) +{ + GAL_COMPRESSIONPARAMS sCompParams; + + INIT_GAL(&sCompParams); + sCompParams.dwSubfunction = GALFN_SETCOMPRESSIONPARAMS; + sCompParams.dwFlags = flags; + sCompParams.dwCompOffset = offset; + sCompParams.dwCompPitch = pitch; + sCompParams.dwCompSize = size; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCompParams)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_compression_parameters + * + * Description: This function gets the compression parameters of the + * frame buffer device. + * parameters: + * flags: It specifies the flag. + * offset: gets the base offset in graphics memory for the + * compression buffer. + * pitch: gets the pitch of compression buffer, in bytes. + * size: gets the maximum line size of the compression buffer + * in bytes. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_compression_parameters(unsigned long flags, + unsigned long *offset, + unsigned short *pitch, unsigned short *size) +{ + GAL_COMPRESSIONPARAMS sCompParams; + + INIT_GAL(&sCompParams); + sCompParams.dwSubfunction = GALFN_GETCOMPRESSIONPARAMS; + sCompParams.dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sCompParams)) + return 0; + else { + *offset = sCompParams.dwCompOffset; + *pitch = sCompParams.dwCompPitch; + *size = sCompParams.dwCompSize; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_vga_mode_switch + * + * Description:This function signals the beginning or end of a + * mode switch. + * parameters: + * active: It specifies the mode switch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_mode_switch(int active) +{ + GAL_VGAMODEDATA sVgaData; + + INIT_GAL(&sVgaData); + sVgaData.dwSubfunction = GALFN_VGAMODESWITCH; + sVgaData.dwFlags = active; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgaData)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_vga_clear_extended + * + * Description: This will clear the Svga data. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_clear_extended(void) +{ + GAL_VGAMODEDATA sVgaData; + + INIT_GAL(&sVgaData); + sVgaData.dwSubfunction = GALFN_VGACLEARCRTEXT; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sVgaData)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_vga_pitch + * + * Description: This function sets VGA register values in VGA + * structure for specified pitch. + * parameters: + * pVgaData: It specifies the vga structure. + * pitch: It specifies the number of bytes between scanlines. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_pitch(PGAL_VGAMODEDATA pVgaData, unsigned short pitch) +{ + INIT_GAL(pVgaData); + pVgaData->dwSubfunction = GALFN_VGASETPITCH; + pVgaData->dwFlags = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pVgaData)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_vga_restore + * + * Description: This function sets the VGA state to the values in the + * VGA structure. + * parameters: + * pVgaData: It specifies the vga structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_restore(PGAL_VGAMODEDATA pVgaData) +{ + INIT_GAL(pVgaData); + pVgaData->dwSubfunction = GALFN_VGARESTORE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pVgaData)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_vga_save + * + * Description: This function saves the current VGA state in the + * VGA structure. + * parameters: + * pVgaData: It specifies the vga structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_save(PGAL_VGAMODEDATA pVgaData) +{ + INIT_GAL(pVgaData); + pVgaData->dwSubfunction = GALFN_VGASAVE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pVgaData)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_vga_mode + * + * Description: This function sets VGA register values in VGA + * structure for specified mode. + * parameters: + * pVgaData: It specifies the vga structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_vga_mode(PGAL_VGAMODEDATA pVgaData) +{ + INIT_GAL(pVgaData); + pVgaData->dwSubfunction = GALFN_VGASETMODE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pVgaData)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_enabled_in_bios + * + * Description: This function gets the status of the FP in BIOS. + * parameters: + * status: returns the state of FP in Bios. + * pParam: It specifies the panel parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_enabled_in_bios(int *state) +{ + GAL_PNLBIOS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLBIOSENABLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + *state = pStat.state; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_info_from_bios + * + * Description: This function gets the parameters of the FP in BIOS. + * parameters: + * status: returns the state of FP in Bios. + * pParam: It specifies the panel parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_info_from_bios(int *xres, int *yres, int *bpp, int *hz) +{ + GAL_PNLBIOS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLBIOSINFO; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + *xres = pStat.XRes; + *yres = pStat.YRes; + *bpp = pStat.Bpp; + *hz = pStat.Freq; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_set_params + * + * Description: This function sets the panel parameters. + * parameters: + * flags: + * pParam: It specifies the panel parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_set_params(unsigned long flags, PPnl_PanelParams pParam) +{ + GAL_PNLPARAMS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLSETPARAMS; + pParam->Flags = flags; + direct_memcpy(&(pStat.PanelParams), pParam, sizeof(Pnl_PanelParams)); + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_get_params + * + * Description: This function gets the panel parameters. + * parameters: + * flags: + * pParam: It specifies the panel parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_get_params(unsigned long flags, PPnl_PanelParams pParam) +{ + GAL_PNLPARAMS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLGETPARAMS; + direct_memcpy(&(pStat.PanelParams), pParam, sizeof(Pnl_PanelParams)); + pStat.PanelParams.Flags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + direct_memcpy(pParam, &(pStat.PanelParams), sizeof(Pnl_PanelParams)); + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_init + * + * Description: This function initializes the panel parameters. + * parameters: + * pParam: It specifies the panel parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_init(PPnl_PanelParams pParam) +{ + GAL_PNLPARAMS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLINITPANEL; + direct_memcpy(&(pStat.PanelParams), pParam, sizeof(Pnl_PanelParams)); + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else + return 1; + +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_save + * + * Description: This function saves the current panel parameters. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_save(void) +{ + GAL_PNLPARAMS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLSAVESTATE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_restore + * + * Description: This function restores the current panel parameters. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_restore(void) +{ + GAL_PNLPARAMS pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLRESTORESTATE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_powerup + * + * Description: This function powers up the panel. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_powerup(void) +{ + GAL_BASE pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLPOWERUP; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_pnl_powerdown + * + * Description: This function powers down the panel. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_pnl_powerdown(void) +{ + GAL_BASE pStat; + + INIT_GAL(&pStat); + pStat.dwSubfunction = GALFN_PNLPOWERDOWN; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pStat)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_enable_panning + * + * Description: This routine enables the panning when the Mode + * is bigger than the panel size. + * parameters: + * x: x-positon of the screen. + * y: y-positon of the screen. + * + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_enable_panning(int x, int y) +{ + GAL_ENABLEPANNING pEnablePanning; + + INIT_GAL(&pEnablePanning); + pEnablePanning.dwSubfunction = GALFN_ENABLEPANNING; + pEnablePanning.x = x; + pEnablePanning.y = y; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pEnablePanning)) + return 0; + else { + return 1; + } +} + + +/*-------------------------------------------------------------------------- + * Gal_tv_set_params + * + * Description: This function sets the tv parameters of + * tvparameters structure. + * parameters: + * flags: + * pTV: It specifies the tv parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_tv_set_params(unsigned long flags, PGAL_TVPARAMS pTV) +{ + INIT_GAL(pTV); + pTV->dwSubfunction = GALFN_SETTVPARAMS; + pTV->dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pTV)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_tv_get_params + * + * Description: This function gets the tv parameters of + * tvparameters structure. + * parameters: + * flags: Dummy flag + * pTV: It specifies the tv parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_tv_get_params(unsigned long flags, PGAL_TVPARAMS pTV) +{ + INIT_GAL(pTV); + pTV->dwSubfunction = GALFN_GETTVPARAMS; + pTV->dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pTV)) + return 0; + else + return 1; + +} + +/*-------------------------------------------------------------------------- + * Gal_tv_set_timings + * + * Description: This function sets the tv timing registers. + * parameters: + * flags: Dummy flag. + * pTV: It specifies the tv parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_tv_set_timings(unsigned long flags, PGAL_TVTIMING pTV) +{ + INIT_GAL(pTV); + pTV->dwSubfunction = GALFN_SETTVTIMING; + pTV->dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pTV)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_tv_get_timings + * + * Description: This function gets the tv timing registers. + * parameters: + * flags: Dummy flag. + * pTV: It specifies the tv parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_tv_get_timings(unsigned long flags, PGAL_TVTIMING pTV) +{ + INIT_GAL(pTV); + pTV->dwSubfunction = GALFN_GETTVTIMING; + pTV->dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pTV)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_tv_enable + * + * Description: This function sets the tv state of the device . + * parameters: + * bState : set the tv state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_tv_enable(int bState) +{ + GAL_TVPARAMS pTV; + + INIT_GAL(&pTV); + pTV.dwSubfunction = GALFN_SETENABLE; + pTV.bState = bState; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pTV)) + return 0; + else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_tv_enable + * + * Description: This function gets the tv state of the device . + * parameters: + * bState : get the tv state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_tv_enable(unsigned int *bState) +{ + GAL_TVPARAMS pTV; + + INIT_GAL(&pTV); + pTV.dwSubfunction = GALFN_GETENABLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &pTV)) { + *bState = 0; + return 0; + } else { + *bState = pTV.bState; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_is_tv_mode_supported + * + * Description: This function checks the tv mode is supported or not. + * parameters: + * flags: Dummy flag + * pTV: It specifies the tv parameters structure. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_is_tv_mode_supported(unsigned long flags, PGAL_TVPARAMS pTV, int *bState) +{ + INIT_GAL(pTV); + pTV->dwSubfunction = GALFN_ISTVMODESUPPORTED; + pTV->dwFlags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, pTV)) { + return 0; + } else { + *bState = pTV->bState; + return 1; + } +} + +/** Video **********************************************************/ + +/*-------------------------------------------------------------------------- + * Gal_set_video_enable + * + * Description: This function sets the video enable state. + * parameters: + * enable: Its value is '1' to enable video and '0' to disable video. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_enable(int enable) +{ + GAL_VIDEOENABLE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOENABLE; + sSetVideo.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_format + * + * Description: This function sets the video format. + * parameters: + * format: Its video format value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_format(int format) +{ + GAL_VIDEOFORMAT sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOFORMAT; + sSetVideo.format = format; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_size + * + * Description: This function sets the video size. + * parameters: + * width: Width of the video. + * height: Height of the video. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_size(unsigned short width, unsigned short height) +{ + GAL_VIDEOSIZE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOSIZE; + sSetVideo.width = width; + sSetVideo.height = height; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_offset + * + * Description: This function sets the video size. + * parameters: + * offset: Offset of the video. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_offset(unsigned long offset) +{ + GAL_VIDEOOFFSET sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOOFFSET; + sSetVideo.offset = offset; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_window + * + * Description: This function sets the video window. + * parameters: + * x: X co-ordinate of the Video screen. + * y: Y co-ordinate of the Video screen. + * w: Width of the Video screen. + * h: Height of the Video screen. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_window(short x, short y, short w, short h) +{ + GAL_VIDEOWINDOW sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOWINDOW; + sSetVideo.x = x; + sSetVideo.y = y; + sSetVideo.w = w; + sSetVideo.h = h; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_scale + * + * Description: This function sets the video scale. + * parameters: + * srcw: Source width. + * srch: Source height. + * dstw: Destination width. + * dsth: Destination height. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +{ + GAL_VIDEOSCALE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOSCALE; + sSetVideo.srcw = srcw; + sSetVideo.srch = srch; + sSetVideo.dstw = dstw; + sSetVideo.dsth = dsth; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_filter. + * + * Description: This function sets the video filter. + * parameters: + * xfilter: X-co-ordinate filter. + * yfilter: Y-co-ordinate filter. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_filter(int xfilter, int yfilter) +{ + GAL_VIDEOFILTER sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOFILTER; + sSetVideo.xfilter = xfilter; + sSetVideo.yfilter = yfilter; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_color_key. + * + * Description: This function sets the video color key. + * parameters: + * key: Color key. + * mask: Color mask. + * bluescreen: Value for bluescreen. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_color_key(unsigned long key, unsigned long mask, int bluescreen) +{ + GAL_VIDEOCOLORKEY sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOCOLORKEY; + sSetVideo.key = key; + sSetVideo.mask = mask; + sSetVideo.bluescreen = bluescreen; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_downscale_enable. + * + * Description: This function sets the video downscale enable state. + * parameters: + * enable: Value for enable or disable the video downscale. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_downscale_enable(int enable) +{ + GAL_VIDEODOWNSCALEENABLE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEODOWNSCALEENABLE; + sSetVideo.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_downscale_config. + * + * Description: This function sets the video downscale configuration. + * parameters: + * type: Video down scale type. + * m: Factor for the Video overlay window. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_downscale_config(unsigned short type, unsigned short m) +{ + GAL_VIDEODOWNSCALECONFIG sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEODOWNSCALECONFIG; + sSetVideo.type = type; + sSetVideo.m = m; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_downscale_coefficients. + * + * Description: This function sets the video downscale coefficients. + * parameters: + * coef1: Video downscale filter coefficient. + * coef2: Video downscale filter coefficient. + * coef3: Video downscale filter coefficient. + * coef4: Video downscale filter coefficient. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_downscale_coefficients(unsigned short coef1, + unsigned short coef2, + unsigned short coef3, + unsigned short coef4) +{ + GAL_VIDEODOWNSCALECOEFF sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEODOWNSCALECOEFF; + sSetVideo.coef1 = coef1; + sSetVideo.coef2 = coef2; + sSetVideo.coef3 = coef3; + sSetVideo.coef4 = coef4; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_source. + * + * Description: This function sets the video source to either memory or Direct + * VIP + * parameters: + * source: Video source. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_source(int source) +{ + GAL_VIDEOSOURCE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOSOURCE; + sSetVideo.source = source; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_interlaced + * + * Description: This function configures the Video processor video overlay mode + * to be interlaced YUV. + * parameters: + * enable: Value used to enable or disalbe the Video interlaced. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ + +BOOLEAN +Gal_set_video_interlaced(int enable) +{ + GAL_SETVIDEOINTERLACED sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOINTERLACED; + sSetVideo.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_color_space + * + * Description: This function configures the Video processor to prcoess + * graphics and video in either YUV or RGB color space. + * + * parameters: + * enable: Value used to enable or disalbe the Video color space. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_color_space_YUV(int colorspace) +{ + GAL_COLORSPACEYUV sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOCOLORSPACE; + sSetVideo.colorspace = colorspace; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_cursor. + * + * Description: This function configures the Video Hardware cursor. + * + * + * parameters: + * key: color key. + * mask: color mask. + *select_color2: selected for color2. + * color1: color1 value. + * color2: color2 value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_cursor(unsigned long key, + unsigned long mask, + unsigned short select_color2, + unsigned long color1, unsigned long color2) +{ + GAL_VIDEOCURSOR sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOCURSOR; + sSetVideo.key = key; + sSetVideo.mask = mask; + sSetVideo.select_color2 = select_color2; + sSetVideo.color1 = color1; + sSetVideo.color2 = color2; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_request. + * + * Description: This function sets the horizontal(pixel) and vertical(line) + * video request values. + * + * parameters: + * x: X video request value. + * y: Y video request value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_request(short x, short y) +{ + GAL_VIDEOREQUEST sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOREQUEST; + sSetVideo.x = x; + sSetVideo.y = y; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_enable. + * + * Description: This function enables or disables the currently selected + * alpha region. + * + * parameters: + * enable: Value to enalbe or disable alha region. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_alpha_enable(int enable) +{ + GAL_ALPHAENABLE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHAENABLE; + sSetVideo.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_alpha_enable. + * + * Description: This function gets the alpha enable state. + * + * parameters: + * enable: Pointer to get the enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_alpha_enable(int *enable) +{ + GAL_ALPHAENABLE sGetalphaenable; + + INIT_GAL(&sGetalphaenable); + sGetalphaenable.dwSubfunction = GALFN_GETALPHAENABLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetalphaenable)) + return 0; + else + + *enable = sGetalphaenable.enable; + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_window + * + * Description: This function sets the size of the currently selected + * alpha region. + * parameters: + * x: X co-ordinate of the alpha region. + * y: Y co-ordinate of the alpha region. + * width: Width of the alpha region. + * height: Height of the alpha region. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +{ + GAL_ALPHAWINDOW sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHAWINDOW; + sSetVideo.x = x; + sSetVideo.y = y; + sSetVideo.width = width; + sSetVideo.height = height; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_alpha_size + * + * Description: This function gets the size of the currently selected + * alpha region. + * parameters: + * x: X co-ordinate of the alpha region. + * y: Y co-ordinate of the alpha region. + * width: Width of the alpha region. + * height: Height of the alpha region. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +{ + GAL_ALPHASIZE sGetalphasize; + + INIT_GAL(&sGetalphasize); + sGetalphasize.dwSubfunction = GALFN_GETALPHASIZE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetalphasize)) + return 0; + else { + *x = *(sGetalphasize.x); + *y = *(sGetalphasize.y); + *width = *(sGetalphasize.width); + *height = *(sGetalphasize.height); + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_value + * + * Description: This function sets the alpha value for the selected alpha + * region. It also specifies an increment/decrement value for + * fading. + * parameters: + * alpha: Alpha value for the currently selected alpha region. + * delta: Gives the increment/decrement fading value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_alpha_value(unsigned char alpha, char delta) +{ + GAL_ALPHAVALUE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHAVALUE; + sSetVideo.alpha = alpha; + sSetVideo.delta = delta; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_alpha_value + * + * Description: This function gets the alpha value for the selected alpha + * region. It also gets increment/decrement value for + * fading. + * parameters: + * alpha: Alpha value for the currently selected alpha region. + * delta: Gives the increment/decrement fading value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_alpha_value(unsigned char *alpha, char *delta) +{ + GAL_ALPHAVALUE sGetalphavalue; + + INIT_GAL(&sGetalphavalue); + sGetalphavalue.dwSubfunction = GALFN_GETALPHAVALUE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetalphavalue)) + return 0; + else { + *alpha = sGetalphavalue.alpha; + *delta = sGetalphavalue.delta; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_priority + * + * Description: This function sets the priority of the selected alpha + * region. + * parameters: + * priority: Gives the priority value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_alpha_priority(int priority) +{ + GAL_ALPHAPRIORITY sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHAPRIORITY; + sSetVideo.priority = priority; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_alpha_priority + * + * Description: This function gets the priority of the selected alpha + * region. + * parameters: + * priority: Gives the priority value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_alpha_priority(int *priority) +{ + GAL_ALPHAPRIORITY sGetalphapriority; + + INIT_GAL(&sGetalphapriority); + sGetalphapriority.dwSubfunction = GALFN_GETALPHAPRIORITY; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetalphapriority)) + return 0; + else { + *priority = sGetalphapriority.priority; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_color + * + * Description: This function sets the color to be displayed inside the + * currently of the selected alpha window. + * parameters: + * color: Gives the color value to be displayed. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_alpha_color(unsigned long color) +{ + GAL_ALPHACOLOR sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHACOLOR; + sSetVideo.color = color; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_get_alpha_color + * + * Description: This function gets the color to be displayed inside the + * currently of the selected alpha window. + * parameters: + * color: Gives the color value to be displayed. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_alpha_color(unsigned long *color) +{ + GAL_ALPHACOLOR sGetalphacolor; + + INIT_GAL(&sGetalphacolor); + sGetalphacolor.dwSubfunction = GALFN_GETALPHACOLOR; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetalphacolor)) + return 0; + else { + *color = sGetalphacolor.color; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_select_alpha_region + * + * Description: This function selects the alpha region should be used for + * future updates. + * parameters: + * region: Gives the alpha window number. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_select_alpha_region(int region) +{ + GAL_ALPHAREGION sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETALPHAREGION; + sSetVideo.region = region; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_outside_alpha + * + * Description: This function enable/disable the video outside alpha region. + * parameters: + * enable: Gives the value for enable/disable. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_outside_alpha(int enable) +{ + GAL_VIDEOOUTSIDEALPHA sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOOUTSIDEALPHA; + sSetVideo.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_palette + * + * Description: This function loads the video hardware palette. + * parameters: + * palette: Gives value for hardware palette. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_palette(unsigned long *palette) +{ + GAL_VIDEOPALETTE sSetVideo; + + INIT_GAL(&sSetVideo); + sSetVideo.dwSubfunction = GALFN_SETVIDEOPALETTE; + + if (palette == NULL) { + sSetVideo.identity = 1; + } else { + sSetVideo.identity = 0; + direct_memcpy(sSetVideo.palette, palette, 256 * sizeof(*palette)); + } + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideo)) + return 0; + else + return 1; +} + +/** Video **********************************************************/ + +/*-------------------------------------------------------------------------- + * Gal_set_icon_enable + * + * Description: This function enable/disables the hardware icon. The icon + * position and colors should be programmed prior to calling + * this routine. + * parameters: + * enable: Gives value for enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_icon_enable(int enable) +{ + GAL_ICONENABLE sSetIconenable; + + INIT_GAL(&sSetIconenable); + sSetIconenable.dwSubfunction = GALFN_SETICONENABLE; + sSetIconenable.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetIconenable)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_icon_colors + * + * Description: This function sets the three hardware icon colors. + * parameters: + * color0: Gives first color value. + * color1: Gives second color value. + * color2: Gives third color value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_icon_colors(unsigned long color0, unsigned long color1, + unsigned long color2) +{ + GAL_ICONCOLORS sSetIconcolors; + + INIT_GAL(&sSetIconcolors); + sSetIconcolors.dwSubfunction = GALFN_SETICONCOLORS; + sSetIconcolors.color0 = color0; + sSetIconcolors.color1 = color1; + sSetIconcolors.color2 = color2; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetIconcolors)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_icon_position. + * + * Description: This function sets the hardware icon position. + * parameters: + * memoffset: Memory offset of the icon buffer. + * xpos: Starting X co-ordinate for the hardware icon. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_icon_position(unsigned long memoffset, unsigned short xpos) +{ + GAL_ICONPOSITION sSetIconposi; + + INIT_GAL(&sSetIconposi); + sSetIconposi.dwSubfunction = GALFN_SETICONPOSITION; + sSetIconposi.memoffset = memoffset; + sSetIconposi.xpos = xpos; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetIconposi)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_icon_shape64. + * + * Description: This function initializes the icon buffer according to + * the current mode. + * parameters: + * memoffset: Memory offset of the icon buffer. + * andmask: Andmask of the icon buffer. + * xormask: Xormask of the icon buffer. + * lines: Lines of the icon buffer. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned int lines) +{ + GAL_ICONSHAPE64 sSetIconshape64; + + INIT_GAL(&sSetIconshape64); + sSetIconshape64.dwSubfunction = GALFN_SETICONSHAPE64; + sSetIconshape64.memoffset = memoffset; + *(sSetIconshape64.andmask) = *andmask; + *(sSetIconshape64.xormask) = *xormask; + sSetIconshape64.lines = lines; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetIconshape64)) { + return 0; + } else { + return 1; + } +} + +/* VIP Functions */ + +/*-------------------------------------------------------------------------- + * Gal_set_vip_enable + * + * Description: This function enable/disables the writes to memory from the + * video port. + * position and colors should be programmed prior to calling + * this routine. + * parameters: + * enable: Gives value for enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_enable(int enable) +{ + GAL_VIPENABLE sSetVipenable; + + INIT_GAL(&sSetVipenable); + sSetVipenable.dwSubfunction = GALFN_SETVIPENABLE; + sSetVipenable.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipenable)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_enable + * + * Description: This function gets the enable state of the + * video port. + * parameters: + * enable: Gives value for enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_enable(int *enable) +{ + GAL_VIPENABLE sGetVipenable; + + INIT_GAL(&sGetVipenable); + sGetVipenable.dwSubfunction = GALFN_GETVIPENABLE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipenable)) { + return 0; + } else { + + *enable = sGetVipenable.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_capture_run_mode + * + * Description: This function selects the VIP capture run mode. + * + * parameters: + * mode: VIP capture run mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_capture_run_mode(int mode) +{ + GAL_VIPCAPTURERUNMODE sSetVipcapturerunmode; + + INIT_GAL(&sSetVipcapturerunmode); + sSetVipcapturerunmode.dwSubfunction = GALFN_SETVIPCAPTURERUNMODE; + sSetVipcapturerunmode.mode = mode; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipcapturerunmode)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_base + * + * Description: This routine sets the odd and even base address values for + * the VIP memory buffer. + * parameters: + * even: Even base address. + * odd: odd base address. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_base(unsigned long even, unsigned long odd) +{ + GAL_VIPBASE sSetVipBase; + + INIT_GAL(&sSetVipBase); + sSetVipBase.dwSubfunction = GALFN_SETVIPBASE; + sSetVipBase.even = even; + sSetVipBase.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipBase)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_base + * + * Description: This routine gets the base address value for + * the VIP memory buffer. + * parameters: + * address: VIP base address. + * odd: odd base address. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_base(unsigned long *address, int odd) +{ + GAL_VIPBASE sGetVipBase; + + INIT_GAL(&sGetVipBase); + sGetVipBase.dwSubfunction = GALFN_GETVIPBASE; + sGetVipBase.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipBase)) { + return 0; + } else { + *address = sGetVipBase.address; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_pitch + * + * Description: This routine sets the number of bytes between scanlines + * for the VIP data. + * parameters: + * pitch: VIP pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_pitch(unsigned long pitch) +{ + GAL_VIPPITCH sSetVipPitch; + + INIT_GAL(&sSetVipPitch); + sSetVipPitch.dwSubfunction = GALFN_SETVIPPITCH; + sSetVipPitch.pitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipPitch)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_pitch + * + * Description: This routine gets the number of bytes between scanlines + * for the VIP data. + * parameters: + * pitch: VIP pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_pitch(unsigned long *pitch) +{ + GAL_VIPPITCH sGetVipPitch; + + INIT_GAL(&sGetVipPitch); + sGetVipPitch.dwSubfunction = GALFN_GETVIPPITCH; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipPitch)) { + return 0; + } else { + *pitch = sGetVipPitch.pitch; + return 1; + + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_mode + * + * Description: This routine sets the VIP operating mode. + * parameters: + * mode: VIP operating mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_mode(int mode) +{ + GAL_VIPMODE sSetVipMode; + + INIT_GAL(&sSetVipMode); + sSetVipMode.dwSubfunction = GALFN_SETVIPMODE; + sSetVipMode.mode = mode; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipMode)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_mode + * + * Description: This routine gets the VIP operating mode. + * parameters: + * mode: VIP operating mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_mode(int *mode) +{ + GAL_VIPMODE sGetVipMode; + + INIT_GAL(&sGetVipMode); + sGetVipMode.dwSubfunction = GALFN_GETVIPMODE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipMode)) { + return 0; + } else { + + *mode = sGetVipMode.mode; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_bus_request_threshold_high + * + * Description: This function sets the VIP FIFO bus request threshold. + * + * parameters: + * enable: Enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_bus_request_threshold_high(int enable) +{ + GAL_VIPBUS_RTH sSetVipBRTH; + + INIT_GAL(&sSetVipBRTH); + sSetVipBRTH.dwSubfunction = GALFN_SETVIPBRTH; + sSetVipBRTH.enable = enable; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVipBRTH)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_bus_request_threshold_high + * + * Description: This function gets the VIP FIFO bus request threshold. + * + * parameters: + * enable: Enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_bus_request_threshold_high(int *enable) +{ + GAL_VIPBUS_RTH sGetVipBRTH; + + INIT_GAL(&sGetVipBRTH); + sGetVipBRTH.dwSubfunction = GALFN_GETVIPBRTH; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipBRTH)) { + return 0; + } else { + + *enable = sGetVipBRTH.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vip_last_line + * + * Description: This function sets the maximum number of lines captured + * in each field. + * + * parameters: + * last_line: Maximum number of lines captured in each field. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vip_last_line(int last_line) +{ + GAL_VIPLASTLINE sSetViplastline; + + INIT_GAL(&sSetViplastline); + sSetViplastline.dwSubfunction = GALFN_SETVIPLASTLINE; + sSetViplastline.last_line = last_line; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetViplastline)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vip_line + * + * Description: This function gets the number of the current video line being + * recieved by the VIP interface. + * + * parameters: + * vip_line: Number of the current video line. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vip_line(int *vip_line) +{ + GAL_VIPLINE sGetVipline; + + INIT_GAL(&sGetVipline); + sGetVipline.dwSubfunction = GALFN_GETVIPLINE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVipline)) { + return 0; + } else { + *vip_line = sGetVipline.status; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_test_vip_odd_field + * + * Description: This function tests the VIP odd field. + * + * parameters: + * status: Status of the odd field. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_test_vip_odd_field(int *status) +{ + GAL_TESTVIPODDFIELD sTestVipoddfield; + + INIT_GAL(&sTestVipoddfield); + sTestVipoddfield.dwSubfunction = GALFN_TESTVIPODDFIELD; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sTestVipoddfield)) { + return 0; + } else { + *status = sTestVipoddfield.status; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_test_vip_bases_updated + * + * Description: This function tests the VIP bases updated. + * + * parameters: + * status: Status of the VIP bases updated. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_test_vip_bases_updated(int *status) +{ + GAL_TESTVIPBASESUPDATED sTestVipbasesupdated; + + INIT_GAL(&sTestVipbasesupdated); + sTestVipbasesupdated.dwSubfunction = GALFN_TESTVIPBASESUPDATED; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sTestVipbasesupdated)) { + return 0; + } else { + *status = sTestVipbasesupdated.status; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_test_vip_fifo_overflow + * + * Description: This function tests the VIP FIFO overflow. + * + * parameters: + * status: Status of the VIP FIFO overflow. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_test_vip_fifo_overflow(int *status) +{ + GAL_TESTVIPOVERFLOW sTestVipoverflow; + + INIT_GAL(&sTestVipoverflow); + sTestVipoverflow.dwSubfunction = GALFN_TESTVIPFIFOOVERFLOW; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sTestVipoverflow)) { + return 0; + } else { + *status = sTestVipoverflow.status; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_enable + * + * Description: This function enable/disables the VBI data capture. + * + * parameters: + * enable: VBI enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_enable(int enable) +{ + GAL_VBIENABLE sSetVbienable; + + INIT_GAL(&sSetVbienable); + sSetVbienable.dwSubfunction = GALFN_SETVBIENABLE; + sSetVbienable.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbienable)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_enable + * + * Description: This function gets the enable state of the VBI data capture. + * + * parameters: + * enable: VBI enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_enable(int *enable) +{ + GAL_VBIENABLE sGetVbienable; + + INIT_GAL(&sGetVbienable); + sGetVbienable.dwSubfunction = GALFN_GETVBIENABLE; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbienable)) { + return 0; + } else { + + *enable = sGetVbienable.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_base + * + * Description: This function sets the VBI base addresses. + * + * parameters: + * even: Even base address. + * odd: Odd base address. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_base(unsigned long even, unsigned long odd) +{ + GAL_VBIBASE sSetVbiBase; + + INIT_GAL(&sSetVbiBase); + sSetVbiBase.dwSubfunction = GALFN_SETVBIBASE; + sSetVbiBase.even = even; + sSetVbiBase.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbiBase)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_base + * + * Description: This function gets the VBI base address. + * + * parameters: + * address: VBI base address. + * odd: Odd base address. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_base(unsigned long *address, int odd) +{ + GAL_VBIBASE sGetVbiBase; + + INIT_GAL(&sGetVbiBase); + sGetVbiBase.dwSubfunction = GALFN_GETVBIBASE; + sGetVbiBase.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbiBase)) { + return 0; + } else { + *address = sGetVbiBase.address; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_pitch + * + * Description: This function sets the number of bytes between scanlines for + * VBI capture. + * + * parameters: + * pitch: VBI pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_pitch(unsigned long pitch) +{ + GAL_VBIPITCH sSetVbiPitch; + + INIT_GAL(&sSetVbiPitch); + sSetVbiPitch.dwSubfunction = GALFN_SETVBIPITCH; + sSetVbiPitch.pitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbiPitch)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_pitch + * + * Description: This function gets the number of bytes between scanlines for + * VBI capture. + * + * parameters: + * pitch: VBI pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_pitch(unsigned long *pitch) +{ + GAL_VBIPITCH sGetVbiPitch; + + INIT_GAL(&sGetVbiPitch); + sGetVbiPitch.dwSubfunction = GALFN_GETVBIPITCH; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbiPitch)) { + return 0; + } else { + *pitch = sGetVbiPitch.pitch; + return 1; + + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_mode + * + * Description: This function sets the VBI data types captured to memory. + * + * parameters: + * mode: VBI mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_mode(int mode) +{ + GAL_VBIMODE sSetVbiMode; + + INIT_GAL(&sSetVbiMode); + sSetVbiMode.dwSubfunction = GALFN_SETVBIMODE; + sSetVbiMode.mode = mode; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbiMode)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_mode + * + * Description: This function gets the VBI data types captured to memory. + * + * parameters: + * mode: VBI mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_mode(int *mode) +{ + GAL_VBIMODE sGetVbiMode; + + INIT_GAL(&sGetVbiMode); + sGetVbiMode.dwSubfunction = GALFN_GETVBIMODE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbiMode)) { + return 0; + } else { + + *mode = sGetVbiMode.mode; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_direct + * + * Description: This function sets the VBI lines to be passed to the + * Direct VIP. + * + * parameters: + * even_lines: VBI even lines. + * odd_lines: VBI odd lines. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines) +{ + GAL_SETVBIDIRECT sSetVbidirect; + + INIT_GAL(&sSetVbidirect); + sSetVbidirect.dwSubfunction = GALFN_SETVBIDIRECT; + sSetVbidirect.even_lines = even_lines; + sSetVbidirect.odd_lines = odd_lines; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbidirect)) { + return 0; + } else { + return 1; + } +} +BOOLEAN +Gal2_set_destination_stride(unsigned short stride) +{ + GAL_STRIDE sSetStride; + + INIT_GAL(&sSetStride); + sSetStride.dwSubfunction = GALFN_SETDESTINATIONSTRIDE; + + sSetStride.stride = stride; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetStride)) + return 0; + else + return 1; +} + +BOOLEAN +Gal2_set_pattern_origin(int x, int y) +{ + GAL_PATTERNORIGIN sSetPatOrigin; + + INIT_GAL(&sSetPatOrigin); + sSetPatOrigin.dwSubfunction = GALFN_SETPATTERNORIGIN; + + sSetPatOrigin.x = x; + sSetPatOrigin.y = y; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetPatOrigin)) + return 0; + else + return 1; +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_direct + * + * Description: This function gets the VBI lines to be passed to the + * Direct VIP. + * + * parameters: + * odd: VBI odd lines. + * direct_lines: VBI direct lines. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_direct(int odd, unsigned long *direct_lines) +{ + GAL_GETVBIDIRECT sGetVbidirect; + + INIT_GAL(&sGetVbidirect); + sGetVbidirect.dwSubfunction = GALFN_GETVBIDIRECT; + sGetVbidirect.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbidirect)) { + return 0; + } else { + *direct_lines = sGetVbidirect.direct_lines; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_interrupt + * + * Description: This function enable/disables the VBI field interrupt. + * + * parameters: + * enable: Value to enable/disable VBI interrupt. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_interrupt(int enable) +{ + GAL_VBIINTERRUPT sSetVbiinterrupt; + + INIT_GAL(&sSetVbiinterrupt); + sSetVbiinterrupt.dwSubfunction = GALFN_SETVBIINTERRUPT; + sSetVbiinterrupt.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbiinterrupt)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_interrupt + * + * Description: This function gets the VBI field interrupt. + * + * parameters: + * enable: Value of enable/disable VBI interrupt. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_interrupt(int *enable) +{ + GAL_VBIINTERRUPT sGetVbiinterrupt; + + INIT_GAL(&sGetVbiinterrupt); + sGetVbiinterrupt.dwSubfunction = GALFN_GETVBIINTERRUPT; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbiinterrupt)) { + return 0; + } else { + *enable = sGetVbiinterrupt.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_source_stride + * + * Description: This function sets the stride to be used in successive screen + * to screen BLTs. + * + * parameters: + * enable: Value of enable/disable VBI interrupt. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_set_source_stride(unsigned short stride) +{ + GAL_STRIDE sSetsourcestride; + + INIT_GAL(&sSetsourcestride); + sSetsourcestride.dwSubfunction = GALFN_SETSOURCESTRIDE; + + sSetsourcestride.stride = stride; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetsourcestride)) { + return 0; + } else { + + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_source_transparency + * + * Description: This function sets the source transparency color and + * mask to be used in future rendering routines. + * to screen BLTs. + * + * parameters: + * color: Source color. + * mask: Source mask. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_set_source_transparency(unsigned long color, unsigned long mask) +{ + GAL_SOURCETRANSPARENCY sSetsourcetransparency; + + INIT_GAL(&sSetsourcetransparency); + sSetsourcetransparency.dwSubfunction = GALFN_SETSOURCETRANSPARENCY; + + sSetsourcetransparency.color = color; + sSetsourcetransparency.mask = mask; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetsourcetransparency)) { + return 0; + } else { + + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_alpha_mode + * + * Description: This function sets the alpha blending mode. + * parameters: + * mode: Alpha blending mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_set_alpha_mode(int mode) +{ + GAL_GFX2ALPHAMODE sSetalphamode; + + INIT_GAL(&sSetalphamode); + sSetalphamode.dwSubfunction = GALFN_GFX2SETALPHAMODE; + + sSetalphamode.mode = mode; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetalphamode)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_gfx2_set_alpha_value + * + * Description: This function sets the alpha value to be used with certain + * alpha blending modes. + * parameters: + * value: Alpha blending value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_set_alpha_value(unsigned char value) +{ + GAL_GFX2ALPHAVALUE sSetalphavalue; + + INIT_GAL(&sSetalphavalue); + sSetalphavalue.dwSubfunction = GALFN_GFX2SETALPHAVALUE; + + sSetalphavalue.value = value; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetalphavalue)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal2_pattern_fill + * + * Description: This function used to fill the pattern of GX2. + * It allows the arbitary destination stride. The rendering + * position is also specified as an offset instead of (x,y) + * position. + * parameters: + * dstoffset: Rendering offset. + * width: Width of the pattern. + * height: Height of the pattern. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height) +{ + GAL_GFX2PATTERNFILL sPatternfill; + + INIT_GAL(&sPatternfill); + sPatternfill.dwSubfunction = GALFN_GFX2PATTERNFILL; + + sPatternfill.dstoffset = dstoffset; + sPatternfill.width = width; + sPatternfill.height = height; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sPatternfill)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_gfx2_screen_to_screen_blt + * + * Description: This function used for screen to screen BLTs of GX2. + * It allows the arbitary source and destination strides and + * alpha blending. + * parameters: + * srcoffset: Source Rendering offset. + * dstoffset: Destination Rendering offset. + * width: Width of the screen. + * height: Height of the screen. + * flags: Flags of the screen to screen BLT. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_screen_to_screen_blt(unsigned long srcoffset, + unsigned long dstoffset, unsigned short width, + unsigned short height, int flags) +{ + GAL_GFX2SCREENTOSCREENBLT sScreentoScreenblt; + + INIT_GAL(&sScreentoScreenblt); + sScreentoScreenblt.dwSubfunction = GALFN_GFX2SCREENTOSCREENBLT; + + sScreentoScreenblt.srcoffset = srcoffset; + sScreentoScreenblt.dstoffset = dstoffset; + sScreentoScreenblt.width = width; + sScreentoScreenblt.height = height; + sScreentoScreenblt.flags = flags; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sScreentoScreenblt)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal2_mono_expand_blt + * + * Description: This function used to expand monochrome data stored in + * graphics memory for screen to screen BLTs. + * parameters: + * srcbase: Source Rendering base address. + * srcx: Source X offset. + * srcy: Source Y offset. + * dstoffset: Destination Rendering offset. + * width: Width of the screen. + * height: Height of the screen. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_mono_expand_blt(unsigned long srcbase, unsigned short srcx, + unsigned short srcy, unsigned long dstoffset, + unsigned short width, unsigned short height, + int byte_packed) +{ + GAL_GFX2MONOEXPANDBLT sMonoexpandblt; + + INIT_GAL(&sMonoexpandblt); + sMonoexpandblt.dwSubfunction = GALFN_GFX2MONOEXPANDBLT; + sMonoexpandblt.srcbase = srcbase; + sMonoexpandblt.srcx = srcx; + sMonoexpandblt.srcy = srcy; + sMonoexpandblt.dstoffset = dstoffset; + sMonoexpandblt.width = width; + sMonoexpandblt.height = height; + sMonoexpandblt.byte_packed = byte_packed; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sMonoexpandblt)) { + return 0; + } else { + return 1; + + } +} + +/*-------------------------------------------------------------------------- + * Gal2_color_bitmap_to_screen_blt + * + * Description: This function used for color bmp to screen BLTs. + * parameters: + * srcx: Source X offset. + * srcy: Source Y offset. + * dstoffset: Destination Rendering offset. + * width: Width of the screen. + * height: Height of the screen. + * *data: Color bmp data. + * pitch: Pitch of the dispaly mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_color_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned long dstoffset, + unsigned short width, + unsigned short height, + unsigned char *data, unsigned short pitch) +{ + GAL_GFX2COLORBMPTOSCRBLT sColorbmptoscrblt; + + INIT_GAL(&sColorbmptoscrblt); + sColorbmptoscrblt.dwSubfunction = GALFN_GFX2COLORBMPTOSCRBLT; + sColorbmptoscrblt.srcx = srcx; + sColorbmptoscrblt.srcy = srcy; + sColorbmptoscrblt.dstoffset = dstoffset; + sColorbmptoscrblt.width = width; + sColorbmptoscrblt.height = height; + sColorbmptoscrblt.data = *data; + sColorbmptoscrblt.pitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sColorbmptoscrblt)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal2_mono_bitmap_to_screen_blt + * + * Description: This function used for mono bmp to screen BLTs. + * parameters: + * srcx: Source X offset. + * srcy: Source Y offset. + * dstoffset: Destination Rendering offset. + * width: Width of the screen. + * height: Height of the screen. + * *data: mono bmp data. + * pitch: Pitch of the display mode. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_mono_bitmap_to_screen_blt(unsigned short srcx, + unsigned short srcy, + unsigned long dstoffset, + unsigned short width, + unsigned short height, + unsigned char *data, unsigned short pitch) +{ + GAL_GFX2MONOBMPTOSCRBLT sMonobmptoscrblt; + + INIT_GAL(&sMonobmptoscrblt); + sMonobmptoscrblt.dwSubfunction = GALFN_GFX2MONOBMPTOSCRBLT; + sMonobmptoscrblt.srcx = srcx; + sMonobmptoscrblt.srcy = srcy; + sMonobmptoscrblt.dstoffset = dstoffset; + sMonobmptoscrblt.width = width; + sMonobmptoscrblt.height = height; + sMonobmptoscrblt.data = *data; + sMonobmptoscrblt.pitch = pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sMonobmptoscrblt)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal2_bresenham_line + * + * Description: This function used to draw bresenham line. It allows the + * arbitary destination stride. + * parameters: + * dstoffset: Destination offset. + * length: Length of the line. + * initerr: Intial error. + * axialerr: + * diagerr: + * flags: + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_bresenham_line(unsigned long dstoffset, unsigned short length, + unsigned short initerr, unsigned short axialerr, + unsigned short diagerr, unsigned short flags) +{ + GAL_GFX2BRESENHAMLINE sBresenhamline; + + INIT_GAL(&sBresenhamline); + sBresenhamline.dwSubfunction = GALFN_GFX2BRESENHAMLINE; + sBresenhamline.dstoffset = dstoffset; + sBresenhamline.length = length; + sBresenhamline.initerr = initerr; + sBresenhamline.axialerr = axialerr; + sBresenhamline.diagerr = diagerr; + sBresenhamline.flags = flags; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sBresenhamline)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal2_sync_to_vblank + * + * Description: This function sets the a flag to synchronize the next + * rendering routine to VBLANK. + * parameters: none. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal2_sync_to_vblank(void) +{ + GAL_GFX2SYNCTOVBLANK sSynctovblank; + + INIT_GAL(&sSynctovblank); + sSynctovblank.dwSubfunction = GALFN_GFX2SYNCTOVBLANK; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSynctovblank)) { + return 0; + } else { + return 1; + } +} + +/* Video routines */ + +/*-------------------------------------------------------------------------- + * Gal_set_video_yuv_pitch + * + * Description: This function sets the Video YUV pitch. + * + * parameters: + * y_pitch: Y pitch. + * uv_pitch: UV pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_yuv_pitch(unsigned long y_pitch, unsigned long uv_pitch) +{ + GAL_VIDEOYUVPITCH sSetVideoyuvpitch; + + INIT_GAL(&sSetVideoyuvpitch); + sSetVideoyuvpitch.dwSubfunction = GALFN_SETVIDEOYUVPITCH; + sSetVideoyuvpitch.y_pitch = y_pitch; + sSetVideoyuvpitch.uv_pitch = uv_pitch; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideoyuvpitch)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_video_yuv_pitch + * + * Description: This function gets the Video YUV pitch. + * + * parameters: + * y_pitch: Y pitch. + * uv_pitch: UV pitch. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_video_yuv_pitch(unsigned long *y_pitch, unsigned long *uv_pitch) +{ + GAL_VIDEOYUVPITCH sGetVideoyuvpitch; + + INIT_GAL(&sGetVideoyuvpitch); + sGetVideoyuvpitch.dwSubfunction = GALFN_GETVIDEOYUVPITCH; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVideoyuvpitch)) { + return 0; + } else { + *y_pitch = sGetVideoyuvpitch.y_pitch; + *uv_pitch = sGetVideoyuvpitch.uv_pitch; + + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_yuv_offsets + * + * Description: This function sets the Video YUV offsets. + * + * parameters: + * y_offset: Y offset. + * u_offset: U offset. + * v_offset: V offset. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_video_yuv_offsets(unsigned long y_offset, unsigned long u_offset, + unsigned long v_offset) +{ + GAL_VIDEOYUVOFFSETS sSetVideoyuvoffsets; + + INIT_GAL(&sSetVideoyuvoffsets); + sSetVideoyuvoffsets.dwSubfunction = GALFN_SETVIDEOYUVOFFSETS; + sSetVideoyuvoffsets.dwYoffset = y_offset; + sSetVideoyuvoffsets.dwUoffset = u_offset; + sSetVideoyuvoffsets.dwVoffset = v_offset; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideoyuvoffsets)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_video_yuv_offsets + * + * Description: This function gets the Video YUV offsets. + * + * parameters: + * y_offset: Y offset. + * u_offset: U offset. + * v_offset: V offset. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_get_video_yuv_offsets(unsigned long *y_offset, + unsigned long *u_offset, unsigned long *v_offset) +{ + GAL_VIDEOYUVOFFSETS sGetVideoyuvoffsets; + + INIT_GAL(&sGetVideoyuvoffsets); + sGetVideoyuvoffsets.dwSubfunction = GALFN_GETVIDEOYUVOFFSETS; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVideoyuvoffsets)) { + return 0; + } else { + *y_offset = sGetVideoyuvoffsets.dwYoffset; + *u_offset = sGetVideoyuvoffsets.dwUoffset; + *v_offset = sGetVideoyuvoffsets.dwVoffset; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_left_crop + * + * Description: This function sets the number of pixels which will be cropped + * from the beginning of each video line. + * + * parameters: + * x: + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_set_video_left_crop(unsigned short x) +{ + GAL_VIDEOLEFTCROP sSetVideoleftcrop;; + + INIT_GAL(&sSetVideoleftcrop); + sSetVideoleftcrop.dwSubfunction = GALFN_SETVIDEOLEFTCROP; + sSetVideoleftcrop.x = x; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideoleftcrop)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_video_vertical_downscale + * + * Description: This function sets the vertical downscale factor for the video + * overlay window. + * + * parameters: + * srch: Height of the source. + * dsth: Height of the destination. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_set_video_vertical_downscale(unsigned short srch, unsigned short dsth) +{ + GAL_VIDEOVERTICALDOWNSCALE sSetVideoverticaldownscale; + + INIT_GAL(&sSetVideoverticaldownscale); + sSetVideoverticaldownscale.dwSubfunction = GALFN_SETVIDEOVERTICALDOWNSCALE; + sSetVideoverticaldownscale.srch = srch; + sSetVideoverticaldownscale.dsth = dsth; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVideoverticaldownscale)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_source + * + * Description: This function sets the VBI source. + * + * parameters: + * source: VBI Source type. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_set_vbi_source(VbiSourceType source) +{ + GAL_VBISOURCE sSetVbisource; + + INIT_GAL(&sSetVbisource); + sSetVbisource.dwSubfunction = GALFN_SETVBISOURCE; + sSetVbisource.source = source; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbisource)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_source + * + * Description: This function gets the VBI source. + * + * parameters: + * source: VBI Source type. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_vbi_source(VbiSourceType * source) +{ + GAL_VBISOURCE sGetVbisource; + + INIT_GAL(&sGetVbisource); + sGetVbisource.dwSubfunction = GALFN_GETVBISOURCE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbisource)) { + return 0; + } else { + + *source = sGetVbisource.source; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_lines + * + * Description: This function sets the VBI lines. + * + * parameters: + * even: VBI even lines. + * odd: VBI odd lines. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_lines(unsigned long even, unsigned long odd) +{ + GAL_VBILINES sSetVbilines; + + INIT_GAL(&sSetVbilines); + sSetVbilines.dwSubfunction = GALFN_SETVBILINES; + sSetVbilines.even = even; + sSetVbilines.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbilines)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vbi_lines + * + * Description: This function gets the VBI lines. + * + * parameters: + * lines: VBI lines. + * odd: VBI odd lines. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_get_vbi_lines(int odd, unsigned long *lines) +{ + GAL_VBILINES sGetVbilines; + + INIT_GAL(&sGetVbilines); + sGetVbilines.dwSubfunction = GALFN_GETVBILINES; + sGetVbilines.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbilines)) { + return 0; + } else { + *lines = sGetVbilines.lines; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_total + * + * Description: This function sets the total number of VBI bytes for each + * field. + * + * parameters: + * even: + * odd: + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_vbi_total(unsigned long even, unsigned long odd) +{ + GAL_VBITOTAL sSetVbitotal; + + INIT_GAL(&sSetVbitotal); + sSetVbitotal.dwSubfunction = GALFN_SETVBITOTAL; + sSetVbitotal.even = even; + sSetVbitotal.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVbitotal)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vbi_total + * + * Description: This function gets the total number of VBI bytes in the + * field. + * + * parameters: + * even: + * odd: + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_get_vbi_total(int odd, unsigned long *total) +{ + GAL_VBITOTAL sGetVbitotal; + + INIT_GAL(&sGetVbitotal); + sGetVbitotal.dwSubfunction = GALFN_GETVBITOTAL; + sGetVbitotal.odd = odd; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVbitotal)) { + return 0; + } else { + *total = sGetVbitotal.total; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_vertical_scaler_offset + * + * Description: This function sets the Video vertical scaler offset. + * + * parameters: + * offset: Vertical Scaler offset. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_set_vertical_scaler_offset(char offset) +{ + GAL_VSCALEROFFSET sSetVscaleroffset; + + INIT_GAL(&sSetVscaleroffset); + sSetVscaleroffset.dwSubfunction = GALFN_SETVSCALEROFFSET; + sSetVscaleroffset.offset = offset; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetVscaleroffset)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_vertical_scaler_offset + * + * Description: This function gets the Video vertical scaler offset. + * + * parameters: + * offset: Vertical Scaler offset. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ BOOLEAN +Gal_get_vertical_scaler_offset(char *offset) +{ + GAL_VSCALEROFFSET sGetVscaleroffset; + + INIT_GAL(&sGetVscaleroffset); + sGetVscaleroffset.dwSubfunction = GALFN_GETVSCALEROFFSET; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetVscaleroffset)) { + return 0; + } else { + + *offset = sGetVscaleroffset.offset; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_video_interlaced + * + * Description: This function gets the video interlaced mode. + * parameters: + * interlaced: ptr to the interlaced status. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_video_interlaced(int *interlaced) +{ + GAL_GETVIDEOINTERLACED sGetvideointerlaced; + + INIT_GAL(&sGetvideointerlaced); + sGetvideointerlaced.dwSubfunction = GALFN_GETVIDEOINTERLACED; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetvideointerlaced)) { + return 0; + } else { + *interlaced = sGetvideointerlaced.interlaced; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_color_space_YUV + * + * Description: This function gets the video color space YUV. + * parameters: + * colorspace: ptr to the color space. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_color_space_YUV(int *colorspace) +{ + GAL_COLORSPACEYUV sGetcolorspaceyuv; + + INIT_GAL(&sGetcolorspaceyuv); + sGetcolorspaceyuv.dwSubfunction = GALFN_GETCOLORSPACEYUV; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetcolorspaceyuv)) { + return 0; + } else { + *colorspace = sGetcolorspaceyuv.colorspace; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_genlock_enable + * + * Description: This function gets the enable state of the genlock. + * parameters: + * enable: ptr to the enable state of the genlock. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_genlock_enable(int *enable) +{ + GAL_GENLOCKENABLE sGetgenlockenable; + + INIT_GAL(&sGetgenlockenable); + sGetgenlockenable.dwSubfunction = GALFN_GETGENLOCKENABLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetgenlockenable)) { + return 0; + } else { + *enable = sGetgenlockenable.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_genlock_enable + * + * Description: This function enable/disables and configure the genlock + * according to the parameters. + * parameters: + * enable: enable state of the genlock. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_genlock_enable(int enable) +{ + GAL_GENLOCKENABLE sSetgenlockenable; + + INIT_GAL(&sSetgenlockenable); + sSetgenlockenable.dwSubfunction = GALFN_SETGENLOCKENABLE; + + sSetgenlockenable.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetgenlockenable)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_genlock_delay + * + * Description: This function gets the genlock delay. + * parameters: + * delay: Ptr to the genlock delay. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_genlock_delay(unsigned long *delay) +{ + GAL_GENLOCKDELAY sGetgenlockdelay; + + INIT_GAL(&sGetgenlockdelay); + sGetgenlockdelay.dwSubfunction = GALFN_GETGENLOCKDELAY; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetgenlockdelay)) { + return 0; + } else { + *delay = sGetgenlockdelay.delay; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_genlock_delay + * + * Description: This function sets the genlock delay. + * parameters: + * delay: genlock delay. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_genlock_delay(unsigned long delay) +{ + GAL_GENLOCKDELAY sSetgenlockdelay; + + INIT_GAL(&sSetgenlockdelay); + sSetgenlockdelay.dwSubfunction = GALFN_SETGENLOCKDELAY; + + sSetgenlockdelay.delay = delay; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetgenlockdelay)) { + return 0; + } else { + return 1; + } +} + +BOOLEAN +Gal_set_top_line_in_odd(int enable) +{ + GAL_TOPLINEINODD sSettoplineinodd; + + INIT_GAL(&sSettoplineinodd); + sSettoplineinodd.dwSubfunction = GALFN_SETTOPLINEINODD; + + sSettoplineinodd.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSettoplineinodd)) { + return 0; + } else { + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_video_cursor. + * + * Description: This function gets configuration of the Video Hardware + * cursor. + * parameters: + * key: color key. + * mask: color mask. + *select_color2: selected for color2. + * color1: color1 value. + * color2: color2 value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_video_cursor(unsigned long *key, + unsigned long *mask, + unsigned short *select_color2, + unsigned long *color1, unsigned long *color2) +{ + GAL_VIDEOCURSOR sGetvideocursor; + + INIT_GAL(&sGetvideocursor); + sGetvideocursor.dwSubfunction = GALFN_GETVIDEOCURSOR; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetvideocursor)) { + return 0; + } else { + *key = sGetvideocursor.key; + *mask = sGetvideocursor.mask; + *select_color2 = sGetvideocursor.select_color2; + *color1 = sGetvideocursor.color1; + *color2 = sGetvideocursor.color2; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_read_crc. + * + * Description: This function reads the hardware CRC value, which is used for + * automated testing. + * parameters: + * crc: Holds the crc value. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_read_crc(unsigned long *crc) +{ + GAL_READCRC sReadcrc; + + INIT_GAL(&sReadcrc); + sReadcrc.dwSubfunction = GALFN_READCRC; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sReadcrc)) { + return 0; + } else { + *crc = sReadcrc.crc; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_read_window_crc. + * + * Description: This function reads the hardware CRC value for a subsection + * of the display. + * + * parameters: + * source: + * x: + * y: + * width: + * height: + * crc: + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, + int crc32, unsigned long *crc) +{ + GAL_READWINDOWCRC sReadwindowcrc; + + INIT_GAL(&sReadwindowcrc); + sReadwindowcrc.dwSubfunction = GALFN_READWINDOWCRC; + sReadwindowcrc.source = source; + sReadwindowcrc.x = x; + sReadwindowcrc.y = y; + sReadwindowcrc.width = width; + sReadwindowcrc.height = height; + sReadwindowcrc.crc32 = crc32; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sReadwindowcrc)) { + return 0; + } else { + *crc = sReadwindowcrc.crc; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_get_macrovision_enable. + * + * Description: This function gets the enable state of the macrovision. + * + * parameters: + * enable: ptr holds the macrovision enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_get_macrovision_enable(int *enable) +{ + GAL_MACROVISIONENABLE sGetmacrovisionenable; + + INIT_GAL(&sGetmacrovisionenable); + sGetmacrovisionenable.dwSubfunction = GALFN_GETMACROVISIONENABLE; + + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sGetmacrovisionenable)) { + return 0; + } else { + *enable = sGetmacrovisionenable.enable; + return 1; + } +} + +/*-------------------------------------------------------------------------- + * Gal_set_macrovision_enable. + * + * Description: This function gets the enable state of the macrovision. + * + * parameters: + * enable: macrovision enable state. + * return: '1' was returned on success otherwise '0' was returned. + *------------------------------------------------------------------------*/ +BOOLEAN +Gal_set_macrovision_enable(int enable) +{ + GAL_MACROVISIONENABLE sSetmacrovisionenable; + + INIT_GAL(&sSetmacrovisionenable); + sSetmacrovisionenable.dwSubfunction = GALFN_SETMACROVISIONENABLE; + + sSetmacrovisionenable.enable = enable; + if (ioctl(dfb_fbdev->fd, FBIOGAL_API, &sSetmacrovisionenable)) { + return 0; + } else { + return 1; + } +} diff --git a/Source/DirectFB/gfxdrivers/nvidia/Makefile.am b/Source/DirectFB/gfxdrivers/nvidia/Makefile.am new file mode 100755 index 0000000..8b495e9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/Makefile.am @@ -0,0 +1,45 @@ +## Makefile.am for DirectFB/src/core/gfxcards/nvidia + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +nvidia_LTLIBRARIES = libdirectfb_nvidia.la + +if BUILD_STATIC +nvidia_DATA = $(nvidia_LTLIBRARIES:.la=.o) +endif + +nvidiadir = $(MODULEDIR)/gfxdrivers + +libdirectfb_nvidia_la_SOURCES = \ + nvidia.c \ + nvidia_state.c \ + nvidia_2d.c \ + nvidia_3d.c \ + nvidia_primary.c \ + nvidia_overlay.c \ + nvidia.h \ + nvidia_regs.h \ + nvidia_accel.h \ + nvidia_objects.h \ + nvidia_state.h \ + nvidia_2d.h \ + nvidia_3d.h + +libdirectfb_nvidia_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_nvidia_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make diff --git a/Source/DirectFB/gfxdrivers/nvidia/Makefile.in b/Source/DirectFB/gfxdrivers/nvidia/Makefile.in new file mode 100755 index 0000000..472373c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/Makefile.in @@ -0,0 +1,614 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/nvidia +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(nvidiadir)" "$(DESTDIR)$(nvidiadir)" +nvidiaLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(nvidia_LTLIBRARIES) +libdirectfb_nvidia_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_nvidia_la_OBJECTS = nvidia.lo nvidia_state.lo \ + nvidia_2d.lo nvidia_3d.lo nvidia_primary.lo nvidia_overlay.lo +libdirectfb_nvidia_la_OBJECTS = $(am_libdirectfb_nvidia_la_OBJECTS) +libdirectfb_nvidia_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_nvidia_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_nvidia_la_SOURCES) +DIST_SOURCES = $(libdirectfb_nvidia_la_SOURCES) +nvidiaDATA_INSTALL = $(INSTALL_DATA) +DATA = $(nvidia_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ 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SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia.c new file mode 100755 index 0000000..6ecb17f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia.c @@ -0,0 +1,2046 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include + +DFB_GRAPHICS_DRIVER( nvidia ) + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_objects.h" +#include "nvidia_state.h" +#include "nvidia_2d.h" +#include "nvidia_3d.h" + + +/* Riva TNT */ +#define NV4_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV4_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV4_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_DEINTERLACE) + +#define NV4_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* Riva TNT2 */ +#define NV5_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV5_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV5_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_DEINTERLACE) + +#define NV5_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* GeForce1/GeForce2/GeForce4 */ +#define NV10_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV10_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV10_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE) + +#define NV10_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* GeForce3/GeForce4Ti */ +#define NV20_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV20_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV20_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE) + +#define NV20_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) + +/* GeForceFX */ +#define NV30_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV30_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV30_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_NOFX) + +#define NV30_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT) + + +#define DSBLIT_MODULATE_ALPHA \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL) + +#define DSBLIT_MODULATE_COLOR \ + (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) + +#define DSBLIT_MODULATE \ + (DSBLIT_MODULATE_ALPHA | DSBLIT_MODULATE_COLOR) + + + + +static void nvAfterSetVar( void *driver_data, + void *device_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + volatile u8 *mmio = nvdrv->mmio_base; + int i; + + nv_waitidle( nvdrv, nvdev ); + + /* reconfigure PFIFO for selected mode (DMA/PIO) */ + nv_out32( mmio, PFIFO_CACHES, PFIFO_CACHES_REASSIGN_DISABLED ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_MODE, PFIFO_MODE_CHANNEL_0_DMA ); + nv_out32( mmio, PFIFO_NEXT_CHANNEL, PFIFO_NEXT_CHANNEL_MODE_DMA ); + } else { + nv_out32( mmio, PFIFO_MODE, PFIFO_MODE_CHANNEL_0_PIO ); + nv_out32( mmio, PFIFO_NEXT_CHANNEL, PFIFO_NEXT_CHANNEL_MODE_PIO ); + } + nv_out32( mmio, PFIFO_CACHE1_PUSH0, PFIFO_CACHE1_PULL1_ENGINE_SW ); + nv_out32( mmio, PFIFO_CACHE1_PULL0, PFIFO_CACHE1_PULL0_ACCESS_DISABLED ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_CACHE1_PUSH1, PFIFO_CACHE1_PUSH1_MODE_DMA ); + } else { + nv_out32( mmio, PFIFO_CACHE1_PUSH1, PFIFO_CACHE1_PUSH1_MODE_PIO ); + } + nv_out32( mmio, PFIFO_CACHE1_DMA_PUT, 0 ); + nv_out32( mmio, PFIFO_CACHE1_DMA_GET, 0 ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_CACHE1_DMA_INSTANCE, ADDR_DMA_OUT ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_INSTANCE, 0 ); + } + nv_out32( mmio, PFIFO_CACHE0_PUSH0, PFIFO_CACHE0_PUSH0_ACCESS_DISABLED ); + nv_out32( mmio, PFIFO_CACHE0_PULL0, PFIFO_CACHE0_PULL0_ACCESS_DISABLED ); + nv_out32( mmio, PFIFO_RAMHT, 0x00000100 | + PFIFO_RAMHT_SIZE_4K | + PFIFO_RAMHT_SEARCH_128 ); + nv_out32( mmio, PFIFO_RAMFC, 0x00000110 ); + nv_out32( mmio, PFIFO_RAMRO, 0x00000112 | PFIFO_RAMRO_SIZE_512 ); + nv_out32( mmio, PFIFO_SIZE, 0x0000FFFF ); + nv_out32( mmio, PFIFO_CACHE1_HASH, 0x0000FFFF ); + nv_out32( mmio, PFIFO_INTR_EN, PFIFO_INTR_EN_DISABLED ); + nv_out32( mmio, PFIFO_INTR, PFIFO_INTR_RESET ); + nv_out32( mmio, PFIFO_CACHE0_PULL1, PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS ); + if (nvdev->use_dma) { + if (nvdev->use_agp) { + nv_out32( mmio, PFIFO_CACHE1_DMA_CTL, + PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT | + PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR | + PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_CTL, + PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT | + PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR | + PFIFO_CACHE1_DMA_CTL_TARGET_NODE_NVM ); + } + nv_out32( mmio, PFIFO_CACHE1_DMA_LIMIT, nvdev->dma_size - 4 ); + nv_out32( mmio, PFIFO_CACHE1_ENGINE, PFIFO_CACHE1_ENGINE_0_SW ); +#ifdef WORDS_BIGENDIAN + nv_out32( mmio, PFIFO_CACHE1_DMA_FETCH, + PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 | + PFIFO_CACHE1_BIG_ENDIAN ); +#else + nv_out32( mmio, PFIFO_CACHE1_DMA_FETCH, + PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 | + PFIFO_CACHE1_LITTLE_ENDIAN ); +#endif + nv_out32( mmio, PFIFO_CACHE1_DMA_PUSH, + PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_PUSH, + PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED ); + } + nv_out32( mmio, PFIFO_CACHE1_PUSH0, PFIFO_CACHE1_PUSH0_ACCESS_ENABLED ); + nv_out32( mmio, PFIFO_CACHE1_PULL0, PFIFO_CACHE1_PULL0_ACCESS_ENABLED ); + nv_out32( mmio, PFIFO_CACHE1_PULL1, PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS ); + nv_out32( mmio, PFIFO_CACHES, PFIFO_CACHES_REASSIGN_ENABLED ); + nv_out32( mmio, PFIFO_INTR_EN, PFIFO_INTR_EN_CACHE_ERROR_ENABLED ); + + if (nvdev->arch == NV_ARCH_10) { + nv_out32( mmio, PGRAPH_DEBUG_1, 0x00118701 ); + nv_out32( mmio, PGRAPH_DEBUG_2, 0x24F82AD9 ); + + for (i = 0; i < 8; i++) { + nv_out32( mmio, NV10_PGRAPH_WINDOWCLIP_HORIZONTAL+i*4, 0x07FF0800 ); + nv_out32( mmio, NV10_PGRAPH_WINDOWCLIP_VERTICAL +i*4, 0x07FF0800 ); + } + + nv_out32( mmio, NV10_PGRAPH_XFMODE0, 0x10000000 ); + nv_out32( mmio, NV10_PGRAPH_XFMODE1, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006740 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006750 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006760 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006770 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006780 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000067A0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AB0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AC0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006C10 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xBF800000 ); + + for (i = 0; i < 8; i++) { + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x7030+i*16 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x7149F2CA ); + } + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006A80 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AA0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000005 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006400 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x4B7FFFFF ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006410 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006420 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006430 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064C0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x477FFFFF ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064D0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064E0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC4FFF000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC4FFF000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064F0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_XFMODE0, 0x30000000 ); + nv_out32( mmio, NV10_PGRAPH_XFMODE1, 0x00000004 ); + nv_out32( mmio, NV10_PGRAPH_GLOBALSTATE0, 0x10000000 ); + nv_out32( mmio, NV10_PGRAPH_GLOBALSTATE1, 0x00000000 ); + } + + nvdev->dma_max = nvdev->dma_size/4 - 1; + nvdev->dma_cur = 0; + nvdev->dma_free = nvdev->dma_max; + nvdev->dma_put = 0; + nvdev->dma_get = 0; + nvdev->fifo_free = 0; +} + +static void nvEngineReset( void *drv, void *dev ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + int i; + + /* reput objects into subchannels */ + for (i = 0; i < 8; i++) { + nv_assign_object( nvdrv, nvdev, i, + nvdev->subchannel_object[i], true ); + } + + nvdev->set = 0; + nvdev->dst_format = DSPF_UNKNOWN; + nvdev->dst_pitch = 0; + nvdev->src_pitch = 0; + nvdev->beta1_set = false; + nvdev->beta4_set = false; +} + +static DFBResult nvEngineSync( void *drv, void *dev ) +{ + nv_waitidle( (NVidiaDriverData*)drv, (NVidiaDeviceData*)dev ); + + return DFB_OK; +} + +static void nvFlushTextureCache( void *drv, void *dev ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + /* invalidate source texture */ + nvdev->set &= ~SMF_SOURCE_TEXTURE; +} + +static void nvEmitCommands( void *drv, void *dev ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->use_dma) + nv_emitdma( nvdrv, nvdev ); +} + +static void nv4CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV4_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV4_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->src_blend != DSBF_SRCALPHA || + state->dst_blend != DSBF_INVSRCALPHA) + return; + } + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_A8: + case DSPF_RGB332: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_RGB16: + switch (accel) { + case DFXL_BLIT: + if (state->blittingflags != DSBLIT_NOFX || + destination->config.format != DSPF_RGB16) + return; + break; + case DFXL_STRETCHBLIT: + return; + default: + break; + } + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel == DFXL_TEXTRIANGLES) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV4_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV4_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV4_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv5CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV5_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV5_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_MODULATE) { + if (state->blittingflags & DSBLIT_MODULATE_ALPHA && + state->blittingflags & DSBLIT_MODULATE_COLOR) + return; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->src_blend != DSBF_SRCALPHA || + state->dst_blend != DSBF_INVSRCALPHA) + return; + } + } + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_A8: + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV5_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV5_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV5_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv10CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV10_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV10_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->blittingflags & DSBLIT_MODULATE_COLOR) { + if (source->config.format == DSPF_ARGB && + state->src_blend != DSBF_ONE) + return; + } + + if (state->src_blend != DSBF_ONE && + state->src_blend != DSBF_SRCALPHA) + return; + + if (state->dst_blend != DSBF_INVSRCALPHA) + return; + } + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_A8: + if (DFB_BYTES_PER_PIXEL(destination->config.format) != 4 /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV10_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV10_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV10_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv20CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting functions/flags */ + if (accel & ~NV20_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV20_SUPPORTED_BLITTINGFLAGS) + return; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->blittingflags & DSBLIT_MODULATE_COLOR) { + if (source->config.format == DSPF_ARGB && state->src_blend != DSBF_ONE) + return; + } + + if (state->src_blend != DSBF_ONE && + state->src_blend != DSBF_SRCALPHA) + return; + + if (state->dst_blend != DSBF_INVSRCALPHA) + return; + } + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + + switch (source->config.format) { + case DSPF_A8: + /*if (state->src.buffer->policy == CSP_SYSTEMONLY) + return;*/ + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + /*if (state->src.buffer->policy == CSP_SYSTEMONLY) + return;*/ + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV20_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV20_SUPPORTED_DRAWINGFLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->src_blend != DSBF_SRCALPHA && + state->dst_blend != DSBF_INVSRCALPHA) + return; + + state->accel |= NV20_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv30CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_DRAWING_FUNCTION( accel ) && + state->drawingflags != DSDRAW_NOFX) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting functions/flags */ + if (accel & ~NV30_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV30_SUPPORTED_BLITTINGFLAGS) + return; + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] != 0x10000 || state->matrix[1] || + state->matrix[3] || state->matrix[4] != 0x10000)) + return; + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (!dfb_palette_equal( source->palette, + destination->palette )) + return; + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_YUY2: + case DSPF_UYVY: + if (/*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + source->config.format != destination->config.format) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV30_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV30_SUPPORTED_DRAWINGFLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->src_blend != DSBF_SRCALPHA && + state->dst_blend != DSBF_INVSRCALPHA) + return; + + state->accel |= NV30_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +#define M_IDENTITY(m) ((m)[0] == 0x10000 && (m)[1] == 0 && (m)[2] == 0 && \ + (m)[3] == 0 && (m)[4] == 0x10000 && (m)[5] == 0) + +static void nv4SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv5SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } else { + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv10SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } else { + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv20SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + if (state->modified & SMF_SRC_BLEND) + nvdev->set &= ~SMF_BLITTING_FLAGS; + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } + else { + if (DFB_BITS_PER_PIXEL(nvdev->dst_format) == 8) + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CORNER | + SCALER_IN_FORMAT_FILTER_NEAREST; + else + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CENTER | + SCALER_IN_FORMAT_FILTER_LINEAR; + + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv30SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + nv_set_source( nvdrv, nvdev, state ); + + state->set = DFXL_BLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_NV4: + case FB_ACCEL_NV5: + case FB_ACCEL_NV_10: + case FB_ACCEL_NV_20: + case FB_ACCEL_NV_30: + case FB_ACCEL_NV_40: + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "nVidia NV4/NV5/NV10/NV20/NV30 Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + snprintf( info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org" ); + + snprintf( info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL" ); + + info->version.major = 0; + info->version.minor = 6; + + info->driver_data_size = sizeof(NVidiaDriverData); + info->device_data_size = sizeof(NVidiaDeviceData); +} + +static void +nv_find_architecture( NVidiaDriverData *nvdrv, u32 *ret_chip, u32 *ret_arch ) +{ + unsigned int vendor_id; + unsigned int device_id; + unsigned int arch = 0; + + device_id = nv_in32( nvdrv->mmio_base, 0x00 ) >> 16; /* id:rev */ + if (!device_id) { + dfb_system_get_deviceid( &vendor_id, &device_id ); + if (vendor_id != 0x10DE) { + D_ERROR( "DirectFB/NVidia: Could not detect device id!\n" + " -> Please, specify the bus location of" + " the card by using the 'busid' option.\n" ); + vendor_id = device_id = 0; + } + } + + switch (device_id & 0xFFF0) { + case 0x0020: /* Riva TNT/TNT2 */ + arch = (device_id == 0x0020) ? NV_ARCH_04 : NV_ARCH_05; + break; + case 0x0100: /* GeForce */ + case 0x0110: /* GeForce2 MX */ + case 0x0150: /* GeForce2 GTS/Ti/Ultra */ + case 0x0170: /* GeForce4 MX/Go */ + case 0x0180: /* GeForce4 MX/Go AGP8X */ + //case 0x01A0: /* GeForce2 Integrated GPU */ + //case 0x01F0: /* GeForce4 MX Integrated GPU */ + arch = NV_ARCH_10; + break; + case 0x0200: /* GeForce3 */ + case 0x0250: /* GeForce4 Ti */ + case 0x0280: /* GeForce4 Ti AGP8X */ + case 0x02A0: /* GeForce3 Integrated GPU (XBox) */ + arch = NV_ARCH_20; + break; + case 0x0300: /* GeForce FX 5800 */ + case 0x0310: /* GeForce FX 5600 */ + case 0x0320: /* GeForce FX 5200 */ + case 0x0330: /* GeForce FX 5900 */ + case 0x0340: /* GeForce FX 5700 */ + arch = NV_ARCH_30; + break; + default: + break; + } + + if (ret_chip) + *ret_chip = device_id; + if (ret_arch) + *ret_arch = arch; +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + u32 arch = 0; + + nvdrv->device = device; + nvdrv->device_data = device_data; + + nvdrv->fb_base = (volatile void*) dfb_gfxcard_memory_virtual( device, 0 ); + nvdrv->agp_base = (volatile void*) dfb_gfxcard_auxmemory_virtual( device, 0 ); + + nvdrv->mmio_base = (volatile void*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!nvdrv->mmio_base) + return DFB_IO; + + if (nvdev->use_dma) { + nvdrv->dma_base = nvdev->use_agp ? nvdrv->agp_base : nvdrv->fb_base; + nvdrv->dma_base += nvdev->dma_offset; + } + + funcs->AfterSetVar = nvAfterSetVar; + funcs->EngineReset = nvEngineReset; + funcs->EngineSync = nvEngineSync; + funcs->EmitCommands = nvEmitCommands; + funcs->FillRectangle = nvFillRectangle2D; // dynamic + funcs->FillTriangle = nvFillTriangle2D; // dynamic + funcs->DrawRectangle = nvDrawRectangle2D; // dynamic + funcs->DrawLine = nvDrawLine2D; // dynamic + funcs->Blit = nvBlit; // dynamic + + nv_find_architecture( nvdrv, NULL, &arch ); + + switch (arch) { + case NV_ARCH_04: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv4CheckState; + funcs->SetState = nv4SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_05: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv5CheckState; + funcs->SetState = nv5SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_10: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv10CheckState; + funcs->SetState = nv10SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_20: + funcs->CheckState = nv20CheckState; + funcs->SetState = nv20SetState; + funcs->StretchBlit = nvStretchBlit; + break; + case NV_ARCH_30: + funcs->CheckState = nv30CheckState; + funcs->SetState = nv30SetState; + break; + default: + funcs->AfterSetVar = NULL; + funcs->EngineReset = NULL; + break; + } + + dfb_screens_hook_primary( device, driver_data, + &nvidiaPrimaryScreenFuncs, + &OldPrimaryScreenFuncs, + &OldPrimaryScreenDriverData ); + + dfb_layers_hook_primary( device, driver_data, + &nvidiaPrimaryLayerFuncs, + &OldPrimaryLayerFuncs, + &OldPrimaryLayerDriverData ); + + dfb_layers_register( dfb_screens_at( DSCID_PRIMARY ), + driver_data, &nvidiaOverlayFuncs ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + int ram_total = dfb_system_videoram_length(); + int ram_used = dfb_gfxcard_memory_length(); + + nv_find_architecture( nvdrv, &nvdev->chip, &nvdev->arch ); + + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, + "NV%02X (%04x)", (nvdev->chip >> 4) & 0xFF, nvdev->chip ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "nVidia" ); + + switch (nvdev->arch) { + case NV_ARCH_04: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = NV4_SUPPORTED_DRAWINGFUNCTIONS | + NV4_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV4_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV4_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_05: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /*| CCF_READSYSMEM*/; + device_info->caps.accel = NV5_SUPPORTED_DRAWINGFUNCTIONS | + NV5_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV5_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV5_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_10: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /*| CCF_READSYSMEM*/; + device_info->caps.accel = NV10_SUPPORTED_DRAWINGFUNCTIONS | + NV10_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV10_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV10_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_20: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /* | CCF_READSYSMEM*/; /* Crash reported when the flag is on. */ + device_info->caps.accel = NV20_SUPPORTED_DRAWINGFUNCTIONS | + NV20_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV20_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV20_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_30: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = NV30_SUPPORTED_DRAWINGFUNCTIONS | + NV30_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV30_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV30_SUPPORTED_BLITTINGFLAGS; + break; + default: + device_info->caps.flags = 0; + device_info->caps.accel = 0; + device_info->caps.drawing = 0; + device_info->caps.blitting = 0; + break; + } + + device_info->limits.surface_byteoffset_alignment = 64; + device_info->limits.surface_pixelpitch_alignment = 32; + + dfb_config->pollvsync_after = 1; + + /* GeForce3 Intergrated GPU (XBox) */ + if (nvdev->chip == 0x02A0) { + nvdev->fb_offset = (long)nvdrv->fb_base & 0x0FFFFFFF; + ram_total += nvdev->fb_offset; + } + + nvdev->fb_size = 1 << direct_log2( ram_total ); + + /* skip if unsupported arch (NV40) */ + if (!nvdev->arch) + return DFB_OK; + + nvdev->agp_offset = dfb_gfxcard_auxmemory_physical( nvdrv->device, 0 ); + + if (dfb_config->dma) { + int offset = -1; + + if (dfb_gfxcard_auxmemory_length() >= 64*1024) { + offset = dfb_gfxcard_reserve_auxmemory( nvdrv->device, 64*1024 ); + if (offset < 0) { + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve 64Kb of agp memory!\n" ); + } + else { + nvdev->use_agp = true; + nvdev->use_dma = true; + nvdev->dma_size = 64*1024; + nvdev->dma_offset = offset; + nvdrv->dma_base = nvdrv->agp_base + offset; + } + } + + if (offset < 0) { + int len; + + len = 32*1024 + ((ram_used - 32*1024) & 0x1FFFF); + offset = dfb_gfxcard_reserve_memory( nvdrv->device, len ); + if (offset < 0) { + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve %d bytes of video memory!\n", len ); + } + else { + nvdev->use_dma = true; + nvdev->dma_size = 32*1024; + nvdev->dma_offset = offset; + nvdrv->dma_base = nvdrv->fb_base + offset; + + ram_used -= len; + } + } + + D_INFO ( "DirectFB/NVidia: DMA acceleration %s.\n", + nvdev->use_dma ? "enabled" : "disabled" ); + D_DEBUG( "DirectFB/NVidia: DMA target is %s.\n", + nvdev->use_agp ? "AGP" : "NVM" ); + } + + /* reserve memory for textures/color buffers */ + if (device_info->caps.accel & DFXL_TEXTRIANGLES) { + unsigned tex_size; + int len, offset; + + /* if we have more than 32MB of video memory, use a 1024x1024 texture */ + if (ram_used > (32 << 20)) + tex_size = 1024*1024; + /* if we have more than 16MB of video memory, use a 1024x512 texture */ + else if (ram_used > (16 << 20)) + tex_size = 1024*512; + /* otherwise use a 512x512 texture */ + else + tex_size = 512*512; + + len = tex_size*2 + 8; + len += (ram_used - len) & 0xFF; + offset = dfb_gfxcard_reserve_memory( nvdrv->device, len ); + + if (offset < 0) { + /* if video memory allocation failed, disable 3d acceleration */ + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve %d bytes of video memory!\n", len ); + D_INFO( "DirectFB/NVidia: 3D acceleration disabled.\n" ); + device_info->caps.accel &= ~DFXL_TEXTRIANGLES; + } + else { + D_DEBUG( "DirectFB/NVidia: " + "reserved %d bytes for 3D buffers at offset 0x%08x.\n", + len, offset ); + + nvdev->enabled_3d = true; + nvdev->buf_offset[0] = offset + tex_size*2; // color + nvdev->buf_offset[1] = offset; // texture + nvdev->max_texture_size = tex_size; + } + } + + if (nvdev->enabled_3d) { + /* set default 3d state for drawing functions */ + nvdev->state3d[0].modified = true; + nvdev->state3d[0].colorkey = 0; + nvdev->state3d[0].offset = nvdev->fb_offset + nvdev->buf_offset[0]; + nvdev->state3d[0].format = TXTRI_FORMAT_CONTEXT_DMA_A | + TXTRI_FORMAT_ORIGIN_ZOH_CORNER | + TXTRI_FORMAT_ORIGIN_FOH_CORNER | + TXTRI_FORMAT_COLOR_R5G6B5 | + TXTRI_FORMAT_U_WRAP | + TXTRI_FORMAT_V_WRAP | + 0x00111000; // 2x2 + nvdev->state3d[0].filter = TXTRI_FILTER_TEXTUREMIN_NEAREST | + TXTRI_FILTER_TEXTUREMAG_NEAREST; + nvdev->state3d[0].blend = TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA | + TXTRI_BLEND_OPERATION_MUX_TALPHAMSB | + TXTRI_BLEND_SHADEMODE_FLAT | + TXTRI_BLEND_SRCBLEND_ONE | + TXTRI_BLEND_DESTBLEND_ZERO; + nvdev->state3d[0].control = TXTRI_CONTROL_ALPHAFUNC_ALWAYS | + TXTRI_CONTROL_ORIGIN_CORNER | + TXTRI_CONTROL_ZFUNC_ALWAYS | + TXTRI_CONTROL_CULLMODE_NONE | + TXTRI_CONTROL_Z_FORMAT_FIXED; + nvdev->state3d[0].fog = 0; + + /* set default 3d state for blitting functions */ + nvdev->state3d[1].modified = true; + nvdev->state3d[1].colorkey = 0; + nvdev->state3d[1].offset = nvdev->fb_offset + nvdev->buf_offset[1]; + nvdev->state3d[1].format = TXTRI_FORMAT_CONTEXT_DMA_A | + TXTRI_FORMAT_ORIGIN_ZOH_CORNER | + TXTRI_FORMAT_ORIGIN_FOH_CORNER | + TXTRI_FORMAT_COLOR_R5G6B5 | + TXTRI_FORMAT_U_CLAMP | + TXTRI_FORMAT_V_CLAMP | + 0x00001000; + nvdev->state3d[1].filter = TXTRI_FILTER_TEXTUREMIN_LINEAR | + TXTRI_FILTER_TEXTUREMAG_LINEAR; + nvdev->state3d[1].blend = TXTRI_BLEND_TEXTUREMAPBLEND_COPY | + TXTRI_BLEND_OPERATION_MUX_TALPHAMSB | + TXTRI_BLEND_SHADEMODE_GOURAUD | + TXTRI_BLEND_TEXTUREPERSPECTIVE_ENABLE | + TXTRI_BLEND_SRCBLEND_ONE | + TXTRI_BLEND_DESTBLEND_ZERO; + nvdev->state3d[1].control = TXTRI_CONTROL_ALPHAFUNC_ALWAYS | + TXTRI_CONTROL_ORIGIN_CENTER | + TXTRI_CONTROL_ZFUNC_ALWAYS | + TXTRI_CONTROL_CULLMODE_NONE | + TXTRI_CONTROL_DITHER_ENABLE | + TXTRI_CONTROL_Z_FORMAT_FIXED; + nvdev->state3d[1].fog = 0; + + /* clear color buffer */ + memset( dfb_gfxcard_memory_virtual( device, + nvdev->buf_offset[0] ), 0xFF, 8 ); + } + + /* write dma objects configuration */ + nv_store_dma( nvdrv, OBJ_DMA_IN, ADDR_DMA_IN, 0x00, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_NVM, + nvdev->fb_size, 0x00000000, DMA_FRAME_ACCESS_RDWR ); + + if (nvdev->use_dma) { + if (nvdev->use_agp) { + nv_store_dma( nvdrv, OBJ_DMA_OUT, ADDR_DMA_OUT, 0x02, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_AGP, + nvdev->dma_size, nvdev->agp_offset+nvdev->dma_offset, + DMA_FRAME_ACCESS_RDWR ); + } + else { + nv_store_dma( nvdrv, OBJ_DMA_OUT, ADDR_DMA_OUT, 0x02, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_NVM, + nvdev->dma_size, nvdev->fb_offset+nvdev->dma_offset, + DMA_FRAME_ACCESS_RDWR ); + } + } + + /* write graphics objects configuration */ + nv_store_object( nvdrv, OBJ_SURFACES2D, ADDR_SURFACES2D, 0x42, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_CLIP, ADDR_CLIP, 0x19, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_BETA1, ADDR_BETA1, 0x12, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_BETA4, ADDR_BETA4, 0x72, 0, 0, 0 ); + + nv_store_object( nvdrv, OBJ_RECTANGLE, ADDR_RECTANGLE, 0x5E, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TRIANGLE, ADDR_TRIANGLE, 0x5D, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_LINE, ADDR_LINE, 0x5C, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + + switch (nvdev->arch) { + case NV_ARCH_04: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x1F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x37, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_COPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x54, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_COPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x53, 0, 0, 0 ); + break; + + case NV_ARCH_05: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x5F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x63, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x54, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x53, 0, 0, 0 ); + break; + + case NV_ARCH_10: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x5F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x89, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x94, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x93, 0, 0, 0 ); + break; + + case NV_ARCH_20: + case NV_ARCH_30: + default: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x9F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x89, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x94, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x93, 0, 0, 0 ); + break; + } + + /* assign default objects to subchannels */ + nvdev->subchannel_object[SUBC_SURFACES2D] = OBJ_SURFACES2D; + nvdev->subchannel_object[SUBC_CLIP] = OBJ_CLIP; + nvdev->subchannel_object[SUBC_RECTANGLE] = OBJ_RECTANGLE; + nvdev->subchannel_object[SUBC_TRIANGLE] = OBJ_TRIANGLE; + nvdev->subchannel_object[SUBC_LINE] = OBJ_LINE; + nvdev->subchannel_object[SUBC_SCREENBLT] = OBJ_SCREENBLT; + nvdev->subchannel_object[SUBC_SCALEDIMAGE] = OBJ_SCALEDIMAGE; + nvdev->subchannel_object[SUBC_TEXTRIANGLE] = OBJ_TEXTRIANGLE; + + if (nvdev->arch == NV_ARCH_04) { + nvdev->drawing_operation = OPERATION_COPY; + nvdev->scaler_operation = OPERATION_COPY; + nvdev->scaler_filter = 0; + nvdev->system_operation = OPERATION_COPY; + } else { + nvdev->drawing_operation = OPERATION_SRCCOPY; + nvdev->scaler_operation = OPERATION_SRCCOPY; + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CENTER | + SCALER_IN_FORMAT_FILTER_LINEAR; + nvdev->system_operation = OPERATION_SRCCOPY; + } + + nvAfterSetVar( driver_data, device_data ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + + D_DEBUG( "DirectFB/NVidia: Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/NVidia: %9d nv_wait* calls\n", + nvdev->waitfree_calls ); + D_DEBUG( "DirectFB/NVidia: %9d register writes\n", + nvdev->waitfree_sum ); + D_DEBUG( "DirectFB/NVidia: %9d FIFO/DMA wait cycles (depends on CPU)\n", + nvdev->free_waitcycles ); + D_DEBUG( "DirectFB/NVidia: %9d IDLE wait cycles (depends on CPU)\n", + nvdev->idle_waitcycles ); + D_DEBUG( "DirectFB/NVidia: %9d FIFO/DMA space cache hits (depends on CPU)\n", + nvdev->cache_hits ); + D_DEBUG( "DirectFB/NVidia: Conclusion:\n" ); + D_DEBUG( "DirectFB/NVidia: Average register writes/nv_wait* call:%.2f\n", + nvdev->waitfree_sum/(float)(nvdev->waitfree_calls ? : 1) ); + D_DEBUG( "DirectFB/NVidia: Average wait cycles/nv_wait* call: %.2f\n", + nvdev->free_waitcycles/(float)(nvdev->waitfree_calls ? : 1) ); + D_DEBUG( "DirectFB/NVidia: Average FIFO/DMA space cache hits: %02d%%\n", + (int)(100 * nvdev->cache_hits/ + (float)(nvdev->waitfree_calls ? : 1)) ); + + /* reset channel mode to PIO to avoid crash in rivafb */ + if (nvdev->use_dma) { + nvdev->use_dma = false; + nvAfterSetVar( driver_data, device_data ); + } +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, nvdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia.h new file mode 100755 index 0000000..9b9062c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia.h @@ -0,0 +1,238 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_H__ +#define __NVIDIA_H__ + +#include + +#include +#include +#include + + +/* + * Object's identifier + */ +enum { + OBJ_DMA_IN = 0x00800000, + OBJ_SURFACES2D = 0x00800001, + OBJ_SURFACES3D = 0x00800002, + OBJ_CLIP = 0x00800003, + OBJ_BETA1 = 0x00800004, + OBJ_BETA4 = 0x00800005, + OBJ_RECTANGLE = 0x00800010, + OBJ_TRIANGLE = 0x00800011, + OBJ_LINE = 0x00800012, + OBJ_SCREENBLT = 0x00800013, + OBJ_IMAGEBLT = 0x00800014, + OBJ_SCALEDIMAGE = 0x00800015, + OBJ_STRETCHEDIMAGE = 0x00800016, + OBJ_TEXTRIANGLE = 0x00800017, + OBJ_DMA_OUT = 0x00800018 +}; + +/* + * Object's offset into context table [PRAMIN + (address)*16] + */ +enum { + ADDR_DMA_IN = 0x1160, + ADDR_SURFACES2D = 0x1162, + ADDR_SURFACES3D = 0x1163, + ADDR_CLIP = 0x1164, + ADDR_BETA1 = 0x1165, + ADDR_BETA4 = 0x1166, + ADDR_RECTANGLE = 0x1167, + ADDR_TRIANGLE = 0x1168, + ADDR_LINE = 0x1169, + ADDR_SCREENBLT = 0x116A, + ADDR_IMAGEBLT = 0x116B, + ADDR_SCALEDIMAGE = 0x116C, + ADDR_STRETCHEDIMAGE = 0x116D, + ADDR_TEXTRIANGLE = 0x116E, + ADDR_DMA_OUT = 0x116F +}; + +/* + * Object's subchannel + */ +enum { + SUBC_SURFACES2D = 0, + SUBC_SURFACES3D = 0, + SUBC_BETA1 = 0, + SUBC_BETA4 = 0, + SUBC_CLIP = 1, + SUBC_RECTANGLE = 2, + SUBC_TRIANGLE = 3, + SUBC_LINE = 4, + SUBC_SCREENBLT = 5, + SUBC_IMAGEBLT = 5, + SUBC_SCALEDIMAGE = 6, + SUBC_STRETCHEDIMAGE = 6, + SUBC_TEXTRIANGLE = 7 +}; + + +#define SMF_DRAWING_COLOR (SMF_COLOR << 16) +#define SMF_BLITTING_COLOR (SMF_COLOR << 17) +#define SMF_SOURCE_TEXTURE (SMF_SOURCE << 1) + +typedef struct { + StateModificationFlags set; + + u32 fb_offset; + u32 fb_size; + u32 agp_offset; + + DFBSurfacePixelFormat dst_format; + u32 dst_offset; + u32 dst_pitch; + bool dst_422; + + DFBSurfacePixelFormat src_format; + u32 src_offset; + u8 *src_address; + u32 src_pitch; + u32 src_width; + u32 src_height; + bool src_system; + bool src_interlaced; + CoreSurfaceBufferLock *src_lock; + + DFBRectangle clip; + + u32 color2d; + u32 color3d; + + DFBSurfaceDrawingFlags drawingflags; + DFBSurfaceBlittingFlags blittingflags; + + const s32 *matrix; + + /* NVRectangle/NVTriangle/NVLine registers */ + u32 drawing_operation; // SetOperation + + /* NVScaledImage registers */ + u32 scaler_operation; // SetOperation + u32 scaler_format; // SetColorFormat + u32 scaler_filter; // SetImageInFormat + + /* NVImageBlt/NVStretchedImage registers */ + u32 system_operation; // SetOperation + u32 system_format; // SetColorFormat + + /* Remember value of NVBeta1 & NVBeta4 */ + bool beta1_set; + u32 beta1_val; + bool beta4_set; + u32 beta4_val; + + /* 3D stuff */ + bool enabled_3d; // 3d engine enabled + u32 buf_offset[2]; // reserved buffers + CoreSurfaceBuffer *src_texture; // current source for TextureTriangles + u32 max_texture_size; + + struct { + bool modified; + u32 colorkey; + u32 offset; + u32 format; + u32 filter; + u32 blend; + u32 control; + u32 fog; + } state3d[2]; // 0 => drawing | 1 => blitting + + /* Remember subchannels configuration */ + u32 subchannel_object[8]; + + /* Chipsets informations */ + u32 chip; + u32 arch; + + /* AGP control */ + bool use_agp; + int agp_key; + unsigned int agp_aper_base; + unsigned int agp_aper_size; + + /* DMA control */ + bool use_dma; + unsigned int dma_size; + unsigned int dma_offset; + unsigned int dma_max; + unsigned int dma_cur; + unsigned int dma_free; + unsigned int dma_put; + unsigned int dma_get; + volatile u32 *cmd_ptr; + + /* FIFO control */ + unsigned int fifo_free; + + /* for performance monitoring */ + unsigned int waitfree_sum; + unsigned int waitfree_calls; + unsigned int free_waitcycles; + unsigned int idle_waitcycles; + unsigned int cache_hits; +} NVidiaDeviceData; + + +enum { + NV_ARCH_04 = 0x04, + NV_ARCH_05 = 0x05, + NV_ARCH_10 = 0x10, + NV_ARCH_20 = 0x20, + NV_ARCH_30 = 0x30 +}; + +typedef struct { + CoreGraphicsDevice *device; + NVidiaDeviceData *device_data; + + volatile void *fb_base; + volatile void *agp_base; + volatile void *mmio_base; + volatile void *dma_base; +} NVidiaDriverData; + + +extern ScreenFuncs nvidiaPrimaryScreenFuncs; +extern ScreenFuncs OldPrimaryScreenFuncs; +extern void *OldPrimaryScreenDriverData; + +extern DisplayLayerFuncs nvidiaPrimaryLayerFuncs; +extern DisplayLayerFuncs OldPrimaryLayerFuncs; +extern void *OldPrimaryLayerDriverData; + +extern DisplayLayerFuncs nvidiaOverlayFuncs; + + +#endif /* __NVIDIA_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c new file mode 100755 index 0000000..63e1728 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c @@ -0,0 +1,549 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_2d.h" + + +static void +nv_copy32( volatile u32 *dst, u8 *src, int n ) +{ + u32 *D = (u32*) dst; + u32 *S = (u32*) src; + +#ifdef ARCH_X86 + __asm__ __volatile__( + "rep; movsl" + : "=&D" (D), "=&S" (S) + : "c" (n), "0" (D), "1" (S) + : "memory" ); +#else + do { + *D++ = *S++; + } while (--n); +#endif +} + +static void +nv_copy16( volatile u32 *dst, u8 *src, int n ) +{ + u32 *D = (u32*) dst; + u16 *S = (u16*) src; + +#ifdef ARCH_X86 + __asm__ __volatile__( + "rep; movsl" + : "=&D" (D), "=&S" (S) + : "c" (n/2), "0" (D), "1" (S) + : "memory" ); +#else + for (; n > 1; n -= 2) { + *D++ = *((u32*)S); + S += 2; + } +#endif + + if (n & 1) + *D = *S; +} + +static inline bool +nv_clip_source( DFBRectangle *rect, u32 width, u32 height ) +{ + if (rect->x >= width || rect->y >= height) + return false; + + if (rect->x < 0) { + rect->w += rect->x; + rect->x = 0; + } + if (rect->y < 0) { + rect->h += rect->y; + rect->y = 0; + } + + rect->w = MIN( rect->w, width - rect->x ); + rect->h = MIN( rect->h, height - rect->y ); + + return (rect->w > 0 && rect->h > 0); +} + + +#define M_TRANSFORM(x, y, retx, rety, m) { \ + s32 _x, _y; \ + _x = ((s64)(x) * (m)[0] + (y) * (m)[1] + (m)[2] + 0x8000) >> 16; \ + _y = ((s64)(x) * (m)[3] + (y) * (m)[4] + (m)[5] + 0x8000) >> 16; \ + retx = _x; \ + rety = _y; \ +} + + +bool nvFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->matrix) { + int x1 = rect->x, x2 = rect->x+rect->w; + int y1 = rect->y, y2 = rect->y+rect->h; + int x, y; + + nv_begin( SUBC_TRIANGLE, TRI_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + } + else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_RECTANGLE, RECT_TOP_LEFT, 2 ); + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + } + + return true; +} + +bool nvFillTriangle2D( void *drv, void *dev, DFBTriangle *tri ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->matrix) { + M_TRANSFORM( tri->x1, tri->y1, tri->x1, tri->y1, nvdev->matrix ); + M_TRANSFORM( tri->x2, tri->y3, tri->x2, tri->y2, nvdev->matrix ); + M_TRANSFORM( tri->x3, tri->y3, tri->x3, tri->y3, nvdev->matrix ); + } + + nv_begin( SUBC_TRIANGLE, TRI_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + nv_outr( (tri->y1 << 16) | (tri->x1 & 0xFFFF) ); + nv_outr( (tri->y2 << 16) | (tri->x2 & 0xFFFF) ); + nv_outr( (tri->y3 << 16) | (tri->x3 & 0xFFFF) ); + + return true; +} + +bool nvDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->matrix) { + int x1 = rect->x, x2 = rect->x+rect->w; + int y1 = rect->y, y2 = rect->y+rect->h; + int x, y; + + nv_begin( SUBC_LINE, LINE_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_LINE, LINE_POINT0, 8 ); + /* top */ + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* right */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* bottom */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* left */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + } + else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_RECTANGLE, RECT_TOP_LEFT, 8 ); + /* top */ + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (1 << 16) | (rect->w & 0xFFFF) ); + /* bottom */ + nv_outr( ((rect->y + rect->h - 1) << 16) | (rect->x & 0xFFFF) ); + nv_outr( (1 << 16) | (rect->w & 0xFFFF) ); + /* left */ + nv_outr( ((rect->y + 1) << 16) | (rect->x & 0xFFFF) ); + nv_outr( ((rect->h - 2) << 16) | 1 ); + /* right */ + nv_outr( ((rect->y + 1) << 16) | ((rect->x + rect->w - 1) & 0xFFFF) ); + nv_outr( ((rect->h - 2) << 16) | 1 ); + } + + return true; +} + +bool nvDrawLine2D( void *drv, void *dev, DFBRegion *line ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->matrix) { + M_TRANSFORM( line->x1, line->y1, line->x1, line->y1, nvdev->matrix ); + M_TRANSFORM( line->x2, line->y2, line->x2, line->y2, nvdev->matrix ); + } + + nv_begin( SUBC_LINE, LINE_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_LINE, LINE_POINT0, 2 ); + nv_outr( (line->y1 << 16) | (line->x1 & 0xFFFF) ); + nv_outr( (line->y2 << 16) | (line->x2 & 0xFFFF) ); + + return true; +} + +bool nvBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE || nvdev->matrix) { + DFBRectangle dr = { dx, dy, rect->w, rect->h }; + return nvStretchBlit( drv, dev, rect, &dr ); + } + + if (nvdev->dst_422) { + dx /= 2; + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->blittingflags || nvdev->src_format != nvdev->dst_format) { + DFBRectangle *clip = &nvdev->clip; + u32 src_width = (nvdev->src_width + 1) & ~1; + u32 src_height = (nvdev->src_height + 1) & ~1; + u32 filter = 0; + + if (nvdev->dst_422) + src_width >>= 1; + + if (nvdev->arch > NV_ARCH_04) + filter = SCALER_IN_FORMAT_ORIGIN_CORNER | + SCALER_IN_FORMAT_FILTER_NEAREST; + + nv_begin( SUBC_SCALEDIMAGE, SCALER_COLOR_FORMAT, 1 ); + nv_outr( nvdev->scaler_format ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_CLIP_POINT, 6 ); + nv_outr( (clip->y << 16) | (clip->x & 0xFFFF) ); + nv_outr( (clip->h << 16) | (clip->w & 0xFFFF) ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + nv_outr( 0x100000 ); + nv_outr( 0x100000 ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_IN_SIZE, 4 ); + nv_outr( (src_height << 16) | (src_width & 0xFFFF) ); + nv_outr( (nvdev->src_pitch & 0xFFFF) | filter ); + nv_outr( nvdev->src_offset ); + nv_outr( (rect->y << 20) | ((rect->x<<4) & 0xFFFF) ); + } + else { + nv_begin( SUBC_SCREENBLT, BLIT_TOP_LEFT_SRC, 3 ); + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + } + + return true; +} + +bool nvBlitFromCPU( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + u8 *src = nvdev->src_address; + u32 src_w; + u32 src_h; + int w, h, n; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE || nvdev->matrix) { + DFBRectangle dr = { dx, dy, rect->x, rect->y }; + return nvStretchBlitFromCPU( drv, dev, rect, &dr ); + } + + if (!nv_clip_source( rect, nvdev->src_width, nvdev->src_height )) + return true; + + src_w = (DFB_BYTES_PER_PIXEL(nvdev->src_format) == 2) + ? ((rect->w + 1) & ~1) : rect->w; + src_h = rect->h; + + nv_begin( SUBC_IMAGEBLT, IBLIT_COLOR_FORMAT, 1 ); + nv_outr( nvdev->system_format ); + + nv_begin( SUBC_IMAGEBLT, IBLIT_POINT, 3 ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + nv_outr( (src_h << 16) | (src_w & 0xFFFF) ); + + n = nvdev->use_dma ? 256 : 128; + + switch (nvdev->src_format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + src += rect->y * nvdev->src_pitch + rect->x * 2; + for (h = rect->h; h--;) { + u8 *s = src; + + for (w = rect->w; w >= n*2; w -= n*2) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, (w+1)>>1 ); + nv_copy16( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + + default: + src += rect->y * nvdev->src_pitch + rect->x * 4; + for (h = rect->h; h--;) { + u8 *s = src; + + for (w = rect->w; w >= n; w -= n) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, w ); + nv_copy32( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + } + + return true; +} + +bool nvStretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRectangle *cr = &nvdev->clip; + u32 src_width = (nvdev->src_width + 1) & ~1; + u32 src_height = (nvdev->src_height + 1) & ~1; + + if (nvdev->dst_422) { + sr->x /= 2; + sr->w = (sr->w+1) >> 1; + dr->x /= 2; + dr->w = (dr->w+1) >> 1; + src_width >>= 1; + } + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h = (sr->h+1) / 2; + } + + if (nvdev->matrix) { + int x1, y1, x2, y2; + + if (!nvdev->matrix[0] || !nvdev->matrix[4]) + return true; + + M_TRANSFORM( dr->x, dr->y, x1, y1, nvdev->matrix ); + M_TRANSFORM( dr->x+dr->w, dr->y+dr->h, x2, y2, nvdev->matrix ); + + dr->x = x1; dr->w = x2-x1; + dr->y = y1; dr->h = y2-y1; + } + + nv_begin( SUBC_SCALEDIMAGE, SCALER_COLOR_FORMAT, 1 ); + nv_outr( nvdev->scaler_format ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_CLIP_POINT, 6 ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + nv_outr( (dr->y << 16) | (dr->x & 0xFFFF) ); + nv_outr( (dr->h << 16) | (dr->w & 0xFFFF) ); + nv_outr( (sr->w << 20) / dr->w ); + nv_outr( (sr->h << 20) / dr->h ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_IN_SIZE, 4 ); + nv_outr( (src_height << 16) | (src_width & 0xFFFF) ); + nv_outr( (nvdev->src_pitch & 0xFFFF) | nvdev->scaler_filter ); + nv_outr( nvdev->src_offset ); + nv_outr( (sr->y << 20) | ((sr->x << 4) & 0xFFFF) ); + + return true; +} + +bool nvStretchBlitFromCPU( void *drv, void *dev, + DFBRectangle *sr, DFBRectangle *dr ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRectangle *cr = &nvdev->clip; + u8 *src = nvdev->src_address; + u32 src_w; + u32 src_h; + int w, h, n; + + if (!nv_clip_source( sr, nvdev->src_width, nvdev->src_height )) + return true; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h /= 2; + } + + if (nvdev->matrix) { + int x1, y1, x2, y2; + + if (!nvdev->matrix[0] || !nvdev->matrix[4]) + return true; + + M_TRANSFORM( dr->x, dr->y, x1, y1, nvdev->matrix ); + M_TRANSFORM( dr->x+dr->w, dr->y+dr->h, x2, y2, nvdev->matrix ); + + dr->x = x1; dr->w = x2-x1; + dr->y = y1; dr->h = y2-y1; + } + + src_w = (DFB_BYTES_PER_PIXEL(nvdev->src_format) == 2) + ? ((sr->w + 1) & ~1) : sr->w; + src_h = sr->h; + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_COLOR_FORMAT, 1 ); + nv_outr( nvdev->system_format ); + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_IN_SIZE, 6 ); + nv_outr( (src_h << 16) | (src_w & 0xFFFF) ); + nv_outr( (dr->w << 20) / src_w ); + nv_outr( (dr->h << 20) / src_h ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + nv_outr( (dr->y << 20) | ((dr->x<<4) & 0xFFFF) ); + + n = nvdev->use_dma ? 256 : 128; + + switch (nvdev->src_format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + src += sr->y * nvdev->src_pitch + sr->x * 2; + for (h = sr->h; h--;) { + u8 *s = src; + + for (w = sr->w; w >= n*2; w -= n*2) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, (w+1)>>1 ); + nv_copy16( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + + default: + src += sr->y * nvdev->src_pitch + sr->x * 4; + for (h = sr->h; h--;) { + u8 *s= src; + + for (w = sr->w; w >= n; w -= n) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, w ); + nv_copy32( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + } + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h new file mode 100755 index 0000000..b195aef --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h @@ -0,0 +1,48 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_2D_H__ +#define __NVIDIA_2D_H__ + +bool nvFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvFillTriangle2D( void *drv, void *dev, DFBTriangle *tri ); + +bool nvDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvDrawLine2D( void *drv, void *dev, DFBRegion *line ); + +bool nvBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +bool nvBlitFromCPU( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +bool nvStretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +bool nvStretchBlitFromCPU( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +#endif /* __NVIDIA_2D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c new file mode 100755 index 0000000..ae8dffc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c @@ -0,0 +1,522 @@ +/* + Copyright (C) 2004-2006 Claudio Ciccani + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_3d.h" + + +static __inline__ u32 +f2d( float f ) { + union { + float f; + u32 d; + } t; + t.f = f; + return t.d; +} + +#define nv_setstate3d( state3d ) { \ + if ((state3d)->modified) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_COLOR_KEY, 7 ); \ + nv_outr( (state3d)->colorkey ); \ + nv_outr( (state3d)->offset ); \ + nv_outr( (state3d)->format ); \ + nv_outr( (state3d)->filter ); \ + nv_outr( (state3d)->blend ); \ + nv_outr( (state3d)->control ); \ + nv_outr( (state3d)->fog ); \ + \ + (state3d)->modified = false; \ + } \ +} + +#define nv_putvertex( i, x, y, z, w, col, spc, s, t ) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_VERTEX0+(i)*32, 8 ); \ + nv_outr( f2d( x ) ); \ + nv_outr( f2d( y ) ); \ + nv_outr( f2d( z ) ); \ + nv_outr( f2d( w ) ); \ + nv_outr( col ); \ + nv_outr( spc ); \ + nv_outr( f2d( s ) ); \ + nv_outr( f2d( t ) ); \ +} + +#define nv_emit_vertices( i, v0, v1, v2, v3, v4, v5, v6, v7 ) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_PRIMITIVE0+(i)*4, 1 ); \ + nv_outr( ((v7) << 28) | ((v6) << 24) | \ + ((v5) << 20) | ((v4) << 16) | \ + ((v3) << 12) | ((v2) << 8) | \ + ((v1) << 4) | (v0) ); \ +} + + +static void nv_load_texture( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ); + + +#define M_TRANSFORM(x, y, retx, rety, m) { \ + float _x, _y; \ + _x = ((x) * (m)[0] + (y) * (m)[1] + (m)[2]) / 65536.f; \ + _y = ((x) * (m)[3] + (y) * (m)[4] + (m)[5]) / 65536.f; \ + retx = _x; \ + rety = _y; \ +} + + +bool nvFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float x1, y1; + float x2, y2; + + x1 = rect->x; x2 = rect->x+rect->w; + y1 = rect->y; y2 = rect->y+rect->h; + + nv_setstate3d( &nvdev->state3d[0] ); + + if (nvdev->matrix) { + float x, y; + + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_putvertex( 0, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_putvertex( 1, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_putvertex( 2, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_putvertex( 3, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + } + else { + nv_putvertex( 0, x1, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x2, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x2, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, x1, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + } + + nv_emit_vertices( 0, 0, 1, 2, 0, 2, 3, 0, 0 ); + + return true; +} + +bool nvFillTriangle3D( void *drv, void *dev, DFBTriangle *tri ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float x1, y1; + float x2, y2; + float x3, y3; + + x1 = tri->x1; x2 = tri->x2; x3 = tri->x3; + y1 = tri->y1; y2 = tri->y2; y3 = tri->y3; + if (nvdev->matrix) { + M_TRANSFORM( x1, y1, x1, y1, nvdev->matrix ); + M_TRANSFORM( x2, y2, x2, y2, nvdev->matrix ); + M_TRANSFORM( x3, y3, x3, y3, nvdev->matrix ); + } + + nv_setstate3d( &nvdev->state3d[0] ); + + nv_putvertex( 0, x1, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x2, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x3, y3, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + return true; +} + +bool nvDrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRegion r[4]; + int i; + + if (nvdev->matrix) { + DFBRegion line; + + /* top */ + line = (DFBRegion) { rect->x, rect->y, rect->x+rect->w, rect->y }; + nvDrawLine3D( drv, dev, &line ); + /* right */ + line = (DFBRegion) { rect->x+rect->w, rect->y, rect->x+rect->w, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + /* bottom */ + line = (DFBRegion) { rect->x, rect->y+rect->h, rect->x+rect->w, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + /* left */ + line = (DFBRegion) { rect->x, rect->y, rect->x, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + + return true; + } + + /* top */ + r[0].x1 = rect->x; + r[0].y1 = rect->y; + r[0].x2 = rect->x + rect->w; + r[0].y2 = rect->y + 1; + + /* right */ + r[1].x1 = rect->x + rect->w - 1; + r[1].y1 = rect->y + 1; + r[1].x2 = rect->x + rect->w; + r[1].y2 = rect->y + rect->h - 1; + + /* bottom */ + r[2].x1 = rect->x; + r[2].y1 = rect->y + rect->h - 1; + r[2].x2 = rect->x + rect->w; + r[2].y2 = rect->y + rect->h; + + /* left */ + r[3].x1 = rect->x; + r[3].y1 = rect->y + 1; + r[3].x2 = rect->x + 1; + r[3].y2 = rect->y + rect->h - 1; + + nv_setstate3d( &nvdev->state3d[0] ); + + for (i = 0; i < 4; i++) { + nv_putvertex( 0, r[i].x1, r[i].y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, r[i].x2, r[i].y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, r[i].x2, r[i].y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, r[i].x1, r[i].y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 0, 1, 2, 0, 2, 3, 0, 0 ); + } + + return true; +} + +bool nvDrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float xinc, yinc; + float x1, y1; + float x2, y2; + float dx, dy; + + x1 = line->x1; x2 = line->x2; + y1 = line->y1; y2 = line->y2; + if (nvdev->matrix) { + M_TRANSFORM( x1, y1, x1, y1, nvdev->matrix ); + M_TRANSFORM( x2, y2, x2, y2, nvdev->matrix ); + + dx = fabs(x2 - x1); + dy = fabs(y2 - y1); + } + else { + dx = abs(line->x2 - line->x1); + dy = abs(line->y2 - line->y1); + } + + if (dx > dy) { /* more horizontal */ + xinc = 0.0; + yinc = 0.5; + } else { /* more vertical */ + xinc = 0.5; + yinc = 0.0; + } + + nv_setstate3d( &nvdev->state3d[0] ); + + nv_putvertex( 0, x1 - xinc, y1 - yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x1 + xinc, y1 + yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x2 + xinc, y2 + yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, x2 - xinc, y2 - yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 2, 0, 1, 3, 0, 2, 0, 0 ); + + return true; +} + +bool nvTextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float s_scale; + float t_scale; + int i; + + /* load source texture into texture buffer */ + nv_load_texture( nvdrv, nvdev ); + + s_scale = (float)nvdev->src_width / + (float)(1 << ((nvdev->state3d[1].format >> 16) & 0xF)); + t_scale = (float)nvdev->src_height / + (float)(1 << ((nvdev->state3d[1].format >> 20) & 0xF)); + + for (i = 0; i < num; i++) { + if (nvdev->matrix) + M_TRANSFORM( ve[i].x, ve[i].y, ve[i].x, ve[i].y, nvdev->matrix ); + ve[i].x += 0.5; + ve[i].y += 0.5; + ve[i].s *= s_scale; + ve[i].t *= t_scale; + } + + nv_setstate3d( &nvdev->state3d[1] ); + + switch (formation) { + case DTTF_LIST: + for (i = 0; i < num; i += 3) { + nv_putvertex( 0, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_putvertex( 1, ve[i+1].x, ve[i+1].y, ve[i+1].z, ve[i+1].w, + nvdev->color3d, 0, ve[i+1].s, ve[i+1].t ); + nv_putvertex( 2, ve[i+2].x, ve[i+2].y, ve[i+2].z, ve[i+2].w, + nvdev->color3d, 0, ve[i+2].s, ve[i+2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + case DTTF_STRIP: + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[1].x, ve[1].y, ve[1].z, ve[1].w, + nvdev->color3d, 0, ve[1].s, ve[1].t ); + nv_putvertex( 2, ve[2].x, ve[2].y, ve[2].z, ve[2].w, + nvdev->color3d, 0, ve[2].s, ve[2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + for (i = 3; i < num; i++) { + nv_putvertex( 0, ve[i-2].x, ve[i-2].y, ve[i-2].z, ve[i-2].w, + nvdev->color3d, 0, ve[i-2].s, ve[i-2].t ); + nv_putvertex( 1, ve[i-1].x, ve[i-1].y, ve[i-1].z, ve[i-1].w, + nvdev->color3d, 0, ve[i-1].s, ve[i-1].t ); + nv_putvertex( 2, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + case DTTF_FAN: + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[1].x, ve[1].y, ve[1].z, ve[1].w, + nvdev->color3d, 0, ve[1].s, ve[1].t ); + nv_putvertex( 2, ve[2].x, ve[2].y, ve[2].z, ve[2].w, + nvdev->color3d, 0, ve[2].s, ve[2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + for (i = 3; i < num; i++) { + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[i-1].x, ve[i-1].y, ve[i-1].z, ve[i-1].w, + nvdev->color3d, 0, ve[i-1].s, ve[i-1].t ); + nv_putvertex( 2, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + default: + D_BUG( "unexpected triangle formation" ); + return false; + } + + return true; +} + +/* + * Surface to Texture conversion routines. + */ + +#define VINC 0xAAAAAAAC +#define VMASK 0x55555555 +#define UINC 0x55555558 +#define UMASK 0xAAAAAAAA + +static inline void +a8_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = ((src[i+0] & 0xF0) << 24) | + ((src[i+1] & 0xF0) << 8) | + 0x0FFF0FFF; +#else + dst[(u|v)/4] = ((src[i+0] & 0xF0) << 8) | + ((src[i+1] & 0xF0) << 24) | + 0x0FFF0FFF; +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ((src[width-1] & 0xF0) << 8) | 0x0FFF; + } + + src += pitch; + } +} + +static inline void +rgb16_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width/2; i++, u = (u + UINC) & UMASK) + dst[(u|v)/4] = ((u32*) src)[i]; + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ((u16*) src)[width-1]; + } + + src += pitch; + } +} + +static inline void +rgb32_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { + register u32 pix0, pix1; + pix0 = ((u32*) src)[i]; + pix0 = RGB32_TO_RGB16( pix0 ); + pix1 = ((u32*) src)[i+1]; + pix1 = RGB32_TO_RGB16( pix1 ); +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = (pix0 << 16) | pix1; +#else + dst[(u|v)/4] = pix0 | (pix1 << 16); +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = RGB32_TO_RGB16( ((u32*) src)[width-1] ); + } + + src += pitch; + } +} + +static inline void +argb_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { + register u32 pix0, pix1; + pix0 = ((u32*) src)[i]; + pix0 = ARGB_TO_ARGB4444( pix0 ); + pix1 = ((u32*) src)[i+1]; + pix1 = ARGB_TO_ARGB4444( pix1 ); +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = (pix0 << 16) | pix1; +#else + dst[(u|v)/4] = pix0 | (pix1 << 16); +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ARGB_TO_ARGB4444( ((u32*) src)[width-1] ); + } + + src += pitch; + } +} + +static void nv_load_texture( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev ) +{ + CoreSurfaceBuffer *buffer = nvdev->src_texture; + u32 *dst; + + dst = dfb_gfxcard_memory_virtual( nvdrv->device, nvdev->buf_offset[1] ); + +#if 0 + if (nvdev->src_interlaced) { + if (surface->caps & DSCAPS_SEPARATED) { + if (surface->field) + field_offset = nvdev->src_height * src_pitch; + } else { + if (surface->field) + field_offset = src_pitch; + src_pitch *= 2; + } + } +#endif + + switch (buffer->format) { + case DSPF_A8: + a8_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + rgb16_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_RGB32: + rgb32_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_ARGB: + argb_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h new file mode 100755 index 0000000..ade71f7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h @@ -0,0 +1,36 @@ +/* + Copyright (C) 2004-2006 Claudio Ciccani + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_3D_H__ +#define __NVIDIA_3D_H__ + + +bool nvFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvFillTriangle3D( void *drv, void *dev, DFBTriangle *tri ); + +bool nvDrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvDrawLine3D( void *drv, void *dev, DFBRegion *line ); + +bool nvTextureTriangles( void *drv, void *dev, DFBVertex *vertices, + int num, DFBTriangleFormation formation ); + + +#endif /* __NVIDIA_3D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h new file mode 100755 index 0000000..2858947 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h @@ -0,0 +1,246 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_ACCEL_H__ +#define __NVIDIA_ACCEL_H__ + +#include + +#include "nvidia.h" +#include "nvidia_regs.h" + + +static __inline__ void +nv_out8( volatile void *mmioaddr, u32 reg, u8 value ) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static __inline__ void +nv_out16( volatile void *mmioaddr, u32 reg, u16 value ) +{ + *((volatile u16*)(mmioaddr+reg)) = value; +} + +static __inline__ void +nv_out32( volatile void *mmioaddr, u32 reg, u32 value ) +{ + *((volatile u32*)(mmioaddr+reg)) = value; +} + +static __inline__ u8 +nv_in8( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static __inline__ u16 +nv_in16( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u16*)(mmioaddr+reg)); +} + +static __inline__ u32 +nv_in32( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u32*)(mmioaddr+reg)); +} + +static __inline__ void +nv_outcrtc( volatile void *mmioaddr, u8 reg, u8 value ) +{ + nv_out8( mmioaddr, PCIO_CRTC_INDEX, reg ); + nv_out8( mmioaddr, PCIO_CRTC_DATA, value ); +} + +static __inline__ u8 +nv_incrtc( volatile void *mmioaddr, u8 reg ) +{ + nv_out8( mmioaddr, PCIO_CRTC_INDEX, reg ); + return nv_in8( mmioaddr, PCIO_CRTC_DATA ); +} + +#define WAIT_MAX 10000000 + +static inline void +nv_waitidle( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ) +{ + u32 status; + int waitcycles = 0; + + do { + status = nv_in32( nvdrv->mmio_base, PGRAPH_STATUS ); + if (++waitcycles > WAIT_MAX) { + D_BREAK( "Engine timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (status & PGRAPH_STATUS_STATE_BUSY); + + nvdev->idle_waitcycles += waitcycles; +} + +/* + * FIFO control + */ + +static inline void +nv_waitfifo( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + unsigned int space ) +{ + volatile void *mmio = nvdrv->mmio_base; + int waitcycles = 0; + + nvdev->waitfree_sum += (space); + nvdev->waitfree_calls++; + + if (nvdev->fifo_free < space) { + do { +#ifdef WORDS_BIGENDIAN + nvdev->fifo_free = nv_in16( mmio, FIFO_FREE ) >> 2; +#else + nvdev->fifo_free = nv_in32( mmio, FIFO_FREE ) >> 2; +#endif + if (++waitcycles > WAIT_MAX) { + D_BREAK( "FIFO timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (nvdev->fifo_free < space); + + nvdev->free_waitcycles += waitcycles; + } else + nvdev->cache_hits++; + + nvdev->fifo_free -= space; +} + +/* + * DMA control + */ + +static inline void +nv_emitdma( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ) +{ + if (nvdev->dma_put != nvdev->dma_cur) { + volatile u8 scratch; + + /* flush MTRR buffers */ + scratch = nv_in8( nvdrv->fb_base, 0 ); + nv_out32( nvdrv->mmio_base, DMA_PUT, nvdev->dma_cur << 2 ); + + nvdev->dma_put = nvdev->dma_cur; + } +} + +static inline void +nv_waitdma( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + unsigned int space ) +{ + volatile void *mmio = nvdrv->mmio_base; + volatile void *ring = nvdrv->dma_base; + int waitcycles = 0; + + nvdev->waitfree_sum += (space); + nvdev->waitfree_calls++; + + if (nvdev->dma_free < space) { + do { + nvdev->dma_get = nv_in32( mmio, DMA_GET ) >> 2; + + if (nvdev->dma_put >= nvdev->dma_get) { + nvdev->dma_free = nvdev->dma_max - nvdev->dma_cur; + + if (nvdev->dma_free < space) { + /* rewind ring */ + nv_out32( ring, nvdev->dma_cur << 2, 0x20000000 ); + + if (!nvdev->dma_get) { + if (!nvdev->dma_put) { + nvdev->dma_cur = 1; + nv_emitdma( nvdrv, nvdev ); + } + + do { + nvdev->dma_get = nv_in32( mmio, DMA_GET ) >> 2; + if (++waitcycles > WAIT_MAX) { + D_BREAK( "DMA timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (!nvdev->dma_get); + } + + nvdev->dma_cur = 0; + nv_emitdma( nvdrv, nvdev ); + + nvdev->dma_free = nvdev->dma_get - 1; + } + } + else { + nvdev->dma_free = nvdev->dma_get - nvdev->dma_cur - 1; + } + + if (++waitcycles > WAIT_MAX) { + D_BREAK( "DMA timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (nvdev->dma_free < space); + + nvdev->free_waitcycles += waitcycles; + } else + nvdev->cache_hits++; + + nvdev->dma_free -= space; +} + +/* Begin writing into ring/fifo */ +#define nv_begin( subc, start, size ) { \ + if (nvdev->use_dma) { \ + nv_waitdma( nvdrv, nvdev, (size)+1 ); \ + nv_out32( nvdrv->dma_base, nvdev->dma_cur << 2, \ + ((size) << 18) | ((subc)*0x2000 + (start)) ); \ + nvdev->cmd_ptr = nvdrv->dma_base; \ + nvdev->cmd_ptr += nvdev->dma_cur + 1; \ + nvdev->dma_cur += (size) + 1; \ + D_ASSERT( nvdev->dma_cur <= nvdev->dma_max ); \ + } else { \ + nv_waitfifo( nvdrv, nvdev, size ); \ + nvdev->cmd_ptr = (nvdrv->mmio_base + FIFO_ADDRESS + \ + (subc)*0x2000 + (start)); \ + } \ +} + +/* Output to ring/register */ +#define nv_outr( value ) *nvdev->cmd_ptr++ = (value) + + +#endif /* __NVIDIA_ACCEL_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h new file mode 100755 index 0000000..a0e329f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h @@ -0,0 +1,160 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_OBJECTS_H__ +#define __NVIDIA_OBJECTS_H__ + +#include "nvidia.h" +#include "nvidia_accel.h" + +/* Engine */ +#define ENGINE_SW 0 +#define ENGINE_GRAPHICS 1 +#define ENGINE_DVD 2 + + +static __inline__ u32 +nv_hashkey( u32 obj ) +{ + return ((obj >> 0) & 0x000001FF) ^ + ((obj >> 9) & 0x000001FF) ^ + ((obj >> 18) & 0x000001FF) ^ + ((obj >> 27) & 0x000001FF) ^ (0 << 5); /* channel 0 */ +} + + +/* DMA flags */ +#define DMA_FLAG_PAGE_TABLE (1 << 12) /* valid */ +#define DMA_FLAG_PAGE_ENTRY_NONLIN (0 << 13) +#define DMA_FLAG_PAGE_ENTRY_LINEAR (1 << 13) +#define DMA_FLAG_ACCESS_RDWR (0 << 14) +#define DMA_FLAG_ACCESS_RDONLY (1 << 14) +#define DMA_FLAG_ACCESS_WRONLY (2 << 14) +#define DMA_FLAG_TARGET_NVM (0 << 16) +#define DMA_FLAG_TARGET_NVM_TILED (1 << 16) +#define DMA_FLAG_TARGET_PCI (2 << 16) +#define DMA_FLAG_TARGET_AGP (3 << 16) + +/* DMA frame access */ +#define DMA_FRAME_UNKNOWN_FLAG (1 << 0) +#define DMA_FRAME_ACCESS_RDONLY (0 << 1) +#define DMA_FRAME_ACCESS_RDWR (1 << 1) + +static inline void +nv_store_dma( NVidiaDriverData *nvdrv, u32 obj, + u32 addr, u32 class, u32 flags, + u32 size, u32 frame, u32 access ) +{ + volatile void *mmio = nvdrv->mmio_base; + u32 key = nv_hashkey( obj ); + u32 ctx = addr | (ENGINE_SW << 16) | (1 << 31); + + /* NV_PRAMIN_RAMRO_0 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 0, class | flags ); + nv_out32( mmio, PRAMIN + (addr << 4) + 4, size - 1 ); + nv_out32( mmio, PRAMIN + (addr << 4) + 8, (frame & 0xFFFFF000) | access ); + nv_out32( mmio, PRAMIN + (addr << 4) + 12, (frame & 0xFFFFF000) | access ); + + /* store object id and context */ + nv_out32( mmio, PRAMHT + (key << 3) + 0, obj ); + nv_out32( mmio, PRAMHT + (key << 3) + 4, ctx ); +} + + +/* Context flags */ +#define CTX_FLAG_CHROMA_KEY (1 << 12) +#define CTX_FLAG_USER_CLIP (1 << 13) +#define CTX_FLAG_SWIZZLE (1 << 14) +#define CTX_FLAG_PATCH_COPY (0 << 15) +#define CTX_FLAG_PATCH_ROP (1 << 15) +#define CTX_FLAG_PATCH_BLEND (2 << 15) +#define CTX_FLAG_PATCH_SRCCOPY (3 << 15) +#define CTX_FLAG_PATCH_COLOR_MULTIPLY (4 << 15) +#define CTX_FLAG_PATCH_BLEND_PREMULTIPLIED (5 << 15) +#define CTX_FLAG_SYNCHRONIZE (1 << 18) +#define CTX_FLAG_ENDIAN_LITTLE (0 << 19) +#define CTX_FLAG_ENDIAN_BIG (1 << 19) +#define CTX_FLAG_CONVERSION_COMPAT (0 << 20) +#define CTX_FLAG_CONVERSION_DITHER (1 << 20) +#define CTX_FLAG_CONVERSION_TRUNC (2 << 20) +#define CTX_FLAG_CONVERSION_SUB_TRUNC (3 << 20) +#define CTX_FLAG_SINGLE_STEP (1 << 23) +#define CTX_FLAG_PATCH (1 << 24) /* valid */ +#define CTX_FLAG_CTX_SURFACE0 (1 << 25) /* valid */ +#define CTX_FLAG_CTX_SURFACE1 (1 << 26) /* valid */ +#define CTX_FLAG_CTX_PATTERN (1 << 27) /* valid */ +#define CTX_FLAG_CTX_ROP (1 << 28) /* valid */ +#define CTX_FLAG_CTX_BETA1 (1 << 29) /* valid */ +#define CTX_FLAG_CTX_BETA4 (1 << 30) /* valid */ + + +static inline void +nv_store_object( NVidiaDriverData *nvdrv, + u32 obj, u32 addr, + u32 class, u32 flags, + u32 dma0, u32 dma1 ) +{ + volatile void *mmio = nvdrv->mmio_base; + u32 key = nv_hashkey( obj ); + u32 ctx = addr | (ENGINE_GRAPHICS << 16) | (1 << 31); + + /* set the endian flag here, for simplicity */ +#ifdef WORDS_BIGENDIAN + flags |= CTX_FLAG_ENDIAN_BIG; +#endif + /* NV_PRAMIN_CTX_0 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 0, class | flags ); + /* NV_PRAMIN_CTX_1 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 4, 0x00000000 ); /* color */ + /* NV_PRAMIN_CTX_2 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 8, dma0 | (dma1 << 16) ); + /* NV_PRAMIN_CTX_3 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 12, 0x00000000 ); /* traps */ + + /* store object id and context */ + nv_out32( mmio, PRAMHT + (key << 3) + 0, obj ); + nv_out32( mmio, PRAMHT + (key << 3) + 4, ctx ); +} + + +static inline void +nv_assign_object( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + int subc, + u32 object, + bool reset ) +{ + if (reset || nvdev->subchannel_object[subc] != object) { + nv_begin( subc, SET_OBJECT, 1 ); + nv_outr( object ); + + nvdev->subchannel_object[subc] = object; + } +} + +#endif /* __NVIDIA_OBJECTS_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c new file mode 100755 index 0000000..747f14c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c @@ -0,0 +1,566 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Oliver Schwartz and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" + + +typedef struct { + CoreLayerRegionConfig config; + CoreSurface *videoSurface; + CoreSurfaceBufferLock *lock; + + short brightness; + short contrast; + short hue; + short saturation; + int field; + + struct { + u32 BUFFER; + u32 STOP; + u32 UVBASE_0; + u32 UVBASE_1; + u32 UVOFFSET_0; + u32 UVOFFSET_1; + u32 BASE_0; + u32 BASE_1; + u32 OFFSET_0; + u32 OFFSET_1; + u32 SIZE_IN_0; + u32 SIZE_IN_1; + u32 POINT_IN_0; + u32 POINT_IN_1; + u32 DS_DX_0; + u32 DS_DX_1; + u32 DT_DY_0; + u32 DT_DY_1; + u32 POINT_OUT_0; + u32 POINT_OUT_1; + u32 SIZE_OUT_0; + u32 SIZE_OUT_1; + u32 FORMAT_0; + u32 FORMAT_1; + } regs; +} NVidiaOverlayLayerData; + +static void ov0_set_regs ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfigFlags flags ); +static void ov0_calc_regs ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags flags ); +static void ov0_set_colorkey( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config ); +static void ov0_set_csc ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0 ); + +#define OV0_SUPPORTED_OPTIONS \ + ( DLOP_DST_COLORKEY | DLOP_DEINTERLACING ) + +/**********************/ + + + +static int +ov0LayerDataSize( void ) +{ + return sizeof(NVidiaOverlayLayerData); +} + +static DFBResult +ov0InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | + DLCAPS_SATURATION | DLCAPS_HUE | + DLCAPS_DST_COLORKEY | DLCAPS_DEINTERLACING; + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "NVidia Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | + DCAF_SATURATION | DCAF_HUE; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + + /* reset overlay */ + nvov0->brightness = 0; + nvov0->contrast = 4096; + nvov0->hue = 0; + nvov0->saturation = 4096; + ov0_set_csc( nvdrv, nvov0 ); + + return DFB_OK; +} + +static DFBResult +ov0Remove( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + /* disable overlay */ + nv_out32( mmio, PVIDEO_STOP, PVIDEO_STOP_OVERLAY_ACTIVE | + PVIDEO_STOP_METHOD_IMMEDIATELY ); + nv_out32( mmio, PVIDEO_BUFFER, 0 ); + + return DFB_OK; +} + +static DFBResult +ov0TestRegion(CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + NVidiaDriverData *nvdrv = driver_data; + NVidiaDeviceData *nvdev = nvdrv->device_data; + CoreLayerRegionConfigFlags fail = CLRCF_NONE; + + + /* check for unsupported options */ + if (config->options & ~OV0_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* check buffermode */ + switch (config->buffermode) { + case DLBM_FRONTONLY: + case DLBM_BACKSYSTEM: + case DLBM_BACKVIDEO: + case DLBM_TRIPLE: + break; + + default: + fail |= CLRCF_BUFFERMODE; + break; + } + + /* check pixel format */ + switch (config->format) { + case DSPF_YUY2: + case DSPF_UYVY: + break; + + case DSPF_NV12: + /*case DSPF_NV21:*/ + if (nvdev->arch < NV_ARCH_30) + fail |= CLRCF_FORMAT; + break; + + default: + fail |= CLRCF_FORMAT; + break; + } + + /* check width */ + if (config->width > 2046 || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 2046 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ov0SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + /* remember configuration */ + nvov0->config = *config; + + nvov0->videoSurface = surface; + nvov0->lock = lock; + + /* set configuration */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | + CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS | CLRCF_OPACITY)) + { + ov0_calc_regs( nvdrv, nvov0, config, updated ); + ov0_set_regs( nvdrv, nvov0, updated ); + } + + /* set destination colorkey */ + if (updated & CLRCF_DSTKEY) + ov0_set_colorkey( nvdrv, nvov0, config ); + + return DFB_OK; +} + +static DFBResult +ov0FlipRegion ( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + nvov0->videoSurface = surface; + nvov0->lock = lock; + + dfb_surface_flip( nvov0->videoSurface, false ); + + ov0_calc_regs( nvdrv, nvov0, &nvov0->config, CLRCF_SURFACE ); + ov0_set_regs( nvdrv, nvov0, CLRCF_SURFACE ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + return DFB_OK; +} + +static DFBResult +ov0SetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + if (adj->flags & DCAF_BRIGHTNESS) { + nvov0->brightness = (adj->brightness >> 8) - 128; + D_DEBUG( "DirectFB/NVidia/Overlay: brightness=%i\n", nvov0->brightness ); + } + + if (adj->flags & DCAF_CONTRAST) { + nvov0->contrast = 8191 - (adj->contrast >> 3); /* contrast inverted ?! */ + D_DEBUG( "DirectFB/NVidia/Overlay: contrast=%i\n", nvov0->contrast ); + } + + if (adj->flags & DCAF_SATURATION) { + nvov0->saturation = adj->saturation >> 3; + D_DEBUG( "DirectFB/NVidia/Overlay: saturation=%i\n", nvov0->saturation ); + } + + if (adj->flags & DCAF_HUE) { + nvov0->hue = (adj->hue / 182 - 180) % 360; + D_DEBUG( "DirectFB/NVidia/Overlay: hue=%i\n", nvov0->hue ); + } + + ov0_set_csc( nvdrv, nvov0 ); + + return DFB_OK; +} + +static DFBResult +ov0SetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + nvov0->field = field; + nvov0->regs.BUFFER = 1 << (field << 2); + + nv_out32( nvdrv->mmio_base, PVIDEO_BUFFER, nvov0->regs.BUFFER ); + + return DFB_OK; +} + +DisplayLayerFuncs nvidiaOverlayFuncs = { + .LayerDataSize = ov0LayerDataSize, + .InitLayer = ov0InitLayer, + .SetRegion = ov0SetRegion, + .RemoveRegion = ov0Remove, + .TestRegion = ov0TestRegion, + .FlipRegion = ov0FlipRegion, + .SetColorAdjustment = ov0SetColorAdjustment, + .SetInputField = ov0SetInputField, +}; + + +/* internal */ + +static void ov0_set_regs( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfigFlags flags ) +{ + volatile u8 *mmio = nvdrv->mmio_base; + + if (flags & CLRCF_SURFACE) { + if (DFB_PLANAR_PIXELFORMAT(nvov0->config.format)) { + nv_out32( mmio, PVIDEO_UVBASE_0, nvov0->regs.UVBASE_0 ); + nv_out32( mmio, PVIDEO_UVBASE_1, nvov0->regs.UVBASE_1 ); + nv_out32( mmio, PVIDEO_UVOFFSET_0, nvov0->regs.UVOFFSET_0 ); + nv_out32( mmio, PVIDEO_UVOFFSET_1, nvov0->regs.UVOFFSET_1 ); + } + nv_out32( mmio, PVIDEO_BASE_0, nvov0->regs.BASE_0 ); + nv_out32( mmio, PVIDEO_BASE_1, nvov0->regs.BASE_1 ); + nv_out32( mmio, PVIDEO_OFFSET_0, nvov0->regs.OFFSET_0 ); + nv_out32( mmio, PVIDEO_OFFSET_1, nvov0->regs.OFFSET_1 ); + } + if (flags & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_SIZE_IN_0, nvov0->regs.SIZE_IN_0 ); + nv_out32( mmio, PVIDEO_SIZE_IN_1, nvov0->regs.SIZE_IN_1 ); + } + if (flags & (CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_POINT_IN_0, nvov0->regs.POINT_IN_0 ); + nv_out32( mmio, PVIDEO_POINT_IN_1, nvov0->regs.POINT_IN_1 ); + nv_out32( mmio, PVIDEO_DS_DX_0, nvov0->regs.DS_DX_0 ); + nv_out32( mmio, PVIDEO_DS_DX_1, nvov0->regs.DS_DX_1 ); + nv_out32( mmio, PVIDEO_DT_DY_0, nvov0->regs.DT_DY_0 ); + nv_out32( mmio, PVIDEO_DT_DY_1, nvov0->regs.DT_DY_1 ); + } + if (flags & CLRCF_DEST) { + nv_out32( mmio, PVIDEO_POINT_OUT_0, nvov0->regs.POINT_OUT_0 ); + nv_out32( mmio, PVIDEO_POINT_OUT_1, nvov0->regs.POINT_OUT_1 ); + nv_out32( mmio, PVIDEO_SIZE_OUT_0, nvov0->regs.SIZE_OUT_0 ); + nv_out32( mmio, PVIDEO_SIZE_OUT_1, nvov0->regs.SIZE_OUT_1 ); + } + if (flags & (CLRCF_FORMAT | CLRCF_SURFACE | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_FORMAT_0, nvov0->regs.FORMAT_0 ); + nv_out32( mmio, PVIDEO_FORMAT_1, nvov0->regs.FORMAT_1 ); + } + nv_out32( mmio, PVIDEO_BUFFER, nvov0->regs.BUFFER ); + nv_out32( mmio, PVIDEO_STOP, nvov0->regs.STOP ); +} + +static void +ov0_calc_regs( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags flags ) +{ + NVidiaDeviceData *nvdev = nvdrv->device_data; + + if (flags & (CLRCF_WIDTH | CLRCF_HEIGHT | + CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS)) { + int width = config->width; + int height = config->height; + DFBRectangle source = config->source; + DFBRectangle dest = config->dest; + + source.x <<= 4; + source.y <<= 4; + + if (dest.x < 0) { + source.x -= (dest.x * source.w << 4) / dest.w; + source.w += dest.x * source.w / dest.w; + dest.w += dest.x; + dest.x = 0; + } + + if (dest.y < 0) { + source.y -= (dest.y * source.h << 4) / dest.h; + source.h += dest.y * source.h / dest.h; + dest.h += dest.y; + dest.y = 0; + } + + if (config->options & DLOP_DEINTERLACING) { + height /= 2; + source.y /= 2; + source.h /= 2; + } + + if (source.w < 1 || source.h < 1 || dest.w < 1 || dest.h < 1) { + nvov0->regs.STOP = PVIDEO_STOP_OVERLAY_ACTIVE | + PVIDEO_STOP_METHOD_NORMALLY; + return; + } + + nvov0->regs.SIZE_IN_0 = + nvov0->regs.SIZE_IN_1 = ((height << 16) & PVIDEO_SIZE_IN_HEIGHT_MSK) | + ( width & PVIDEO_SIZE_IN_WIDTH_MSK); + nvov0->regs.POINT_IN_0 = + nvov0->regs.POINT_IN_1 = ((source.y << 16) & PVIDEO_POINT_IN_T_MSK) | + ( source.x & PVIDEO_POINT_IN_S_MSK); + nvov0->regs.DS_DX_0 = + nvov0->regs.DS_DX_1 = (source.w << 20) / dest.w; + nvov0->regs.DT_DY_0 = + nvov0->regs.DT_DY_1 = (source.h << 20) / dest.h; + nvov0->regs.POINT_OUT_0 = + nvov0->regs.POINT_OUT_1 = ((dest.y << 16) & PVIDEO_POINT_OUT_Y_MSK) | + ( dest.x & PVIDEO_POINT_OUT_X_MSK); + nvov0->regs.SIZE_OUT_0 = + nvov0->regs.SIZE_OUT_1 = ((dest.h << 16) & PVIDEO_SIZE_OUT_HEIGHT_MSK) | + ( dest.w & PVIDEO_SIZE_OUT_WIDTH_MSK); + } + + if (flags & (CLRCF_SURFACE | CLRCF_FORMAT | CLRCF_OPTIONS)) { + CoreSurfaceBufferLock *lock = nvov0->lock; + u32 format; + + if (config->options & DLOP_DEINTERLACING) + format = (lock->pitch*2) & PVIDEO_FORMAT_PITCH_MSK; + else + format = lock->pitch & PVIDEO_FORMAT_PITCH_MSK; + + if (DFB_PLANAR_PIXELFORMAT(config->format)) + format |= PVIDEO_FORMAT_PLANAR_NV; + + if (config->format == DSPF_UYVY) + format |= PVIDEO_FORMAT_COLOR_YB8CR8YA8CB8; + else + format |= PVIDEO_FORMAT_COLOR_CR8YB8CB8YA8; + + if (config->options & DLOP_DST_COLORKEY) + format |= PVIDEO_FORMAT_DISPLAY_COLOR_KEY_EQUAL; + + /* Use Buffer 0 for Odd field */ + nvov0->regs.OFFSET_0 = (nvdev->fb_offset + lock->offset) & PVIDEO_OFFSET_MSK; + /* Use Buffer 1 for Even field */ + nvov0->regs.OFFSET_1 = nvov0->regs.OFFSET_0 + lock->pitch; + if (DFB_PLANAR_PIXELFORMAT(config->format)) { + CoreSurface *surface = nvov0->videoSurface; + nvov0->regs.UVOFFSET_0 = (nvov0->regs.OFFSET_0 + + lock->pitch * surface->config.size.h) & PVIDEO_UVOFFSET_MSK; + nvov0->regs.UVOFFSET_1 = nvov0->regs.UVOFFSET_0 + lock->pitch; + } + nvov0->regs.FORMAT_0 = + nvov0->regs.FORMAT_1 = format; + } + + nvov0->regs.BUFFER = 1 << (nvov0->field << 2); + nvov0->regs.STOP = (config->opacity) + ? PVIDEO_STOP_OVERLAY_INACTIVE + : PVIDEO_STOP_OVERLAY_ACTIVE; + nvov0->regs.STOP |= PVIDEO_STOP_METHOD_NORMALLY; +} + +static void +ov0_set_colorkey( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config ) +{ + u32 key; + + key = dfb_color_to_pixel( dfb_primary_layer_pixelformat(), + config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + + nv_out32( nvdrv->mmio_base, PVIDEO_COLOR_KEY, key ); +} + +static void +ov0_set_csc( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0 ) +{ + volatile u8 *mmio = nvdrv->mmio_base; + s32 satSine; + s32 satCosine; + double angle; + + angle = (double) nvov0->hue * M_PI / 180.0; + satSine = nvov0->saturation * sin(angle); + if (satSine < -1024) + satSine = -1024; + satCosine = nvov0->saturation * cos(angle); + if (satCosine < -1024) + satCosine = -1024; + + nv_out32( mmio, PVIDEO_LUMINANCE_0, (nvov0->brightness << 16) | + (nvov0->contrast & 0xffff) ); + nv_out32( mmio, PVIDEO_LUMINANCE_1, (nvov0->brightness << 16) | + (nvov0->contrast & 0xffff) ); + nv_out32( mmio, PVIDEO_CHROMINANCE_0, (satSine << 16) | + (satCosine & 0xffff) ); + nv_out32( mmio, PVIDEO_CHROMINANCE_1, (satSine << 16) | + (satCosine & 0xffff) ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c new file mode 100755 index 0000000..50bde37 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c @@ -0,0 +1,189 @@ +/* + Copyright (C) 2005-2006 Claudio Ciccani + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" + + +/************************** Primary Screen functions **************************/ + +static DFBResult +crtc1InitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + if (OldPrimaryScreenFuncs.InitScreen) + OldPrimaryScreenFuncs.InitScreen( screen, device, + OldPrimaryScreenDriverData, + screen_data, description ); + + description->caps |= DSCCAPS_VSYNC; + + snprintf( description->name, + DFB_SCREEN_DESC_NAME_LENGTH, "NVidia Primary Screen" ); + + nv_out32( mmio, PCRTC_INTR_EN, PCRTC_INTR_EN_VBLANK_DISABLED ); +#ifdef WORDS_BIGENDIAN + nv_out32( mmio, PCRTC_CONFIG, PCRTC_CONFIG_SIGNAL_HSYNC | + PCRTC_CONFIG_ENDIAN_BIG ); +#else + nv_out32( mmio, PCRTC_CONFIG, PCRTC_CONFIG_SIGNAL_HSYNC | + PCRTC_CONFIG_ENDIAN_LITTLE ); +#endif + nv_out32( mmio, PCRTC_INTR, PCRTC_INTR_VBLANK_RESET ); + + return DFB_OK; +} + +static DFBResult +crtc1WaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + if (!dfb_config->pollvsync_none) { + int i; + + for (i = 0; i < 2000000; i++) { + if (!(nv_in8( mmio, PCIO_CRTC_STATUS ) & 8)) + break; + } + + for (i = 0; i < 2000000;) { + if (nv_in8( mmio, PCIO_CRTC_STATUS ) & 8) + break; + + i++; + if ((i % 2000) == 0) { + struct timespec ts = { 0, 10000 }; + nanosleep( &ts, NULL ); + } + } + } + + return DFB_OK; +} + +#if 0 +static DFBResult +crtc1GetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + int w, h; + int val; + + /* stolen from RivaTV */ + + w = nv_incrtc( mmio, CRTC_HORIZ_DISPLAY_END ); + w |= (nv_incrtc( mmio, CRTC_HORIZ_EXTRA ) & 0x02) << 7; + w = (w + 1) << 3; + + h = nv_incrtc( mmio, CRTC_VERT_DISPLAY_END ); + val = nv_incrtc( mmio, CRTC_OVERFLOW ); + h |= (val & 0x02) << 7; + h |= (val & 0x40) << 3; + h++; + h |= nv_incrtc( mmio, CRTC_EXTRA ) << 9; + h |= nv_incrtc( mmio, 0x41 ) << 9; + h >>= (nv_incrtc( mmio, CRTC_MAX_SCAN_LINE ) & 0x80) >> 7; + + D_DEBUG( "DirectFB/NVidia/Crtc1: " + "detected screen resolution %dx%d.\n", w, h ); + + *ret_width = w; + *ret_height = h; + + return DFB_OK; +} +#endif + +ScreenFuncs nvidiaPrimaryScreenFuncs = { + .InitScreen = crtc1InitScreen, + .WaitVSync = crtc1WaitVSync, + //.GetScreenSize = crtc1GetScreenSize +}; + +ScreenFuncs OldPrimaryScreenFuncs; +void *OldPrimaryScreenDriverData; + +/*************************** Primary Layer hooks ******************************/ + +static DFBResult +fb0FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = nvdrv->device_data; + u32 offset; + + dfb_surface_flip( surface, false ); + + offset = (lock->offset + nvdev->fb_offset) & ~3; + nv_out32( nvdrv->mmio_base, PCRTC_START, offset ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + return DFB_OK; +} + + +DisplayLayerFuncs nvidiaPrimaryLayerFuncs = { + .FlipRegion = fb0FlipRegion +}; + +DisplayLayerFuncs OldPrimaryLayerFuncs; +void *OldPrimaryLayerDriverData; diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h new file mode 100755 index 0000000..64257cc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h @@ -0,0 +1,1636 @@ +#ifndef __NVIDIA_REGS_H__ +#define __NVIDIA_REGS_H__ + + +/* PMC */ +#define PMC 0x00000000 + + + +/* PBUS */ +#define PBUS 0x00001000 + + + +/* PFIFO */ +#define PFIFO 0x00002000 + +#define PFIFO_DELAY_0 0x00002040 +#define PFIFO_DELAY_0_WAIT_RETRY_MSK 0x000003FF + +#define PFIFO_DMA_TIMESLICE 0x00002044 +#define PFIFO_DMA_TIMESLICE_SELECT_MSK 0x0001FFFF +#define PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 +#define PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003FFF +#define PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007FFF +#define PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000FFFF +#define PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001FFFF +#define PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_PIO_TIMESLICE 0x00002048 +#define PFIFO_PIO_TIMESLICE_SELECT_MSK 0x0001FFFF +#define PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 +#define PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003FFF +#define PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007FFF +#define PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000FFFF +#define PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001FFFF +#define PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_TIMESLICE 0x0000204C +#define PFIFO_TIMESLICE_TIMER_MSK 0x0003FFFF + +#define PFIFO_NEXT_CHANNEL 0x00002050 +#define PFIFO_NEXT_CHANNEL_CHID_MSK 0x0000001F +#define PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 +#define PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000100 +#define PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 +#define PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00001000 + +#define PFIFO_DEBUG_0 0x00002080 +#define PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 +#define PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 +#define PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 +#define PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000010 + +#define PFIFO_INTR 0x00002100 +#define PFIFO_INTR_RESET 0xFFFFFFFF +#define PFIFO_INTR_CACHE_ERROR_NOT_PENDING 0x00000000 +#define PFIFO_INTR_CACHE_ERROR_PENDING 0x00000001 +#define PFIFO_INTR_CACHE_ERROR_RESET 0x00000001 +#define PFIFO_INTR_RUNOUT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_RUNOUT_PENDING 0x00000010 +#define PFIFO_INTR_RUNOUT_RESET 0x00000010 +#define PFIFO_INTR_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 +#define PFIFO_INTR_RUNOUT_OVERFLOW_PENDING 0x00000100 +#define PFIFO_INTR_RUNOUT_OVERFLOW_RESET 0x00000100 +#define PFIFO_INTR_DMA_PUSHER_NOT_PENDING 0x00000000 +#define PFIFO_INTR_DMA_PUSHER_PENDING 0x00001000 +#define PFIFO_INTR_DMA_PUSHER_RESET 0x00001000 +#define PFIFO_INTR_DMA_PT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_DMA_PT_PENDING 0x00010000 +#define PFIFO_INTR_DMA_PT_RESET 0x00010000 +#define PFIFO_INTR_SEMAPHORE_NOT_PENDING 0x00000000 +#define PFIFO_INTR_SEMAPHORE_PENDING 0x00100000 +#define PFIFO_INTR_SEMAPHORE_RESET 0x00100000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_PENDING 0x01000000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_RESET 0x01000000 + +#define PFIFO_INTR_EN 0x00002140 +#define PFIFO_INTR_EN_DISABLED 0x00000000 +#define PFIFO_INTR_EN_CACHE_ERROR_DISABLED 0x00000000 +#define PFIFO_INTR_EN_CACHE_ERROR_ENABLED 0x00000001 +#define PFIFO_INTR_EN_RUNOUT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_RUNOUT_ENABLED 0x00000010 +#define PFIFO_INTR_EN_RUNOUT_OVERFLOW_DISABLED 0x00000000 +#define PFIFO_INTR_EN_RUNOUT_OVERFLOW_ENABLED 0x00000100 +#define PFIFO_INTR_EN_DMA_PUSHER_DISABLED 0x00000000 +#define PFIFO_INTR_EN_DMA_PUSHER_ENABLED 0x00001000 +#define PFIFO_INTR_EN_DMA_PT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_DMA_PT_ENABLED 0x00010000 +#define PFIFO_INTR_EN_SEMAPHORE_DISABLED 0x00000000 +#define PFIFO_INTR_EN_SEMAPHORE_ENABLED 0x00100000 +#define PFIFO_INTR_EN_ACQUIRE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_ACQUIRE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_RAMHT 0x00002210 +#define PFIFO_RAMHT_BASE_ADDRESS_MSK 0x000001F0 +#define PFIFO_RAMHT_SIZE_4K 0x00000000 +#define PFIFO_RAMHT_SIZE_8K 0x00010000 +#define PFIFO_RAMHT_SIZE_16K 0x00020000 +#define PFIFO_RAMHT_SIZE_32K 0x00030000 +#define PFIFO_RAMHT_SEARCH_16 0x00000000 +#define PFIFO_RAMHT_SEARCH_32 0x01000000 +#define PFIFO_RAMHT_SEARCH_64 0x02000000 +#define PFIFO_RAMHT_SEARCH_128 0x03000000 + +#define PFIFO_RAMFC 0x00002214 +#define PFIFO_RAMFC_BASE_ADDRESS_MSK 0x000001F8 + +#define PFIFO_RAMRO 0x00002218 +#define PFIFO_RAMRO_BASE_ADDRESS_MSK 0x000001FE +#define PFIFO_RAMRO_BASE_ADDRESS_11800 0x00000118 +#define PFIFO_RAMRO_BASE_ADDRESS_11400 0x00000114 +#define PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000112 +#define PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000120 +#define PFIFO_RAMRO_SIZE_512 0x00000000 +#define PFIFO_RAMRO_SIZE_8K 0x00010000 + +#define PFIFO_CACHES 0x00002500 +#define PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 +#define PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 +#define PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 +#define PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000010 + +#define PFIFO_MODE 0x00002504 +#define PFIFO_MODE_CHANNEL_0_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_0_DMA 0x00000001 +#define PFIFO_MODE_CHANNEL_1_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_1_DMA 0x00000002 +#define PFIFO_MODE_CHANNEL_2_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_2_DMA 0x00000004 +#define PFIFO_MODE_CHANNEL_3_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_3_DMA 0x00000008 +#define PFIFO_MODE_CHANNEL_4_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_4_DMA 0x00000010 +#define PFIFO_MODE_CHANNEL_5_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_5_DMA 0x00000020 +#define PFIFO_MODE_CHANNEL_6_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_6_DMA 0x00000040 +#define PFIFO_MODE_CHANNEL_7_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_7_DMA 0x00000080 + +#define PFIFO_DMA 0x00002508 +#define PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 +#define PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_1_PENDING 0x00000002 +#define PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_2_PENDING 0x00000004 +#define PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_3_PENDING 0x00000008 +#define PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_4_PENDING 0x00000010 +#define PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_5_PENDING 0x00000020 +#define PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_6_PENDING 0x00000040 +#define PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_7_PENDING 0x00000080 + +#define PFIFO_SIZE 0x0000250C +#define PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 +#define PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000002 +#define PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000004 +#define PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000008 +#define PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000010 +#define PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000020 +#define PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000040 +#define PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000080 + +#define PFIFO_CACHE0_PUSH0 0x00003000 +#define PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 + +#define PFIFO_CACHE1_PUSH0 0x00003200 +#define PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 + +#define PFIFO_CACHE0_PUSH1 0x00003004 +#define PFIFO_CACHE0_PUSH1_CHID_MSK 0x0000001F + +#define PFIFO_CACHE1_PUSH1 0x00003204 +#define PFIFO_CACHE1_PUSH1_CHID_MSK 0x0000001F +#define PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 +#define PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000100 + +#define PFIFO_CACHE1_DMA_PUSH 0x00003220 +#define PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000010 +#define PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000100 +#define PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00001000 + +#define PFIFO_CACHE1_DMA_FETCH 0x00003224 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +#define PFIFO_CACHE1_LITTLE_ENDIAN 0x00000000 +#define PFIFO_CACHE1_BIG_ENDIAN 0x80000000 + +#define PFIFO_CACHE1_DMA_PUT 0x00003240 + +#define PFIFO_CACHE1_DMA_GET 0x00003244 + +#define PFIFO_CACHE1_REF 0x00003248 + +#define PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +#define PFIFO_CACHE1_DMA_SUBROUTINE_OFFSET_MSK 0x1FFFFFFC +#define PFIFO_CACHE1_DMA_SUBROUTINE_STATE_INACTIVE 0x00000000 +#define PFIFO_CACHE1_DMA_SUBROUTINE_STATE_ACTIVE 0x00000001 + +#define PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +#define PFIFO_CACHE1_DMA_DCOUNT_VALUE_MSK 0x00001FFC + +#define PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x000032A4 + +#define PFIFO_CACHE1_DMA_RSVD_SHADOW 0x000032A8 + +#define PFIFO_CACHE1_DMA_DATA_SHADOW 0x000032AC + +#define PFIFO_CACHE1_DMA_STATE 0x00003228 +#define PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC 0x00000000 +#define PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_NON_INC 0x00000001 +#define PFIFO_CACHE1_DMA_STATE_METHOD_MSK 0x00001FFC +#define PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 0x0000E000 +#define PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_MSK 0x1FFC0000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_CALL 0x20000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x40000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_RETURN 0x60000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x80000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0xC0000000 + +#define PFIFO_CACHE1_DMA_INSTANCE 0x0000322C + +#define PFIFO_CACHE1_DMA_CTL 0x00003230 +#define PFIFO_CACHE1_DMA_CTL_ADJUST_MSK 0x00000FFC +#define PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00001000 +#define PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00002000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_NVM 0x00000000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00020000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00030000 +#define PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 +#define PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x80000000 + +#define PFIFO_CACHE1_DMA_LIMIT 0x00003234 + +#define PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 +#define PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS_MSK 0x1FFFF000 +#define PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 +#define PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 + +#define PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C +#define PFIFO_CACHE1_DMA_TLB_PTE_ADDRESS_MSK 0xFFFFF000 + +#define PFIFO_CACHE0_PULL0 0x00003050 +#define PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 +#define PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000010 +#define PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 +#define PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000100 +#define PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00001000 + +#define PFIFO_CACHE1_PULL0 0x00003250 +#define PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 +#define PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 +#define PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 +#define PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000100 +#define PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00001000 +#define PFIFO_CACHE1_PULL0_ACQUIRE_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_PULL0_ACQUIRE_STATE_BUSY 0x00010000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_NO_ERROR 0x00000000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_BAD_ARG 0x00100000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_ISTATE 0x00200000 + +#define PFIFO_CACHE0_PULL1 0x00003054 +#define PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 +#define PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 +#define PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 + +#define PFIFO_CACHE1_PULL1 0x00003254 +#define PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 +#define PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 +#define PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 + +#define PFIFO_CACHE1_PULL1_ACQUIRE 0x00000010 +#define PFIFO_CACHE1_PULL1_ACQUIRE_INACTIVE 0x00000000 +#define PFIFO_CACHE1_PULL1_ACQUIRE_ACTIVE 0x00000010 + +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE 0x00030000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_NVM 0x00000000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_PCI 0x00020000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_AGP 0x00030000 + +#define PFIFO_CACHE0_HASH 0x00003058 +#define PFIFO_CACHE0_HASH_INSTANCE_MSK 0x0000FFFF + +#define PFIFO_CACHE1_HASH 0x00003258 +#define PFIFO_CACHE1_HASH_INSTANCE_MSK 0x0000FFFF + +#define PFIFO_CACHE1_ACQUIRE_0 0x00003260 + +#define PFIFO_CACHE1_ACQUIRE_1 0x00003264 + +#define PFIFO_CACHE1_ACQUIRE_2 0x00003268 + +#define PFIFO_CACHE1_SEMAPHORE 0x0000326C +#define PFIFO_CACHE1_SEMAPHORE_CTXDMA_INVALID 0x00000000 +#define PFIFO_CACHE1_SEMAPHORE_CTXDMA_VALID 0x00000001 +#define PFIFO_CACHE1_SEMAPHORE_OFFSET_MSK 0x00000FFC +#define PFIFO_CACHE1_SEMAPHORE_PAGE_ADDRESS_MSK 0xFFFFF000 + +#define PFIFO_CACHE0_STATUS 0x00003014 +#define PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_CACHE1_STATUS 0x00003214 +#define PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_CACHE1_STATUS1 0x00003218 +#define PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 +#define PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 + +#define PFIFO_CACHE0_PUT 0x00003010 + +#define PFIFO_CACHE1_PUT 0x00003210 + +#define PFIFO_CACHE0_GET 0x00003070 + +#define PFIFO_CACHE1_GET 0x00003270 + +#define PFIFO_CACHE0_ENGINE 0x00003080 +#define PFIFO_CACHE0_ENGINE_0_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 +#define PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 +#define PFIFO_CACHE0_ENGINE_1_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000010 +#define PFIFO_CACHE0_ENGINE_1_DVD 0x00000020 +#define PFIFO_CACHE0_ENGINE_2_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000100 +#define PFIFO_CACHE0_ENGINE_2_DVD 0x00000200 +#define PFIFO_CACHE0_ENGINE_3_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00001000 +#define PFIFO_CACHE0_ENGINE_3_DVD 0x00002000 +#define PFIFO_CACHE0_ENGINE_4_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00010000 +#define PFIFO_CACHE0_ENGINE_4_DVD 0x00020000 +#define PFIFO_CACHE0_ENGINE_5_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00100000 +#define PFIFO_CACHE0_ENGINE_5_DVD 0x00200000 +#define PFIFO_CACHE0_ENGINE_6_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x01000000 +#define PFIFO_CACHE0_ENGINE_6_DVD 0x02000000 +#define PFIFO_CACHE0_ENGINE_7_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x10000000 +#define PFIFO_CACHE0_ENGINE_7_DVD 0x20000000 + +#define PFIFO_CACHE1_ENGINE 0x00003280 +#define PFIFO_CACHE1_ENGINE_0_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 +#define PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 +#define PFIFO_CACHE1_ENGINE_1_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000010 +#define PFIFO_CACHE1_ENGINE_1_DVD 0x00000020 +#define PFIFO_CACHE1_ENGINE_2_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000100 +#define PFIFO_CACHE1_ENGINE_2_DVD 0x00000200 +#define PFIFO_CACHE1_ENGINE_3_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00001000 +#define PFIFO_CACHE1_ENGINE_3_DVD 0x00002000 +#define PFIFO_CACHE1_ENGINE_4_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00010000 +#define PFIFO_CACHE1_ENGINE_4_DVD 0x00020000 +#define PFIFO_CACHE1_ENGINE_5_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00100000 +#define PFIFO_CACHE1_ENGINE_5_DVD 0x00200000 +#define PFIFO_CACHE1_ENGINE_6_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x01000000 +#define PFIFO_CACHE1_ENGINE_6_DVD 0x02000000 +#define PFIFO_CACHE1_ENGINE_7_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x10000000 +#define PFIFO_CACHE1_ENGINE_7_DVD 0x20000000 + +#define PFIFO_CACHE0_METHOD 0x00003100 +#define PFIFO_CACHE0_METHOD_ADDRESS_MSK 0x00001FFC +#define PFIFO_CACHE0_METHOD_SUBCHANNEL_MSK 0x0000E000 + +#define PFIFO_CACHE1_METHOD 0x00003800 +#define PFIFO_CACHE1_METHOD_ADDRESS_MSK 0x00001FFC +#define PFIFO_CACHE1_METHOD_SUBCHANNEL_MSK 0x0000E000 + +#define PFIFO_CACHE1_METHOD_ALIAS 0x00003C00 + +#define PFIFO_CACHE0_DATA 0x00003104 + +#define PFIFO_CACHE1_DATA 0x00003804 + +#define PFIFO_CACHE1_DATA_ALIAS 0x00003C04 + +#define PFIFO_DEVICE 0x00002800 +#define PFIFO_DEVICE_CHID_MSK 0x0000001F +#define PFIFO_DEVICE_SWITCH 0x01000000 +#define PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 +#define PFIFO_DEVICE_SWITCH_AVAILABLE 0x01000000 + +#define PFIFO_RUNOUT_STATUS 0x00002400 +#define PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 +#define PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 +#define PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_RUNOUT_PUT 0x00002410 +#define PFIFO_RUNOUT_PUT_ADDRES_MSK 0x00001FF8 + +#define PFIFO_RUNOUT_GET 0x00002420 +#define PFIFO_RUNOUT_GET_ADDRESS_MSK 0x00003FF8 + + + +/* PVIDEO */ +#define PVIDEO 0x00008000 + +#define PVIDEO_DEBUG_0 0x00008080 +#define PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_ENABLED 0x00000001 +#define PVIDEO_DEBUG_0_LIMIT_CHECK_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_LIMIT_CHECK_ENABLED 0x00000010 +#define PVIDEO_DEBUG_0_HUE_FOLD_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_HUE_FOLD_ENABLED 0x00000100 + +#define PVIDEO_DEBUG_1 0x00008084 +#define PVIDEO_DEBUG_1_REQ_DELAY_MSK 0x000007FF +#define PVIDEO_DEBUG_1_REQ_DELAY_DEFAULT 0x00000064 +#define PVIDEO_DEBUG_1_REQ_DELAY_INIT 0x00000050 + +#define PVIDEO_DEBUG_2 0x00008088 +#define PVIDEO_DEBUG_2_BURST1_MSK 0x000007E0 +#define PVIDEO_DEBUG_2_BURST1_DEFAULT 0x00000100 +#define PVIDEO_DEBUG_2_BURST1_INIT 0x00000200 +#define PVIDEO_DEBUG_2_BURST2_MSK 0x07E00000 +#define PVIDEO_DEBUG_2_BURST2_DEFAULT 0x02000000 + +#define PVIDEO_DEBUG_3 0x0000808C +#define PVIDEO_DEBUG_3_WATER_MARK1_MSK 0x000007F0 +#define PVIDEO_DEBUG_3_WATER_MARK1_DEFAULT 0x000004B0 +#define PVIDEO_DEBUG_3_WATER_MARK1_INIT 0x00000400 +#define PVIDEO_DEBUG_3_WATER_MARK2_MSK 0x07F00000 +#define PVIDEO_DEBUG_3_WATER_MARK2_DEFAULT 0x03B00000 +#define PVIDEO_DEBUG_3_WATER_MARK2_INIT 0x04000000 + +#define PVIDEO_DEBUG_4 0x00008090 +#define PVIDEO_DEBUG_4_V_COEFF_B_MSK 0x00FFFFE0 +#define PVIDEO_DEBUG_4_V_COEFF_B_DEFAULT 0x0016A0A0 +#define PVIDEO_DEBUG_4_V_COEFF_B_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_4_V_COEFF_B_NEVER 0x00FFFFE0 + +#define PVIDEO_DEBUG_5 0x00008094 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_DEFAULT 0x00188160 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_6 0x00008098 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_DEFAULT 0x0012C730 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_7 0x0000809C +#define PVIDEO_DEBUG_7_H_L_COEFF_B_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_DEFAULT 0x00000000 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_8 0x000080A0 +#define PVIDEO_DEBUG_8_PIPE_FILL_MSK 0x000007F0 +#define PVIDEO_DEBUG_8_PIPE_FILL_DEFAULT 0x000000B0 + +#define PVIDEO_DEBUG_9 0x000080A4 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_TRUE 0x00000001 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_RESET 0x00000001 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_TRUE 0x00000010 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_RESET 0x00000010 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_TRUE 0x00000100 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_RESET 0x00000100 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_TRUE 0x00001000 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_RESET 0x00001000 + +#define PVIDEO_DEBUG_10 0x000080A8 +#define PVIDEO_DEBUG_10_SCREEN_LINE_MSK 0x00001FFF +#define PVIDEO_DEBUG_10_SCREEN_LINE_FIRST 0x00000000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_MSK 0x001F0000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_FIRST 0x00000000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_OVERFLOW 0x00100000 +#define PVIDEO_DEBUG_10_SCANNING_NEITHER 0x00000000 +#define PVIDEO_DEBUG_10_SCANNING_BUFFER_0 0x02000000 +#define PVIDEO_DEBUG_10_SCANNING_BUFFER_1 0x03000000 + +#define PVIDEO_INTR 0x00008100 +#define PVIDEO_INTR_BUFFER_0_NOT_PENDING 0x00000000 +#define PVIDEO_INTR_BUFFER_0_PENDING 0x00000001 +#define PVIDEO_INTR_BUFFER_0_RESET 0x00000001 +#define PVIDEO_INTR_BUFFER_1_NOT_PENDING 0x00000000 +#define PVIDEO_INTR_BUFFER_1_PENDING 0x00000010 +#define PVIDEO_INTR_BUFFER_1_RESET 0x00000010 + +#define PVIDEO_INTR_REASON 0x00008104 +#define PVIDEO_INTR_REASON_BUFFER_0_NOTIFICATION 0x00000000 +#define PVIDEO_INTR_REASON_BUFFER_0_PROTECTION_FAULT 0x00000001 +#define PVIDEO_INTR_REASON_BUFFER_1_NOTIFICATION 0x00000000 +#define PVIDEO_INTR_REASON_BUFFER_1_PROTECTION_FAULT 0x00000010 + +#define PVIDEO_INTR_EN 0x00008140 +#define PVIDEO_INTR_EN_BUFFER_0_DISABLED 0x00000000 +#define PVIDEO_INTR_EN_BUFFER_0_ENABLED 0x00000001 +#define PVIDEO_INTR_EN_BUFFER_1_DISABLED 0x00000000 +#define PVIDEO_INTR_EN_BUFFER_1_ENABLED 0x00000010 + +#define PVIDEO_BUFFER 0x00008700 +#define PVIDEO_BUFFER_0_USE_NOT_PENDING 0x00000000 +#define PVIDEO_BUFFER_0_USE_PENDING 0x00000001 +#define PVIDEO_BUFFER_0_USE_SET 0x00000001 +#define PVIDEO_BUFFER_1_USE_NOT_PENDING 0x00000000 +#define PVIDEO_BUFFER_1_USE_PENDING 0x00000010 +#define PVIDEO_BUFFER_1_USE_SET 0x00000010 + +#define PVIDEO_STOP 0x00008704 +#define PVIDEO_STOP_OVERLAY_INACTIVE 0x00000000 +#define PVIDEO_STOP_OVERLAY_ACTIVE 0x00000001 +#define PVIDEO_STOP_METHOD_IMMEDIATELY 0x00000000 +#define PVIDEO_STOP_METHOD_NORMALLY 0x00000010 + +#define PVIDEO_UVBASE_0 0x00008800 +#define PVIDEO_UVBASE_1 0x00008804 +#define PVIDEO_UVBASE_MSK 0xFFFFFFC0 + +#define PVIDEO_UVLIMIT_0 0x00008808 +#define PVIDEO_UVLIMIT_1 0x0000880C + +#define PVIDEO_UVOFFSET_0 0x00008820 +#define PVIDEO_UVOFFSET_1 0x00008824 +#define PVIDEO_UVOFFSET_MSK 0xFFFFFFC0 + +#define PVIDEO_BASE_0 0x00008900 +#define PVIDEO_BASE_1 0x00008904 +#define PVIDEO_BASE_MSK 0xFFFFFFC0 + +#define PVIDEO_LIMIT_0 0x00008908 +#define PVIDEO_LIMIT_1 0x0000890C + +#define PVIDEO_LUMINANCE_0 0x00008910 +#define PVIDEO_LUMINANCE_1 0x00008914 + +#define PVIDEO_CHROMINANCE_0 0x00008918 +#define PVIDEO_CHROMINANCE_1 0x0000891C + +#define PVIDEO_OFFSET_0 0x00008920 +#define PVIDEO_OFFSET_1 0x00008924 +#define PVIDEO_OFFSET_MSK 0xFFFFFFC0 + +#define PVIDEO_SIZE_IN_0 0x00008928 +#define PVIDEO_SIZE_IN_1 0x0000892C +#define PVIDEO_SIZE_IN_WIDTH_MSK 0x000007FF +#define PVIDEO_SIZE_IN_HEIGHT_MSK 0x07FF0000 + +#define PVIDEO_POINT_IN_0 0x00008930 +#define PVIDEO_POINT_IN_1 0x00008934 +#define PVIDEO_POINT_IN_S_MSK 0x00007FFF +#define PVIDEO_POINT_IN_T_MSK 0xFFFE0000 + +#define PVIDEO_DS_DX_0 0x00008938 +#define PVIDEO_DS_DX_1 0x0000893C + +#define PVIDEO_DT_DY_0 0x00008940 +#define PVIDEO_DT_DY_1 0x00008944 + +#define PVIDEO_POINT_OUT_0 0x00008948 +#define PVIDEO_POINT_OUT_1 0x0000894C +#define PVIDEO_POINT_OUT_X_MSK 0x00000FFF +#define PVIDEO_POINT_OUT_Y_MSK 0x0FFF0000 + +#define PVIDEO_SIZE_OUT_0 0x00008950 +#define PVIDEO_SIZE_OUT_1 0x00008954 +#define PVIDEO_SIZE_OUT_WIDTH_MSK 0x00000FFF +#define PVIDEO_SIZE_OUT_HEIGHT_MSK 0x0FFF0000 + +#define PVIDEO_FORMAT_0 0x00008958 +#define PVIDEO_FORMAT_1 0x0000895C +#define PVIDEO_FORMAT_PLANAR_NV 0x00000001 +#define PVIDEO_FORMAT_PITCH_MSK 0x00001FC0 +#define PVIDEO_FORMAT_COLOR_YB8CR8YA8CB8 0x00000000 +#define PVIDEO_FORMAT_COLOR_CR8YB8CB8YA8 0x00010000 +#define PVIDEO_FORMAT_COLOR_ECR8EYB8ECB8EYA8 0x00110000 +#define PVIDEO_FORMAT_DISPLAY_ALWAYS 0x00000000 +#define PVIDEO_FORMAT_DISPLAY_COLOR_KEY_EQUAL 0x00100000 +#define PVIDEO_FORMAT_MATRIX_ITURBT601 0x00000000 +#define PVIDEO_FORMAT_MATRIX_ITURBT709 0x01000000 + +#define PVIDEO_COLOR_KEY 0x00008B00 + +#define PVIDEO_TEST 0x00008D00 +#define PVIDEO_TEST_MODE_DISABLE 0x00000000 +#define PVIDEO_TEST_MODE_ENABLE 0x00000001 +#define PVIDEO_TEST_ADDRESS_MSK 0x00007F00 + +/* Array [0...11] */ +#define PVIDEO_TST_WRITE 0x00008D10 + +/* Array [0...11] */ +#define PVIDEO_TST_READ 0x00008D40 + + + +/* PTIMER */ +#define PTIMER 0x00009000 + + + +/* PVIO */ +#define PVIO 0x000C0000 + +#define PVIO_SEQ_INDEX 0x000C03C4 + +#define PVIO_SEQ_DATA 0x000C03C5 + +#define PVIO_GRA_INDEX 0x000C03CE + +#define PCIO_GRA_DATA 0x000C03CF + + + +/* PVGA */ +#define PVGA 0x000A0000 + + + +/* PFB */ +#define PFB 0x00100000 + +#define PFB_BOOT_0 0x00100000 +#define PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 +#define PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 +#define PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 +#define PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 +#define PFB_BOOT_0_RAM_WIDTH_128 0x00000004 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 + + + +/* PEXTDEV */ +#define PEXTDEV 0x00101000 + + + +/* PGRAPH */ +#define PGRAPH 0x00400000 + +#define PGRAPH_DEBUG_0 0x00400080 + +#define PGRAPH_DEBUG_1 0x00400084 + +#define PGRAPH_DEBUG_2 0x00400088 + +#define PGRAPH_DEBUG_3 0x0040008C + +#define PGRAPH_DEBUG_4 0x00400090 + +#define PGRAPH_DEBUG_5 0x00400094 + +#define PGRAPH_DEBUG_6 0x00400820 + +#define PGRAPH_INTR 0x00400100 + +#define PGRAPH_NSTATUS 0x00400104 + +#define PGRAPH_NSOURCE 0x00400108 + +#define PGRAPH_INTR_EN 0x00400140 + +#define PGRAPH_FIFO 0x00400720 +#define PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 +#define PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 + +#define PGRAPH_STATUS 0x00400700 +#define PGRAPH_STATUS_STATE_IDLE 0x00000000 +#define PGRAPH_STATUS_STATE_BUSY 0x00000001 +#define PGRAPH_STATUS_FINE_RASTERIZER_IDLE 0x00000000 +#define PGRAPH_STATUS_FINE_RASTERIZER_BUSY 0x00000002 +#define PGRAPH_STATUS_COARSE_RASTERIZER_IDLE 0x00000000 +#define PGRAPH_STATUS_COARSE_RASTERIZER_BUSY 0x00000004 +#define PGRAPH_STATUS_FE_3D_IDLE 0x00000000 +#define PGRAPH_STATUS_FE_3D_BUSY 0x00000008 +#define PGRAPH_STATUS_FE_2D_IDLE 0x00000000 +#define PGRAPH_STATUS_FE_2D_BUSY 0x00000010 +#define PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 +#define PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000020 +#define PGRAPH_STATUS_RASTERIZER_2D_IDLE 0x00000000 +#define PGRAPH_STATUS_RASTERIZER_2D_BUSY 0x00000080 +#define PGRAPH_STATUS_IDX_IDLE 0x00000000 +#define PGRAPH_STATUS_IDX_BUSY 0x00000100 +#define PGRAPH_STATUS_XF_IDLE 0x00000000 +#define PGRAPH_STATUS_XF_BUSY 0x00000200 +#define PGRAPH_STATUS_VTX_IDLE 0x00000000 +#define PGRAPH_STATUS_VTX_BUSY 0x00000400 +#define PGRAPH_STATUS_CAS_IDLE 0x00000000 +#define PGRAPH_STATUS_CAS_BUSY 0x00000800 +#define PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00001000 +#define PGRAPH_STATUS_SHADER_IDLE 0x00000000 +#define PGRAPH_STATUS_SHADER_BUSY 0x00002000 +#define PGRAPH_STATUS_SHADER_BE_IDLE 0x00000000 +#define PGRAPH_STATUS_SHADER_BE_BUSY 0x00004000 +#define PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_DMA_BUSY 0x00010000 +#define PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00020000 +#define PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00100000 +#define PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00200000 +#define PGRAPH_STATUS_DMA_WARNING_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_WARNING_NOTIFY_BUSY 0x00400000 +#define PGRAPH_STATUS_ZCULL_IDLE 0x00000000 +#define PGRAPH_STATUS_ZCULL_BUSY 0x00800000 +#define PGRAPH_STATUS_FDIFF_IDLE 0x00000000 +#define PGRAPH_STATUS_FDIFF_BUSY 0x01000000 +#define PGRAPH_STATUS_SETUP_IDLE 0x00000000 +#define PGRAPH_STATUS_SETUP_BUSY 0x02000000 +#define PGRAPH_STATUS_CACHE_IDLE 0x00000000 +#define PGRAPH_STATUS_CACHE_BUSY 0x04000000 +#define PGRAPH_STATUS_COMBINER_IDLE 0x00000000 +#define PGRAPH_STATUS_COMBINER_BUSY 0x08000000 +#define PGRAPH_STATUS_PREROP_IDLE 0x00000000 +#define PGRAPH_STATUS_PREROP_BUSY 0x10000000 +#define PGRAPH_STATUS_ROP_IDLE 0x00000000 +#define PGRAPH_STATUS_ROP_BUSY 0x20000000 +#define PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_USER_BUSY 0x40000000 +#define PGRAPH_STATUS_PORT_FB_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_FB_BUSY 0x80000000 + +#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 + +#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 + +#define NV10_PGRAPH_XFMODE0 0x00400F40 + +#define NV10_PGRAPH_XFMODE1 0x00400F44 + +#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 + +#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C + +#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 + +#define NV10_PGRAPH_PIPE_DATA 0x00400F54 + + + +/* PCRTC */ +#define PCRTC 0x00600000 + +#define PCRTC_INTR 0x00600100 +#define PCRTC_INTR_VBLANK_RESET 0x00000001 + +#define PCRTC_INTR_EN 0x00600140 +#define PCRTC_INTR_EN_VBLANK_DISABLED 0x00000000 +#define PCRTC_INTR_EN_VBLANK_ENABLED 0x00000001 + +#define PCRTC_START 0x00600800 + +#define PCRTC_CONFIG 0x00600804 +#define PCRTC_CONFIG_SIGNAL_VGA 0x00000000 +#define PCRTC_CONFIG_SIGNAL_NON_VGA 0x00000001 +#define PCRTC_CONFIG_SIGNAL_HSYNC 0x00000002 +#define PCRTC_CONFIG_ENDIAN 0x80000000 +#define PCRTC_CONFIG_ENDIAN_LITTLE 0x00000000 +#define PCRTC_CONFIG_ENDIAN_BIG 0x80000000 + +#define PCRTC_RASTER 0x00600808 +#define PCRTC_RASTER_POSITION_MSK 0x000007FF +#define PCRTC_RASTER_SA_LOAD_DISPLAY 0x00000000 +#define PCRTC_RASTER_SA_LOAD_BEFORE 0x00001000 +#define PCRTC_RASTER_SA_LOAD_AFTER 0x00002000 +#define PCRTC_RASTER_VERT_BLANK_ACTIVE 0x00010000 +#define PCRTC_RASTER_VERT_BLANK_INACTIVE 0x00000000 +#define PCRTC_RASTER_FIELD_EVEN 0x00000000 +#define PCRTC_RASTER_FIELD_ODD 0x00100000 +#define PCRTC_RASTER_STEREO_LEFT 0x00000000 +#define PCRTC_RASTER_STEREO_RIGHT 0x01000000 + + + +/* PCRTC2 */ +#define PCRTC2 0x00600800 + +#define PCRTC2_INTR 0x00600900 +#define PCRTC2_INTR_VBLANK_RESET 0x00000001 + +#define PCRTC2_INTR_EN 0x00600940 +#define PCRTC2_INTR_EN_VBLANK_DISABLED 0x00000000 +#define PCRTC2_INTR_EN_VBLANK_ENABLED 0x00000001 + +#define PCRTC2_START 0x00601000 + +#define PCRTC2_CONFIG 0x00601004 +#define PCRTC2_CONFIG_SIGNAL_VGA 0x00000000 +#define PCRTC2_CONFIG_SIGNAL_NON_VGA 0x00000001 +#define PCRTC2_CONFIG_SIGNAL_HSYNC 0x00000002 +#define PCRTC2_CONFIG_ENDIAN 0x80000000 +#define PCRTC2_CONFIG_ENDIAN_LITTLE 0x00000000 +#define PCRTC2_CONFIG_ENDIAN_BIG 0x80000000 + +#define PCRTC2_RASTER 0x00601008 +#define PCRTC2_RASTER_POSITION_MSK 0x000007FF +#define PCRTC2_RASTER_SA_LOAD_DISPLAY 0x00000000 +#define PCRTC2_RASTER_SA_LOAD_BEFORE 0x00001000 +#define PCRTC2_RASTER_SA_LOAD_AFTER 0x00002000 +#define PCRTC2_RASTER_VERT_BLANK_ACTIVE 0x00010000 +#define PCRTC2_RASTER_VERT_BLANK_INACTIVE 0x00000000 +#define PCRTC2_RASTER_FIELD_EVEN 0x00000000 +#define PCRTC2_RASTER_FIELD_ODD 0x00100000 +#define PCRTC2_RASTER_STEREO_LEFT 0x00000000 +#define PCRTC2_RASTER_STEREO_RIGHT 0x01000000 + + + +/* PCIO */ +#define PCIO 0x00601000 + +#define PCIO_ATTR_INDEX 0x006013C0 + +#define PCIO_ATTR_DATA 0x006013C1 + +#define PCIO_CRTC_INDEX 0x006013D4 + +#define PCIO_CRTC_DATA 0x006013D5 + +/* CRTC Registers */ +#define CRTC_HORIZ_TOTAL 0x00 +#define CRTC_HORIZ_DISPLAY_END 0x01 +#define CRTC_HORIZ_BLANK_START 0x02 +#define CRTC_HORIZ_BLANK_END 0x03 +#define CRTC_HORIZ_RETRACE_START 0x04 +#define CRTC_HORIZ_RETRACE_END 0x05 +#define CRTC_VERT_TOTAL 0x06 +#define CRTC_OVERFLOW 0x07 +#define CRTC_PRESET_ROW_SCAN 0x08 +#define CRTC_MAX_SCAN_LINE 0x09 +#define CRTC_CURSOR_START 0x0A +#define CRTC_CURSOR_END 0x0B +#define CRTC_START_ADDR_HIGH 0x0C +#define CRTC_START_ADDR_LOW 0x0D +#define CRTC_CURSOR_LOCATION_HIGH 0x0E +#define CRTC_CURSOR_LOCATION_LOW 0x0F +#define CRTC_VERT_RETRACE_START 0x10 +#define CRTC_VERT_RETRACE_END 0x11 +#define CRTC_VERT_DISPLAY_END 0x12 +#define CRTC_OFFSET 0x13 +#define CRTC_UNDERLINE_LOCATION 0x14 +#define CRTC_VERT_BLANK_START 0x15 +#define CRTC_VERT_BLANK_END 0x16 +#define CRTC_MODE_CONTROL 0x17 +#define CRTC_LINE_COMPARE 0x18 +#define CRTC_REPAINT0 0x19 +#define CRTC_HORIZ_EXTRA 0x2d +#define CRTC_EXTRA 0x25 +#define CRTC_FIFO_CONTROL 0x1b +#define CRTC_FIFO 0x20 +#define CRTC_REPAINT1 0x1a +#define CRTC_GRCURSOR0 0x30 +#define CRTC_GRCURSOR1 0x31 +#define CRTC_PIXEL 0x28 + +#define PCIO_CRTC_STATUS 0x006013DA + + + +/* PRAMDAC */ +#define PRAMDAC 0x00680000 + + + +/* PDIO */ +#define PDIO 0x00681000 + + + +/* PRAMIN */ +#define PRAMIN 0x00700000 + + + +/* PRAMHT */ +#define PRAMHT 0x00710000 + + + +/*************************** FIFO Registers ******************************/ + + +#define FIFO_ADDRESS 0x00800000 + +#define FIFO_FREE 0x00800010 + +#define DMA_PUT 0x00800040 + +#define DMA_GET 0x00800044 + + +/* + * Generic subchannel registers + */ +#define SET_OBJECT 0x00000000 + + +/* + * 2D surfaces + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaSource; /* 0184-0187 */ + u32 SetContextDmaDestin; /* 0188-018B */ + u32 Reserved01[0x05D]; + u32 Format; /* 0300-0303 */ + u32 Pitch; /* 0304-0307 */ + u32 SourceOffset; /* 0308-030B */ + u32 DestOffset; /* 030C-030F */ + u32 Reserved02[0x73C]; +} NVSurfaces2D; +#define SURFACES2D_FORMAT 0x00000300 +#define SURFACES2D_FORMAT_Y8 0x00000001 +#define SURFACES2D_FORMAT_X1R5G5B5 0x00000002 +#define SURFACES2D_FORMAT_A1R5G5B5 0x00000003 +#define SURFACES2D_FORMAT_R5G6B5 0x00000004 +#define SURFACES2D_FORMAT_Y16 0x00000005 +#define SURFACES2D_FORMAT_X8R8G8B8 0x00000006 +#define SURFACES2D_FORMAT_A8R8G8B8 0x0000000A +#define SURFACES2D_FORMAT_Y32 0x0000000B +#define SURFACES2D_PITCH 0x00000304 +#define SURFACES2D_SRC_OFFSET 0x00000308 +#define SURFACES2D_DST_OFFSET 0x0000030C + +/* + * 3D surfaces + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaColor; /* 0184-0187 */ + u32 SetContextDmaZeta; /* 0188-018B */ + u32 Reserved01[0x05B]; + u32 ClipHorizontal; /* 02F8-02FB */ + u32 ClipVertical; /* 02FC-02FF */ + u32 Format; /* 0300-0303 */ + u32 ClipSize; /* 0304-0307 */ + u32 Pitch; /* 0308-030B */ + u32 RenderOffset; /* 030C-030F */ + u32 DepthOffset; /* 0310-0313 */ + u32 Reserved02[0x73B]; +} NVSurfaces3D; +#define SURFACES3D_CLIP_HORIZONTAL 0x000002F8 +#define SURFACES3D_CLIP_VERTICAL 0x000002FC +#define SURFACES3D_FORMAT 0x00000300 +#define SURFACES3D_FORMAT_COLOR_A1R5G5B5 0x00000001 +#define SURFACES3D_FORMAT_COLOR_X1R5G5B5 0x00000002 +#define SURFACES3D_FORMAT_COLOR_R5G6B5 0x00000003 +#define SURAFCES3D_FORMAT_COLOR_X8R8G8B8 0x00000006 +#define SURFACES3D_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define SURFACES3D_FORMAT_TYPE_PITCH 0x00000100 +#define SURFACES3D_FORMAT_TYPE_SWIZZLE 0x00000200 +#define SURFACES3D_CLIP_SIZE 0x00000304 +#define SURFACES3D_PITCH 0x00000308 +#define SURFACES3D_RENDER_OFFSET 0x0000030C +#define SURFACES3D_DEPTH_OFFSET 0x00000310 + +/* + * Scissor clip rectangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaImage; /* 0184-0187 */ + u32 Reserved01[0x05E]; + u32 TopLeft; /* 0300-0303 */ + u32 WidthHeight; /* 0304-0307 */ + u32 Reserved02[0x73E]; +} NVClip; +#define CLIP_TOP_LEFT 0x00000300 +#define CLIP_WIDTH_HEIGHT 0x00000304 + +/* + * Global alpha factor + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 Reserved01[0x05F]; + u32 SetBeta1D31; /* 0300-0303 */ + u32 Reserved02[0x73F]; +} NVBeta1; +#define BETA1_FACTOR 0x00000300 + +/* + * Global ARGB factor + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 Reserved01[0x05F]; + u32 SetBetaFactor; /* 0300-0303 */ + u32 Reserved02[0x73F]; +} NVBeta4; +#define BETA4_FACTOR 0x00000300 + +/* + * Generic Flags + */ +/* Operation */ +#define OPERATION_COPY 0 +#define OPERATION_ROP 1 +#define OPERATION_BLEND 2 +#define OPERATION_SRCCOPY 3 +#define OPERATION_COLOR_MULTIPLY 4 +#define OPERATION_BLEND_PREMULTIPLIED 5 +/* ColorConversion */ +#define COLOR_CONVERSION_DITHER 0 +#define COLOR_CONVERSION_TRUNCATE 1 +#define COLOR_CONVERSION_SUBTR_TRUNCATE 2 + +/* + * 2D solid rectangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x03E]; + u32 TopLeft; /* 0400-0403 */ + u32 WidthHeight; /* 0404-0407 */ + u32 Reserved03[0x6FE]; +} NVRectangle; +#define RECT_OPERATION 0x000002FC +#define RECT_COLOR_FORMAT 0x00000300 +#define RECT_COLOR_FORMAT_Y16 0x00000001 +#define RECT_COLOR_FORMAT_A1Y15 0x00000002 +#define RECT_COLOR_FORMAT_Y32 0x00000003 +#define RECT_COLOR 0x00000304 +#define RECT_TOP_LEFT 0x00000400 +#define RECT_WIDTH_HEIGHT 0x00000404 + +/* + * 2D solid triangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x002]; + u32 TrianglePoint0; /* 0310-0313 */ + u32 TrianglePoint1; /* 0314-0317 */ + u32 TrianglePoint2; /* 0318-031B */ + u32 Reserved03[0x001]; + s32 Triangle32Point0X; /* 0320-0323 */ + s32 Triangle32Point0Y; /* 0324-0327 */ + s32 Triangle32Point1X; /* 0328-032B */ + s32 Triangle32Point1Y; /* 032C-032F */ + s32 Triangle32Point2X; /* 0330-0333 */ + s32 Triangle32Point2Y; /* 0334-0337 */ + u32 Reserved04[0x032]; + u32 Trimesh[32]; /* 0400-047F */ + struct { /* 0480- */ + s32 x; /* 0- 3 */ + s32 y; /* 4- 7 */ + } Trimesh32[16]; /* -04FF */ + struct { /* 0500- */ + u32 color; /* 0- 3 */ + u32 point0; /* 4- 7 */ + u32 point1; /* 8- B */ + u32 point2; /* C- F */ + } ColorTriangle[8]; /* -057F */ + struct { /* 0580- */ + u32 color; /* 0- 3 */ + u32 point; /* 4- 7 */ + } ColorTrimesh[16]; /* -05FF */ + u32 Reserved05[0x680]; +} NVTriangle; +#define TRI_OPERATION 0x000002FC +#define TRI_COLOR_FORMAT 0x00000300 +#define TRI_COLOR_FORMAT_Y16 0x00000001 +#define TRI_COLOR_FORMAT_A1Y15 0x00000002 +#define TRI_COLOR_FORMAT_Y32 0x00000003 +#define TRI_COLOR 0x00000304 +#define TRI_POINT0 0x00000310 +#define TRI_POINT1 0x00000314 +#define TRI_POINT2 0x00000318 + +/* + * 2D solid + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x03E]; + struct { /* 0400- */ + u32 point0; /* 0- 3 */ + u32 point1; /* 4- 7 */ + } Lin[16]; /* -047F */ + struct { /* 0480- */ + u32 point0X; /* 0- 3 */ + u32 point0Y; /* 4- 7 */ + u32 point1X; /* 8- B */ + u32 point1Y; /* C- F */ + } Lin32[8]; /* -04FF */ + u32 PolyLin[32]; /* 0500-057F */ + struct { /* 0580- */ + u32 x; /* 0- 3 */ + u32 y; /* 4- 7 */ + } PolyLin32[16]; /* -05FF */ + struct { /* 0600- */ + u32 color; /* 0- 3 */ + u32 point; /* 4- 7 */ + } ColorPolyLin[16]; /* -067F */ + u32 Reserved03[0x660]; +} NVLine; +#define LINE_OPERATION 0x000002FC +#define LINE_COLOR_FORMAT 0x00000300 +#define LINE_COLOR_FORMAT_Y16 0x00000001 +#define LINE_COLOR_FORMAT_A1Y15 0x00000002 +#define LINE_COLOR_FORMAT_Y32 0x00000003 +#define LINE_COLOR 0x00000304 +#define LINE_POINT0 0x00000400 +#define LINE_POINT1 0x00000404 + +/* + * 2D screen-screen BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 WaitForIdle; /* 0108-010B (09F_WAIT_FOR_IDLE) */ + u32 WaitForSync; /* 010C-010F (09F_WAIT_FOR_CRTC) */ + u32 Reserved00[0x01C]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextClip; /* 0188-018B */ + u32 SetContextPattern; /* 018C-018F */ + u32 SetContextRop; /* 0190-0193 */ + u32 SetContextBeta1; /* 0194-0197 */ + u32 SetContextBeta4; /* 0198-019B */ + u32 SetContextSurface; /* 019C-019F */ + u32 Reserved01[0x057]; + u32 SetOperation; /* 02FC-02FF */ + u32 TopLeftSrc; /* 0300-0303 */ + u32 TopLeftDst; /* 0304-0307 */ + u32 WidthHeight; /* 0308-030B */ + u32 Reserved02[0x73D]; +} NVScreenBlt; +#define BLIT_OPERATION 0x000002FC +#define BLIT_TOP_LEFT_SRC 0x00000300 +#define BLIT_TOP_LEFT_DST 0x00000304 +#define BLIT_WIDTH_HEIGHT 0x00000308 + +/* + * 2D CPU to screen BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextClip; /* 0188-018B */ + u32 SetContextPattern; /* 018C-018F */ + u32 SetContextRop; /* 0190-0193 */ + u32 SetContextBeta1; /* 0194-0197 */ + u32 SetContextBeta4; /* 0198-019B */ + u32 SetContextSurface; /* 019C-019F */ + u32 Reserved01[0x056]; + u32 SetColorConversion; /* 02F8-02FB */ + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Point; /* 0304-0307 */ + u32 SizeOut; /* 0308-030B */ + u32 SizeIn; /* 030C-030F */ + u32 Reserved02[0x03C]; + u32 Pixel[1792]; /* 0400- */ +} NVImageBlt; +#define IBLIT_COLOR_CONVERSION 0x000002F8 +#define IBLIT_OPERATION 0x000002FC +#define IBLIT_COLOR_FORMAT 0x00000300 +#define IBLIT_COLOR_FORMAT_R5G6B5 0x00000001 +#define IBLIT_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define IBLIT_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define IBLIT_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define IBLIT_COLOR_FORMAT_X8R8G8B8 0x00000005 +#define IBLIT_POINT 0x00000304 +#define IBLIT_SIZE_OUT 0x00000308 +#define IBLIT_SIZE_IN 0x0000030C +#define IBLIT_PIXEL0 0x00000400 + +/* + * 2D scaled image BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaImage; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextBeta4; /* 0194-0197 */ + u32 SetContextSurface; /* 0198-019C */ + u32 Reserved01[0x058]; + u32 SetColorConversion; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 SetOperation; /* 0304-0307 */ + u32 ClipPoint; /* 0308-030B */ + u32 ClipSize; /* 030C-030F */ + u32 ImageOutPoint; /* 0310-0313 */ + u32 ImageOutSize; /* 0314-0317 */ + u32 DuDx; /* 0318-031B */ + u32 DvDy; /* 031C-031F */ + u32 Reserved02[0x038]; + u32 ImageInSize; /* 0400-0403 */ + u32 ImageInFormat; /* 0404-0407 */ + u32 ImageInOffset; /* 0408-040B */ + u32 ImageInPoint; /* 040C-040F */ + u32 Reserved03[0x6FC]; +} NVScaledImage; +#define SCALER_COLOR_CONVERSION 0x000002FC +#define SCALER_COLOR_FORMAT 0x00000300 +#define SCALER_COLOR_FORMAT_A1R5G5B5 0x00000001 +#define SCALER_COLOR_FORMAT_X1R5G5B5 0x00000002 +#define SCALER_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define SCALER_COLOR_FORMAT_X8R8G8B8 0x00000004 +#define SCALER_COLOR_FORMAT_V8YB8U8YA8 0x00000005 +#define SCALER_COLOR_FORMAT_YB8V8YA8U8 0x00000006 +#define SCALER_COLOR_FORMAT_R5G6B5 0x00000007 +#define SCALER_COLOR_FORMAT_Y8 0x00000008 +#define SCALER_COLOR_FORMAT_AY8 0x00000009 +#define SCALER_OPERATION 0x00000304 +#define SCALER_CLIP_POINT 0x00000308 +#define SCALER_CLIP_SIZE 0x0000030C +#define SCALER_OUT_POINT 0x00000310 +#define SCALER_OUT_SIZE 0x00000314 +#define SCALER_DU_DX 0x00000318 +#define SCALER_DV_DY 0x0000031C +#define SCALER_IN_SIZE 0x00000400 +#define SCALER_IN_FORMAT 0x00000404 +#define SCALER_IN_FORMAT_ORIGIN_CENTER 0x00010000 +#define SCALER_IN_FORMAT_ORIGIN_CORNER 0x00020000 +#define SCALER_IN_FORMAT_FILTER_NEAREST 0x00000000 +#define SCALER_IN_FORMAT_FILTER_LINEAR 0x01000000 +#define SCALER_IN_OFFSET 0x00000408 +#define SCALER_IN_POINT 0x0000040C + +/* + * 2D stretched image from CPU BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextBeta4; /* 0194-0197 */ + u32 SetContextSurface; /* 0198-019C */ + u32 Reserved01[0x057]; + u32 SetColorConversion; /* 02F8-02FB */ + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 ImageInSize; /* 0304-0307 */ + u32 DxDu; /* 0308-030B */ + u32 DyDv; /* 030C-030F */ + u32 ClipPoint; /* 0310-0313 */ + u32 ClipSize; /* 0314-0317 */ + u32 ImageOutPoint; /* 0318-031B */ + u32 Reserved02[0x039]; + u32 Pixel[1792]; /* 0400- */ +} NVStretchedImage; +#define ISTRETCH_COLOR_CONVERSION 0x000002F8 +#define ISTRETCH_OPERATION 0x000002FC +#define ISTRETCH_COLOR_FORMAT 0x00000300 +#define ISTRETCH_COLOR_FORMAT_R5G6B5 0x00000001 +#define ISTRETCH_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define ISTRETCH_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define ISTRETCH_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define ISTRETCH_COLOR_FORMAT_X8R8G8B8 0x00000005 +#define ISTRETCH_IN_SIZE 0x00000304 +#define ISTRETCH_DX_DU 0x00000308 +#define ISTRETCH_DY_DV 0x0000030C +#define ISTRETCH_CLIP_POINT 0x00000310 +#define ISTRETCH_CLIP_SIZE 0x00000314 +#define ISTRETCH_OUT_POINT 0x00000318 +#define ISTRETCH_PIXEL0 0x00000400 + +/* + * 3D textured, Z buffered triangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaA; /* 0184-0187 */ + u32 SetContextDmaB; /* 0188-018B */ + u32 SetContextSurfaces; /* 018C-018F */ + u32 Reserved01[0x05C]; + u32 ColorKey; /* 0300-0303 */ + u32 TextureOffset; /* 0304-0307 */ + u32 TextureFormat; /* 0308-030B */ + u32 TextureFilter; /* 030C-030F */ + u32 Blend; /* 0310-0313 */ + u32 Control; /* 0314-0317 */ + u32 FogColor; /* 0318-031B */ + u32 Reserved02[0x039]; + struct { /* 0400- */ + float sx; /* 00- 03 */ + float sy; /* 04- 07 */ + float sz; /* 08- 0B */ + float rhw; /* 0C- 0F */ + u32 color; /* 10- 13 */ + u32 specular; /* 14- 17 */ + float ts; /* 18- 1B */ + float tt; /* 1C- 1F */ + } Tlvertex[16]; /* -05FF */ + u32 DrawPrimitives[64]; /* 0600-063F */ + u32 Reserved03[0x640]; +} NVTexturedTriangleDx5; +#define TXTRI_COLOR_KEY 0x00000300 +#define TXTRI_OFFSET 0x00000304 +#define TXTRI_FORMAT 0x00000308 +#define TXTRI_FORMAT_CONTEXT_DMA_A 0x00000001 +#define TXTRI_FORMAT_CONTEXT_DMA_B 0x00000002 +#define TXTRI_FORMAT_COLORKEYENABLE 0x00000004 +#define TXTRI_FORMAT_ORIGIN_ZOH_CENTER 0x00000010 +#define TXTRI_FORMAT_ORIGIN_ZOH_CORNER 0x00000020 +#define TXTRI_FORMAT_ORIGIN_FOH_CENTER 0x00000040 +#define TXTRI_FORMAT_ORIGIN_FOH_CORNER 0x00000080 +#define TXTRI_FORMAT_COLOR_Y8 0x00000100 +#define TXTRI_FORMAT_COLOR_A1R5G5B5 0x00000200 +#define TXTRI_FORMAT_COLOR_X1R5G5B5 0x00000300 +#define TXTRI_FORMAT_COLOR_A4R4G4B4 0x00000400 +#define TXTRI_FORMAT_COLOR_R5G6B5 0x00000500 +#define TXTRI_FORMAT_COLOR_A8R8G8B8 0x00000600 +#define TXTRI_FORMAT_COLOR_X8R8G8B8 0x00000700 +#define TXTRI_FORMAT_MIPMAP_LEVELS_MSK 0x0000F000 +#define TXTRI_FORMAT_BASE_SIZE_U_MSK 0x000F0000 +#define TXTRI_FORMAT_BASE_SIZE_V_MSK 0x00F00000 +#define TXTRI_FORMAT_U_WRAP 0x01000000 +#define TXTRI_FORMAT_U_MIRROR 0x02000000 +#define TXTRI_FORMAT_U_CLAMP 0x03000000 +#define TXTRI_FORMAT_U_CLAMP_BORDER 0x04000000 +#define TXTRI_FORMAT_WRAPU_ENABLE 0x08000000 +#define TXTRI_FORMAT_V_WRAP 0x10000000 +#define TXTRI_FORMAT_V_MIRROR 0x20000000 +#define TXTRI_FORMAT_V_CLAMP 0x30000000 +#define TXTRI_FORMAT_V_CLAMP_BORDER 0x40000000 +#define TXTRI_FORMAT_WRAPV_ENABLE 0x80000000 +#define TXTRI_FILTER 0x0000030C +#define TXTRI_FILTER_KERNEL_SIZE_X_MSK 0x000000FF +#define TXTRI_FILTER_KERNEL_SIZE_Y_MSK 0x00007F00 +#define TXTRI_FILTER_MIPMAP_DITHER_ENABLE 0x00008000 +#define TXTRI_FILTER_MIPMAPLODBIAS_MSK 0x00FF0000 +#define TXTRI_FILTER_TEXTUREMIN_NEAREST 0x01000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEAR 0x02000000 +#define TXTRI_FILTER_TEXTUREMIN_MIPNEAREST 0x03000000 +#define TXTRI_FILTER_TEXTUREMIN_MIPLINEAR 0x04000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x05000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x06000000 +#define TXTRI_FILTER_ANISOTROPIC_MIN_ENABLE 0x08000000 +#define TXTRI_FILTER_TEXTUREMAG_NEAREST 0x10000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEAR 0x20000000 +#define TXTRI_FILTER_TEXTUREMAG_MIPNEAREST 0x30000000 +#define TXTRI_FILTER_TEXTUREMAG_MIPLINEAR 0x40000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x50000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x60000000 +#define TXTRI_FILTER_ANISOTROPIC_MAG_ENABLE 0x80000000 +#define TXTRI_BLEND 0x00000310 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECAL 0x00000001 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATE 0x00000002 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x00000003 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x00000004 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECALMASK 0x00000005 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x00000006 +#define TXTRI_BLEND_TEXTUREMAPBLEND_COPY 0x00000007 +#define TXTRI_BLEND_TEXTUREMAPBLEND_ADD 0x00000008 +#define TXTRI_BLEND_OPERATION_MUX_TALPHALSB 0x00000010 +#define TXTRI_BLEND_OPERATION_MUX_TALPHAMSB 0x00000020 +#define TXTRI_BLEND_SHADEMODE_FLAT 0x00000040 +#define TXTRI_BLEND_SHADEMODE_GOURAUD 0x00000080 +#define TXTRI_BLEND_SHADEMODE_PHONG 0x000000C0 +#define TXTRI_BLEND_TEXTUREPERSPECTIVE_ENABLE 0x00000100 +#define TXTRI_BLEND_SPECULAR_ENABLE 0x00001000 +#define TXTRI_BLEND_FOG_ENABLE 0x00010000 +#define TXTRI_BLEND_ALPHABLEND_ENABLE 0x00100000 +#define TXTRI_BLEND_SRCBLEND_ZERO 0x01000000 +#define TXTRI_BLEND_SRCBLEND_ONE 0x02000000 +#define TXTRI_BLEND_SRCBLEND_SRCCOLOR 0x03000000 +#define TXTRI_BLEND_SRCBLEND_INVSRCCOLOR 0x04000000 +#define TXTRI_BLEND_SRCBLEND_SRCALPHA 0x05000000 +#define TXTRI_BLEND_SRCBLEND_INVSRCALPHA 0x06000000 +#define TXTRI_BLEND_SRCBLEND_DESTALPHA 0x07000000 +#define TXTRI_BLEND_SRCBLEND_INVDESTALPHA 0x08000000 +#define TXTRI_BLEND_SRCBLEND_DESTCOLOR 0x09000000 +#define TXTRI_BLEND_SRCBLEND_INVDESTCOLOR 0x0A000000 +#define TXTRI_BLEND_SRCBLEND_SRCALPHASAT 0x0B000000 +#define TXTRI_BLEND_DESTBLEND_ZERO 0x10000000 +#define TXTRI_BLEND_DESTBLEND_ONE 0x20000000 +#define TXTRI_BLEND_DESTBLEND_SRCCOLOR 0x30000000 +#define TXTRI_BLEND_DESTBLEND_INVSRCCOLOR 0x40000000 +#define TXTRI_BLEND_DESTBLEND_SRCALPHA 0x50000000 +#define TXTRI_BLEND_DESTBLEND_INVSRCALPHA 0x60000000 +#define TXTRI_BLEND_DESTBLEND_DESTALPHA 0x70000000 +#define TXTRI_BLEND_DESTBLEND_INVDESTALPHA 0x80000000 +#define TXTRI_BLEND_DESTBLEND_DESTCOLOR 0x90000000 +#define TXTRI_BLEND_DESTBLEND_INVDESTCOLOR 0xA0000000 +#define TXTRI_BLEND_DESTBLEND_SRCALPHASAT 0xB0000000 +#define TXTRI_CONTROL 0x00000314 +#define TXTRI_CONTROL_ALPHAREF_MSK 0x000000FF +#define TXTRI_CONTROL_ALPHAFUNC_NEVER 0x00000100 +#define TXTRI_CONTROL_ALPHAFUNC_LESS 0x00000200 +#define TXTRI_CONTROL_ALPHAFUNC_EQUAL 0x00000300 +#define TXTRI_CONTROL_ALPHAFUNC_LESSEQUAL 0x00000400 +#define TXTRI_CONTROL_ALPHAFUNC_GREATER 0x00000500 +#define TXTRI_CONTROL_ALPHAFUNC_NOTEQUAL 0x00000600 +#define TXTRI_CONTROL_ALPHAFUNC_GREATEREQUAL 0x00000700 +#define TXTRI_CONTROL_ALPHAFUNC_ALWAYS 0x00000800 +#define TXTRI_CONTROL_ALPHATEST_ENABLE 0x00001000 +#define TXTRI_CONTROL_ORIGIN_CENTER 0x00000000 +#define TXTRI_CONTROL_ORIGIN_CORNER 0x00002000 +#define TXTRI_CONTROL_Z_ENABLE 0x00004000 +#define TXTRI_CONTROL_ZFUNC_NEVER 0x00010000 +#define TXTRI_CONTROL_ZFUNC_LESS 0x00020000 +#define TXTRI_CONTROL_ZFUNC_EQUAL 0x00030000 +#define TXTRI_CONTROL_ZFUNC_LESSEQUAL 0x00040000 +#define TXTRI_CONTROL_ZFUNC_GREATER 0x00050000 +#define TXTRI_CONTROL_ZFUNC_NOTEQUAL 0x00060000 +#define TXTRI_CONTROL_ZFUNC_GREATEREQUAL 0x00070000 +#define TXTRI_CONTROL_ZFUNC_ALWAYS 0x00080000 +#define TXTRI_CONTROL_CULLMODE_NONE 0x00100000 +#define TXTRI_CONTROL_CULLMODE_CW 0x00200000 +#define TXTRI_CONTROL_CULLMODE_CCW 0x00300000 +#define TXTRI_CONTROL_DITHER_ENABLE 0x00400000 +#define TXTRI_CONTROL_Z_PERSPECTIVE_ENABLE 0x00800000 +#define TXTRI_CONTROL_ZWRITE_ENABLE 0x01000000 +#define TXTRI_CONTROL_Z_FORMAT_FIXED 0x40000000 +#define TXTRI_CONTROL_Z_FORMAT_FLOAT 0x80000000 +#define TXTRI_FOG_COLOR 0x00000318 +#define TXTRI_VERTEX0 0x00000400 +#define TXTRI_VERTEX0_X 0x00000400 +#define TXTRI_VERTEX0_Y 0x00000404 +#define TXTRI_VERTEX0_Z 0x00000408 +#define TXTRI_VERTEX0_W 0x0000040C +#define TXTRI_VERTEX0_COLOR 0x00000410 +#define TXTRI_VERTEX0_SPECULAR 0x00000414 +#define TXTRI_VERTEX0_S 0x00000418 +#define TXTRI_VERTEX0_T 0x0000041C +#define TXTRI_PRIMITIVE0 0x00000600 + + + + +typedef volatile struct { + u32 SetObject; /* 0000-0003 */ + u32 Reserved00[0x003]; +#ifdef WORDS_BIGENDIAN + u32 Free; /* 0010-0013 */ +#else + u16 Free; /* 0010-0011 */ + u16 Nop; /* 0012-0013 */ +#endif + u32 Reserved01[0x00B]; + u32 DmaPut; /* 0040-0043 */ + u32 DmaGet; /* 0044-0047 */ + u32 Reserved02[0x02E]; + union { + NVSurfaces2D Surfaces2D; + NVSurfaces3D Surfaces3D; + NVClip Clip; + NVBeta1 Beta1; + NVBeta4 Beta4; + NVRectangle Rectangle; + NVTriangle Triangle; + NVLine Line; + NVScreenBlt ScreenBlt; + NVImageBlt ImageBlt; + NVScaledImage ScaledImage; + NVStretchedImage StretchedImage; + NVTexturedTriangleDx5 TexTriangle; + } o; +} NVDmaSubChannel; + + +typedef volatile struct { + NVDmaSubChannel sub[8]; +} NVDmaChannel; + + + +#endif /* __NVIDIA_REGS_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c new file mode 100755 index 0000000..70645f2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c @@ -0,0 +1,730 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_objects.h" +#include "nvidia_state.h" + + +#define NVIDIA_IS_SET( flag ) ((nvdev->set & SMF_##flag) == SMF_##flag) + +#define NVIDIA_SET( flag ) nvdev->set |= SMF_##flag + +#define NVIDIA_UNSET( flag ) nvdev->set &= ~SMF_##flag + + + +void nv_set_destination( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + volatile u8 *mmio = nvdrv->mmio_base; + u32 dst_offset; + u32 dst_pitch; + u32 src_pitch; + + if (NVIDIA_IS_SET( DESTINATION )) + return; + + dst_offset = (state->dst.offset + nvdev->fb_offset) & ~63; + dst_pitch = state->dst.pitch & ~31; + src_pitch = (nvdev->src_pitch & ~31) ? : 32; // align to 32, maybe system buffer pitch + + if (nvdev->dst_format != surface->config.format) { + u32 sformat2D = 0; + u32 sformat3D = 0; + u32 cformat = 0; + bool dst_422 = false; + + switch (surface->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + sformat2D = SURFACES2D_FORMAT_Y8; + cformat = RECT_COLOR_FORMAT_Y32; + break; + case DSPF_RGB555: + sformat2D = SURFACES2D_FORMAT_X1R5G5B5; + sformat3D = SURFACES3D_FORMAT_COLOR_X1R5G5B5; + cformat = RECT_COLOR_FORMAT_A1Y15; + break; + case DSPF_ARGB1555: + sformat2D = SURFACES2D_FORMAT_A1R5G5B5; + sformat3D = SURFACES3D_FORMAT_COLOR_A1R5G5B5; + cformat = RECT_COLOR_FORMAT_A1Y15; + break; + case DSPF_RGB16: + sformat2D = SURFACES2D_FORMAT_R5G6B5; + sformat3D = SURFACES3D_FORMAT_COLOR_R5G6B5; + cformat = RECT_COLOR_FORMAT_Y16; + break; + case DSPF_RGB32: + sformat2D = SURFACES2D_FORMAT_X8R8G8B8; + sformat3D = SURAFCES3D_FORMAT_COLOR_X8R8G8B8; + cformat = RECT_COLOR_FORMAT_Y32; + break; + case DSPF_ARGB: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + sformat3D = SURFACES3D_FORMAT_COLOR_A8R8G8B8; + cformat = 0x0D; + break; + case DSPF_YUY2: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + cformat = 0x12; + dst_422 = true; + break; + case DSPF_UYVY: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + cformat = 0x13; + dst_422 = true; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (sformat2D == SURFACES2D_FORMAT_A8R8G8B8) { + /* need to set color format manually */ + nv_waitidle( nvdrv, nvdev ); + + nv_out32( mmio, PRAMIN + (ADDR_RECTANGLE << 4) + 4, cformat << 8 ); + nv_out32( mmio, PRAMIN + (ADDR_TRIANGLE << 4) + 4, cformat << 8 ); + nv_out32( mmio, PRAMIN + (ADDR_LINE << 4) + 4, cformat << 8 ); + + nv_assign_object( nvdrv, nvdev, + SUBC_RECTANGLE, OBJ_RECTANGLE, true ); + nv_assign_object( nvdrv, nvdev, + SUBC_TRIANGLE, OBJ_TRIANGLE, true ); + nv_assign_object( nvdrv, nvdev, + SUBC_LINE, OBJ_LINE, true ); + } else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + + nv_begin( SUBC_TRIANGLE, TRI_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + + nv_begin( SUBC_LINE, LINE_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + } + + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_FORMAT, 2 ); + nv_outr( sformat2D ); + nv_outr( (dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_begin( SUBC_SURFACES2D, SURFACES2D_DST_OFFSET, 1 ); + nv_outr( dst_offset ); + + if (nvdev->enabled_3d && sformat3D) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES3D, OBJ_SURFACES3D, false ); + + nv_begin( SUBC_SURFACES3D, SURFACES3D_FORMAT, 1 ); + nv_outr( sformat3D | SURFACES3D_FORMAT_TYPE_PITCH ); + nv_begin( SUBC_SURFACES3D, SURFACES3D_PITCH, 2 ); + nv_outr( (64 << 16) | (dst_pitch & 0xFFFF) ); + nv_outr( dst_offset ); + } + + if (nvdev->dst_422 != dst_422) { + NVIDIA_UNSET( CLIP ); + NVIDIA_UNSET( BLITTING_FLAGS ); + nvdev->dst_422 = dst_422; + } + + NVIDIA_UNSET( COLOR ); + NVIDIA_UNSET( DST_BLEND ); + } + else if (nvdev->dst_offset != dst_offset || + nvdev->dst_pitch != dst_pitch) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_PITCH, 1 ); + nv_outr( (dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_begin( SUBC_SURFACES2D, SURFACES2D_DST_OFFSET, 1 ); + nv_outr( dst_offset ); + + if (nvdev->enabled_3d) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES3D, OBJ_SURFACES3D, false ); + + nv_begin( SUBC_SURFACES3D, SURFACES3D_PITCH, 2 ); + nv_outr( (64 << 16) | (dst_pitch & 0xFFFF) ); + nv_outr( dst_offset ); + } + } + + nvdev->dst_format = surface->config.format; + nvdev->dst_offset = dst_offset; + nvdev->dst_pitch = dst_pitch; + + NVIDIA_SET( DESTINATION ); +} + +void nv_set_source( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + + nvdev->src_lock = &state->src; + + if (NVIDIA_IS_SET( SOURCE )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (nvdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + if (state->src.buffer->policy == CSP_SYSTEMONLY) { + if (!nvdev->src_system) { + nv_assign_object( nvdrv, nvdev, + SUBC_IMAGEBLT, OBJ_IMAGEBLT, false ); + nv_assign_object( nvdrv, nvdev, + SUBC_STRETCHEDIMAGE, OBJ_STRETCHEDIMAGE, false ); + + NVIDIA_UNSET( BLITTING_FLAGS ); + } + + nvdev->src_address = state->src.addr; + nvdev->src_pitch = state->src.pitch; + nvdev->src_system = true; + } + else { + u32 src_offset = (state->src.offset + nvdev->fb_offset) & ~63; + u32 src_pitch = state->src.pitch & ~31; + + if (nvdev->src_offset != src_offset || + nvdev->src_pitch != src_pitch) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_PITCH, 2 ); + nv_outr( (nvdev->dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_outr( src_offset ); + } + + if (nvdev->src_system) { + nv_assign_object( nvdrv, nvdev, + SUBC_SCREENBLT, OBJ_SCREENBLT, false ); + nv_assign_object( nvdrv, nvdev, + SUBC_SCALEDIMAGE, OBJ_SCALEDIMAGE, false ); + + NVIDIA_UNSET( BLITTING_FLAGS ); + } + + nvdev->src_offset = src_offset; + nvdev->src_pitch = src_pitch; + nvdev->src_system = false; + } + + nvdev->src_width = surface->config.size.w; + nvdev->src_height = surface->config.size.h; + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + nvdev->src_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) { + nvdev->src_address += nvdev->src_height * nvdev->src_pitch; + nvdev->src_offset += nvdev->src_height * nvdev->src_pitch; + } + } else { + if (surface->field) { + nvdev->src_address += nvdev->src_pitch; + nvdev->src_offset += nvdev->src_pitch; + } + nvdev->src_pitch *= 2; + } + nvdev->src_interlaced = true; + } else + nvdev->src_interlaced = false; + + if (nvdev->enabled_3d) { + u32 size_u = direct_log2(surface->config.size.w) & 0xF; + u32 size_v = direct_log2(surface->config.size.h) & 0xF; + + nvdev->state3d[1].offset = nvdev->fb_offset + nvdev->buf_offset[1]; + nvdev->state3d[1].format &= 0xFF00FFFF; + nvdev->state3d[1].format |= (size_u << 16) | (size_v << 20); + } + + if (nvdev->src_format != surface->config.format) { + NVIDIA_UNSET( SRC_BLEND ); + NVIDIA_UNSET( BLITTING_FLAGS ); + nvdev->src_format = surface->config.format; + } + + NVIDIA_SET( SOURCE ); +} + +void nv_set_clip( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBRectangle *cr = &nvdev->clip; + + if (NVIDIA_IS_SET( CLIP )) + return; + + cr->x = state->clip.x1; + cr->y = state->clip.y1; + cr->w = state->clip.x2 - state->clip.x1 + 1; + cr->h = state->clip.y2 - state->clip.y1 + 1; + + if (nvdev->dst_422) { + cr->x = cr->x / 2; + cr->w = (cr->w / 2) ? : 1; + } + + nv_begin( SUBC_CLIP, CLIP_TOP_LEFT, 2 ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + + NVIDIA_SET( CLIP ); +} + +void nv_set_drawing_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBColor color = state->color; + int y, u, v; + + if (NVIDIA_IS_SET( DRAWING_COLOR ) && NVIDIA_IS_SET( DRAWING_FLAGS )) + return; + + switch (nvdev->dst_format) { + case DSPF_A8: + nvdev->color2d = color.a; + break; + case DSPF_LUT8: + nvdev->color2d = state->color_index; + break; + case DSPF_ALUT44: + nvdev->color2d = (state->color_index & 0x0F) | + (state->color.a & 0xF0); + break; + case DSPF_RGB332: + nvdev->color2d = PIXEL_RGB332( color.r, + color.g, + color.b ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + nvdev->color2d = PIXEL_ARGB1555( color.a, + color.r, + color.g, + color.b ); + break; + case DSPF_RGB16: + nvdev->color2d = PIXEL_RGB16( color.r, + color.g, + color.b ); + break; + case DSPF_RGB32: + nvdev->color2d = PIXEL_RGB32( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB: + nvdev->color2d = PIXEL_ARGB( color.a, + color.r, + color.g, + color.b ); + break; + + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + nvdev->color2d = PIXEL_YUY2( y, u, v ); + break; + + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + nvdev->color2d = PIXEL_UYVY( y, u, v ); + break; + + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + nvdev->color3d = PIXEL_ARGB(color.a, color.r, color.g, color.b); + + if (nvdev->dst_format == DSPF_ARGB1555) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_FORMAT, 1 ); + nv_outr( (nvdev->color2d & 0x8000) + ? SURFACES2D_FORMAT_A1R5G5B5 + : SURFACES2D_FORMAT_X1R5G5B5 ); + } + + if (state->drawingflags & DSDRAW_BLEND && !nvdev->enabled_3d) { + if (!nvdev->beta1_set || nvdev->beta1_val != (color.a << 23)) { + nv_assign_object( nvdrv, nvdev, SUBC_BETA1, OBJ_BETA1, false ); + + nv_begin( SUBC_BETA1, BETA1_FACTOR, 1 ); + nv_outr( color.a << 23 ); + + nvdev->beta1_val = color.a << 23; + nvdev->beta1_set = true; + } + } + + NVIDIA_SET ( DRAWING_COLOR ); + NVIDIA_UNSET( BLITTING_COLOR ); +} + +void nv_set_blitting_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBColor color = state->color; + + if (NVIDIA_IS_SET( BLITTING_COLOR ) && NVIDIA_IS_SET( BLITTING_FLAGS )) + return; + + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) || + (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && state->src_blend == DSBF_ONE)) { + nvdev->color3d = (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + ? (color.a << 24) : 0xFF000000; + + if (state->blittingflags & DSBLIT_COLORIZE && + state->blittingflags & (DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + nvdev->color3d |= PIXEL_RGB32( color.r * color.a / 0xFF, + color.g * color.a / 0xFF, + color.b * color.a / 0xFF ); + } + else if (state->blittingflags & DSBLIT_COLORIZE) { + nvdev->color3d |= PIXEL_RGB32( color.r, color.g, color.b ); + } + else if (state->blittingflags & (DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + nvdev->color3d |= PIXEL_RGB32( color.a, color.a, color.a ); + } + else { + nvdev->color3d |= 0x00FFFFFF; + } + + if (!nvdev->beta4_set || nvdev->beta4_val != nvdev->color3d) { + nv_assign_object( nvdrv, nvdev, + SUBC_BETA4, OBJ_BETA4, false ); + + nv_begin( SUBC_BETA4, BETA4_FACTOR, 1 ); + nv_outr( nvdev->color3d ); + + nvdev->beta4_val = nvdev->color3d; + nvdev->beta4_set = true; + } + } + else if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + u32 beta1; + + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + nvdev->color3d = (color.a << 24) | 0x00FFFFFF; + beta1 = color.a << 23; + } else { + nvdev->color3d = 0xFFFFFFFF; + beta1 = 0x7F800000; + } + + if (!nvdev->beta1_set || nvdev->beta1_val != beta1) { + nv_assign_object( nvdrv, nvdev, + SUBC_BETA1, OBJ_BETA1, false ); + + nv_begin( SUBC_BETA1, BETA1_FACTOR, 1 ); + nv_outr( beta1 ); + + nvdev->beta1_val = beta1; + nvdev->beta1_set = true; + } + } + + NVIDIA_SET ( BLITTING_COLOR ); + NVIDIA_UNSET( DRAWING_COLOR ); +} + +void nv_set_blend_function( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBSurfaceBlendFunction sblend, dblend; + + if (NVIDIA_IS_SET( SRC_BLEND ) && NVIDIA_IS_SET( DST_BLEND )) + return; + + sblend = state->src_blend; + dblend = state->dst_blend; + + if (!DFB_PIXELFORMAT_HAS_ALPHA(nvdev->dst_format)) { + if (sblend == DSBF_DESTALPHA) + sblend = DSBF_ONE; + else if (sblend == DSBF_INVDESTALPHA) + sblend = DSBF_ZERO; + + if (dblend == DSBF_DESTALPHA) + dblend = DSBF_ONE; + else if (dblend == DSBF_INVDESTALPHA) + dblend = DSBF_ZERO; + } + + nvdev->state3d[0].blend &= 0x00FFFFFF; + nvdev->state3d[0].blend |= (sblend << 24) | (dblend << 28); + nvdev->state3d[1].blend &= 0x00FFFFFF; + nvdev->state3d[1].blend |= (sblend << 24) | (dblend << 28); + + if (!NVIDIA_IS_SET( SRC_BLEND )) + NVIDIA_UNSET( BLITTING_FLAGS ); + NVIDIA_SET( SRC_BLEND ); + NVIDIA_SET( DST_BLEND ); +} + +void nv_set_drawingflags( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + if (NVIDIA_IS_SET( DRAWING_FLAGS )) + return; + + if (!nvdev->enabled_3d) { + u32 operation; + + if (state->drawingflags & DSDRAW_BLEND) + operation = OPERATION_BLEND; + else + operation = OPERATION_SRCCOPY; + + if (nvdev->drawing_operation != operation) { + nv_begin( SUBC_RECTANGLE, RECT_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_TRIANGLE, TRI_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_LINE, LINE_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->drawing_operation = operation; + } + } + else { + if (state->drawingflags & DSDRAW_BLEND) + nvdev->state3d[0].blend |= TXTRI_BLEND_ALPHABLEND_ENABLE; + else + nvdev->state3d[0].blend &= ~TXTRI_BLEND_ALPHABLEND_ENABLE; + } + + nvdev->drawingflags = state->drawingflags; + + NVIDIA_SET( DRAWING_FLAGS ); +} + +void nv_set_blittingflags( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + u32 operation; + bool src_alpha; + + if (NVIDIA_IS_SET( BLITTING_FLAGS )) + return; + + operation = (nvdev->arch > NV_ARCH_04) ? OPERATION_SRCCOPY : OPERATION_COPY; + src_alpha = true; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) || + (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && state->src_blend == DSBF_ONE)) { + operation = OPERATION_BLEND_PREMULTIPLIED; + } + else { + operation = OPERATION_BLEND; + src_alpha = !!(state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL); + } + } + else if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) { + operation = OPERATION_COLOR_MULTIPLY; + } + + if (nvdev->src_system) { + switch (nvdev->src_format) { + case DSPF_RGB555: + nvdev->system_format = IBLIT_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->system_format = src_alpha + ? IBLIT_COLOR_FORMAT_A1R5G5B5 + : IBLIT_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_RGB16: + nvdev->system_format = IBLIT_COLOR_FORMAT_R5G6B5; + break; + case DSPF_RGB32: + nvdev->system_format = IBLIT_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_ARGB: + nvdev->system_format = src_alpha + ? IBLIT_COLOR_FORMAT_A8R8G8B8 + : IBLIT_COLOR_FORMAT_X8R8G8B8; + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + if (nvdev->system_operation != operation) { + nv_begin( SUBC_IMAGEBLT, IBLIT_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->system_operation = operation; + } + } + else { + switch (nvdev->src_format) { + case DSPF_A8: + nvdev->scaler_format = SCALER_COLOR_FORMAT_AY8; + break; + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + nvdev->scaler_format = SCALER_COLOR_FORMAT_Y8; + break; + case DSPF_RGB555: + nvdev->scaler_format = SCALER_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->scaler_format = src_alpha + ? SCALER_COLOR_FORMAT_A1R5G5B5 + : SCALER_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_RGB16: + nvdev->scaler_format = SCALER_COLOR_FORMAT_R5G6B5; + break; + case DSPF_RGB32: + nvdev->scaler_format = SCALER_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_ARGB: + nvdev->scaler_format = src_alpha + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_YUY2: + nvdev->scaler_format = nvdev->dst_422 + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_V8YB8U8YA8; + break; + case DSPF_UYVY: + nvdev->scaler_format = nvdev->dst_422 + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_YB8V8YA8U8; + break; + default: + D_BUG( "unexpected pixelformat 0x%08x", nvdev->src_format ); + break; + } + + if (nvdev->scaler_operation != operation) { + nv_begin( SUBC_SCALEDIMAGE, SCALER_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->scaler_operation = operation; + } + } + + if (nvdev->enabled_3d) { + nvdev->state3d[1].format &= 0xFFFFF0FF; + nvdev->state3d[1].blend &= 0xFF00FFF0; + + switch (nvdev->src_format) { + case DSPF_RGB555: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_A1R5G5B5; + break; + case DSPF_A8: + case DSPF_ARGB: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_A4R4G4B4; + break; + default: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_R5G6B5; + break; + } + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | DSBLIT_COLORIZE | + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_SRC_PREMULTCOLOR)) { + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + nvdev->state3d[1].blend |= + TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA; + else + nvdev->state3d[1].blend |= + TXTRI_BLEND_TEXTUREMAPBLEND_MODULATE; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) + nvdev->state3d[1].blend |= TXTRI_BLEND_ALPHABLEND_ENABLE; + } else + nvdev->state3d[1].blend |= TXTRI_BLEND_TEXTUREMAPBLEND_COPY; + } + + nvdev->blittingflags = state->blittingflags; + + NVIDIA_SET( BLITTING_FLAGS ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h new file mode 100755 index 0000000..5bfc8f1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h @@ -0,0 +1,58 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_STATE_H__ +#define __NVIDIA_STATE_H__ + + +void nv_set_destination ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_source ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_clip ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_drawing_color ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blitting_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blend_function( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_drawingflags ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blittingflags ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); + +#endif /* __NVIDIA_STATE_H__ */ diff --git a/Source/DirectFB/gfxdrivers/omap/Makefile.am b/Source/DirectFB/gfxdrivers/omap/Makefile.am new file mode 100755 index 0000000..2132563 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/omap/Makefile.am @@ -0,0 +1,34 @@ +## Makefile.am for DirectFB/gfxdrivers/omap + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +omap_LTLIBRARIES = libdirectfb_omap.la + +if BUILD_STATIC +omap_DATA = $(omap_LTLIBRARIES:.la=.o) +endif + +omapdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_omap_la_SOURCES = \ + omap.c \ + omap.h \ + omapfb.h \ + omap_primary.c + +libdirectfb_omap_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_omap_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + +include $(top_srcdir)/rules/libobject.make diff --git a/Source/DirectFB/gfxdrivers/omap/Makefile.in b/Source/DirectFB/gfxdrivers/omap/Makefile.in new file mode 100755 index 0000000..ba95bd1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/omap/Makefile.in @@ -0,0 +1,598 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/omap +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = 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(directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include + +#include +#include "omapfb.h" + +#include + +#include + +#include +#include +#include + +#include + +#include + +DFB_GRAPHICS_DRIVER( omap ) + +#include "omap.h" + +/* */ + +static DFBResult +omapEngineSync( void *drv, void *dev ) +{ + FBDev *dfb_fbdev = dfb_system_data(); + + /* FIXME needed? */ + ioctl( dfb_fbdev->fd, OMAPFB_SYNC_GFX ); + + return DFB_OK; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + FBDev *dfb_fbdev = dfb_system_data(); + struct omapfb_caps caps; + + if (ioctl( dfb_fbdev->fd, OMAPFB_GET_CAPS, &caps)) + return 0; + + return 1; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *driver_info ) +{ + driver_info->version.major = 0; + driver_info->version.minor = 1; + + direct_snputs( driver_info->name, + "TI OMAP Driver", DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH ); + direct_snputs( driver_info->vendor, + "Ville Syrjala", DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH ); + direct_snputs( driver_info->url, + "http://www.directfb.org", DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH ); + direct_snputs( driver_info->license, + "LGPL", DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH ); + +#if 0 + driver_info->driver_data_size = sizeof (OmapDriverData); + driver_info->device_data_size = sizeof (OmapDeviceData); +#endif +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + funcs->EngineSync = omapEngineSync; + + dfb_layers_hook_primary( device, driver_data, &omapPrimaryLayerFuncs, NULL, NULL ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + direct_snputs( device_info->name, + "OMAP", DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH ); + direct_snputs( device_info->vendor, + "TI", DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} diff --git a/Source/DirectFB/gfxdrivers/omap/omap.h b/Source/DirectFB/gfxdrivers/omap/omap.h new file mode 100755 index 0000000..3eeaa7a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/omap/omap.h @@ -0,0 +1,48 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef OMAP_H +#define OMAP_H + +#include + +#include + +D_DEBUG_DOMAIN( omap, "OMAP", "TI OMAP gfx driver" ); + +#if 0 +typedef struct { +} OmapDeviceData; + +typedef struct { +} OmapDriverData; +#endif + +extern DisplayLayerFuncs omapPrimaryLayerFuncs; + +#endif diff --git a/Source/DirectFB/gfxdrivers/omap/omap_primary.c b/Source/DirectFB/gfxdrivers/omap/omap_primary.c new file mode 100755 index 0000000..8bdfc61 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/omap/omap_primary.c @@ -0,0 +1,102 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include + +#include + +#include +#include "omapfb.h" + +#include +#include + +#include + +#include +#include +#include + +#include + +#include "omap.h" + +/* */ + +static DFBResult +omapUpdateRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + const DFBRegion *update, + CoreSurfaceBufferLock *lock ) +{ + FBDev *dfb_fbdev = dfb_system_data(); + struct omapfb_update_window window; + DFBRectangle rect; + + dfb_rectangle_from_region( &rect, update ); + + D_DEBUG_AT( omap, "Update rectangle %d %d %dx%d\n", + rect.x, rect.y, rect.w, rect.h ); + + if (rect.x & 1) + rect.w++; + if (rect.y & 1) + rect.h++; + + window.x = rect.x & ~1; + window.y = rect.y & ~1; + + window.width = (rect.w + 1) & ~1; + window.height = (rect.h + 1) & ~1; + + window.out_x = window.x; + window.out_y = window.y; + + window.out_width = window.width; + window.out_height = window.height; + + window.format = 0; + + D_DEBUG_AT( omap, "Update window %d %d %dx%d\n", + window.x, window.y, window.width, window.height ); + + if (ioctl( dfb_fbdev->fd, OMAPFB_UPDATE_WINDOW, &window )) + D_DEBUG_AT( omap, "Can't update window -> %s\n", strerror( errno ) ); + + return DFB_OK; +} + +DisplayLayerFuncs omapPrimaryLayerFuncs = { + .UpdateRegion = omapUpdateRegion, +}; diff --git a/Source/DirectFB/gfxdrivers/omap/omapfb.h b/Source/DirectFB/gfxdrivers/omap/omapfb.h new file mode 100755 index 0000000..5d511b9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/omap/omapfb.h @@ -0,0 +1,163 @@ +/* + * File: include/asm-arm/arch-omap/omapfb.h + * + * Framebuffer driver for TI OMAP boards + * + * Copyright (C) 2004 Nokia Corporation + * Author: Imre Deak + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __OMAPFB_H +#define __OMAPFB_H + +#include +#include + +/* IOCTL commands. */ + +#define OMAP_IOW(num, dtype) _IOW('O', num, dtype) +#define OMAP_IOR(num, dtype) _IOR('O', num, dtype) +#define OMAP_IOWR(num, dtype) _IOWR('O', num, dtype) +#define OMAP_IO(num) _IO('O', num) + +#define OMAPFB_MIRROR OMAP_IOW(31, int) +#define OMAPFB_SYNC_GFX OMAP_IO(37) +#define OMAPFB_VSYNC OMAP_IO(38) +#define OMAPFB_SET_UPDATE_MODE OMAP_IOW(40, int) +#define OMAPFB_GET_CAPS OMAP_IOR(42, struct omapfb_caps) +#define OMAPFB_GET_UPDATE_MODE OMAP_IOW(43, int) +#define OMAPFB_LCD_TEST OMAP_IOW(45, int) +#define OMAPFB_CTRL_TEST OMAP_IOW(46, int) +#define OMAPFB_UPDATE_WINDOW_OLD OMAP_IOW(47, struct omapfb_update_window_old) +#define OMAPFB_SET_COLOR_KEY OMAP_IOW(50, struct omapfb_color_key) +#define OMAPFB_GET_COLOR_KEY OMAP_IOW(51, struct omapfb_color_key) +#define OMAPFB_SETUP_PLANE OMAP_IOW(52, struct omapfb_plane_info) +#define OMAPFB_QUERY_PLANE OMAP_IOW(53, struct omapfb_plane_info) +#define OMAPFB_UPDATE_WINDOW OMAP_IOW(54, struct omapfb_update_window) +#define OMAPFB_SETUP_MEM OMAP_IOW(55, struct omapfb_mem_info) +#define OMAPFB_QUERY_MEM OMAP_IOW(56, struct omapfb_mem_info) + +#define OMAPFB_CAPS_GENERIC_MASK 0x00000fff +#define OMAPFB_CAPS_LCDC_MASK 0x00fff000 +#define OMAPFB_CAPS_PANEL_MASK 0xff000000 + +#define OMAPFB_CAPS_MANUAL_UPDATE 0x00001000 +#define OMAPFB_CAPS_TEARSYNC 0x00002000 +#define OMAPFB_CAPS_PLANE_RELOCATE_MEM 0x00004000 +#define OMAPFB_CAPS_PLANE_SCALE 0x00008000 +#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 +#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 +#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 +#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 + +/* Values from DSP must map to lower 16-bits */ +#define OMAPFB_FORMAT_MASK 0x00ff +#define OMAPFB_FORMAT_FLAG_DOUBLE 0x0100 +#define OMAPFB_FORMAT_FLAG_TEARSYNC 0x0200 +#define OMAPFB_FORMAT_FLAG_FORCE_VSYNC 0x0400 +#define OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY 0x0800 +#define OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY 0x1000 + +#define OMAPFB_EVENT_READY 1 +#define OMAPFB_EVENT_DISABLED 2 + +#define OMAPFB_MEMTYPE_SDRAM 0 +#define OMAPFB_MEMTYPE_SRAM 1 +#define OMAPFB_MEMTYPE_MAX 1 + +enum omapfb_color_format { + OMAPFB_COLOR_RGB565 = 0, + OMAPFB_COLOR_YUV422, + OMAPFB_COLOR_YUV420, + OMAPFB_COLOR_CLUT_8BPP, + OMAPFB_COLOR_CLUT_4BPP, + OMAPFB_COLOR_CLUT_2BPP, + OMAPFB_COLOR_CLUT_1BPP, + OMAPFB_COLOR_RGB444, + OMAPFB_COLOR_YUY422, +}; + +struct omapfb_update_window { + u32 x, y; + u32 width, height; + u32 format; + u32 out_x, out_y; + u32 out_width, out_height; + u32 reserved[8]; +}; + +struct omapfb_update_window_old { + u32 x, y; + u32 width, height; + u32 format; +}; + +enum omapfb_plane { + OMAPFB_PLANE_GFX = 0, + OMAPFB_PLANE_VID1, + OMAPFB_PLANE_VID2, +}; + +enum omapfb_channel_out { + OMAPFB_CHANNEL_OUT_LCD = 0, + OMAPFB_CHANNEL_OUT_DIGIT, +}; + +struct omapfb_plane_info { + u32 pos_x; + u32 pos_y; + u8 enabled; + u8 channel_out; + u8 mirror; + u8 reserved1; + u32 out_width; + u32 out_height; + u32 reserved2[12]; +}; + +struct omapfb_mem_info { + u32 size; + u8 type; + u8 reserved[3]; +}; + +struct omapfb_caps { + u32 ctrl; + u32 plane_color; + u32 wnd_color; +}; + +enum omapfb_color_key_type { + OMAPFB_COLOR_KEY_DISABLED = 0, + OMAPFB_COLOR_KEY_GFX_DST, + OMAPFB_COLOR_KEY_VID_SRC, +}; + +struct omapfb_color_key { + u8 channel_out; + u32 background; + u32 trans_key; + u8 key_type; +}; + +enum omapfb_update_mode { + OMAPFB_UPDATE_DISABLED = 0, + OMAPFB_AUTO_UPDATE, + OMAPFB_MANUAL_UPDATE +}; + +#endif /* __OMAPFB_H */ diff --git a/Source/DirectFB/gfxdrivers/radeon/Makefile.am b/Source/DirectFB/gfxdrivers/radeon/Makefile.am new file mode 100755 index 0000000..322ae30 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/Makefile.am @@ -0,0 +1,52 @@ +## Makefile.am for DirectFB/src/core/gfxcards/radeon + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +radeon_LTLIBRARIES = libdirectfb_radeon.la + +if BUILD_STATIC +radeon_DATA = $(radeon_LTLIBRARIES:.la=.o) +endif + +radeondir = $(MODULEDIR)/gfxdrivers + +libdirectfb_radeon_la_SOURCES = \ + radeon.c \ + r100_state.c \ + r200_state.c \ + r300_state.c \ + radeon_2d.c \ + r100_3d.c \ + r200_3d.c \ + r300_3d.c \ + radeon_overlay.c \ + radeon_crtc1.c \ + radeon_crtc2.c \ + radeon.h \ + radeon_chipsets.h \ + radeon_regs.h \ + r300_program.h \ + radeon_mmio.h \ + radeon_state.h \ + radeon_2d.h \ + radeon_3d.h \ + vertex_shader.h + +libdirectfb_radeon_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) -lm + +libdirectfb_radeon_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/radeon/Makefile.in b/Source/DirectFB/gfxdrivers/radeon/Makefile.in new file mode 100755 index 0000000..50e9cb1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/Makefile.in @@ -0,0 +1,625 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/radeon +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(radeondir)" "$(DESTDIR)$(radeondir)" +radeonLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(radeon_LTLIBRARIES) +libdirectfb_radeon_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_radeon_la_OBJECTS = radeon.lo r100_state.lo \ + r200_state.lo r300_state.lo radeon_2d.lo r100_3d.lo r200_3d.lo \ + r300_3d.lo radeon_overlay.lo radeon_crtc1.lo radeon_crtc2.lo +libdirectfb_radeon_la_OBJECTS = $(am_libdirectfb_radeon_la_OBJECTS) +libdirectfb_radeon_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_radeon_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_radeon_la_SOURCES) +DIST_SOURCES = $(libdirectfb_radeon_la_SOURCES) +radeonDATA_INSTALL = $(INSTALL_DATA) +DATA = $(radeon_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +radeon_LTLIBRARIES = libdirectfb_radeon.la +@BUILD_STATIC_TRUE@radeon_DATA = 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a/Source/DirectFB/gfxdrivers/radeon/r100_3d.c b/Source/DirectFB/gfxdrivers/radeon/r100_3d.c new file mode 100755 index 0000000..c647b55 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r100_3d.c @@ -0,0 +1,523 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_3d.h" + + +#define EMIT_VERTICES( rdrv, rdev, mmio ) { \ + u32 *_v = (rdev)->vb; \ + u32 _s = (rdev)->vb_size; \ + radeon_waitfifo( rdrv, rdev, 1 ); \ + radeon_out32( mmio, SE_VF_CNTL, rdev->vb_type | VF_PRIM_WALK_DATA | VF_RADEON_MODE | \ + (rdev->vb_count << VF_NUM_VERTICES_SHIFT) ); \ + do { \ + u32 _n = MIN(_s, 64); \ + _s -= _n; \ + radeon_waitfifo( rdrv, rdev, _n ); \ + while (_n--) \ + radeon_out32( mmio, SE_PORT_DATA0, *_v++ ); \ + } while (_s); \ +} + +static void +r100_flush_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + EMIT_VERTICES( rdrv, rdev, mmio ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + DFBRegion *clip = &rdev->clip; + bool s420 = DFB_PLANAR_PIXELFORMAT(rdev->src_format); + int i; + + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + for (i = 0; i < rdev->vb_size; i += 4) { + rdev->vb[i+0] = f2d(d2f(rdev->vb[i+0])*0.5f); + rdev->vb[i+1] = f2d(d2f(rdev->vb[i+1])*0.5f); + if (s420) { + rdev->vb[i+2] = f2d(d2f(rdev->vb[i+2])*0.5f); + rdev->vb[i+3] = f2d(d2f(rdev->vb[i+3])*0.5f); + } + } + } else { + for (i = 0; i < rdev->vb_size; i += 2) { + rdev->vb[i+0] = f2d(d2f(rdev->vb[i+0])*0.5f); + rdev->vb[i+1] = f2d(d2f(rdev->vb[i+1])*0.5f); + } + } + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2/2 << 16) | + (clip->x2/2 & 0xffff) ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, PP_TFACTOR_0, rdev->cb_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, PP_TEX_SIZE_0, ((rdev->src_height/2-1) << 16) | + ((rdev->src_width/2-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_0, rdev->src_pitch/2 - 32 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset_cb ); + } + } else { + radeon_out32( mmio, PP_TFACTOR_1, rdev->cb_cop ); + } + + /* Fill Cb plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cr ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, PP_TFACTOR_0, rdev->cr_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset_cr ); + } + } else { + radeon_out32( mmio, PP_TFACTOR_1, rdev->cr_cop ); + } + + /* Fill Cr plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch ); + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2 << 16) | + (clip->x2 & 0xffff) ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, PP_TFACTOR_0, rdev->y_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, PP_TEX_SIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset ); + } + } else { + radeon_out32( mmio, PP_TFACTOR_1, rdev->y_cop ); + } + } + + rdev->vb_size = 0; + rdev->vb_count = 0; +} + +static inline u32* +r100_init_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev, u32 type, u32 count, u32 size ) +{ + u32 *vb; + + if ((rdev->vb_size && rdev->vb_type != type) || + rdev->vb_size+size > D_ARRAY_SIZE(rdev->vb)) + r100_flush_vb( rdrv, rdev ); + + vb = &rdev->vb[rdev->vb_size]; + rdev->vb_type = type; + rdev->vb_size += size; + rdev->vb_count += count; + + return vb; +} + + +bool r100FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + if (rect->w == 1 && rect->h == 1) { + x1 = rect->x+1; y1 = rect->y+1; + if (rdev->matrix) + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_POINT_LIST, 1, 2 ); + *v++ = f2d(x1); *v++ = f2d(y1); + + return true; + } + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float X1, Y1, X2, Y2, X3, Y3, X4, Y4; + + RADEON_TRANSFORM( x1, y1, X1, Y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y1, X2, Y2, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, X3, Y3, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x1, y2, X4, Y4, rdev->matrix, rdev->affine_matrix ); + + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_TRIANGLE_LIST, 6, 12 ); + *v++ = f2d(X1); *v++ = f2d(Y1); + *v++ = f2d(X2); *v++ = f2d(Y2); + *v++ = f2d(X3); *v++ = f2d(Y3); + *v++ = f2d(X1); *v++ = f2d(Y1); + *v++ = f2d(X3); *v++ = f2d(Y3); + *v++ = f2d(X4); *v++ = f2d(Y4); + } + else { + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 3, 6 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + } + + return true; +} + +bool r100FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float x3, y3; + u32 *v; + + x1 = tri->x1; y1 = tri->y1; + x2 = tri->x2; y2 = tri->y2; + x3 = tri->x3; y3 = tri->y3; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x3, y3, x3, y3, rdev->matrix, rdev->affine_matrix ); + } + + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_TRIANGLE_LIST, 3, 6 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + *v++ = f2d(x3); *v++ = f2d(y3); + + return true; +} + +bool r100DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float x, y; + + /* XXX: better LINE_STRIP?! */ + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LIST, 8, 16 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + } + else { + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 12, 24 ); + /* top line */ + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1+1); + /* right line */ + *v++ = f2d(x2-1); *v++ = f2d(y1+1); + *v++ = f2d(x2); *v++ = f2d(y1+1); + *v++ = f2d(x2); *v++ = f2d(y2-1); + /* bottom line */ + *v++ = f2d(x1); *v++ = f2d(y2-1); + *v++ = f2d(x2); *v++ = f2d(y2-1); + *v++ = f2d(x2); *v++ = f2d(y2); + /* left line */ + *v++ = f2d(x1); *v++ = f2d(y1+1); + *v++ = f2d(x1+1); *v++ = f2d(y1+1); + *v++ = f2d(x1+1); *v++ = f2d(y2-1); + } + + return true; +} + +bool r100DrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = line->x1; y1 = line->y1; + x2 = line->x2; y2 = line->y2; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + } + + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LIST, 2, 4 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + + return true; +} + +bool r100Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ) +{ + DFBRectangle dr = { dx, dy, sr->w, sr->h }; + + return r100StretchBlit( drv, dev, sr, &dr ); +} + +bool r100StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float s1, t1; + float s2, t2; + u32 *v; + + if (rdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h /= 2; + } + + s1 = sr->x; t1 = sr->y; + s2 = sr->x+sr->w; t2 = sr->y+sr->h; + if (rdev->blittingflags & DSBLIT_ROTATE180) { + float tmp; + tmp = s2; s2 = s1; s1 = tmp; + tmp = t2; t2 = t1; t1 = tmp; + } + + x1 = dr->x; y1 = dr->y; + x2 = dr->x+dr->w; y2 = dr->y+dr->h; + if (rdev->matrix) { + float X1, Y1, X2, Y2, X3, Y3, X4, Y4; + + RADEON_TRANSFORM( x1, y1, X1, Y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y1, X2, Y2, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, X3, Y3, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x1, y2, X4, Y4, rdev->matrix, rdev->affine_matrix ); + + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_TRIANGLE_LIST, 6, 24 ); + *v++ = f2d(X1); *v++ = f2d(Y1); *v++ = f2d(s1); *v++ = f2d(t1); + *v++ = f2d(X2); *v++ = f2d(Y2); *v++ = f2d(s2); *v++ = f2d(t1); + *v++ = f2d(X3); *v++ = f2d(Y3); *v++ = f2d(s2); *v++ = f2d(t2); + *v++ = f2d(X1); *v++ = f2d(Y1); *v++ = f2d(s1); *v++ = f2d(t1); + *v++ = f2d(X3); *v++ = f2d(Y3); *v++ = f2d(s2); *v++ = f2d(t2); + *v++ = f2d(X4); *v++ = f2d(Y4); *v++ = f2d(s1); *v++ = f2d(t2); + } + else { + v = r100_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 3, 12 ); + *v++ = f2d(x1); *v++ = f2d(y1); *v++ = f2d(s1); *v++ = f2d(t1); + *v++ = f2d(x2); *v++ = f2d(y1); *v++ = f2d(s2); *v++ = f2d(t1); + *v++ = f2d(x2); *v++ = f2d(y2); *v++ = f2d(s2); *v++ = f2d(t2); + } + + return true; +} + +static void +r100DoTextureTriangles( RadeonDriverData *rdrv, RadeonDeviceData *rdev, + DFBVertex *ve, int num, u32 primitive ) +{ + volatile u8 *mmio = rdrv->mmio_base; + int i; + + radeon_waitfifo( rdrv, rdev, 1 ); + + radeon_out32( mmio, SE_VF_CNTL, primitive | + VF_PRIM_WALK_DATA | + VF_RADEON_MODE | + (num << VF_NUM_VERTICES_SHIFT) ); + + for (; num >= 10; num -= 10) { + radeon_waitfifo( rdrv, rdev, 60 ); + for (i = 0; i < 10; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].w) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + } + ve += 10; + } + + if (num > 0) { + radeon_waitfifo( rdrv, rdev, num*6 ); + for (i = 0; i < num; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].w) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + } + } +} + +bool r100TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + u32 prim = 0; + int i; + + if (num > 65535) { + D_WARN( "R100 supports maximum 65535 vertices" ); + return false; + } + + switch (formation) { + case DTTF_LIST: + prim = VF_PRIM_TYPE_TRIANGLE_LIST; + break; + case DTTF_STRIP: + prim = VF_PRIM_TYPE_TRIANGLE_STRIP; + break; + case DTTF_FAN: + prim = VF_PRIM_TYPE_TRIANGLE_FAN; + break; + default: + D_BUG( "unexpected triangle formation" ); + return false; + } + + if (rdev->matrix) { + for (i = 0; i < num; i++) + RADEON_TRANSFORM( ve[i].x, ve[i].y, ve[i].x, ve[i].y, rdev->matrix, rdev->affine_matrix ); + } + + r100DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + bool s420 = DFB_PLANAR_PIXELFORMAT(rdev->src_format); + int i; + + /* Scale coordinates */ + for (i = 0; i < num; i++) { + ve[i].x *= 0.5; + ve[i].y *= 0.5; + } + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, s420 ? 8 : 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch/2 ); + if (s420) { + radeon_out32( mmio, PP_TEX_SIZE_0, ((rdev->src_height/2-1) << 16) | + ((rdev->src_width/2-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_0, rdev->src_pitch/2 - 32 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset_cb ); + } + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2/2 << 16) | + (clip->x2/2 & 0xffff) ); + radeon_out32( mmio, PP_TFACTOR_0, rdev->cb_cop ); + + /* Map Cb plane */ + r100DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, s420 ? 3 : 2 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cr ); + if (s420) + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset_cr ); + radeon_out32( mmio, PP_TFACTOR_0, rdev->cr_cop ); + + /* Map Cr plane */ + r100DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, s420 ? 8 : 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch ); + if (s420) { + radeon_out32( mmio, PP_TEX_SIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset ); + } + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2 << 16) | + (clip->x2 & 0xffff) ); + radeon_out32( mmio, PP_TFACTOR_0, rdev->y_cop ); + } + + return true; +} + +void r100EmitCommands3D( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->vb_count) + r100_flush_vb( rdrv, rdev ); +} diff --git a/Source/DirectFB/gfxdrivers/radeon/r100_state.c b/Source/DirectFB/gfxdrivers/radeon/r100_state.c new file mode 100755 index 0000000..8985733 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r100_state.c @@ -0,0 +1,954 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_state.h" + + +static const u32 r100SrcBlend[] = { + SRC_BLEND_GL_ZERO, // DSBF_ZERO + SRC_BLEND_GL_ONE, // DSBF_ONE + SRC_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + SRC_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + SRC_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + SRC_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + SRC_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + SRC_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + SRC_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + SRC_BLEND_GL_SRC_ALPHA_SATURATE // DSBF_SRCALPHASAT +}; + +static const u32 r100DstBlend[] = { + DST_BLEND_GL_ZERO, // DSBF_ZERO + DST_BLEND_GL_ONE, // DSBF_ONE + DST_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + DST_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + DST_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + DST_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + DST_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + DST_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + DST_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + DST_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + DST_BLEND_GL_ZERO // DSBF_SRCALPHASAT +}; + + +void r100_restore( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 8 ); + /* enable caches */ + radeon_out32( mmio, RB2D_DSTCACHE_MODE, RB2D_DC_2D_CACHE_AUTOFLUSH | + RB2D_DC_3D_CACHE_AUTOFLUSH ); + radeon_out32( mmio, RB3D_DSTCACHE_MODE, RB3D_DC_2D_CACHE_AUTOFLUSH | + RB3D_DC_3D_CACHE_AUTOFLUSH ); + /* restore 3d engine state */ + radeon_out32( mmio, SE_COORD_FMT, VTX_XY_PRE_MULT_1_OVER_W0 | + TEX1_W_ROUTING_USE_W0 ); + radeon_out32( mmio, SE_LINE_WIDTH, 0x10 ); +#ifdef WORDS_BIGENDIAN + radeon_out32( mmio, SE_CNTL_STATUS, TCL_BYPASS | VC_32BIT_SWAP ); +#else + radeon_out32( mmio, SE_CNTL_STATUS, TCL_BYPASS ); +#endif + radeon_out32( mmio, PP_MISC, ALPHA_TEST_PASS ); + radeon_out32( mmio, RB3D_ZSTENCILCNTL, Z_TEST_ALWAYS ); + radeon_out32( mmio, RB3D_ROPCNTL, ROP_XOR ); +} + +void r100_set_destination( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + CoreSurfaceBuffer *buffer = state->dst.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 offset; + u32 pitch; + + if (RADEON_IS_SET( DESTINATION )) + return; + + D_ASSERT( (state->dst.offset % 32) == 0 ); + D_ASSERT( (state->dst.pitch % 32) == 0 ); + + offset = radeon_buffer_offset( rdev, &state->dst ); + pitch = state->dst.pitch; + + if (rdev->dst_offset != offset || + rdev->dst_pitch != pitch || + rdev->dst_format != buffer->format) + { + bool dst_422 = false; + + switch (buffer->format) { + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_A8: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + break; + case DSPF_RGB332: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB332 | DITHER_ENABLE; + break; + case DSPF_ARGB2554: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB565; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB4444 | DITHER_ENABLE; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + rdev->gui_master_cntl = GMC_DST_15BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB1555 | DITHER_ENABLE; + break; + case DSPF_RGB16: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB565 | DITHER_ENABLE; + break; + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + rdev->gui_master_cntl = GMC_DST_32BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB8888; + break; + case DSPF_UYVY: + rdev->gui_master_cntl = GMC_DST_YVYU; + rdev->rb3d_cntl = COLOR_FORMAT_YUV422_YVYU; + dst_422 = true; + break; + case DSPF_YUY2: + rdev->gui_master_cntl = GMC_DST_VYUY; + rdev->rb3d_cntl = COLOR_FORMAT_YUV422_VYUY; + dst_422 = true; + break; + case DSPF_I420: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + rdev->dst_offset_cb = offset + pitch * surface->config.size.h; + rdev->dst_offset_cr = rdev->dst_offset_cb + + pitch/2 * surface->config.size.h/2; + break; + case DSPF_YV12: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + rdev->dst_offset_cr = offset + pitch * surface->config.size.h; + rdev->dst_offset_cb = rdev->dst_offset_cr + + pitch/2 * surface->config.size.h/2; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + rdev->gui_master_cntl |= GMC_DP_SRC_SOURCE_MEMORY | + GMC_WR_MSK_DIS | + GMC_SRC_PITCH_OFFSET_CNTL | + GMC_DST_PITCH_OFFSET_CNTL | + GMC_DST_CLIPPING; + + radeon_waitfifo( rdrv, rdev, 4 ); + radeon_out32( mmio, DST_OFFSET, offset ); + radeon_out32( mmio, DST_PITCH, pitch ); + radeon_out32( mmio, RB3D_COLOROFFSET, offset ); + radeon_out32( mmio, RB3D_COLORPITCH, + pitch / DFB_BYTES_PER_PIXEL(buffer->format) ); + + if (rdev->dst_format != buffer->format) { + if (dst_422 && !rdev->dst_422) { + RADEON_UNSET( SOURCE ); + RADEON_UNSET( CLIP ); + } + + RADEON_UNSET( COLOR ); + RADEON_UNSET( DST_BLEND ); + } + + rdev->dst_format = buffer->format; + rdev->dst_offset = offset; + rdev->dst_pitch = pitch; + rdev->dst_422 = dst_422; + } + + RADEON_SET( DESTINATION ); +} + +void r100_set_source( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + CoreSurfaceBuffer *buffer = state->src.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 txformat = TXFORMAT_NON_POWER2; + u32 txfilter = MAG_FILTER_LINEAR | + MIN_FILTER_LINEAR | + CLAMP_S_CLAMP_LAST | + CLAMP_T_CLAMP_LAST; + + if (RADEON_IS_SET( SOURCE )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (rdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + D_ASSERT( (state->src.offset % 32) == 0 ); + D_ASSERT( (state->src.pitch % 32) == 0 ); + + rdev->src_offset = radeon_buffer_offset( rdev, &state->src ); + rdev->src_pitch = state->src.pitch; + rdev->src_width = surface->config.size.w; + rdev->src_height = surface->config.size.h; + + switch (buffer->format) { + case DSPF_LUT8: + txformat |= TXFORMAT_I8; + txfilter &= ~(MAG_FILTER_LINEAR | + MIN_FILTER_LINEAR); + rdev->src_mask = 0x000000ff; + break; + case DSPF_ALUT44: + txformat |= TXFORMAT_I8; + txfilter &= ~(MAG_FILTER_LINEAR | + MIN_FILTER_LINEAR); + rdev->src_mask = 0x0000000f; + break; + case DSPF_A8: + txformat |= TXFORMAT_I8 | + TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0; + break; + case DSPF_RGB332: + txformat |= TXFORMAT_RGB332; + rdev->src_mask = 0x000000ff; + break; + case DSPF_ARGB2554: + txformat |= TXFORMAT_RGB565; + txfilter &= ~(MAG_FILTER_LINEAR | + MIN_FILTER_LINEAR); + rdev->src_mask = 0x00003fff; + break; + case DSPF_RGB444: + txformat |= TXFORMAT_ARGB4444; + rdev->src_mask = 0x00000fff; + break; + case DSPF_ARGB4444: + txformat |= TXFORMAT_ARGB4444 | + TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00000fff; + break; + case DSPF_RGB555: + txformat |= TXFORMAT_ARGB1555; + rdev->src_mask = 0x00007fff; + break; + case DSPF_ARGB1555: + txformat |= TXFORMAT_ARGB1555 | + TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00007fff; + break; + case DSPF_RGB16: + txformat |= TXFORMAT_RGB565; + rdev->src_mask = 0x0000ffff; + break; + case DSPF_RGB32: + txformat |= TXFORMAT_ARGB8888; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + txformat |= TXFORMAT_ARGB8888 | + TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_UYVY: + txformat |= TXFORMAT_YVYU422; + if (!rdev->dst_422) + txfilter |= YUV_TO_RGB; + rdev->src_mask = 0xffffffff; + break; + case DSPF_YUY2: + txformat |= TXFORMAT_VYUY422; + if (!rdev->dst_422) + txfilter |= YUV_TO_RGB; + rdev->src_mask = 0xffffffff; + break; + case DSPF_I420: + txformat |= TXFORMAT_I8; + rdev->src_offset_cb = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cr = rdev->src_offset_cb + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + case DSPF_YV12: + txformat |= TXFORMAT_I8; + rdev->src_offset_cr = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cb = rdev->src_offset_cr + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + rdev->src_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) { + rdev->src_offset += rdev->src_height * rdev->src_pitch; + rdev->src_offset_cr += rdev->src_height * rdev->src_pitch/4; + rdev->src_offset_cb += rdev->src_height * rdev->src_pitch/4; + } + } else { + if (surface->field) { + rdev->src_offset += rdev->src_pitch; + rdev->src_offset_cr += rdev->src_pitch/2; + rdev->src_offset_cb += rdev->src_pitch/2; + } + rdev->src_pitch *= 2; + } + } + + radeon_waitfifo( rdrv, rdev, 7 ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset ); + radeon_out32( mmio, SRC_PITCH, rdev->src_pitch ); + radeon_out32( mmio, PP_TXFILTER_0, txfilter ); + radeon_out32( mmio, PP_TXFORMAT_0, txformat ); + radeon_out32( mmio, PP_TEX_SIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset ); + + if (rdev->src_format != buffer->format) + RADEON_UNSET( BLITTING_FLAGS ); + rdev->src_format = buffer->format; + + RADEON_SET( SOURCE ); +} + +void r100_set_source_mask( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->source_mask; + CoreSurfaceBuffer *buffer = state->src_mask.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 txformat = TXFORMAT_NON_POWER2; + u32 txfilter = MAG_FILTER_LINEAR | + MIN_FILTER_LINEAR | + CLAMP_S_CLAMP_LAST | + CLAMP_T_CLAMP_LAST; + + if (RADEON_IS_SET( SOURCE_MASK )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (rdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + D_ASSERT( (state->src_mask.offset % 32) == 0 ); + D_ASSERT( (state->src_mask.pitch % 32) == 0 ); + + rdev->msk_format = buffer->format; + rdev->msk_offset = radeon_buffer_offset( rdev, &state->src_mask ); + rdev->msk_pitch = state->src_mask.pitch; + rdev->msk_width = surface->config.size.w; + rdev->msk_height = surface->config.size.h; + + switch (buffer->format) { + case DSPF_A8: + txformat |= TXFORMAT_I8 | + TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB332: + txformat |= TXFORMAT_RGB332; + break; + case DSPF_RGB444: + txformat |= TXFORMAT_ARGB4444; + break; + case DSPF_ARGB4444: + txformat |= TXFORMAT_ARGB4444 | + TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB555: + txformat |= TXFORMAT_ARGB1555; + break; + case DSPF_ARGB1555: + txformat |= TXFORMAT_ARGB1555 | + TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB16: + txformat |= TXFORMAT_RGB565; + break; + case DSPF_RGB32: + txformat |= TXFORMAT_ARGB8888; + break; + case DSPF_ARGB: + case DSPF_AiRGB: + txformat |= TXFORMAT_ARGB8888 | + TXFORMAT_ALPHA_IN_MAP; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + rdev->msk_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) + rdev->msk_offset += rdev->msk_height * rdev->msk_pitch; + } else { + if (surface->field) + rdev->msk_offset += rdev->msk_pitch; + rdev->msk_pitch *= 2; + } + } + + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, PP_TXFILTER_1, txfilter ); + radeon_out32( mmio, PP_TXFORMAT_1, txformat ); + radeon_out32( mmio, PP_TEX_SIZE_1, ((rdev->msk_height-1) << 16) | + ((rdev->msk_width-1) & 0xffff) ); + radeon_out32( mmio, PP_TEX_PITCH_1, rdev->msk_pitch - 32 ); + radeon_out32( mmio, PP_TXOFFSET_1, rdev->msk_offset ); + + RADEON_SET( SOURCE_MASK ); +} + +void r100_set_clip( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBRegion *clip = &state->clip; + volatile u8 *mmio = rdrv->mmio_base; + + if (RADEON_IS_SET( CLIP )) + return; + + /* 2d clip */ + radeon_waitfifo( rdrv, rdev, 2 ); + if (rdev->dst_422) { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1)/2 & 0xffff) ); + } else { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1) & 0xffff) ); + } + + /* 3d clip */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, RE_TOP_LEFT, + (clip->y1 << 16) | (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, + (clip->y2 << 16) | (clip->x2 & 0xffff) ); + + rdev->clip = state->clip; + + RADEON_SET( CLIP ); +} + +#define R100_SET_YUV422_COLOR( rdrv, rdev, y, u, v ) { \ + radeon_out32( (rdrv)->fb_base, (rdev)->yuv422_buffer, \ + PIXEL_YUY2( y, u, v ) ); \ + radeon_in8( (rdrv)->fb_base, (rdev)->yuv422_buffer ); \ + radeon_waitfifo( rdrv, rdev, 3 ); \ + radeon_out32( (rdrv)->mmio_base, PP_TXFILTER_1, 0 ); \ + radeon_out32( (rdrv)->mmio_base, PP_TXFORMAT_1, TXFORMAT_VYUY422 ); \ + radeon_out32( (rdrv)->mmio_base, PP_TXOFFSET_1, \ + (rdev)->fb_offset + (rdev)->yuv422_buffer ); \ +} + +void r100_set_drawing_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + int index = state->color_index; + u32 color2d; + u32 color3d; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = color.r * color.a / 255; + color.g = color.g * color.a / 255; + color.b = color.b * color.a / 255; + } + + color3d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + + switch (rdev->dst_format) { + case DSPF_ALUT44: + index |= (color.a & 0xf0); + case DSPF_LUT8: + color2d = index; + color3d = PIXEL_RGB32( index, index, index ); + break; + case DSPF_A8: + color2d = color.a; + color3d = (color.a << 24) | 0x00ffffff; + break; + case DSPF_RGB332: + color2d = PIXEL_RGB332( color.r, color.g, color.b ); + break; + case DSPF_ARGB2554: + color2d = PIXEL_ARGB2554( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + color2d = PIXEL_ARGB4444( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + color2d = PIXEL_ARGB1555( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB16: + color2d = PIXEL_RGB16( color.r, color.g, color.b ); + break; + case DSPF_RGB32: + color2d = PIXEL_RGB32( color.r, color.g, color.b ); + break; + case DSPF_ARGB: + color2d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AiRGB: + color2d = PIXEL_AiRGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color3d = color2d = PIXEL_AYUV( color.a, y, u, v ); + break; + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_UYVY( y, u, v ); + R100_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_YUY2( y, u, v ); + R100_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + color3d = color2d = rdev->y_cop; + break; + default: + D_BUG( "unexpected pixelformat" ); + color2d = 0; + break; + } + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( rdrv->mmio_base, DP_BRUSH_FRGD_CLR, color2d ); + radeon_out32( rdrv->mmio_base, PP_TFACTOR_1, color3d ); + + RADEON_SET( COLOR ); +} + +void r100_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + u32 color3d; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( BLITTING_FLAGS )) + return; + + if (state->blittingflags & DSBLIT_COLORIZE && + state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + color.r = ((long) color.r * color.a / 255L); + color.g = ((long) color.g * color.a / 255L); + color.b = ((long) color.b * color.a / 255L); + } + + switch (rdev->dst_format) { + case DSPF_A8: + color3d = (color.a << 24) | 0x00ffffff; + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + color3d = rdev->y_cop; + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color3d = PIXEL_AYUV( color.a, y, u, v ); + break; + case DSPF_UYVY: + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + R100_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + default: + color3d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + break; + } + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, PP_TFACTOR_0, color3d ); + + RADEON_SET( COLOR ); +} + +void r100_set_src_colorkey( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + if (RADEON_IS_SET( SRC_COLORKEY )) + return; + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, CLR_CMP_CLR_SRC, state->src_colorkey ); + radeon_out32( mmio, CLR_CMP_MASK, rdev->src_mask ); + + RADEON_SET( SRC_COLORKEY ); +} + +void r100_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 sblend; + u32 dblend; + + if (RADEON_IS_SET( SRC_BLEND ) && RADEON_IS_SET( DST_BLEND )) + return; + + sblend = r100SrcBlend[state->src_blend-1]; + dblend = r100DstBlend[state->dst_blend-1]; + + if (!DFB_PIXELFORMAT_HAS_ALPHA(rdev->dst_format)) { + if (sblend == SRC_BLEND_GL_DST_ALPHA) + sblend = SRC_BLEND_GL_ONE; + else if (sblend == SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) + sblend = SRC_BLEND_GL_ZERO; + + if (dblend == DST_BLEND_GL_DST_ALPHA) + dblend = DST_BLEND_GL_ONE; + else if (dblend == DST_BLEND_GL_ONE_MINUS_DST_ALPHA) + dblend = DST_BLEND_GL_ZERO; + } + else if (rdev->dst_format == DSPF_A8) { + if (sblend == SRC_BLEND_GL_DST_ALPHA) + sblend = SRC_BLEND_GL_DST_COLOR; + else if (sblend == SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) + sblend = SRC_BLEND_GL_ONE_MINUS_DST_COLOR; + + if (dblend == DST_BLEND_GL_DST_ALPHA) + dblend = DST_BLEND_GL_DST_COLOR; + else if (dblend == DST_BLEND_GL_ONE_MINUS_DST_ALPHA) + dblend = DST_BLEND_GL_ONE_MINUS_DST_COLOR; + } + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, RB3D_BLENDCNTL, sblend | dblend ); + + RADEON_SET( SRC_BLEND ); + RADEON_SET( DST_BLEND ); +} + +void r100_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + if (RADEON_IS_SET( RENDER_OPTIONS )) + return; + + if (state->render_options & DSRO_MATRIX && + (!state->affine_matrix || + state->matrix[0] != (1<<16) || state->matrix[1] != 0 || state->matrix[2] != 0 || + state->matrix[3] != 0 || state->matrix[4] != (1<<16) || state->matrix[5] != 0)) { + rdev->matrix = state->matrix; + rdev->affine_matrix = state->affine_matrix; + } + else { + rdev->matrix = NULL; + } + + if ((rdev->render_options & DSRO_ANTIALIAS) != (state->render_options & DSRO_ANTIALIAS)) { + RADEON_UNSET( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); + } + rdev->render_options = state->render_options; + + RADEON_SET( RENDER_OPTIONS ); +} + +/* NOTES: + * - We use texture unit 0 for blitting functions, + * texture unit 1 for drawing functions + * - Default blend equation is ADD_CLAMP (A * B + C) + */ + +void r100_set_drawingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_SRC_DATATYPE_MONO_FG_LA | + GMC_BRUSH_SOLID_COLOR | + GMC_CLR_CMP_CNTL_DIS; + u32 rb3d_cntl = rdev->rb3d_cntl & ~DITHER_ENABLE; + u32 pp_cntl = SCISSOR_ENABLE | TEX_BLEND_1_ENABLE; + u32 cblend = COLOR_ARG_C_TFACTOR_COLOR; + + if (RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (rdev->dst_422) { + pp_cntl |= TEX_1_ENABLE; + cblend = COLOR_ARG_C_T1_COLOR; + } + else if (rdev->dst_format == DSPF_A8) { + cblend = COLOR_ARG_C_TFACTOR_ALPHA; + } + + if (state->drawingflags & DSDRAW_BLEND) + rb3d_cntl |= ALPHA_BLEND_ENABLE; + + if (state->drawingflags & DSDRAW_XOR) { + rb3d_cntl |= ROP_ENABLE; + master_cntl |= GMC_ROP3_PATXOR; + } + else { + master_cntl |= GMC_ROP3_PATCOPY; + } + + if (state->render_options & DSRO_ANTIALIAS) + pp_cntl |= ANTI_ALIAS_LINE_POLY; + + radeon_waitfifo( rdrv, rdev, 8 ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + radeon_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM ); + radeon_out32( mmio, RB3D_CNTL, rb3d_cntl ); + radeon_out32( mmio, SE_CNTL, DIFFUSE_SHADE_FLAT | + ALPHA_SHADE_FLAT | + BFACE_SOLID | + FFACE_SOLID | + VTX_PIX_CENTER_OGL | + ROUND_MODE_ROUND | + ROUND_PREC_4TH_PIX ); + radeon_out32( mmio, PP_CNTL, pp_cntl ); + radeon_out32( mmio, PP_TXCBLEND_1, cblend ); + radeon_out32( mmio, PP_TXABLEND_1, ALPHA_ARG_C_TFACTOR_ALPHA ); + radeon_out32( mmio, SE_VTX_FMT, SE_VTX_FMT_XY ); + + rdev->drawingflags = state->drawingflags; + + RADEON_SET ( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); +} + +void r100_set_blittingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_BRUSH_NONE | + GMC_SRC_DATATYPE_COLOR; + u32 cmp_cntl = 0; + u32 rb3d_cntl = rdev->rb3d_cntl; + u32 se_cntl = BFACE_SOLID | + FFACE_SOLID | + VTX_PIX_CENTER_OGL | + ROUND_MODE_ROUND; + u32 pp_cntl = SCISSOR_ENABLE | + TEX_0_ENABLE | + TEX_BLEND_0_ENABLE; + u32 cblend = COLOR_ARG_C_T0_COLOR; + u32 ablend = ALPHA_ARG_C_T0_ALPHA; + u32 vtx_fmt = SE_VTX_FMT_XY | SE_VTX_FMT_ST0; + u32 coord_fmt = VTX_XY_PRE_MULT_1_OVER_W0 | + TEX1_W_ROUTING_USE_W0; + + if (RADEON_IS_SET( BLITTING_FLAGS )) + return; + + if (rdev->accel == DFXL_TEXTRIANGLES) { + se_cntl |= DIFFUSE_SHADE_GOURAUD | + ALPHA_SHADE_GOURAUD | + SPECULAR_SHADE_GOURAUD | + FLAT_SHADE_VTX_LAST | + ROUND_PREC_8TH_PIX; + vtx_fmt |= SE_VTX_FMT_W0 | SE_VTX_FMT_Z; + } + else { + se_cntl |= DIFFUSE_SHADE_FLAT | + ALPHA_SHADE_FLAT | + ROUND_PREC_4TH_PIX; + coord_fmt |= VTX_ST0_NONPARAMETRIC | + VTX_ST1_NONPARAMETRIC; + } + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + ablend = ALPHA_ARG_A_T0_ALPHA | ALPHA_ARG_B_TFACTOR_ALPHA; + else + ablend = ALPHA_ARG_C_TFACTOR_ALPHA; + } + + rb3d_cntl |= ALPHA_BLEND_ENABLE; + } + + if (rdev->dst_format != DSPF_A8) { + if (state->blittingflags & (DSBLIT_SRC_MASK_ALPHA | DSBLIT_SRC_MASK_COLOR)) { + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) + ablend = ALPHA_ARG_A_T0_ALPHA | ALPHA_ARG_B_T1_ALPHA; + + if (state->blittingflags & DSBLIT_SRC_MASK_COLOR) + cblend = COLOR_ARG_A_T0_COLOR | COLOR_ARG_B_T1_COLOR; + + pp_cntl |= TEX_1_ENABLE; + } + else if (state->blittingflags & DSBLIT_COLORIZE) { + if (rdev->dst_422) { + cblend = (rdev->src_format == DSPF_A8) + ? (COLOR_ARG_C_T1_COLOR) + : (COLOR_ARG_A_T0_COLOR | COLOR_ARG_B_T1_COLOR); + + pp_cntl |= TEX_1_ENABLE; + } + else { + cblend = (rdev->src_format == DSPF_A8) + ? (COLOR_ARG_C_TFACTOR_COLOR) + : (COLOR_ARG_A_T0_COLOR | COLOR_ARG_B_TFACTOR_COLOR); + } + } + else if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + cblend = (rdev->src_format == DSPF_A8) + ? (COLOR_ARG_C_T0_ALPHA) + : (COLOR_ARG_A_T0_COLOR | COLOR_ARG_B_TFACTOR_ALPHA); + } + else if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) { + cblend = (rdev->src_format == DSPF_A8) + ? (COLOR_ARG_C_T0_ALPHA) + : (COLOR_ARG_A_T0_COLOR | COLOR_ARG_B_T0_ALPHA); + } + } /* DSPF_A8 */ + else { + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) { + ablend = ALPHA_ARG_A_T0_ALPHA | ALPHA_ARG_B_T1_ALPHA; + cblend = COLOR_ARG_A_T0_ALPHA | COLOR_ARG_B_T1_ALPHA; + pp_cntl |= TEX_1_ENABLE; + } + else if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + cblend = COLOR_ARG_A_T0_ALPHA | COLOR_ARG_B_TFACTOR_ALPHA; + else + cblend = COLOR_ARG_C_TFACTOR_ALPHA; + } + else { + cblend = COLOR_ARG_C_T0_ALPHA; + } + } + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + cmp_cntl = SRC_CMP_EQ_COLOR | CLR_CMP_SRC_SOURCE; + else + master_cntl |= GMC_CLR_CMP_CNTL_DIS; + + if (state->blittingflags & DSBLIT_XOR) { + master_cntl |= GMC_ROP3_XOR; + rb3d_cntl |= ROP_ENABLE; + } + else { + master_cntl |= GMC_ROP3_SRCCOPY; + } + + if (state->render_options & DSRO_ANTIALIAS) + pp_cntl |= ANTI_ALIAS_POLY; + + radeon_waitfifo( rdrv, rdev, 9 ); + radeon_out32( mmio, CLR_CMP_CNTL, cmp_cntl ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + radeon_out32( mmio, RB3D_CNTL, rb3d_cntl ); + radeon_out32( mmio, SE_CNTL, se_cntl ); + radeon_out32( mmio, PP_CNTL, pp_cntl ); + radeon_out32( mmio, PP_TXCBLEND_0, cblend ); + radeon_out32( mmio, PP_TXABLEND_0, ablend ); + radeon_out32( mmio, SE_VTX_FMT, vtx_fmt ); + radeon_out32( mmio, SE_COORD_FMT, coord_fmt ); + + rdev->blittingflags = state->blittingflags; + + RADEON_SET ( BLITTING_FLAGS ); + RADEON_UNSET( DRAWING_FLAGS ); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/r200_3d.c b/Source/DirectFB/gfxdrivers/radeon/r200_3d.c new file mode 100755 index 0000000..2521c68 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r200_3d.c @@ -0,0 +1,508 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_3d.h" + + +#define EMIT_VERTICES( rdrv, rdev, mmio ) { \ + u32 *_v = (rdev)->vb; \ + u32 _s = (rdev)->vb_size; \ + radeon_waitfifo( rdrv, rdev, 1 ); \ + radeon_out32( mmio, SE_VF_CNTL, rdev->vb_type | VF_PRIM_WALK_DATA | \ + (rdev->vb_count << VF_NUM_VERTICES_SHIFT) ); \ + do { \ + u32 _n = MIN(_s, 64); \ + _s -= _n; \ + radeon_waitfifo( rdrv, rdev, _n ); \ + while (_n--) \ + radeon_out32( mmio, SE_PORT_DATA0, *_v++ ); \ + } while (_s); \ +} + +static void +r200_flush_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + EMIT_VERTICES( rdrv, rdev, mmio ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + DFBRegion *clip = &rdev->clip; + bool s420 = DFB_PLANAR_PIXELFORMAT(rdev->src_format); + int i; + + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + for (i = 0; i < rdev->vb_size; i += 4) { + rdev->vb[i+0] = f2d(d2f(rdev->vb[i+0])*0.5f); + rdev->vb[i+1] = f2d(d2f(rdev->vb[i+1])*0.5f); + if (s420) { + rdev->vb[i+2] = f2d(d2f(rdev->vb[i+2])*0.5f); + rdev->vb[i+3] = f2d(d2f(rdev->vb[i+3])*0.5f); + } + } + } else { + for (i = 0; i < rdev->vb_size; i += 2) { + rdev->vb[i+0] = f2d(d2f(rdev->vb[i+0])*0.5f); + rdev->vb[i+1] = f2d(d2f(rdev->vb[i+1])*0.5f); + } + } + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2/2 << 16) | + (clip->x2/2 & 0xffff) ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->cb_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, R200_PP_TXSIZE_0, ((rdev->src_height/2-1) << 16) | + ((rdev->src_width/2-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_0, rdev->src_pitch/2 - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset_cb ); + } + } else { + radeon_out32( mmio, R200_PP_TFACTOR_1, rdev->cb_cop ); + } + + /* Fill Cb plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cr ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->cr_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset_cr ); + } + } else { + radeon_out32( mmio, R200_PP_TFACTOR_1, rdev->cr_cop ); + } + + /* Fill Cr plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch ); + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2 << 16) | + (clip->x2 & 0xffff) ); + if (DFB_BLITTING_FUNCTION(rdev->accel)) { + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->y_cop ); + if (s420) { + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, R200_PP_TXSIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset ); + } + } else { + radeon_out32( mmio, R200_PP_TFACTOR_1, rdev->y_cop ); + } + } + + rdev->vb_size = 0; + rdev->vb_count = 0; +} + +static inline u32* +r200_init_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev, u32 type, u32 count, u32 size ) +{ + u32 *vb; + + if ((rdev->vb_size && rdev->vb_type != type) || + rdev->vb_size+size > D_ARRAY_SIZE(rdev->vb)) + r200_flush_vb( rdrv, rdev ); + + vb = &rdev->vb[rdev->vb_size]; + rdev->vb_type = type; + rdev->vb_size += size; + rdev->vb_count += count; + + return vb; +} + + +bool r200FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + if (rect->w == 1 && rect->h == 1) { + x1 = rect->x+1; y1 = rect->y+1; + if (rdev->matrix) + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_POINT_LIST, 1, 2 ); + *v++ = f2d(x1); *v++ = f2d(y1); + + return true; + } + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float x, y; + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 8 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + } + else { + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 3, 6 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + } + + return true; +} + +bool r200FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float x3, y3; + u32 *v; + + x1 = tri->x1; y1 = tri->y1; + x2 = tri->x2; y2 = tri->y2; + x3 = tri->x3; y3 = tri->y3; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x3, y3, x3, y3, rdev->matrix, rdev->affine_matrix ); + } + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_TRIANGLE_LIST, 3, 6 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + *v++ = f2d(x3); *v++ = f2d(y3); + + return true; +} + +bool r200DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float x, y; + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LOOP, 4, 8 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); + } + else { + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 12, 24 ); + /* top line */ + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y1+1); + /* right line */ + *v++ = f2d(x2-1); *v++ = f2d(y1+1); + *v++ = f2d(x2); *v++ = f2d(y1+1); + *v++ = f2d(x2); *v++ = f2d(y2-1); + /* bottom line */ + *v++ = f2d(x1); *v++ = f2d(y2-1); + *v++ = f2d(x2); *v++ = f2d(y2-1); + *v++ = f2d(x2); *v++ = f2d(y2); + /* left line */ + *v++ = f2d(x1); *v++ = f2d(y1+1); + *v++ = f2d(x1+1); *v++ = f2d(y1+1); + *v++ = f2d(x1+1); *v++ = f2d(y2-1); + } + + return true; +} + +bool r200DrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = line->x1; y1 = line->y1; + x2 = line->x2; y2 = line->y2; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + } + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LIST, 2, 4 ); + *v++ = f2d(x1); *v++ = f2d(y1); + *v++ = f2d(x2); *v++ = f2d(y2); + + return true; +} + +bool r200Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ) +{ + DFBRectangle dr = { dx, dy, sr->w, sr->h }; + + return r200StretchBlit( drv, dev, sr, &dr ); +} + +bool r200StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float s1, t1; + float s2, t2; + u32 *v; + + if (rdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h /= 2; + } + + s1 = sr->x; t1 = sr->y; + s2 = sr->x+sr->w; t2 = sr->y+sr->h; + if (rdev->blittingflags & DSBLIT_ROTATE180) { + float tmp; + tmp = s2; s2 = s1; s1 = tmp; + tmp = t2; t2 = t1; t1 = tmp; + } + + x1 = dr->x; y1 = dr->y; + x2 = dr->x+dr->w; y2 = dr->y+dr->h; + if (rdev->matrix) { + float x, y; + + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 16 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); *v++ = f2d(s1); *v++ = f2d(t1); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); *v++ = f2d(s2); *v++ = f2d(t1); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); *v++ = f2d(s2); *v++ = f2d(t2); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + *v++ = f2d(x); *v++ = f2d(y); *v++ = f2d(s1); *v++ = f2d(t2); + } + else { + v = r200_init_vb( rdrv, rdev, VF_PRIM_TYPE_RECTANGLE_LIST, 3, 12 ); + *v++ = f2d(x1); *v++ = f2d(y1); *v++ = f2d(s1); *v++ = f2d(t1); + *v++ = f2d(x2); *v++ = f2d(y1); *v++ = f2d(s2); *v++ = f2d(t1); + *v++ = f2d(x2); *v++ = f2d(y2); *v++ = f2d(s2); *v++ = f2d(t2); + } + + return true; +} + +static void +r200DoTextureTriangles( RadeonDriverData *rdrv, RadeonDeviceData *rdev, + DFBVertex *ve, int num, u32 primitive ) +{ + volatile u8 *mmio = rdrv->mmio_base; + int i; + + radeon_waitfifo( rdrv, rdev, 1 ); + + radeon_out32( mmio, SE_VF_CNTL, primitive | VF_PRIM_WALK_DATA | + (num << VF_NUM_VERTICES_SHIFT) ); + + for (; num >= 10; num -= 10) { + radeon_waitfifo( rdrv, rdev, 60 ); + for (i = 0; i < 10; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].w) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + } + ve += 10; + } + + if (num > 0) { + radeon_waitfifo( rdrv, rdev, num*6 ); + for (i = 0; i < num; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].w) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + } + } +} + +bool r200TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + u32 prim = 0; + int i; + + if (num > 65535) { + D_WARN( "R200 supports maximum 65535 vertices" ); + return false; + } + + switch (formation) { + case DTTF_LIST: + prim = VF_PRIM_TYPE_TRIANGLE_LIST; + break; + case DTTF_STRIP: + prim = VF_PRIM_TYPE_TRIANGLE_STRIP; + break; + case DTTF_FAN: + prim = VF_PRIM_TYPE_TRIANGLE_FAN; + break; + default: + D_BUG( "unexpected triangle formation" ); + return false; + } + + if (rdev->matrix) { + for (i = 0; i < num; i++) + RADEON_TRANSFORM( ve[i].x, ve[i].y, ve[i].x, ve[i].y, rdev->matrix, rdev->affine_matrix ); + } + + r200DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + bool s420 = DFB_PLANAR_PIXELFORMAT(rdev->src_format); + + /* Scale coordinates */ + for (i = 0; i < num; i++) { + ve[i].x *= 0.5; + ve[i].y *= 0.5; + } + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, s420 ? 8 : 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch/2 ); + if (s420) { + radeon_out32( mmio, R200_PP_TXSIZE_0, ((rdev->src_height/2-1) << 16) | + ((rdev->src_width/2-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_0, rdev->src_pitch/2 - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset_cb ); + } + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2/2 << 16) | + (clip->x2/2 & 0xffff) ); + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->cb_cop ); + + /* Map Cb plane */ + r200DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, s420 ? 3 : 2 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset_cr ); + if (s420) + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset_cr ); + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->cr_cop ); + + /* Map Cr plane */ + r200DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, s420 ? 8 : 5 ); + radeon_out32( mmio, RB3D_COLOROFFSET, rdev->dst_offset ); + radeon_out32( mmio, RB3D_COLORPITCH, rdev->dst_pitch ); + if (s420) { + radeon_out32( mmio, R200_PP_TXSIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset ); + } + radeon_out32( mmio, RE_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, (clip->y2 << 16) | + (clip->x2 & 0xffff) ); + radeon_out32( mmio, R200_PP_TFACTOR_0, rdev->y_cop ); + } + + return true; +} + +void r200EmitCommands3D( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->vb_count) + r200_flush_vb( rdrv, rdev ); +} diff --git a/Source/DirectFB/gfxdrivers/radeon/r200_state.c b/Source/DirectFB/gfxdrivers/radeon/r200_state.c new file mode 100755 index 0000000..c3bf768 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r200_state.c @@ -0,0 +1,985 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_state.h" + + +static const u32 r200SrcBlend[] = { + SRC_BLEND_GL_ZERO, // DSBF_ZERO + SRC_BLEND_GL_ONE, // DSBF_ONE + SRC_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + SRC_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + SRC_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + SRC_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + SRC_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + SRC_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + SRC_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + SRC_BLEND_GL_SRC_ALPHA_SATURATE // DSBF_SRCALPHASAT +}; + +static const u32 r200DstBlend[] = { + DST_BLEND_GL_ZERO, // DSBF_ZERO + DST_BLEND_GL_ONE, // DSBF_ONE + DST_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + DST_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + DST_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + DST_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + DST_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + DST_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + DST_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + DST_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + DST_BLEND_GL_ZERO // DSBF_SRCALPHASAT +}; + + +void r200_restore( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 15 ); + /* enable caches */ + radeon_out32( mmio, RB2D_DSTCACHE_MODE, RB2D_DC_2D_CACHE_AUTOFLUSH | + RB2D_DC_3D_CACHE_AUTOFLUSH | + R200_RB2D_DC_2D_CACHE_AUTOFREE | + R200_RB2D_DC_3D_CACHE_AUTOFREE ); + radeon_out32( mmio, RB3D_DSTCACHE_MODE, RB3D_DC_2D_CACHE_AUTOFLUSH | + RB3D_DC_3D_CACHE_AUTOFLUSH | + R200_RB3D_DC_2D_CACHE_AUTOFREE | + R200_RB3D_DC_3D_CACHE_AUTOFREE ); + /* restore 3d engine state */ + radeon_out32( mmio, SE_LINE_WIDTH, 0x10 ); + radeon_out32( mmio, RE_POINTSIZE, 0x10 ); + radeon_out32( mmio, PP_MISC, ALPHA_TEST_PASS ); + radeon_out32( mmio, R200_PP_CNTL_X, 0 ); + radeon_out32( mmio, R200_PP_TXMULTI_CTL_0, 0 ); + radeon_out32( mmio, R200_RE_CNTL, R200_SCISSOR_ENABLE ); + radeon_out32( mmio, R200_SE_VTX_STATE_CNTL, 0 ); + radeon_out32( mmio, R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM | + R200_VAP_FORCE_W_TO_ONE ); +#ifdef WORDS_BIGENDIAN + radeon_out32( mmio, R200_SE_VAP_CNTL_STATUS, R200_TCL_BYPASS | R200_VC_32BIT_SWAP ); +#else + radeon_out32( mmio, R200_SE_VAP_CNTL_STATUS, R200_TCL_BYPASS ); +#endif + radeon_out32( mmio, RB3D_ZSTENCILCNTL, Z_TEST_ALWAYS ); + radeon_out32( mmio, RB3D_ROPCNTL, ROP_XOR ); + radeon_out32( mmio, R200_PP_TXFORMAT_X_0, 0 ); + radeon_out32( mmio, R200_PP_TXFORMAT_X_1, 0 ); +} + +void r200_set_destination( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + CoreSurfaceBuffer *buffer = state->dst.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 offset; + u32 pitch; + + if (RADEON_IS_SET( DESTINATION )) + return; + + D_ASSERT( (state->dst.offset % 32) == 0 ); + D_ASSERT( (state->dst.pitch % 32) == 0 ); + + offset = radeon_buffer_offset( rdev, &state->dst ); + pitch = state->dst.pitch; + + if (rdev->dst_offset != offset || + rdev->dst_pitch != pitch || + rdev->dst_format != buffer->format) + { + bool dst_422 = false; + + switch (buffer->format) { + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_A8: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + break; + case DSPF_RGB332: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB332 | DITHER_ENABLE; + break; + case DSPF_ARGB2554: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB565; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB4444 | DITHER_ENABLE; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + rdev->gui_master_cntl = GMC_DST_15BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB1555 | DITHER_ENABLE; + break; + case DSPF_RGB16: + rdev->gui_master_cntl = GMC_DST_16BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB565 | DITHER_ENABLE; + break; + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + rdev->gui_master_cntl = GMC_DST_32BPP; + rdev->rb3d_cntl = COLOR_FORMAT_ARGB8888; + break; + case DSPF_UYVY: + rdev->gui_master_cntl = GMC_DST_YVYU; + rdev->rb3d_cntl = COLOR_FORMAT_YUV422_YVYU; + dst_422 = true; + break; + case DSPF_YUY2: + rdev->gui_master_cntl = GMC_DST_VYUY; + rdev->rb3d_cntl = COLOR_FORMAT_YUV422_VYUY; + dst_422 = true; + break; + case DSPF_I420: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + rdev->dst_offset_cb = offset + pitch * surface->config.size.h; + rdev->dst_offset_cr = rdev->dst_offset_cb + + pitch/2 * surface->config.size.h/2; + break; + case DSPF_YV12: + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->rb3d_cntl = COLOR_FORMAT_RGB8; + rdev->dst_offset_cr = offset + pitch * surface->config.size.h; + rdev->dst_offset_cb = rdev->dst_offset_cr + + pitch/2 * surface->config.size.h/2; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + rdev->gui_master_cntl |= GMC_DP_SRC_SOURCE_MEMORY | + GMC_WR_MSK_DIS | + GMC_SRC_PITCH_OFFSET_CNTL | + GMC_DST_PITCH_OFFSET_CNTL | + GMC_DST_CLIPPING; + + radeon_waitfifo( rdrv, rdev, 4 ); + radeon_out32( mmio, DST_OFFSET, offset ); + radeon_out32( mmio, DST_PITCH, pitch ); + radeon_out32( mmio, RB3D_COLOROFFSET, offset ); + radeon_out32( mmio, RB3D_COLORPITCH, + pitch / DFB_BYTES_PER_PIXEL(buffer->format) ); + + if (rdev->dst_format != buffer->format) { + if (dst_422 && !rdev->dst_422) { + RADEON_UNSET( SOURCE ); + RADEON_UNSET( CLIP ); + } + + RADEON_UNSET( COLOR ); + RADEON_UNSET( DST_BLEND ); + } + + rdev->dst_format = buffer->format; + rdev->dst_offset = offset; + rdev->dst_pitch = pitch; + rdev->dst_422 = dst_422; + } + + RADEON_SET( DESTINATION ); +} + +void r200_set_source( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + CoreSurfaceBuffer *buffer = state->src.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 txformat = R200_TXFORMAT_NON_POWER2; + u32 txfilter = R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR | + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST; + + if (RADEON_IS_SET( SOURCE )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (rdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + D_ASSERT( (state->src.offset % 32) == 0 ); + D_ASSERT( (state->src.pitch % 32) == 0 ); + + rdev->src_offset = radeon_buffer_offset( rdev, &state->src ); + rdev->src_pitch = state->src.pitch; + rdev->src_width = surface->config.size.w; + rdev->src_height = surface->config.size.h; + + switch (buffer->format) { + case DSPF_LUT8: + txformat |= R200_TXFORMAT_I8; + txfilter &= ~(R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR); + rdev->src_mask = 0x000000ff; + break; + case DSPF_ALUT44: + txformat |= R200_TXFORMAT_I8; + txfilter &= ~(R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR); + rdev->src_mask = 0x0000000f; + break; + case DSPF_A8: + txformat |= R200_TXFORMAT_I8 | + R200_TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0; + break; + case DSPF_RGB332: + txformat |= R200_TXFORMAT_RGB332; + rdev->src_mask = 0x000000ff; + break; + case DSPF_ARGB2554: + txformat |= R200_TXFORMAT_RGB565; + txfilter &= ~(R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR); + rdev->src_mask = 0x00003fff; + break; + case DSPF_RGB444: + txformat |= R200_TXFORMAT_ARGB4444; + rdev->src_mask = 0x00000fff; + break; + case DSPF_ARGB4444: + txformat |= R200_TXFORMAT_ARGB4444 | + R200_TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00000fff; + break; + case DSPF_RGB555: + txformat |= R200_TXFORMAT_ARGB1555; + rdev->src_mask = 0x00007fff; + break; + case DSPF_ARGB1555: + txformat |= R200_TXFORMAT_ARGB1555 | + R200_TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00007fff; + break; + case DSPF_RGB16: + txformat |= R200_TXFORMAT_RGB565; + rdev->src_mask = 0x0000ffff; + break; + case DSPF_RGB32: + txformat |= R200_TXFORMAT_ARGB8888; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + txformat |= R200_TXFORMAT_ARGB8888 | + R200_TXFORMAT_ALPHA_IN_MAP; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_UYVY: + txformat |= R200_TXFORMAT_YVYU422; + if (!rdev->dst_422) + txfilter |= R200_YUV_TO_RGB; + rdev->src_mask = 0xffffffff; + break; + case DSPF_YUY2: + txformat |= R200_TXFORMAT_VYUY422; + if (!rdev->dst_422) + txfilter |= R200_YUV_TO_RGB; + rdev->src_mask = 0xffffffff; + break; + case DSPF_I420: + txformat |= R200_TXFORMAT_I8; + rdev->src_offset_cb = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cr = rdev->src_offset_cb + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + case DSPF_YV12: + txformat |= R200_TXFORMAT_I8; + rdev->src_offset_cr = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cb = rdev->src_offset_cr + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + rdev->src_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) { + rdev->src_offset += rdev->src_height * rdev->src_pitch; + rdev->src_offset_cr += rdev->src_height * rdev->src_pitch/4; + rdev->src_offset_cb += rdev->src_height * rdev->src_pitch/4; + } + } else { + if (surface->field) { + rdev->src_offset += rdev->src_pitch; + rdev->src_offset_cr += rdev->src_pitch/2; + rdev->src_offset_cb += rdev->src_pitch/2; + } + rdev->src_pitch *= 2; + } + } + + radeon_waitfifo( rdrv, rdev, 7 ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset ); + radeon_out32( mmio, SRC_PITCH, rdev->src_pitch ); + radeon_out32( mmio, R200_PP_TXFILTER_0, txfilter ); + radeon_out32( mmio, R200_PP_TXFORMAT_0, txformat ); + radeon_out32( mmio, R200_PP_TXSIZE_0, ((rdev->src_height-1) << 16) | + ((rdev->src_width-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_0, rdev->src_pitch - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset ); + + if (rdev->src_format != buffer->format) + RADEON_UNSET( BLITTING_FLAGS ); + rdev->src_format = buffer->format; + + RADEON_SET( SOURCE ); +} + +void r200_set_source_mask( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->source_mask; + CoreSurfaceBuffer *buffer = state->src_mask.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 txformat = R200_TXFORMAT_NON_POWER2; + u32 txfilter = R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR | + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST; + + if (RADEON_IS_SET( SOURCE_MASK )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (rdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + D_ASSERT( (state->src_mask.offset % 32) == 0 ); + D_ASSERT( (state->src_mask.pitch % 32) == 0 ); + + rdev->msk_format = buffer->format; + rdev->msk_offset = radeon_buffer_offset( rdev, &state->src_mask ); + rdev->msk_pitch = state->src_mask.pitch; + rdev->msk_width = surface->config.size.w; + rdev->msk_height = surface->config.size.h; + + switch (buffer->format) { + case DSPF_A8: + txformat |= R200_TXFORMAT_I8 | + R200_TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB332: + txformat |= R200_TXFORMAT_RGB332; + break; + case DSPF_RGB444: + txformat |= R200_TXFORMAT_ARGB4444; + break; + case DSPF_ARGB4444: + txformat |= R200_TXFORMAT_ARGB4444 | + R200_TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB555: + txformat |= R200_TXFORMAT_ARGB1555; + break; + case DSPF_ARGB1555: + txformat |= R200_TXFORMAT_ARGB1555 | + R200_TXFORMAT_ALPHA_IN_MAP; + break; + case DSPF_RGB16: + txformat |= R200_TXFORMAT_RGB565; + break; + case DSPF_RGB32: + txformat |= R200_TXFORMAT_ARGB8888; + break; + case DSPF_ARGB: + case DSPF_AiRGB: + txformat |= R200_TXFORMAT_ARGB8888 | + R200_TXFORMAT_ALPHA_IN_MAP; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + rdev->msk_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) + rdev->msk_offset += rdev->msk_height * rdev->msk_pitch; + } else { + if (surface->field) + rdev->msk_offset += rdev->msk_pitch; + rdev->msk_pitch *= 2; + } + } + + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R200_PP_TXFILTER_1, txfilter ); + radeon_out32( mmio, R200_PP_TXFORMAT_1, txformat ); + radeon_out32( mmio, R200_PP_TXSIZE_1, ((rdev->msk_height-1) << 16) | + ((rdev->msk_width-1) & 0xffff) ); + radeon_out32( mmio, R200_PP_TXPITCH_1, rdev->msk_pitch - 32 ); + radeon_out32( mmio, R200_PP_TXOFFSET_1, rdev->msk_offset ); + + RADEON_SET( SOURCE_MASK ); +} + +void r200_set_clip( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBRegion *clip = &state->clip; + volatile u8 *mmio = rdrv->mmio_base; + + if (RADEON_IS_SET( CLIP )) + return; + + /* 2d clip */ + radeon_waitfifo( rdrv, rdev, 2 ); + if (rdev->dst_422) { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1)/2 & 0xffff) ); + } else { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1) & 0xffff) ); + } + + /* 3d clip */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, RE_TOP_LEFT, + (clip->y1 << 16) | (clip->x1 & 0xffff) ); + radeon_out32( mmio, RE_BOTTOM_RIGHT, + (clip->y2 << 16) | (clip->x2 & 0xffff) ); + + rdev->clip = state->clip; + + RADEON_SET( CLIP ); +} + +#define R200_SET_YUV422_COLOR( rdrv, rdev, y, u, v ) { \ + radeon_out32( (rdrv)->fb_base, (rdev)->yuv422_buffer, \ + PIXEL_YUY2( y, u, v ) ); \ + radeon_in8( (rdrv)->fb_base, (rdev)->yuv422_buffer ); \ + radeon_waitfifo( rdrv, rdev, 3 ); \ + radeon_out32( (rdrv)->mmio_base, R200_PP_TXOFFSET_1, \ + (rdev)->fb_offset + (rdev)->yuv422_buffer ); \ + radeon_out32( (rdrv)->mmio_base, R200_PP_TXFORMAT_1, \ + R200_TXFORMAT_VYUY422 ); \ + radeon_out32( (rdrv)->mmio_base, R200_PP_TXFILTER_1, 0 ); \ +} + +void r200_set_drawing_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + int index = state->color_index; + u32 color2d; + u32 color3d; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = ((long) color.r * color.a / 255L); + color.g = ((long) color.g * color.a / 255L); + color.b = ((long) color.b * color.a / 255L); + } + + color3d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + + switch (rdev->dst_format) { + case DSPF_ALUT44: + index |= (color.a & 0xf0); + case DSPF_LUT8: + color2d = index; + color3d = PIXEL_RGB32( index, index, index ); + break; + case DSPF_A8: + color2d = color.a; + color3d = (color.a << 24) | 0x00ffffff; + break; + case DSPF_RGB332: + color2d = PIXEL_RGB332( color.r, color.g, color.b ); + break; + case DSPF_ARGB2554: + color2d = PIXEL_ARGB2554( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + color2d = PIXEL_ARGB4444( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + color2d = PIXEL_ARGB1555( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB16: + color2d = PIXEL_RGB16( color.r, color.g, color.b ); + break; + case DSPF_RGB32: + color2d = PIXEL_RGB32( color.r, color.g, color.b ); + break; + case DSPF_ARGB: + color2d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AiRGB: + color2d = PIXEL_AiRGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color3d = color2d = PIXEL_AYUV( color.a, y, u, v ); + break; + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_UYVY( y, u, v ); + R200_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_YUY2( y, u, v ); + R200_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + color3d = color2d = rdev->y_cop; + break; + default: + D_BUG( "unexpected pixelformat" ); + color2d = 0; + break; + } + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( rdrv->mmio_base, DP_BRUSH_FRGD_CLR, color2d ); + radeon_out32( rdrv->mmio_base, R200_PP_TFACTOR_1, color3d ); + + RADEON_SET( COLOR ); +} + +void r200_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + u32 color3d; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( BLITTING_FLAGS )) + return; + + if (state->blittingflags & DSBLIT_COLORIZE && + state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + color.r = color.r * color.a / 255; + color.g = color.g * color.a / 255; + color.b = color.b * color.a / 255; + } + + switch (rdev->dst_format) { + case DSPF_A8: + color3d = (color.a << 24) | 0x00ffffff; + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + color3d = rdev->y_cop; + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color3d = PIXEL_AYUV( color.a, y, u, v ); + break; + case DSPF_UYVY: + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + R200_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + default: + color3d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + break; + } + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, R200_PP_TFACTOR_0, color3d ); + + RADEON_SET( COLOR ); +} + +void r200_set_src_colorkey( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + if (RADEON_IS_SET( SRC_COLORKEY )) + return; + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, CLR_CMP_CLR_SRC, state->src_colorkey ); + radeon_out32( mmio, CLR_CMP_MASK, rdev->src_mask ); + + RADEON_SET( SRC_COLORKEY ); +} + +void r200_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 sblend; + u32 dblend; + + if (RADEON_IS_SET( SRC_BLEND ) && RADEON_IS_SET( DST_BLEND )) + return; + + sblend = r200SrcBlend[state->src_blend-1]; + dblend = r200DstBlend[state->dst_blend-1]; + + if (!DFB_PIXELFORMAT_HAS_ALPHA(rdev->dst_format)) { + if (sblend == SRC_BLEND_GL_DST_ALPHA) + sblend = SRC_BLEND_GL_ONE; + else if (sblend == SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) + sblend = SRC_BLEND_GL_ZERO; + + if (dblend == DST_BLEND_GL_DST_ALPHA) + dblend = DST_BLEND_GL_ONE; + else if (dblend == DST_BLEND_GL_ONE_MINUS_DST_ALPHA) + dblend = DST_BLEND_GL_ZERO; + } + else if (rdev->dst_format == DSPF_A8) { + if (sblend == SRC_BLEND_GL_DST_ALPHA) + sblend = SRC_BLEND_GL_DST_COLOR; + else if (sblend == SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) + sblend = SRC_BLEND_GL_ONE_MINUS_DST_COLOR; + + if (dblend == DST_BLEND_GL_DST_ALPHA) + dblend = DST_BLEND_GL_DST_COLOR; + else if (dblend == DST_BLEND_GL_ONE_MINUS_DST_ALPHA) + dblend = DST_BLEND_GL_ONE_MINUS_DST_COLOR; + } + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, RB3D_BLENDCNTL, sblend | dblend ); + + RADEON_SET( SRC_BLEND ); + RADEON_SET( DST_BLEND ); +} + +void r200_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + if (RADEON_IS_SET( RENDER_OPTIONS )) + return; + + if (state->render_options & DSRO_MATRIX && + (!state->affine_matrix || + state->matrix[0] != (1<<16) || state->matrix[1] != 0 || state->matrix[2] != 0 || + state->matrix[3] != 0 || state->matrix[4] != (1<<16) || state->matrix[5] != 0)) { + rdev->matrix = state->matrix; + rdev->affine_matrix = state->affine_matrix; + } + else { + rdev->matrix = NULL; + } + + if ((rdev->render_options & DSRO_ANTIALIAS) != (state->render_options & DSRO_ANTIALIAS)) { + RADEON_UNSET( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); + } + rdev->render_options = state->render_options; + + RADEON_SET( RENDER_OPTIONS ); +} + +/* NOTES: + * - We use texture unit 0 for blitting functions, + * texture unit 1 for drawing functions + * - Default blend equation is ADD_CLAMP (A * B + C) + */ + +void r200_set_drawingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_SRC_DATATYPE_MONO_FG_LA | + GMC_BRUSH_SOLID_COLOR | + GMC_CLR_CMP_CNTL_DIS; + u32 rb3d_cntl = rdev->rb3d_cntl & ~DITHER_ENABLE; + u32 pp_cntl = TEX_BLEND_1_ENABLE; + u32 cblend = R200_TXC_ARG_C_TFACTOR_COLOR; + + if (RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (rdev->dst_422) { + pp_cntl |= TEX_1_ENABLE; + cblend = R200_TXC_ARG_C_R1_COLOR; + } + else if (rdev->dst_format == DSPF_A8) { + cblend = R200_TXC_ARG_C_TFACTOR_ALPHA; + } + + if (state->drawingflags & DSDRAW_BLEND) + rb3d_cntl |= ALPHA_BLEND_ENABLE; + + if (state->drawingflags & DSDRAW_XOR) { + rb3d_cntl |= ROP_ENABLE; + master_cntl |= GMC_ROP3_PATXOR; + } + else { + master_cntl |= GMC_ROP3_PATCOPY; + } + + if (state->render_options & DSRO_ANTIALIAS) + pp_cntl |= ANTI_ALIAS_LINE_POLY; + + radeon_waitfifo( rdrv, rdev, 11 ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + radeon_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM ); + radeon_out32( mmio, RB3D_CNTL, rb3d_cntl ); + radeon_out32( mmio, SE_CNTL, DIFFUSE_SHADE_FLAT | + ALPHA_SHADE_FLAT | + BFACE_SOLID | + FFACE_SOLID | + VTX_PIX_CENTER_OGL | + ROUND_MODE_ROUND | + ROUND_PREC_4TH_PIX ); + radeon_out32( mmio, PP_CNTL, pp_cntl ); + radeon_out32( mmio, R200_PP_TXCBLEND_1, cblend ); + radeon_out32( mmio, R200_PP_TXCBLEND2_1, (1 << R200_TXC_TFACTOR_SEL_SHIFT) | + R200_TXC_OUTPUT_REG_R0 | + R200_TXC_CLAMP_0_1 ); + radeon_out32( mmio, R200_PP_TXABLEND_1, R200_TXA_ARG_C_TFACTOR_ALPHA ); + radeon_out32( mmio, R200_PP_TXABLEND2_1, (1 << R200_TXA_TFACTOR_SEL_SHIFT) | + R200_TXA_OUTPUT_REG_R0 | + R200_TXA_CLAMP_0_1 ); + radeon_out32( mmio, R200_SE_VTX_FMT_0, R200_VTX_XY ); + radeon_out32( mmio, R200_SE_VTX_FMT_1, 0 ); + + rdev->drawingflags = state->drawingflags; + + RADEON_SET ( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); +} + +void r200_set_blittingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_BRUSH_NONE | + GMC_SRC_DATATYPE_COLOR; + u32 cmp_cntl = 0; + u32 rb3d_cntl = rdev->rb3d_cntl; + u32 se_cntl = BFACE_SOLID | + FFACE_SOLID | + VTX_PIX_CENTER_OGL | + ROUND_MODE_ROUND; + u32 pp_cntl = TEX_0_ENABLE; + u32 cblend = R200_TXC_ARG_C_R0_COLOR; + u32 ablend = R200_TXA_ARG_C_R0_ALPHA; + u32 vtx_fmt = R200_VTX_XY; + u32 vte_cntl; + + if (RADEON_IS_SET( BLITTING_FLAGS )) + return; + + if (rdev->accel == DFXL_TEXTRIANGLES) { + se_cntl |= DIFFUSE_SHADE_GOURAUD | + ALPHA_SHADE_GOURAUD | + SPECULAR_SHADE_GOURAUD | + FLAT_SHADE_VTX_LAST | + ROUND_PREC_8TH_PIX; + vtx_fmt |= R200_VTX_Z0 | R200_VTX_W0; + vte_cntl = 0; + } + else { + se_cntl |= DIFFUSE_SHADE_FLAT | + ALPHA_SHADE_FLAT | + ROUND_PREC_4TH_PIX; + vte_cntl = R200_VTX_ST_DENORMALIZED; + } + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + ablend = R200_TXA_ARG_A_R0_ALPHA | R200_TXA_ARG_B_TFACTOR_ALPHA; + else + ablend = R200_TXA_ARG_C_TFACTOR_ALPHA; + + pp_cntl |= TEX_BLEND_0_ENABLE; + } + + rb3d_cntl |= ALPHA_BLEND_ENABLE; + } + + if (rdev->dst_format != DSPF_A8) { + if (state->blittingflags & (DSBLIT_SRC_MASK_ALPHA | DSBLIT_SRC_MASK_COLOR)) { + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) + ablend = R200_TXA_ARG_A_R0_ALPHA | R200_TXA_ARG_B_R1_ALPHA; + + if (state->blittingflags & DSBLIT_SRC_MASK_COLOR) + cblend = R200_TXC_ARG_A_R0_COLOR | R200_TXC_ARG_B_R1_COLOR; + + pp_cntl |= TEX_1_ENABLE | TEX_BLEND_0_ENABLE; + } + else if (state->blittingflags & DSBLIT_COLORIZE) { + if (rdev->dst_422) { + cblend = (rdev->src_format == DSPF_A8) + ? (R200_TXC_ARG_C_R1_COLOR) + : (R200_TXC_ARG_A_R0_COLOR | R200_TXC_ARG_B_R1_COLOR); + + pp_cntl |= TEX_1_ENABLE; + } + else { + cblend = (rdev->src_format == DSPF_A8) + ? (R200_TXC_ARG_C_TFACTOR_COLOR) + : (R200_TXC_ARG_A_R0_COLOR | R200_TXC_ARG_B_TFACTOR_COLOR); + } + + pp_cntl |= TEX_BLEND_0_ENABLE; + } + else if (state->blittingflags & DSBLIT_SRC_PREMULTCOLOR) { + cblend = (rdev->src_format == DSPF_A8) + ? (R200_TXC_ARG_C_R0_ALPHA) + : (R200_TXC_ARG_A_R0_COLOR | R200_TXC_ARG_B_TFACTOR_ALPHA); + + pp_cntl |= TEX_BLEND_0_ENABLE; + } + else if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) { + cblend = (rdev->src_format == DSPF_A8) + ? (R200_TXC_ARG_C_R0_ALPHA) + : (R200_TXC_ARG_A_R0_COLOR | R200_TXC_ARG_B_R0_ALPHA); + + pp_cntl |= TEX_BLEND_0_ENABLE; + } + } /* DSPF_A8 */ + else { + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) { + ablend = R200_TXA_ARG_A_R0_ALPHA | R200_TXA_ARG_B_R1_ALPHA; + cblend = R200_TXC_ARG_A_R0_ALPHA | R200_TXC_ARG_B_R1_ALPHA; + pp_cntl |= TEX_1_ENABLE; + } + else if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + cblend = R200_TXC_ARG_A_R0_ALPHA | R200_TXC_ARG_B_TFACTOR_ALPHA; + else + cblend = R200_TXC_ARG_C_TFACTOR_ALPHA; + } + else { + cblend = R200_TXC_ARG_C_R0_ALPHA; + } + + pp_cntl |= TEX_BLEND_0_ENABLE; + } + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + cmp_cntl = SRC_CMP_EQ_COLOR | CLR_CMP_SRC_SOURCE; + else + master_cntl |= GMC_CLR_CMP_CNTL_DIS; + + if (state->blittingflags & DSBLIT_XOR) { + master_cntl |= GMC_ROP3_XOR; + rb3d_cntl |= ROP_ENABLE; + } + else { + master_cntl |= GMC_ROP3_SRCCOPY; + } + + if (state->render_options & DSRO_ANTIALIAS) + pp_cntl |= ANTI_ALIAS_POLY; + + radeon_waitfifo( rdrv, rdev, 12 ); + radeon_out32( mmio, CLR_CMP_CNTL, cmp_cntl ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + radeon_out32( mmio, RB3D_CNTL, rb3d_cntl ); + radeon_out32( mmio, SE_CNTL, se_cntl ); + radeon_out32( mmio, PP_CNTL, pp_cntl ); + radeon_out32( mmio, R200_PP_TXCBLEND_0, cblend ); + radeon_out32( mmio, R200_PP_TXCBLEND2_0, R200_TXC_OUTPUT_REG_R0 | + R200_TXC_CLAMP_0_1 ); + radeon_out32( mmio, R200_PP_TXABLEND_0, ablend ); + radeon_out32( mmio, R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0 | + R200_TXA_CLAMP_0_1 ); + radeon_out32( mmio, R200_SE_VTX_FMT_0, vtx_fmt ); + radeon_out32( mmio, R200_SE_VTX_FMT_1, 2 << R200_VTX_TEX0_COMP_CNT_SHIFT ); + radeon_out32( mmio, R200_SE_VTE_CNTL, vte_cntl ); + + rdev->blittingflags = state->blittingflags; + + RADEON_SET ( BLITTING_FLAGS ); + RADEON_UNSET( DRAWING_FLAGS ); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/r300_3d.c b/Source/DirectFB/gfxdrivers/radeon/r300_3d.c new file mode 100755 index 0000000..c8a1b8c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r300_3d.c @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_state.h" +#include "radeon_3d.h" + + +#define EMIT_VERTICES( rdrv, rdev, mmio ) { \ + u32 *_v = (rdev)->vb; \ + u32 _s = (rdev)->vb_size; \ + radeon_waitfifo( rdrv, rdev, 1 ); \ + radeon_out32( mmio, SE_VF_CNTL, rdev->vb_type | VF_PRIM_WALK_DATA | \ + (rdev->vb_count << VF_NUM_VERTICES_SHIFT) ); \ + do { \ + u32 _n = MIN(_s, 64); \ + _s -= _n; \ + radeon_waitfifo( rdrv, rdev, _n ); \ + while (_n--) \ + radeon_out32( mmio, SE_PORT_DATA0, *_v++ ); \ + } while (_s); \ + radeon_waitfifo( rdrv, rdev, 2 ); \ + radeon_out32( mmio, R300_RB3D_DSTCACHE_CTLSTAT, 0xa ); \ + radeon_out32( mmio, 0x4f18, 0x3 ); \ +} + +static void +r300_flush_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + EMIT_VERTICES( rdrv, rdev, mmio ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + DFBRegion clip; + int i; + + for (i = 0; i < rdev->vb_size; i += 8) { + rdev->vb[i+0] = f2d(d2f(rdev->vb[i+0])*0.5f); + rdev->vb[i+1] = f2d(d2f(rdev->vb[i+1])*0.5f); + } + + clip.x1 = rdev->clip.x1 >> 1; + clip.y1 = rdev->clip.y1 >> 1; + clip.x2 = rdev->clip.x2 >> 1; + clip.y2 = rdev->clip.y2 >> 1; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset_cb ); + radeon_out32( mmio, R300_RB3D_COLORPITCH0, (rdev->dst_pitch>>1) | + R300_COLOR_FORMAT_RGB8 ); + radeon_out32( mmio, R300_TX_SIZE_0, ((rdev->src_width/2 -1) << R300_TX_WIDTH_SHIFT) | + ((rdev->src_height/2-1) << R300_TX_HEIGHT_SHIFT) | + R300_TX_SIZE_TXPITCH_EN ); + radeon_out32( mmio, R300_TX_PITCH_0, (rdev->src_pitch>>1) - 8 ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset_cb ); + r300_set_clip3d( rdrv, rdev, &clip ); + + /* Fill Cb plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset_cr ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset_cr ); + + /* Fill Cr plane */ + EMIT_VERTICES( rdrv, rdev, mmio ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset ); + radeon_out32( mmio, R300_RB3D_COLORPITCH0, rdev->dst_pitch | + R300_COLOR_FORMAT_RGB8 ); + radeon_out32( mmio, R300_TX_SIZE_0, ((rdev->src_width -1) << R300_TX_WIDTH_SHIFT) | + ((rdev->src_height-1) << R300_TX_HEIGHT_SHIFT) | + R300_TX_SIZE_TXPITCH_EN ); + radeon_out32( mmio, R300_TX_PITCH_0, rdev->src_pitch - 8 ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset ); + r300_set_clip3d( rdrv, rdev, &rdev->clip ); + } + + rdev->vb_size = 0; + rdev->vb_count = 0; +} + +static inline u32* +r300_init_vb( RadeonDriverData *rdrv, RadeonDeviceData *rdev, u32 type, u32 count, u32 size ) +{ + u32 *vb; + + if ((rdev->vb_size && rdev->vb_type != type) || + rdev->vb_size+size > D_ARRAY_SIZE(rdev->vb)) + r300_flush_vb( rdrv, rdev ); + + vb = &rdev->vb[rdev->vb_size]; + rdev->vb_type = type; + rdev->vb_size += size; + rdev->vb_count += count; + + return vb; +} + + +#define VTX(v, x, y, c) \ + *(v)++ = f2d(x); \ + *(v)++ = f2d(y); \ + *(v)++ = f2d(0); \ + *(v)++ = f2d(1); \ + *(v)++ = f2d(c[0]); \ + *(v)++ = f2d(c[1]); \ + *(v)++ = f2d(c[2]); \ + *(v)++ = f2d(c[3]) + +bool r300FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + if (rect->w == 1 && rect->h == 1) { + x1 = rect->x+1; y1 = rect->y+1; + if (rdev->matrix) + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_POINT_LIST, 1, 8 ); + VTX( v, x1, y1, rdev->color ); + + return true; + } + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float x, y; + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 32 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + } + else { + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 32 ); + VTX( v, x1, y1, rdev->color ); + VTX( v, x2, y1, rdev->color ); + VTX( v, x2, y2, rdev->color ); + VTX( v, x1, y2, rdev->color ); + } + + return true; +} + +bool r300FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float x3, y3; + u32 *v; + + x1 = tri->x1; y1 = tri->y1; + x2 = tri->x2; y2 = tri->y2; + x3 = tri->x3; y3 = tri->y3; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x3, y3, x3, y3, rdev->matrix, rdev->affine_matrix ); + } + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_TRIANGLE_LIST, 3, 24 ); + VTX( v, x1, y1, rdev->color ); + VTX( v, x2, y2, rdev->color ); + VTX( v, x3, y3, rdev->color ); + + return true; +} + +bool r300DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = rect->x; y1 = rect->y; + x2 = rect->x+rect->w; y2 = rect->y+rect->h; + if (rdev->matrix) { + float x, y; + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LOOP, 4, 32 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, rdev->color ); + } + else { + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LOOP, 4, 32 ); + VTX( v, x1, y1, rdev->color ); + VTX( v, x2, y1, rdev->color ); + VTX( v, x2, y2, rdev->color ); + VTX( v, x1, y2, rdev->color ); + } + + return true; +} + +bool r300DrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + u32 *v; + + x1 = line->x1; y1 = line->y1; + x2 = line->x2; y2 = line->y2; + if (rdev->matrix) { + RADEON_TRANSFORM( x1, y1, x1, y1, rdev->matrix, rdev->affine_matrix ); + RADEON_TRANSFORM( x2, y2, x2, y2, rdev->matrix, rdev->affine_matrix ); + } + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_LINE_LIST, 2, 16 ); + VTX( v, x1, y1, rdev->color ); + VTX( v, x2, y2, rdev->color ); + + return true; +} + +#undef VTX +#define VTX( v, x, y, s, t ) \ + *(v)++ = f2d(x); \ + *(v)++ = f2d(y); \ + *(v)++ = f2d(0); \ + *(v)++ = f2d(1); \ + *(v)++ = f2d(s); \ + *(v)++ = f2d(t); \ + *(v)++ = f2d(0); \ + *(v)++ = f2d(1) + +bool r300Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ) +{ + DFBRectangle dr = { dx, dy, sr->w, sr->h }; + + return r300StretchBlit( drv, dev, sr, &dr ); +} + +bool r300StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + float x1, y1; + float x2, y2; + float s1, t1; + float s2, t2; + u32 *v; + + if (rdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h /= 2; + } + + s1 = (float)sr->x / rdev->src_width; t1 = (float)sr->y / rdev->src_height; + s2 = (float)(sr->x+sr->w) / rdev->src_width; t2 = (float)(sr->y+sr->h) / rdev->src_height; + if (rdev->blittingflags & DSBLIT_ROTATE180) { + float tmp; + tmp = s2; s2 = s1; s1 = tmp; + tmp = t2; t2 = t1; t1 = tmp; + } + + x1 = dr->x; y1 = dr->y; + x2 = dr->x+dr->w; y2 = dr->y+dr->h; + if (rdev->matrix) { + float x, y; + + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 32 ); + RADEON_TRANSFORM( x1, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, s1, t1 ); + RADEON_TRANSFORM( x2, y1, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, s2, t1 ); + RADEON_TRANSFORM( x2, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, s2, t2 ); + RADEON_TRANSFORM( x1, y2, x, y, rdev->matrix, rdev->affine_matrix ); + VTX( v, x, y, s1, t2 ); + } + else { + v = r300_init_vb( rdrv, rdev, VF_PRIM_TYPE_QUAD_LIST, 4, 32 ); + VTX( v, x1, y1, s1, t1 ); + VTX( v, x2, y1, s2, t1 ); + VTX( v, x2, y2, s2, t2 ); + VTX( v, x1, y2, s1, t2 ); + } + + return true; +} + +static void +r300DoTextureTriangles( RadeonDriverData *rdrv, RadeonDeviceData *rdev, + DFBVertex *ve, int num, u32 primitive ) +{ + volatile u8 *mmio = rdrv->mmio_base; + int i; + + radeon_waitfifo( rdrv, rdev, 1 ); + + radeon_out32( mmio, SE_VF_CNTL, primitive | VF_PRIM_WALK_DATA | + (num << VF_NUM_VERTICES_SHIFT) ); + + for (; num >= 8; num -= 8) { + radeon_waitfifo( rdrv, rdev, 64 ); + for (i = 0; i < 8; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(1) ); // FIXME + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(0) ); // r + radeon_out32( mmio, SE_PORT_DATA0, f2d(1) ); // q + } + ve += 8; + } + + if (num > 0) { + radeon_waitfifo( rdrv, rdev, num*8 ); + for (i = 0; i < num; i++) { + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].x) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].y) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].z) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(1) ); // FIXME + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].s) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(ve[i].t) ); + radeon_out32( mmio, SE_PORT_DATA0, f2d(0) ); // r + radeon_out32( mmio, SE_PORT_DATA0, f2d(1) ); // q + } + } + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, R300_RB3D_DSTCACHE_CTLSTAT, 0xa ); + radeon_out32( mmio, 0x4f18, 0x3 ); +} + +bool r300TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + u32 prim = 0; + int i; + + if (num > 65535) { + D_WARN( "R300 supports maximum 65535 vertices" ); + return false; + } + + switch (formation) { + case DTTF_LIST: + prim = VF_PRIM_TYPE_TRIANGLE_LIST; + break; + case DTTF_STRIP: + prim = VF_PRIM_TYPE_TRIANGLE_STRIP; + break; + case DTTF_FAN: + prim = VF_PRIM_TYPE_TRIANGLE_FAN; + break; + default: + D_BUG( "unexpected triangle formation" ); + return false; + } + + if (rdev->matrix) { + for (i = 0; i < num; i++) + RADEON_TRANSFORM( ve[i].x, ve[i].y, ve[i].x, ve[i].y, rdev->matrix, rdev->affine_matrix ); + } + + r300DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + if (DFB_PLANAR_PIXELFORMAT(rdev->dst_format)) { + volatile u8 *mmio = rdrv->mmio_base; + DFBRegion clip; + int i; + + /* Scale coordinates */ + for (i = 0; i < num; i++) { + ve[i].x *= 0.5; + ve[i].y *= 0.5; + } + clip.x1 = rdev->clip.x1 >> 1; + clip.y1 = rdev->clip.y1 >> 1; + clip.x2 = rdev->clip.x2 >> 1; + clip.y2 = rdev->clip.y2 >> 1; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset_cb ); + radeon_out32( mmio, R300_RB3D_COLORPITCH0, (rdev->dst_pitch>>1) | + R300_COLOR_FORMAT_RGB8 ); + radeon_out32( mmio, R300_TX_SIZE_0, ((rdev->src_width/2 -1) << R300_TX_WIDTH_SHIFT) | + ((rdev->src_height/2-1) << R300_TX_HEIGHT_SHIFT) | + R300_TX_SIZE_TXPITCH_EN ); + radeon_out32( mmio, R300_TX_PITCH_0, (rdev->src_pitch>>1) - 8 ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset_cb ); + r300_set_clip3d( rdrv, rdev, &clip ); + + /* Blit Cb plane */ + r300DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset_cr ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset_cr ); + + /* Blit Cr plane */ + r300DoTextureTriangles( rdrv, rdev, ve, num, prim ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, rdev->dst_offset ); + radeon_out32( mmio, R300_RB3D_COLORPITCH0, rdev->dst_pitch | + R300_COLOR_FORMAT_RGB8 ); + radeon_out32( mmio, R300_TX_SIZE_0, ((rdev->src_width -1) << R300_TX_WIDTH_SHIFT) | + ((rdev->src_height-1) << R300_TX_HEIGHT_SHIFT) | + R300_TX_SIZE_TXPITCH_EN ); + radeon_out32( mmio, R300_TX_PITCH_0, rdev->src_pitch - 8 ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset ); + r300_set_clip3d( rdrv, rdev, &rdev->clip ); + } + + return true; +} + +void r300EmitCommands3D( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->vb_count) + r300_flush_vb( rdrv, rdev ); +} diff --git a/Source/DirectFB/gfxdrivers/radeon/r300_program.h b/Source/DirectFB/gfxdrivers/radeon/r300_program.h new file mode 100755 index 0000000..b2bc0dd --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r300_program.h @@ -0,0 +1,151 @@ +/* +Copyright (C) 2004 Nicolai Haehnle. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Nicolai Haehnle + */ + +#ifndef __R300_PROGRAM_H__ +#define __R300_PROGRAM_H__ + +#include "radeon_regs.h" + +/** + * Vertex program helper macros + */ + +/* Produce out dword */ +#define VP_OUTCLASS_TMP R300_VPI_OUT_REG_CLASS_TEMPORARY +#define VP_OUTCLASS_OUT R300_VPI_OUT_REG_CLASS_RESULT + +#define VP_OUTMASK_X R300_VPI_OUT_WRITE_X +#define VP_OUTMASK_Y R300_VPI_OUT_WRITE_Y +#define VP_OUTMASK_Z R300_VPI_OUT_WRITE_Z +#define VP_OUTMASK_W R300_VPI_OUT_WRITE_W +#define VP_OUTMASK_XY (VP_OUTMASK_X|VP_OUTMASK_Y) +#define VP_OUTMASK_XZ (VP_OUTMASK_X|VP_OUTMASK_Z) +#define VP_OUTMASK_XW (VP_OUTMASK_X|VP_OUTMASK_W) +#define VP_OUTMASK_XYZ (VP_OUTMASK_XY|VP_OUTMASK_Z) +#define VP_OUTMASK_XYW (VP_OUTMASK_XY|VP_OUTMASK_W) +#define VP_OUTMASK_XZW (VP_OUTMASK_XZ|VP_OUTMASK_W) +#define VP_OUTMASK_XYZW (VP_OUTMASK_XYZ|VP_OUTMASK_W) +#define VP_OUTMASK_YZ (VP_OUTMASK_Y|VP_OUTMASK_Z) +#define VP_OUTMASK_YW (VP_OUTMASK_Y|VP_OUTMASK_W) +#define VP_OUTMASK_YZW (VP_OUTMASK_YZ|VP_OUTMASK_W) +#define VP_OUTMASK_ZW (VP_OUTMASK_Z|VP_OUTMASK_W) + +#define VP_OUT(instr,outclass,outidx,outmask) \ + (R300_VPI_OUT_OP_##instr | \ + ((outidx) << R300_VPI_OUT_REG_INDEX_SHIFT) | \ + VP_OUTCLASS_##outclass | \ + VP_OUTMASK_##outmask) + +/* Produce in dword */ +#define VP_INCLASS_TMP R300_VPI_IN_REG_CLASS_TEMPORARY +#define VP_INCLASS_IN R300_VPI_IN_REG_CLASS_ATTRIBUTE +#define VP_INCLASS_CONST R300_VPI_IN_REG_CLASS_PARAMETER + +#define VP_IN(class,idx) \ + (((idx) << R300_VPI_IN_REG_INDEX_SHIFT) | \ + VP_INCLASS_##class | \ + (R300_VPI_IN_SELECT_X << R300_VPI_IN_X_SHIFT) | \ + (R300_VPI_IN_SELECT_Y << R300_VPI_IN_Y_SHIFT) | \ + (R300_VPI_IN_SELECT_Z << R300_VPI_IN_Z_SHIFT) | \ + (R300_VPI_IN_SELECT_W << R300_VPI_IN_W_SHIFT)) +#define VP_ZERO() \ + ((R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_X_SHIFT) | \ + (R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_Y_SHIFT) | \ + (R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_Z_SHIFT) | \ + (R300_VPI_IN_SELECT_ZERO << R300_VPI_IN_W_SHIFT)) +#define VP_ONE() \ + ((R300_VPI_IN_SELECT_ONE << R300_VPI_IN_X_SHIFT) | \ + (R300_VPI_IN_SELECT_ONE << R300_VPI_IN_Y_SHIFT) | \ + (R300_VPI_IN_SELECT_ONE << R300_VPI_IN_Z_SHIFT) | \ + (R300_VPI_IN_SELECT_ONE << R300_VPI_IN_W_SHIFT)) + +#define VP_NEG(in,comp) ((in) ^ (R300_VPI_IN_NEG_##comp)) +#define VP_NEGALL(in,comp) VP_NEG(VP_NEG(VP_NEG(VP_NEG((in),X),Y),Z),W) + +/** + * Fragment program helper macros + */ + +/* Produce unshifted source selectors */ +#define FP_TMP(idx) (idx) +#define FP_CONST(idx) ((idx) | (1 << 5)) + +/* Produce source/dest selector dword */ +#define FP_SELC_MASK_NO 0 +#define FP_SELC_MASK_X 1 +#define FP_SELC_MASK_Y 2 +#define FP_SELC_MASK_XY 3 +#define FP_SELC_MASK_Z 4 +#define FP_SELC_MASK_XZ 5 +#define FP_SELC_MASK_YZ 6 +#define FP_SELC_MASK_XYZ 7 + +#define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \ + (((destidx) << R300_FPI1_DSTC_SHIFT) | \ + (FP_SELC_MASK_##regmask << 23) | \ + (FP_SELC_MASK_##outmask << 26) | \ + ((src0) << R300_FPI1_SRC0C_SHIFT) | \ + ((src1) << R300_FPI1_SRC1C_SHIFT) | \ + ((src2) << R300_FPI1_SRC2C_SHIFT)) + +#define FP_SELA_MASK_NO 0 +#define FP_SELA_MASK_W 1 + +#define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \ + (((destidx) << R300_FPI3_DSTA_SHIFT) | \ + (FP_SELA_MASK_##regmask << 23) | \ + (FP_SELA_MASK_##outmask << 24) | \ + ((src0) << R300_FPI3_SRC0A_SHIFT) | \ + ((src1) << R300_FPI3_SRC1A_SHIFT) | \ + ((src2) << R300_FPI3_SRC2A_SHIFT)) + +/* Produce unshifted argument selectors */ +#define FP_ARGC(source) R300_FPI0_ARGC_##source +#define FP_ARGA(source) R300_FPI2_ARGA_##source +#define FP_ABS(arg) ((arg) | (1 << 6)) +#define FP_NEG(arg) ((arg) ^ (1 << 5)) + +/* Produce instruction dword */ +#define FP_INSTRC(opcode,arg0,arg1,arg2) \ + (R300_FPI0_OUTC_##opcode | \ + ((arg0) << R300_FPI0_ARG0C_SHIFT) | \ + ((arg1) << R300_FPI0_ARG1C_SHIFT) | \ + ((arg2) << R300_FPI0_ARG2C_SHIFT)) + +#define FP_INSTRA(opcode,arg0,arg1,arg2) \ + (R300_FPI2_OUTA_##opcode | \ + ((arg0) << R300_FPI2_ARG0A_SHIFT) | \ + ((arg1) << R300_FPI2_ARG1A_SHIFT) | \ + ((arg2) << R300_FPI2_ARG2A_SHIFT)) + + +#include "vertex_shader.h" + +#endif /* __R300_PROGRAM_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/r300_state.c b/Source/DirectFB/gfxdrivers/radeon/r300_state.c new file mode 100755 index 0000000..97bfd6a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/r300_state.c @@ -0,0 +1,1103 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_state.h" + +#include "r300_program.h" + + +#define R300_HAS_3DREGS() (rdrv->mmio_size > 0x4000) + + +static const u32 r300SrcBlend[] = { + SRC_BLEND_GL_ZERO, // DSBF_ZERO + SRC_BLEND_GL_ONE, // DSBF_ONE + SRC_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + SRC_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + SRC_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + SRC_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + SRC_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + SRC_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + SRC_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + SRC_BLEND_GL_SRC_ALPHA_SATURATE // DSBF_SRCALPHASAT +}; + +static const u32 r300DstBlend[] = { + DST_BLEND_GL_ZERO, // DSBF_ZERO + DST_BLEND_GL_ONE, // DSBF_ONE + DST_BLEND_GL_SRC_COLOR, // DSBF_SRCCOLOR + DST_BLEND_GL_ONE_MINUS_SRC_COLOR, // DSBF_INVSRCCOLOR + DST_BLEND_GL_SRC_ALPHA, // DSBF_SRCALPHA + DST_BLEND_GL_ONE_MINUS_SRC_ALPHA, // DSBF_INVSRCALPHA + DST_BLEND_GL_DST_ALPHA, // DSBF_DSTALPHA + DST_BLEND_GL_ONE_MINUS_DST_ALPHA, // DSBF_INVDSTALPHA + DST_BLEND_GL_DST_COLOR, // DSBF_DSTCOLOR + DST_BLEND_GL_ONE_MINUS_DST_COLOR, // DSBF_INVDSTCOLOR + DST_BLEND_GL_ZERO // DSBF_SRCALPHASAT +}; + + +void r300_restore( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + const u32 rs_magic[8] = { 0x00, 0x44, 0x84, 0xc4, + 0x04, 0x04, 0x04, 0x04 }; + volatile u8 *mmio = rdrv->mmio_base; + int i; + + /* enable caches */ + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, RB2D_DSTCACHE_MODE, RB2D_DC_2D_CACHE_AUTOFLUSH | + R300_RB2D_DC_ENABLE ); + + if (!R300_HAS_3DREGS()) + return; + + /* restore 3d engine state */ + radeon_waitfifo( rdrv, rdev, 50 ); + radeon_out32( mmio, 0x2080, 0x0030045a ); + radeon_out32( mmio, R300_SE_VTE_CNTL, R300_VTX_W0_FMT ); + radeon_out32( mmio, R300_SE_VTE_CNTL+4, 0x00000008 ); + radeon_out32( mmio, 0x2134, 0x00FFFFFF ); + radeon_out32( mmio, 0x2138, 0x00000000 ); +#ifdef WORDS_BIGENDIAN + radeon_out32( mmio, 0x2140, 0x00000002 ); +#else + radeon_out32( mmio, 0x2140, 0x00000000 ); +#endif + radeon_out32( mmio, 0x21dc, 0xaaaaaaaa ); + radeon_out32( mmio, 0x2220, f2d(1.0) ); + radeon_out32( mmio, 0x2224, f2d(1.0) ); + radeon_out32( mmio, 0x2228, f2d(1.0) ); + radeon_out32( mmio, 0x222c, f2d(1.0) ); + if (rdev->chipset >= CHIP_RV350) + radeon_out32( mmio, R300_VAP_UNKNOWN_2288, R300_2288_RV350 ); + else + radeon_out32( mmio, R300_VAP_UNKNOWN_2288, R300_2288_R300 ); + radeon_out32( mmio, R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE | + R300_GB_LINE_STUFF_ENABLE | + R300_GB_TRIANGLE_STUFF_ENABLE ); + radeon_out32( mmio, R300_GB_MSPOS0, 0x66666666 ); + radeon_out32( mmio, R300_GB_MSPOS1, 0x06666666 ); + if (rdev->chipset == CHIP_R300 || rdev->chipset == CHIP_R350 || rdev->chipset == CHIP_RV410) { + radeon_out32( mmio, R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | + R300_GB_TILE_PIPE_COUNT_R300 | + R300_GB_TILE_SIZE_16 ); + } + else if (rdev->chipset == CHIP_R420) { + radeon_out32( mmio, R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | + R300_GB_TILE_PIPE_COUNT_R420 | + R300_GB_TILE_SIZE_16 ); + } + else { + radeon_out32( mmio, R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | + R300_GB_TILE_PIPE_COUNT_RV300 | + R300_GB_TILE_SIZE_16 ); + } + radeon_out32( mmio, R300_GB_SELECT, 0 ); + radeon_out32( mmio, R300_GB_AA_CONFIG, 0 ); + radeon_out32( mmio, 0x4200, f2d(0.0) ); + radeon_out32( mmio, 0x4204, f2d(0.0) ); + radeon_out32( mmio, 0x4208, f2d(1.0) ); + radeon_out32( mmio, 0x420c, f2d(1.0) ); + radeon_out32( mmio, 0x4214, 0x00050005 ); + radeon_out32( mmio, R300_RE_POINTSIZE, (6 << R300_POINTSIZE_X_SHIFT) | + (6 << R300_POINTSIZE_Y_SHIFT) ); + radeon_out32( mmio, 0x4230, 0x18000006 ); + radeon_out32( mmio, R300_RE_LINE_CNT, (6 << R300_LINESIZE_SHIFT) | + R300_LINE_CNT_VE ); + radeon_out32( mmio, R300_RE_UNK4238, f2d(1.0/192.0) ); + radeon_out32( mmio, 0x4260, 0x00000000 ); + radeon_out32( mmio, 0x4264, f2d(0.0) ); + radeon_out32( mmio, 0x4268, f2d(1.0) ); + radeon_out32( mmio, 0x4274, 0x00000002 ); + radeon_out32( mmio, 0x427c, 0x00000000 ); + radeon_out32( mmio, 0x4280, 0x00000000 ); + radeon_out32( mmio, R300_RE_POLYGON_MODE, 0 ); + radeon_out32( mmio, 0x428c, 0x00000001 ); + radeon_out32( mmio, 0x4290, 0x00000000 ); + radeon_out32( mmio, 0x4294, 0x00000000 ); + radeon_out32( mmio, 0x4298, 0x00000000 ); + radeon_out32( mmio, 0x42a0, 0x00000000 ); + radeon_out32( mmio, R300_RE_ZBIAS_T_FACTOR, 0 ); + radeon_out32( mmio, R300_RE_ZBIAS_T_CONSTANT, 0 ); + radeon_out32( mmio, R300_RE_ZBIAS_W_FACTOR, 0 ); + radeon_out32( mmio, R300_RE_ZBIAS_W_CONSTANT, 0 ); + radeon_out32( mmio, R300_RE_OCCLUSION_CNTL, 0 ); + radeon_out32( mmio, R300_RE_CULL_CNTL, 0 ); + radeon_out32( mmio, 0x42c0, 0x4b7fffff ); + radeon_out32( mmio, 0x42c4, 0x00000000 ); + + radeon_waitfifo( rdrv, rdev, 16 ); + for (i = 0; i < 8; i++) { + radeon_out32( mmio, R300_RS_INTERP_0+i*4, R300_RS_INTERP_USED | rs_magic[i] ); + //radeon_out32( mmio, R300_RS_ROUTE_0+i*4, 0 ); + } + + radeon_waitfifo( rdrv, rdev, 43 ); + radeon_out32( mmio, 0x43a4, 0x0000001c ); + radeon_out32( mmio, 0x43a8, 0x2da49525 ); + radeon_out32( mmio, 0x43e8, 0x00ffffff ); + radeon_out32( mmio, 0x46a4, 0x00001b01 ); + radeon_out32( mmio, 0x46a8, 0x00001b0f ); + radeon_out32( mmio, 0x46ac, 0x00001b0f ); + radeon_out32( mmio, 0x46b0, 0x00001b0f ); + radeon_out32( mmio, 0x46b4, 0x00000001 ); + radeon_out32( mmio, 0x4bc0, 0x00000000 ); + radeon_out32( mmio, 0x4bc8, 0x00000000 ); + radeon_out32( mmio, 0x4bcc, 0x00000000 ); + radeon_out32( mmio, 0x4bd0, 0x00000000 ); + radeon_out32( mmio, R300_PP_ALPHA_TEST, R300_ALPHA_TEST_PASS ); + radeon_out32( mmio, 0x4bd8, 0x00000000 ); + radeon_out32( mmio, 0x4e00, 0x00000000 ); + radeon_out32( mmio, R300_RB3D_COLORMASK, R300_COLORMASK0_B | + R300_COLORMASK0_G | + R300_COLORMASK0_R | + R300_COLORMASK0_A ); + radeon_out32( mmio, R300_RB3D_BLENDCOLOR, 0xffffffff ); + radeon_out32( mmio, 0x4e14, 0x00000000 ); + radeon_out32( mmio, 0x4e18, 0x00000000 ); + radeon_out32( mmio, 0x4e50, 0x00000000 ); + radeon_out32( mmio, 0x4e54, 0x00000000 ); + radeon_out32( mmio, 0x4e58, 0x00000000 ); + radeon_out32( mmio, 0x4e5c, 0x00000000 ); + radeon_out32( mmio, 0x4e60, 0x00000000 ); + radeon_out32( mmio, 0x4e64, 0x00000000 ); + radeon_out32( mmio, 0x4e68, 0x00000000 ); + radeon_out32( mmio, 0x4e6c, 0x00000000 ); + radeon_out32( mmio, 0x4e70, 0x00000000 ); + radeon_out32( mmio, 0x4e88, 0x00000000 ); + radeon_out32( mmio, 0x4ea0, 0x00000000 ); + radeon_out32( mmio, 0x4ea4, 0xffffffff ); + radeon_out32( mmio, R300_RB3D_ZSTENCIL_CNTL_0, R300_RB3D_Z_DISABLED_1 ); + radeon_out32( mmio, R300_RB3D_ZSTENCIL_CNTL_1, R300_ZS_ALWAYS ); + radeon_out32( mmio, R300_RB3D_ZSTENCIL_CNTL_2, 0xffffff00 ); + radeon_out32( mmio, R300_RB3D_ZSTENCIL_FORMAT, R300_DEPTH_FORMAT_16BIT_INT_Z ); + radeon_out32( mmio, 0x4f14, 0x00000000 ); + radeon_out32( mmio, 0x4f18, 0x00000003 ); + radeon_out32( mmio, 0x4f1c, 0x00000000 ); + radeon_out32( mmio, 0x4f28, 0x00000000 ); + radeon_out32( mmio, 0x4f30, 0x00000000 ); + radeon_out32( mmio, 0x4f34, 0x00000000 ); + radeon_out32( mmio, 0x4f44, 0x00000000 ); + radeon_out32( mmio, 0x4f54, 0x00000000 ); + + /* upload vertex program */ + radeon_waitfifo( rdrv, rdev, 50 ); + radeon_out32( mmio, R300_VAP_PVS_CNTL_1, + (0 << R300_PVS_CNTL_1_PROGRAM_START_SHIFT) | + (4 << R300_PVS_CNTL_1_POS_END_SHIFT) | + (4 << R300_PVS_CNTL_1_PROGRAM_END_SHIFT) ); + radeon_out32( mmio, R300_VAP_PVS_CNTL_2, + (0 << R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT) | + (4 << R300_PVS_CNTL_2_PARAM_COUNT_SHIFT) ); + radeon_out32( mmio, R300_VAP_PVS_CNTL_3, + (4 << R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT) | + (4 << R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT) ); + radeon_out32( mmio, R300_VAP_PVS_WAITIDLE, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_ADDRESS, R300_PVS_UPLOAD_POINTSIZE ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, f2d(1.0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_WAITIDLE, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_ADDRESS, R300_PVS_UPLOAD_PROGRAM ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_OP(MAD, 0, ALL, TMP) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_ATTR_X(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_PARAM(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_SOURCE(0, ZERO, ZERO, ZERO, ZERO, PARAM, NONE) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_OP(MAD, 0, ALL, TMP) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_ATTR_Y(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_PARAM(1) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_TMP(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_OP(MAD, 0, ALL, TMP) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_ATTR_Z(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_PARAM(2) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_TMP(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_OP(MAD, 0, ALL, RESULT) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_ATTR_W(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_PARAM(3) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_TMP(0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_OP(ADD, 1, ALL, RESULT) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, VSF_REG(1) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_SOURCE(1, ZERO, ZERO, ZERO, ZERO, ATTR, NONE) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, EASY_VSF_SOURCE(1, ZERO, ZERO, ZERO, ZERO, ATTR, NONE) ); + radeon_out32( mmio, R300_VAP_PVS_WAITIDLE, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_ADDRESS, R300_PVS_UPLOAD_PARAMETERS ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, f2d(1.0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, f2d(1.0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, f2d(1.0) ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, 0 ); + radeon_out32( mmio, R300_VAP_PVS_UPLOAD_DATA, f2d(1.0) ); + +#if 0 + /* set YUV422 color buffer */ + radeon_waitfifo( rdrv, rdev, 4 ); + radeon_out32( mmio, R300_TX_FILTER_1, R300_TX_MAG_FILTER_NEAREST | + R300_TX_MIN_FILTER_NEAREST ); + radeon_out32( mmio, R300_TX_FILTER1_0, 0 ); + radeon_out32( mmio, R300_TX_SIZE_1, (1 << R300_TX_WIDTHMASK_SHIFT) | + (1 << R300_TX_HEIGHTMASK_SHIFT) ); + radeon_out32( mmio, R300_TX_FORMAT_1, R300_TXFORMAT_VYUY422 ); +#endif +} + +void r300_set_destination( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + CoreSurfaceBuffer *buffer = state->dst.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 offset; + u32 pitch; + u32 format = 0; + bool dst_422 = false; + + if (RADEON_IS_SET( DESTINATION )) + return; + + D_ASSERT( (state->dst.offset % 32) == 0 ); + D_ASSERT( (state->dst.pitch % 64) == 0 ); + + offset = radeon_buffer_offset( rdev, &state->dst ); + pitch = state->dst.pitch; + + if (rdev->dst_offset != offset || + rdev->dst_pitch != pitch || + rdev->dst_format != buffer->format) + { + switch (buffer->format) { + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_A8: + case DSPF_RGB332: + format = R300_COLOR_FORMAT_RGB8; + rdev->gui_master_cntl = GMC_DST_8BPP; + break; + case DSPF_ARGB2554: + rdev->gui_master_cntl = GMC_DST_16BPP; + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + rdev->gui_master_cntl = GMC_DST_16BPP; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + rdev->gui_master_cntl = GMC_DST_15BPP; + break; + case DSPF_RGB16: + format = R300_COLOR_FORMAT_RGB565; + rdev->gui_master_cntl = GMC_DST_16BPP; + break; + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + format = R300_COLOR_FORMAT_ARGB8888; + rdev->gui_master_cntl = GMC_DST_32BPP; + break; + case DSPF_UYVY: + rdev->gui_master_cntl = GMC_DST_YVYU; + dst_422 = true; + break; + case DSPF_YUY2: + rdev->gui_master_cntl = GMC_DST_VYUY; + dst_422 = true; + break; + case DSPF_I420: + format = R300_COLOR_FORMAT_RGB8; + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->dst_offset_cb = offset + pitch * surface->config.size.h; + rdev->dst_offset_cr = rdev->dst_offset_cb + + pitch/2 * surface->config.size.h/2; + break; + case DSPF_YV12: + format = R300_COLOR_FORMAT_RGB8; + rdev->gui_master_cntl = GMC_DST_8BPP; + rdev->dst_offset_cr = offset + pitch * surface->config.size.h; + rdev->dst_offset_cb = rdev->dst_offset_cr + + pitch/2 * surface->config.size.h/2; + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + rdev->gui_master_cntl |= GMC_DP_SRC_SOURCE_MEMORY | + GMC_WR_MSK_DIS | + GMC_SRC_PITCH_OFFSET_CNTL | + GMC_DST_PITCH_OFFSET_CNTL | + GMC_DST_CLIPPING; + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DST_OFFSET, offset ); + radeon_out32( mmio, DST_PITCH, pitch ); + + if (R300_HAS_3DREGS() && format) { + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, R300_RB3D_COLOROFFSET0, offset ); + radeon_out32( mmio, R300_RB3D_COLORPITCH0, + ((pitch / DFB_BYTES_PER_PIXEL(buffer->format)) + & R300_COLORPITCH_MASK) | format ); + } + + if (rdev->dst_format != buffer->format) { + if (dst_422 && !rdev->dst_422) { + RADEON_UNSET( CLIP ); + RADEON_UNSET( SOURCE ); + rdev->src_format = DSPF_UNKNOWN; + } + + RADEON_UNSET( COLOR ); + RADEON_UNSET( DST_BLEND ); + } + + rdev->dst_format = buffer->format; + rdev->dst_offset = offset; + rdev->dst_pitch = pitch; + rdev->dst_422 = dst_422; + } + + RADEON_SET( DESTINATION ); +} + +void r300_set_source( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + CoreSurfaceBuffer *buffer = state->src.buffer; + volatile u8 *mmio = rdrv->mmio_base; + u32 txformat = 0; + u32 txfilter = (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) | + (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) | + (R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_Q_SHIFT) | + R300_TX_MAG_FILTER_LINEAR | + R300_TX_MIN_FILTER_LINEAR; + + if (RADEON_IS_SET( SOURCE )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (rdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + D_ASSERT( (state->src.offset % 32) == 0 ); + D_ASSERT( (state->src.pitch % 64) == 0 ); + + rdev->src_offset = radeon_buffer_offset( rdev, &state->src ); + rdev->src_pitch = state->src.pitch; + rdev->src_width = surface->config.size.w; + rdev->src_height = surface->config.size.h; + + switch (buffer->format) { + case DSPF_LUT8: + txformat = R300_TXFORMAT_I8; + txfilter &= ~(R300_TX_MAG_FILTER_LINEAR | + R300_TX_MIN_FILTER_LINEAR); + txfilter |= R300_TX_MAG_FILTER_NEAREST | + R300_TX_MIN_FILTER_NEAREST; + rdev->src_mask = 0x000000ff; + break; + case DSPF_ALUT44: + txformat = R300_TXFORMAT_I8; + txfilter &= ~(R300_TX_MAG_FILTER_LINEAR | + R300_TX_MIN_FILTER_LINEAR); + txfilter |= R300_TX_MAG_FILTER_NEAREST | + R300_TX_MIN_FILTER_NEAREST; + rdev->src_mask = 0x0000000f; + break; + case DSPF_A8: + txformat = R300_TXFORMAT_A8; + rdev->src_mask = 0; + break; + case DSPF_RGB332: + txformat = R300_TXFORMAT_RGB332; + rdev->src_mask = 0x000000ff; + break; + case DSPF_ARGB2554: + txformat = R300_TXFORMAT_RGB565; + txfilter &= ~(R300_TX_MAG_FILTER_LINEAR | + R300_TX_MIN_FILTER_LINEAR); + txfilter |= R300_TX_MAG_FILTER_NEAREST | + R300_TX_MIN_FILTER_NEAREST; + rdev->src_mask = 0x00003fff; + break; + case DSPF_RGB444: + txformat = R300_TXFORMAT_RGB444; + rdev->src_mask = 0x00000fff; + break; + case DSPF_ARGB4444: + txformat = R300_TXFORMAT_ARGB4444; + rdev->src_mask = 0x00000fff; + break; + case DSPF_RGB555: + txformat = R300_TXFORMAT_RGB555; + rdev->src_mask = 0x00007fff; + break; + case DSPF_ARGB1555: + txformat = R300_TXFORMAT_ARGB1555; + rdev->src_mask = 0x00007fff; + break; + case DSPF_RGB16: + txformat = R300_TXFORMAT_RGB565; + rdev->src_mask = 0x0000ffff; + break; + case DSPF_RGB32: + txformat = R300_TXFORMAT_XRGB8888; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_AYUV: + txformat = R300_TXFORMAT_ARGB8888; + rdev->src_mask = 0x00ffffff; + break; + case DSPF_UYVY: + txformat = R300_TXFORMAT_YVYU422; + rdev->src_mask = 0xffffffff; + break; + case DSPF_YUY2: + txformat = R300_TXFORMAT_VYUY422; + rdev->src_mask = 0xffffffff; + break; + case DSPF_I420: + txformat = R300_TXFORMAT_I8; + rdev->src_offset_cb = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cr = rdev->src_offset_cb + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + case DSPF_YV12: + txformat = R300_TXFORMAT_I8; + rdev->src_offset_cr = rdev->src_offset + + rdev->src_pitch * rdev->src_height; + rdev->src_offset_cb = rdev->src_offset_cr + + rdev->src_pitch/2 * rdev->src_height/2; + rdev->src_mask = 0x000000ff; + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + rdev->src_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) { + rdev->src_offset += rdev->src_height * rdev->src_pitch; + rdev->src_offset_cr += rdev->src_height * rdev->src_pitch/4; + rdev->src_offset_cb += rdev->src_height * rdev->src_pitch/4; + } + } else { + if (surface->field) { + rdev->src_offset += rdev->src_pitch; + rdev->src_offset_cr += rdev->src_pitch/2; + rdev->src_offset_cb += rdev->src_pitch/2; + } + rdev->src_pitch *= 2; + } + } + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset ); + radeon_out32( mmio, SRC_PITCH, rdev->src_pitch ); + + if (R300_HAS_3DREGS()) { + radeon_waitfifo( rdrv, rdev, 6 ); + radeon_out32( mmio, R300_TX_CNTL, 0 ); + radeon_out32( mmio, R300_TX_FILTER_0, txfilter ); + radeon_out32( mmio, R300_TX_FORMAT_0, txformat ); + radeon_out32( mmio, R300_TX_SIZE_0, ((rdev->src_width -1) << R300_TX_WIDTH_SHIFT) | + ((rdev->src_height-1) << R300_TX_HEIGHT_SHIFT) | + R300_TX_SIZE_TXPITCH_EN ); + radeon_out32( mmio, R300_TX_PITCH_0, rdev->src_pitch / + DFB_BYTES_PER_PIXEL(buffer->format) - 8 ); + radeon_out32( mmio, R300_TX_OFFSET_0, rdev->src_offset ); + } + + if (rdev->src_format != buffer->format) + RADEON_UNSET( BLITTING_FLAGS ); + rdev->src_format = buffer->format; + + RADEON_SET( SOURCE ); +} + +void r300_set_clip3d( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + const DFBRegion *clip ) +{ + volatile u8 *mmio = rdrv->mmio_base; + int x1, y1, x2, y2; + + x1 = clip->x1 + R300_CLIPRECT_OFFSET; + y1 = clip->y1 + R300_CLIPRECT_OFFSET; + x2 = clip->x2 + R300_CLIPRECT_OFFSET; + y2 = clip->y2 + R300_CLIPRECT_OFFSET; + + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, R300_RE_CLIPRECT_TL_0, + ((y1 << R300_CLIPRECT_Y_SHIFT) & R300_CLIPRECT_Y_MASK) | + ((x1 << R300_CLIPRECT_X_SHIFT) & R300_CLIPRECT_X_MASK) ); + radeon_out32( mmio, R300_RE_CLIPRECT_BR_0, + ((y2 << R300_CLIPRECT_Y_SHIFT) & R300_CLIPRECT_Y_MASK) | + ((x2 << R300_CLIPRECT_X_SHIFT) & R300_CLIPRECT_X_MASK) ); + radeon_out32( mmio, R300_RE_CLIPRECT_CNTL, 0x0000aaaa ); + radeon_out32( mmio, R300_RE_SCISSORS_TL, + ((y1 << R300_SCISSORS_Y_SHIFT) & R300_SCISSORS_Y_MASK) | + ((x1 << R300_SCISSORS_X_SHIFT) & R300_SCISSORS_X_MASK) ); + radeon_out32( mmio, R300_RE_SCISSORS_BR, + ((y2 << R300_SCISSORS_Y_SHIFT) & R300_SCISSORS_Y_MASK) | + ((x2 << R300_SCISSORS_X_SHIFT) & R300_SCISSORS_X_MASK) ); +} + +void r300_set_clip( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBRegion *clip = &state->clip; + volatile u8 *mmio = rdrv->mmio_base; + + if (RADEON_IS_SET( CLIP )) + return; + + /* 2d clip */ + radeon_waitfifo( rdrv, rdev, 2 ); + if (rdev->dst_422) { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1)/2 & 0xffff) ); + } else { + radeon_out32( mmio, SC_TOP_LEFT, + (clip->y1 << 16) | (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, + ((clip->y2+1) << 16) | ((clip->x2+1) & 0xffff) ); + } + + /* 3d clip */ + if (R300_HAS_3DREGS()) + r300_set_clip3d( rdrv, rdev, clip ); + + rdev->clip = state->clip; + + RADEON_SET( CLIP ); +} + +#define R300_SET_YUV422_COLOR( rdrv, rdev, y, u, v ) \ + if (R300_HAS_3DREGS()) { \ + radeon_out32( (rdrv)->fb_base, \ + (rdev)->yuv422_buffer, PIXEL_YUY2( y, u, v ) ); \ + radeon_in8( (rdrv)->fb_base, (rdev)->yuv422_buffer ); \ + radeon_waitfifo( rdrv, rdev, 1 ); \ + radeon_out32( (rdrv)->mmio_base, R300_TX_OFFSET_1, \ + ((rdev)->fb_offset + (rdev)->yuv422_buffer) ); \ + } + +void r300_set_drawing_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + int index = state->color_index; + u32 color2d; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (state->drawingflags & DSDRAW_SRC_PREMULTIPLY) { + color.r = ((long) color.r * color.a / 255L); + color.g = ((long) color.g * color.a / 255L); + color.b = ((long) color.b * color.a / 255L); + } + + switch (rdev->dst_format) { + case DSPF_ALUT44: + index |= (color.a & 0xf0); + case DSPF_LUT8: + color2d = index; + break; + case DSPF_A8: + color2d = color.a; + break; + case DSPF_RGB332: + color2d = PIXEL_RGB332( color.r, color.g, color.b ); + break; + case DSPF_ARGB2554: + color2d = PIXEL_ARGB2554( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB444: + case DSPF_ARGB4444: + color2d = PIXEL_ARGB4444( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + color2d = PIXEL_ARGB1555( color.a, color.r, + color.g, color.b ); + break; + case DSPF_RGB16: + color2d = PIXEL_RGB16( color.r, color.g, color.b ); + break; + case DSPF_RGB32: + color2d = PIXEL_RGB32( color.r, color.g, color.b ); + break; + case DSPF_ARGB: + color2d = PIXEL_ARGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AiRGB: + color2d = PIXEL_AiRGB( color.a, color.r, + color.g, color.b ); + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_AYUV( color.a, y, u, v ); + break; + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_UYVY( y, u, v ); + //R300_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color2d = PIXEL_YUY2( y, u, v ); + //R300_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + color2d = rdev->y_cop; + break; + default: + D_BUG( "unexpected pixelformat" ); + color2d = 0; + break; + } + + rdev->color[0] = (float)color.r/255.0; + rdev->color[1] = (float)color.g/255.0; + rdev->color[2] = (float)color.b/255.0; + rdev->color[3] = (float)color.a/255.0; + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, DP_BRUSH_FRGD_CLR, color2d ); + + RADEON_SET( COLOR ); +} + +void r300_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + DFBColor color = state->color; + int y, u, v; + + if (RADEON_IS_SET( COLOR ) && RADEON_IS_SET( BLITTING_FLAGS )) + return; + + switch (rdev->dst_format) { + case DSPF_A8: + color.r = color.g = color.b = 0xff; + break; + case DSPF_I420: + case DSPF_YV12: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + rdev->y_cop = PIXEL_ARGB( color.a, y, y, y ); + rdev->cb_cop = PIXEL_ARGB( color.a, u, u, u ); + rdev->cr_cop = PIXEL_ARGB( color.a, v, v, v ); + break; + case DSPF_AYUV: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + color.r = y; + color.g = u; + color.b = v; + break; + case DSPF_UYVY: + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + //R300_SET_YUV422_COLOR( rdrv, rdev, y, u, v ); + default: + break; + } + + /*rdev->color[0] = (float)color.r/255.0; + rdev->color[1] = (float)color.g/255.0; + rdev->color[2] = (float)color.b/255.0; + rdev->color[3] = (float)color.a/255.0;*/ + + if (R300_HAS_3DREGS()) { + u32 argb; + + argb = (state->blittingflags & DSBLIT_BLEND_COLORALPHA) ? (color.a << 24) : 0xff000000; + if (state->blittingflags & DSBLIT_COLORIZE && + state->blittingflags & (DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + argb |= PIXEL_RGB32( (long)color.r * color.a / 255L, + (long)color.g * color.a / 255L, + (long)color.b * color.a / 255L ); + } + else { + argb |= (state->blittingflags & DSBLIT_COLORIZE) + ? PIXEL_RGB32( color.r, color.g, color.b ) + : PIXEL_RGB32( color.a, color.a, color.a ); + } + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, R300_RB3D_BLENDCOLOR, argb ); + } + + RADEON_SET( COLOR ); +} + +void r300_set_src_colorkey( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 key = state->src_colorkey; + + if (RADEON_IS_SET( SRC_COLORKEY )) + return; + + switch (rdev->src_format) { + case DSPF_ARGB4444: + key |= 0xf000; + break; + case DSPF_ARGB2554: + key |= 0xc000; + break; + case DSPF_ARGB1555: + key |= 0x8000; + break; + case DSPF_ARGB: + case DSPF_AYUV: + key |= 0xff000000; + break; + default: + break; + } + + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, CLR_CMP_CLR_SRC, key ); + /* XXX: R300 seems to ignore CLR_CMP_MASK. */ + radeon_out32( mmio, CLR_CMP_MASK, rdev->src_mask ); + if (R300_HAS_3DREGS()) + radeon_out32( mmio, R300_TX_CHROMA_KEY_0, state->src_colorkey ); + + RADEON_SET( SRC_COLORKEY ); +} + +void +r300_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + u32 sblend, dblend; + + if (RADEON_IS_SET( SRC_BLEND ) && RADEON_IS_SET( DST_BLEND )) + return; + + sblend = r300SrcBlend[state->src_blend-1]; + dblend = r300DstBlend[state->dst_blend-1]; + + if (!DFB_PIXELFORMAT_HAS_ALPHA(rdev->dst_format)) { + if (sblend == SRC_BLEND_GL_DST_ALPHA) + sblend = SRC_BLEND_GL_ONE; + else if (sblend == SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) + sblend = SRC_BLEND_GL_ZERO; + + if (dblend == DST_BLEND_GL_DST_ALPHA) + dblend = DST_BLEND_GL_ONE; + else if (dblend == DST_BLEND_GL_ONE_MINUS_DST_ALPHA) + dblend = DST_BLEND_GL_ZERO; + } + + rdev->rb3d_blend = sblend | dblend; + + RADEON_UNSET( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); + RADEON_SET( SRC_BLEND ); + RADEON_SET( DST_BLEND ); +} + +void r300_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + if (RADEON_IS_SET( RENDER_OPTIONS )) + return; + + if (state->render_options & DSRO_MATRIX && + (!state->affine_matrix || + state->matrix[0] != (1<<16) || state->matrix[1] != 0 || state->matrix[2] != 0 || + state->matrix[3] != 0 || state->matrix[4] != (1<<16) || state->matrix[5] != 0)) { + rdev->matrix = state->matrix; + rdev->affine_matrix = state->affine_matrix; + } + else { + rdev->matrix = NULL; + } + + /* TODO: antialiasing */ +#if 0 + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, R300_GB_AA_CONFIG, + (state->render_options & DSRO_ANTIALIAS) ? R300_AA_ENABLE : 0 ); +#endif + rdev->render_options = state->render_options & ~DSRO_ANTIALIAS; + + RADEON_SET( RENDER_OPTIONS ); +} + +void r300_set_drawingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_SRC_DATATYPE_MONO_FG_LA | + GMC_BRUSH_SOLID_COLOR | + GMC_CLR_CMP_CNTL_DIS; + u32 rb3d_blend; + + if (RADEON_IS_SET( DRAWING_FLAGS )) + return; + + if (state->drawingflags & DSDRAW_BLEND) { + rb3d_blend = R300_BLEND_ENABLE | R300_BLEND_UNKNOWN | + R300_BLEND_NO_SEPARATE | rdev->rb3d_blend; + } + else { + rb3d_blend = R300_SRC_BLEND_GL_ONE | R300_DST_BLEND_GL_ZERO; + } + + if (state->drawingflags & DSDRAW_XOR) + master_cntl |= GMC_ROP3_PATXOR; + else + master_cntl |= GMC_ROP3_PATCOPY; + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + radeon_out32( mmio, DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM ); + + if (R300_HAS_3DREGS()) { + radeon_waitfifo( rdrv, rdev, 27 ); + radeon_out32( mmio, R300_TX_ENABLE, 0 ); + radeon_out32( mmio, R300_RE_SHADE_MODEL, R300_RE_SHADE_MODEL_FLAT ); + /* fragment program */ + radeon_out32( mmio, R300_PFS_CNTL_0, 0 ); + radeon_out32( mmio, R300_PFS_CNTL_1, 0 ); + radeon_out32( mmio, R300_PFS_CNTL_2, 0 ); + radeon_out32( mmio, R300_PFS_NODE_0, 0 ); + radeon_out32( mmio, R300_PFS_NODE_1, 0 ); + radeon_out32( mmio, R300_PFS_NODE_2, 0 ); + radeon_out32( mmio, R300_PFS_NODE_3, R300_PFS_NODE_OUTPUT_COLOR ); + radeon_out32( mmio, R300_PFS_INSTR0_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)) ); + radeon_out32( mmio, R300_PFS_INSTR1_0, + FP_SELC(0,NO,XYZ,FP_TMP(0),FP_TMP(2),FP_TMP(2)) ); + radeon_out32( mmio, R300_PFS_INSTR2_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)) ); + radeon_out32( mmio, R300_PFS_INSTR3_0, + FP_SELA(0,NO,W,FP_TMP(0),FP_TMP(2),FP_TMP(2)) ); + /* blend functions */ + radeon_out32( mmio, R300_RB3D_CBLEND, rb3d_blend ); + radeon_out32( mmio, R300_RB3D_ABLEND, rb3d_blend & 0xfffffff0 ); + /* routing */ + radeon_out32( mmio, R300_RS_CNTL_0, (0 << R300_RS_CNTL_TC_CNT_SHIFT) | + (1 << R300_RS_CNTL_CI_CNT_SHIFT) | + R300_RS_CNTL_0_UNKNOWN_18 ); + radeon_out32( mmio, R300_RS_CNTL_1, 0x000000c0 ); + radeon_out32( mmio, R300_RS_ROUTE_0, R300_RS_ROUTE_0_COLOR ); + /* input */ + radeon_out32( mmio, R300_VAP_INPUT_ROUTE_0_0, 0x21030003 ); + radeon_out32( mmio, R300_VAP_INPUT_ROUTE_1_0, 0xf688f688 ); + radeon_out32( mmio, R300_VAP_INPUT_CNTL_0, R300_INPUT_CNTL_0_COLOR ); + radeon_out32( mmio, R300_VAP_INPUT_CNTL_1, R300_INPUT_CNTL_POS | + R300_INPUT_CNTL_COLOR ); + /* output */ + radeon_out32( mmio, R300_VAP_OUTPUT_VTX_FMT_0, + R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | + R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT ); + radeon_out32( mmio, R300_VAP_OUTPUT_VTX_FMT_1, 0 ); + radeon_out32( mmio, R300_GB_VAP_RASTER_VTX_FMT_0, + R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT | + R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT ); + radeon_out32( mmio, R300_GB_VAP_RASTER_VTX_FMT_1, 0 ); + radeon_out32( mmio, R300_VAP_UNKNOWN_221C, R300_221C_CLEAR ); + } + + rdev->drawingflags = state->drawingflags; + + RADEON_SET ( DRAWING_FLAGS ); + RADEON_UNSET( BLITTING_FLAGS ); +} + +void r300_set_blittingflags( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 master_cntl = rdev->gui_master_cntl | + GMC_BRUSH_NONE | + GMC_SRC_DATATYPE_COLOR; + u32 txfilter1 = R300_TX_TRI_PERF_0_8; + u32 cmp_cntl = 0; + u32 rb3d_blend; + + if (RADEON_IS_SET( BLITTING_FLAGS )) + return; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA | + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) { + rb3d_blend = R300_BLEND_ENABLE | R300_BLEND_UNKNOWN | R300_BLEND_NO_SEPARATE; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) + rb3d_blend |= rdev->rb3d_blend; + else + rb3d_blend |= R300_SRC_BLEND_GL_ONE | R300_DST_BLEND_GL_ZERO; + + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + rb3d_blend &= ~(R300_SRC_BLEND_MASK | R300_DST_BLEND_MASK); + rb3d_blend |= R300_SRC_BLEND_GL_CONST_ALPHA | + R300_DST_BLEND_GL_ONE_MINUS_CONST_ALPHA; + } + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) { + rb3d_blend &= ~R300_SRC_BLEND_MASK; + rb3d_blend |= R300_SRC_BLEND_GL_CONST_COLOR; + } + } + else { + rb3d_blend = R300_SRC_BLEND_GL_ONE | R300_DST_BLEND_GL_ZERO; + } + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + txfilter1 |= R300_CHROMA_KEY_FORCE; + cmp_cntl = SRC_CMP_EQ_COLOR | CLR_CMP_SRC_SOURCE; + } + else { + master_cntl |= GMC_CLR_CMP_CNTL_DIS; + } + + if (state->blittingflags & DSBLIT_XOR) + master_cntl |= GMC_ROP3_XOR; + else + master_cntl |= GMC_ROP3_SRCCOPY; + + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, CLR_CMP_CNTL, cmp_cntl ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, master_cntl ); + + if (R300_HAS_3DREGS()) { + radeon_waitfifo( rdrv, rdev, 29 ); + radeon_out32( mmio, R300_TX_FILTER1_0, txfilter1 ); + radeon_out32( mmio, R300_TX_ENABLE, R300_TX_ENABLE_0 ); + if (rdev->accel == DFXL_TEXTRIANGLES) + radeon_out32( mmio, R300_RE_SHADE_MODEL, R300_RE_SHADE_MODEL_SMOOTH ); + else + radeon_out32( mmio, R300_RE_SHADE_MODEL, R300_RE_SHADE_MODEL_FLAT ); + /* fragment program */ + radeon_out32( mmio, R300_PFS_CNTL_0, R300_PFS_CNTL_FIRST_NODE_HAS_TEX ); + radeon_out32( mmio, R300_PFS_CNTL_1, 0 ); + radeon_out32( mmio, R300_PFS_CNTL_2, 0 ); + radeon_out32( mmio, R300_PFS_NODE_0, 0 ); + radeon_out32( mmio, R300_PFS_NODE_1, 0 ); + radeon_out32( mmio, R300_PFS_NODE_2, 0 ); + radeon_out32( mmio, R300_PFS_NODE_3, R300_PFS_NODE_OUTPUT_COLOR ); + radeon_out32( mmio, R300_PFS_TEXI_0, R300_FPITX_OP_TXP ); + radeon_out32( mmio, R300_PFS_INSTR0_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)) ); + radeon_out32( mmio, R300_PFS_INSTR1_0, + FP_SELC(0,NO,XYZ,FP_TMP(0),FP_TMP(2),FP_TMP(2)) ); + radeon_out32( mmio, R300_PFS_INSTR2_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)) ); + radeon_out32( mmio, R300_PFS_INSTR3_0, + FP_SELA(0,NO,W,FP_TMP(0),FP_TMP(2),FP_TMP(2)) ); + /* blend functions */ + radeon_out32( mmio, R300_RB3D_CBLEND, rb3d_blend ); + radeon_out32( mmio, R300_RB3D_ABLEND, rb3d_blend & 0xfffffff0 ); + /* routing */ + radeon_out32( mmio, R300_RS_CNTL_0, (1 << R300_RS_CNTL_TC_CNT_SHIFT) | + (0 << R300_RS_CNTL_CI_CNT_SHIFT) | + R300_RS_CNTL_0_UNKNOWN_18 ); + radeon_out32( mmio, R300_RS_CNTL_1, 0x000000c0 ); + radeon_out32( mmio, R300_RS_ROUTE_0, R300_RS_ROUTE_ENABLE ); + /* input routing */ + radeon_out32( mmio, R300_VAP_INPUT_ROUTE_0_0, 0x21030003 ); + radeon_out32( mmio, R300_VAP_INPUT_ROUTE_1_0, 0xf688f688 ); + radeon_out32( mmio, R300_VAP_INPUT_CNTL_0, 0x5555 ); + radeon_out32( mmio, R300_VAP_INPUT_CNTL_1, R300_INPUT_CNTL_POS | + R300_INPUT_CNTL_TC0 ); + /* output routing */ + radeon_out32( mmio, R300_VAP_OUTPUT_VTX_FMT_0, + R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT ); + radeon_out32( mmio, R300_VAP_OUTPUT_VTX_FMT_1, 4 ); + radeon_out32( mmio, R300_GB_VAP_RASTER_VTX_FMT_0, + R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT ); + radeon_out32( mmio, R300_GB_VAP_RASTER_VTX_FMT_1, 4 ); + radeon_out32( mmio, R300_VAP_UNKNOWN_221C, R300_221C_CLEAR ); + } + + rdev->blittingflags = state->blittingflags; + + RADEON_SET ( BLITTING_FLAGS ); + RADEON_UNSET( DRAWING_FLAGS ); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon.c b/Source/DirectFB/gfxdrivers/radeon/radeon.c new file mode 100755 index 0000000..19f8c49 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon.c @@ -0,0 +1,1753 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( radeon ) + + +#include "radeon.h" +#include "radeon_chipsets.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_state.h" +#include "radeon_2d.h" +#include "radeon_3d.h" + + +/* Enable the following option if you see strange behaviours */ +#define RESET_AFTER_SETVAR 0 + + +/* Driver capability flags */ +#define RADEON_SUPPORTED_2D_DRAWINGFLAGS \ + ( DSDRAW_XOR ) + +#define RADEON_SUPPORTED_2D_DRAWINGFUNCS \ + ( DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE ) + +#define RADEON_SUPPORTED_2D_BLITTINGFLAGS \ + ( DSBLIT_XOR | DSBLIT_SRC_COLORKEY ) + +#define RADEON_SUPPORTED_2D_BLITTINGFUNCS \ + ( DFXL_BLIT ) + + +#define R100_SUPPORTED_DRAWINGFLAGS \ + ( RADEON_SUPPORTED_2D_DRAWINGFLAGS | DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY ) + +#define R100_SUPPORTED_DRAWINGFUNCS \ + ( RADEON_SUPPORTED_2D_DRAWINGFUNCS | DFXL_FILLTRIANGLE ) + +#define R100_SUPPORTED_BLITTINGFLAGS \ + ( RADEON_SUPPORTED_2D_BLITTINGFLAGS | \ + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE | DSBLIT_ROTATE180 | \ + DSBLIT_SRC_MASK_ALPHA | DSBLIT_SRC_MASK_COLOR | \ + DSBLIT_SRC_PREMULTIPLY ) + +#define R100_SUPPORTED_BLITTINGFUNCS \ + ( RADEON_SUPPORTED_2D_BLITTINGFUNCS | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES ) + + +#define R200_SUPPORTED_DRAWINGFLAGS \ + ( RADEON_SUPPORTED_2D_DRAWINGFLAGS | DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY ) + +#define R200_SUPPORTED_DRAWINGFUNCS \ + ( RADEON_SUPPORTED_2D_DRAWINGFUNCS | DFXL_FILLTRIANGLE ) + +#define R200_SUPPORTED_BLITTINGFLAGS \ + ( RADEON_SUPPORTED_2D_BLITTINGFLAGS | \ + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE | DSBLIT_ROTATE180 | \ + DSBLIT_SRC_MASK_ALPHA | DSBLIT_SRC_MASK_COLOR | \ + DSBLIT_SRC_PREMULTIPLY ) + +#define R200_SUPPORTED_BLITTINGFUNCS \ + ( RADEON_SUPPORTED_2D_BLITTINGFUNCS | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES ) + + +#define R300_SUPPORTED_DRAWINGFLAGS \ + ( RADEON_SUPPORTED_2D_DRAWINGFLAGS | DSDRAW_BLEND | DSDRAW_SRC_PREMULTIPLY ) + +#define R300_SUPPORTED_DRAWINGFUNCS \ + ( RADEON_SUPPORTED_2D_DRAWINGFUNCS | DFXL_FILLTRIANGLE ) + +#define R300_SUPPORTED_BLITTINGFLAGS \ + ( RADEON_SUPPORTED_2D_BLITTINGFLAGS | \ + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE | DSBLIT_ROTATE180 ) + +#define R300_SUPPORTED_BLITTINGFUNCS \ + ( RADEON_SUPPORTED_2D_BLITTINGFUNCS | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES ) + + +#define DSBLIT_MODULATE_ALPHA ( DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA ) +#define DSBLIT_MODULATE_COLOR ( DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_SRC_PREMULTCOLOR ) +#define DSBLIT_MODULATE ( DSBLIT_MODULATE_ALPHA | \ + DSBLIT_MODULATE_COLOR | \ + DSBLIT_SRC_PREMULTIPLY ) +#define DSBLIT_MASK ( DSBLIT_SRC_MASK_ALPHA | \ + DSBLIT_SRC_MASK_COLOR ) + +#define RADEON_DRAW_3D() ( rdev->accel & DFXL_FILLTRIANGLE || \ + rdev->drawingflags & ~DSDRAW_XOR || \ + rdev->matrix != NULL || \ + (rdev->render_options & DSRO_ANTIALIAS && \ + rdev->accel & DFXL_DRAWLINE) ) + +#define RADEON_BLIT_3D() ( rdev->accel & ~DFXL_BLIT ||\ + rdev->blittingflags & ~(DSBLIT_XOR | \ + DSBLIT_SRC_COLORKEY) || \ + rdev->matrix != NULL || \ + (rdev->dst_format != rdev->src_format && \ + !(DFB_PLANAR_PIXELFORMAT(rdev->dst_format) && \ + DFB_PLANAR_PIXELFORMAT(rdev->src_format) ))) + +#define RADEON_FUNC( f ) DFB_PLANAR_PIXELFORMAT(rdev->dst_format) ? f##_420 : f + + +static inline bool +radeon_compatible_format( RadeonDriverData *rdrv, DFBSurfacePixelFormat format ) +{ +#ifdef WORDS_BIGENDIAN + u32 tmp, bpp; + + bpp = DFB_BYTES_PER_PIXEL( format ); + tmp = radeon_in32( rdrv->mmio_base, CRTC_GEN_CNTL ); + switch ((tmp >> 8) & 0xf) { + case DST_8BPP: + case DST_24BPP: + if (bpp == 2 || bpp == 4) + return false; + break; + case DST_15BPP: + case DST_16BPP: + if (bpp != 2) + return false; + break; + default: + if (bpp != 4) + return false; + break; + } +#endif + return true; +} + +static void +radeon_get_monitors( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + RadeonMonitorType *ret_monitor1, + RadeonMonitorType *ret_monitor2 ) +{ + RadeonMonitorType dvimon = MT_NONE; + RadeonMonitorType vgamon = MT_NONE; +#if D_DEBUG_ENABLED + const char *name[] = { "NONE", "CRT", "DFP", + "LCD", "CTV", "STV" }; +#endif + u32 tmp; + + if (rdev->chipset != CHIP_R100) { + if (rdev->chipset >= CHIP_R300 || + rdev->chipset == CHIP_UNKNOWN) + tmp = radeon_in32( rdrv->mmio_base, BIOS_0_SCRATCH ); + else + tmp = radeon_in32( rdrv->mmio_base, BIOS_4_SCRATCH ); + + /* DVI/TVO port */ + if (tmp & 0x08) + dvimon = MT_DFP; + else if (tmp & 0x4) + dvimon = MT_LCD; + else if (tmp & 0x200) + dvimon = MT_CRT; + else if (tmp & 0x10) + dvimon = MT_CTV; + else if (tmp & 0x20) + dvimon = MT_STV; + + /* VGA port */ + if (tmp & 0x2) + vgamon = MT_CRT; + else if (tmp & 0x800) + vgamon = MT_DFP; + else if (tmp & 0x400) + vgamon = MT_LCD; + else if (tmp & 0x1000) + vgamon = MT_CTV; + else if (tmp & 0x2000) + vgamon = MT_STV; + } + else { + tmp = radeon_in32( rdrv->mmio_base, FP_GEN_CNTL ); + + if (tmp & FP_EN_TMDS) + vgamon = MT_DFP; + else + vgamon = MT_CRT; + } + + D_DEBUG( "DirectFB/Radeon: " + "DVI/TVO Port -> %s, VGA Port -> %s.\n", + name[dvimon], name[vgamon] ); + + if (dvimon) { + /* If DVI port is connected, then + * DVI port is the primary head and + * CRT port is the secondary head. + */ + if (ret_monitor1) + *ret_monitor1 = dvimon; + if (ret_monitor2) + *ret_monitor2 = vgamon; + } + else { + if (ret_monitor1) + *ret_monitor1 = vgamon; + if (ret_monitor2) + *ret_monitor2 = MT_NONE; + } +} + +void +radeon_reset( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 clock_cntl_index; + u32 mclk_cntl; + u32 rbbm_soft_reset; + u32 host_path_cntl; + + clock_cntl_index = radeon_in32( mmio, CLOCK_CNTL_INDEX ); + + mclk_cntl = radeon_inpll( mmio, MCLK_CNTL ); + radeon_outpll( mmio, MCLK_CNTL, mclk_cntl | + FORCEON_MCLKA | + FORCEON_MCLKB | + FORCEON_YCLKA | + FORCEON_YCLKB | + FORCEON_MC | + FORCEON_AIC ); + + host_path_cntl = radeon_in32( mmio, HOST_PATH_CNTL ); + rbbm_soft_reset = radeon_in32( mmio, RBBM_SOFT_RESET ); + + radeon_out32( mmio, RBBM_SOFT_RESET, rbbm_soft_reset | + SOFT_RESET_CP | SOFT_RESET_HI | + SOFT_RESET_SE | SOFT_RESET_RE | + SOFT_RESET_PP | SOFT_RESET_E2 | + SOFT_RESET_RB ); + radeon_in32( mmio, RBBM_SOFT_RESET ); + + radeon_out32( mmio, RBBM_SOFT_RESET, rbbm_soft_reset & + ~(SOFT_RESET_CP | SOFT_RESET_HI | + SOFT_RESET_SE | SOFT_RESET_RE | + SOFT_RESET_PP | SOFT_RESET_E2 | + SOFT_RESET_RB) ); + radeon_in32( mmio, RBBM_SOFT_RESET ); + + radeon_out32( mmio, HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET ); + radeon_in32( mmio, HOST_PATH_CNTL ); + radeon_out32( mmio, HOST_PATH_CNTL, host_path_cntl ); + + radeon_out32( mmio, RBBM_SOFT_RESET, rbbm_soft_reset ); + + radeon_out32( mmio, CLOCK_CNTL_INDEX, clock_cntl_index ); + radeon_outpll( mmio, MCLK_CNTL, mclk_cntl ); + + rdev->set = 0; + rdev->src_format = DSPF_UNKNOWN; + rdev->dst_format = DSPF_UNKNOWN; + rdev->fifo_space = 0; +} + +static void radeonAfterSetVar( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + volatile u8 *mmio = rdrv->mmio_base; + + rdev->surface_cntl = + rdev->surface_cntl_c = + rdev->surface_cntl_p = radeon_in32( mmio, SURFACE_CNTL ); + + radeon_out32( mmio, CRTC_OFFSET_CNTL, + (radeon_in32( mmio, CRTC_OFFSET_CNTL ) & ~CRTC_TILE_EN) | CRTC_HSYNC_EN ); + +#if RESET_AFTER_SETVAR + radeon_waitidle( rdrv, rdev ); + radeon_reset( rdrv, rdev ); +#endif +} + +static void radeonEngineReset( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + volatile u8 *mmio = rdrv->mmio_base; + + rdev->fifo_space = 0; + + radeon_out32( mmio, SURFACE_CNTL, rdev->surface_cntl_c ); + + radeon_waitfifo( rdrv, rdev, 3 ); +#ifdef WORDS_BIGENDIAN + radeon_out32( mmio, DP_DATATYPE, + radeon_in32( mmio, DP_DATATYPE ) | HOST_BIG_ENDIAN_EN ); +#else + radeon_out32( mmio, DP_DATATYPE, + radeon_in32( mmio, DP_DATATYPE ) & ~HOST_BIG_ENDIAN_EN ); +#endif + radeon_out32( mmio, DEFAULT_SC_BOTTOM_RIGHT, DEFAULT_SC_RIGHT_MAX | + DEFAULT_SC_BOTTOM_MAX ); + radeon_out32( mmio, AUX_SC_CNTL, 0 ); + + if (rdev->chipset >= CHIP_R300) { + r300_restore( rdrv, rdev ); + } + else if (rdev->chipset >= CHIP_R200) { + r200_restore( rdrv, rdev ); + } + else if (rdev->chipset >= CHIP_R100) { + r100_restore( rdrv, rdev ); + } + + /* sync 2d and 3d engines */ + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, ISYNC_CNTL, ISYNC_ANY2D_IDLE3D | + ISYNC_ANY3D_IDLE2D ); +} + +static DFBResult radeonEngineSync( void *drv, void *dev ) +{ + if (!radeon_waitidle( (RadeonDriverData*)drv, (RadeonDeviceData*)dev )) + return DFB_IO; /* DFB_TIMEOUT !? */ + + return DFB_OK; +} + +static void radeonInvalidateState( void *drv, void *dev ) +{ + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + rdev->set = 0; + rdev->dst_format = DSPF_UNKNOWN; + rdev->src_format = DSPF_UNKNOWN; + rdev->msk_format = DSPF_UNKNOWN; +} + +static void radeonFlushTextureCache( void *drv, void *dev ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + volatile u8 *mmio = rdrv->mmio_base; + + if (rdev->chipset >= CHIP_R300) { + if (rdrv->mmio_size > 0x4000) { + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, R300_TX_CNTL, 0 ); + } + } + else if (rdev->chipset >= CHIP_R200) { + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, R200_PP_TXOFFSET_0, rdev->src_offset ); + radeon_out32( mmio, R200_PP_TXOFFSET_1, rdev->msk_offset ); + } + else if (rdev->chipset >= CHIP_R100) { + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, PP_TXOFFSET_0, rdev->src_offset ); + radeon_out32( mmio, PP_TXOFFSET_1, rdev->msk_offset ); + } +} + +#ifdef WORDS_BIGENDIAN +static void radeonSurfaceEnter( void *drv, void *dev, + CoreSurfaceBuffer *buffer, DFBSurfaceLockFlags flags ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + volatile u8 *mmio = rdrv->mmio_base; + u32 tmp; + + if (!(flags & DSLF_WRITE)) + return; + + rdev->surface_cntl_p = radeon_in32( mmio, SURFACE_CNTL ); + + tmp = rdev->surface_cntl_p & ~SURF_TRANSLATION_DIS; + tmp &= ~(NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP | + NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP); + + switch (DFB_BITS_PER_PIXEL( buffer->format )) { + case 16: + tmp |= NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; + break; + case 32: + tmp |= NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; + break; + default: + break; + } + + radeon_out32( mmio, SURFACE_CNTL, tmp ); + rdev->surface_cntl_c = tmp; +} + +static void radeonSurfaceLeave( void *drv, void *dev, CoreSurfaceBuffer *buffer ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + volatile u8 *mmio = rdrv->mmio_base; + + if (rdev->surface_cntl_p != rdev->surface_cntl_c) { + radeon_out32( mmio, SURFACE_CNTL, rdev->surface_cntl_p ); + rdev->surface_cntl_c = rdev->surface_cntl_p; + } +} +#endif + +static void r100CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + int supported_drawingfuncs = R100_SUPPORTED_DRAWINGFUNCS; + int supported_drawingflags = R100_SUPPORTED_DRAWINGFLAGS; + int supported_blittingfuncs = R100_SUPPORTED_BLITTINGFUNCS; + int supported_blittingflags = R100_SUPPORTED_BLITTINGFLAGS; + + if (!radeon_compatible_format( drv, destination->config.format )) + return; + + switch (destination->config.format) { + case DSPF_A8: + if (state->src_blend == DSBF_SRCALPHASAT) { + supported_drawingflags &= ~DSDRAW_BLEND; + supported_blittingflags &= ~DSBLIT_MODULATE_ALPHA; + } + break; + + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != destination->config.format) + return; + supported_drawingflags = DSDRAW_NOFX; + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + supported_blittingflags = ~(DSBLIT_MODULATE | DSBLIT_MASK); + break; + + case DSPF_ARGB2554: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != destination->config.format) + return; + supported_drawingfuncs &= ~DFXL_FILLTRIANGLE; + supported_drawingflags = DSDRAW_XOR; + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + supported_blittingflags &= ~(DSBLIT_MODULATE | DSBLIT_MASK); + break; + + case DSPF_AiRGB: + supported_drawingflags &= ~DSDRAW_BLEND; + supported_blittingflags &= ~DSBLIT_MODULATE_ALPHA; + break; + + case DSPF_I420: + case DSPF_YV12: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != DSPF_A8 && + source->config.format != DSPF_I420 && + source->config.format != DSPF_YV12) + return; + case DSPF_YUY2: + case DSPF_UYVY: + if (source && source->config.format != DSPF_A8) + supported_blittingflags &= ~(DSBLIT_COLORIZE | DSBLIT_SRC_COLORKEY | DSBLIT_MASK); + break; + + case DSPF_AYUV: + if (DFB_BLITTING_FUNCTION( accel ) && source->config.format != DSPF_A8) { + if (source->config.format != DSPF_AYUV) + return; + supported_blittingflags &= ~(DSBLIT_COLORIZE | DSBLIT_MASK); + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + if (state->blittingflags & DSBLIT_MASK || + state->blittingflags & DSBLIT_SRC_PREMULTIPLY) { + if (state->blittingflags & DSBLIT_MASK && + state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + return; + } + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + if (destination->config.format != source->config.format) + return; + supported_blittingfuncs = DFXL_BLIT; + supported_blittingflags &= DSBLIT_SRC_COLORKEY | DSBLIT_XOR; + } + + if (state->blittingflags & DSBLIT_ROTATE180) + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + + if (accel & ~supported_blittingfuncs || + state->blittingflags & ~supported_blittingflags) + return; + + if (source->config.size.w > 2048 || source->config.size.h > 2048) + return; + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + if (!radeon_compatible_format( drv, source->config.format )) + return; + + switch (source->config.format) { + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + if (destination->config.format == DSPF_UYVY || + destination->config.format == DSPF_YUY2) + return; + case DSPF_A8: + case DSPF_YUY2: + case DSPF_UYVY: + break; + + case DSPF_AiRGB: + if (destination->config.format != source->config.format && + (DFB_PIXELFORMAT_HAS_ALPHA(destination->config.format) || + destination->config.format == DSPF_UYVY || + destination->config.format == DSPF_YUY2)) + return; + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_ARGB2554: + case DSPF_AYUV: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_I420: + case DSPF_YV12: + if (source->config.size.w < 2 || source->config.size.h < 2) + return; + if (destination->config.format != DSPF_I420 && + destination->config.format != DSPF_YV12) + return; + break; + + default: + return; + } + + if (state->blittingflags & DSBLIT_MASK) { + CoreSurface *mask = state->source_mask; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + return; + + if (state->src_mask_flags & DSMF_STENCIL || + state->src_mask_offset.x || state->src_mask_offset.y) + return; + + if (mask->config.size.w > 2048 || mask->config.size.h > 2048) + return; + + if (!radeon_compatible_format( drv, mask->config.format )) + return; + + switch (mask->config.format) { + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_AiRGB: + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA && + DFB_PIXELFORMAT_HAS_ALPHA(source->config.format) && + source->config.format != DSPF_AiRGB) + return; + break; + + default: + return; + } + } + + state->accel |= supported_blittingfuncs; + rdev->blitting_mask = supported_blittingfuncs; + } + else { + if (accel & ~supported_drawingfuncs || + state->drawingflags & ~supported_drawingflags) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + state->accel |= supported_drawingfuncs; + rdev->drawing_mask = supported_drawingfuncs; + } +} + +static void r200CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + int supported_drawingfuncs = R200_SUPPORTED_DRAWINGFUNCS; + int supported_drawingflags = R200_SUPPORTED_DRAWINGFLAGS; + int supported_blittingfuncs = R200_SUPPORTED_BLITTINGFUNCS; + int supported_blittingflags = R200_SUPPORTED_BLITTINGFLAGS; + + if (!radeon_compatible_format( drv, destination->config.format )) + return; + + switch (destination->config.format) { + case DSPF_A8: + if (state->src_blend == DSBF_SRCALPHASAT) { + supported_drawingflags &= ~DSDRAW_BLEND; + supported_blittingflags &= ~DSBLIT_MODULATE_ALPHA; + } + break; + + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != destination->config.format) + return; + supported_drawingflags = DSDRAW_NOFX; + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + supported_blittingflags &= ~(DSBLIT_MODULATE | DSBLIT_MASK); + break; + + case DSPF_ARGB2554: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != destination->config.format) + return; + supported_drawingfuncs &= ~DFXL_FILLTRIANGLE; + supported_drawingflags = DSDRAW_XOR; + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + supported_blittingflags &= ~(DSBLIT_MODULATE | DSBLIT_MASK); + break; + + case DSPF_AiRGB: + supported_drawingflags &= ~DSDRAW_BLEND; + supported_blittingflags &= ~DSBLIT_MODULATE_ALPHA; + break; + + case DSPF_I420: + case DSPF_YV12: + if (DFB_BLITTING_FUNCTION( accel ) && + source->config.format != DSPF_A8 && + source->config.format != DSPF_I420 && + source->config.format != DSPF_YV12) + return; + case DSPF_YUY2: + case DSPF_UYVY: + if (source && source->config.format != DSPF_A8) + supported_blittingflags &= ~(DSBLIT_COLORIZE | DSBLIT_SRC_COLORKEY | DSBLIT_MASK); + break; + + case DSPF_AYUV: + if (DFB_BLITTING_FUNCTION( accel ) && source->config.format != DSPF_A8) { + if (source->config.format != DSPF_AYUV) + return; + supported_blittingflags &= ~(DSBLIT_COLORIZE | DSBLIT_MASK); + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + if (state->blittingflags & DSBLIT_MASK || + state->blittingflags & DSBLIT_SRC_PREMULTIPLY) { + if (state->blittingflags & DSBLIT_MASK && + state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + return; + } + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + if (destination->config.format != source->config.format) + return; + supported_blittingfuncs = DFXL_BLIT; + supported_blittingflags &= DSBLIT_SRC_COLORKEY | DSBLIT_XOR; + } + + if (state->blittingflags & DSBLIT_ROTATE180) + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + + if (accel & ~supported_blittingfuncs || + state->blittingflags & ~supported_blittingflags) + return; + + if (source->config.size.w > 2048 || source->config.size.h > 2048) + return; + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + if (!radeon_compatible_format( drv, source->config.format )) + return; + + switch (source->config.format) { + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + if (destination->config.format == DSPF_UYVY || + destination->config.format == DSPF_YUY2) + return; + case DSPF_A8: + break; + + case DSPF_AiRGB: + if (destination->config.format != source->config.format && + (DFB_PIXELFORMAT_HAS_ALPHA(destination->config.format) || + destination->config.format == DSPF_UYVY || + destination->config.format == DSPF_YUY2)) + return; + if (state->blittingflags & DSBLIT_SRC_PREMULTIPLY) + return; + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_ARGB2554: + case DSPF_AYUV: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (rdev->chipset == CHIP_RV250 && + destination->config.format != DSPF_YUY2 && + destination->config.format != DSPF_UYVY) + return; + break; + + case DSPF_I420: + case DSPF_YV12: + if (source->config.size.w < 2 || source->config.size.h < 2) + return; + if (destination->config.format != DSPF_I420 && + destination->config.format != DSPF_YV12) + return; + break; + + default: + return; + } + + if (state->blittingflags & DSBLIT_MASK) { + CoreSurface *mask = state->source_mask; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) + return; + + if (state->src_mask_flags & DSMF_STENCIL || + state->src_mask_offset.x || state->src_mask_offset.y) + return; + + if (mask->config.size.w > 2048 || mask->config.size.h > 2048) + return; + + if (!radeon_compatible_format( drv, mask->config.format )) + return; + + switch (mask->config.format) { + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_AiRGB: + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA && + DFB_PIXELFORMAT_HAS_ALPHA(source->config.format) && + source->config.format != DSPF_AiRGB) + return; + break; + + default: + return; + } + } + + state->accel |= supported_blittingfuncs; + rdev->blitting_mask = supported_blittingfuncs; + } + else { + if (accel & ~supported_drawingfuncs || + state->drawingflags & ~supported_drawingflags) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + state->accel |= supported_drawingfuncs; + rdev->drawing_mask = supported_drawingfuncs; + } +} + +static void r300CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + bool can_convert = true; + + int supported_drawingfuncs = R300_SUPPORTED_DRAWINGFUNCS; + int supported_drawingflags = R300_SUPPORTED_DRAWINGFLAGS; + int supported_blittingfuncs = R300_SUPPORTED_BLITTINGFUNCS; + int supported_blittingflags = R300_SUPPORTED_BLITTINGFLAGS; + if (rdrv->mmio_size <= 0x4000) { + supported_drawingfuncs = RADEON_SUPPORTED_2D_DRAWINGFUNCS; + supported_drawingflags = RADEON_SUPPORTED_2D_DRAWINGFLAGS; + supported_blittingfuncs = RADEON_SUPPORTED_2D_BLITTINGFUNCS; + supported_blittingflags = RADEON_SUPPORTED_2D_BLITTINGFLAGS; + can_convert = false; + } + + if (!radeon_compatible_format( drv, destination->config.format )) + return; + + switch (destination->config.format) { + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_ARGB2554: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_AiRGB: + case DSPF_AYUV: + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (source->config.format != destination->config.format) + return; + } + supported_drawingfuncs &= ~DFXL_FILLTRIANGLE; + supported_drawingflags = DSDRAW_NOFX; + supported_blittingfuncs = DFXL_BLIT; + supported_blittingflags = DSBLIT_NOFX; + break; + + case DSPF_I420: + case DSPF_YV12: + if (DFB_BLITTING_FUNCTION( accel )) { + if (source->config.format != DSPF_I420 && + source->config.format != DSPF_YV12) + return; + } + supported_drawingfuncs &= ~DFXL_FILLTRIANGLE; + supported_drawingflags = DSDRAW_XOR; + supported_blittingflags = DSBLIT_DEINTERLACE; + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + if (state->blittingflags & DSBLIT_XOR) { + can_convert = false; + supported_blittingfuncs = DFXL_BLIT; + supported_blittingflags &= DSBLIT_SRC_COLORKEY | DSBLIT_XOR; + } + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + return; + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) { + if (state->src_blend != DSBF_ONE) + return; + } + } + + if (state->blittingflags & DSBLIT_ROTATE180) + supported_blittingfuncs &= ~DFXL_TEXTRIANGLES; + + if (accel & ~supported_blittingfuncs || + state->blittingflags & ~supported_blittingflags) + return; + + if (source->config.size.w > 2048 || source->config.size.h > 2048) + return; + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + if (!radeon_compatible_format( drv, source->config.format )) + return; + + switch (source->config.format) { + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB444: + case DSPF_ARGB4444: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + if (!can_convert && + destination->config.format != source->config.format) + return; + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_ARGB2554: + case DSPF_AiRGB: + case DSPF_AYUV: + case DSPF_YUY2: + case DSPF_UYVY: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_I420: + case DSPF_YV12: + if (source->config.size.w < 2 || source->config.size.h < 2) + return; + if (destination->config.format != DSPF_I420 && + destination->config.format != DSPF_YV12) + return; + break; + + default: + return; + } + + state->accel |= supported_blittingfuncs; + rdev->blitting_mask = supported_blittingfuncs; + } + else { + if (state->drawingflags & DSDRAW_XOR) { + supported_drawingfuncs &= ~DFXL_FILLTRIANGLE; + supported_drawingflags &= DSDRAW_XOR; + } + + if (accel & ~supported_drawingfuncs || + state->drawingflags & ~supported_drawingflags) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->dst_blend == DSBF_SRCALPHASAT) + return; + + state->accel |= supported_drawingfuncs; + rdev->drawing_mask = supported_drawingfuncs; + } +} + +static void r100SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + rdev->set &= ~state->mod_hw; + if (DFB_BLITTING_FUNCTION( accel )) { + if ((rdev->accel ^ accel) & DFXL_TEXTRIANGLES) + rdev->set &= ~SMF_BLITTING_FLAGS; + } + + rdev->accel = accel; + + r100_set_destination( rdrv, rdev, state ); + r100_set_clip( rdrv, rdev, state ); + r100_set_render_options( rdrv, rdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + r100_set_drawing_color( rdrv, rdev, state ); + + if (state->drawingflags & DSDRAW_BLEND) + r100_set_blend_function( rdrv, rdev, state ); + + r100_set_drawingflags( rdrv, rdev, state ); + + if (RADEON_DRAW_3D()) { + funcs->FillRectangle = r100FillRectangle3D; + funcs->FillTriangle = r100FillTriangle; + funcs->DrawRectangle = r100DrawRectangle3D; + funcs->DrawLine = r100DrawLine3D; + funcs->EmitCommands = r100EmitCommands3D; + } else { + funcs->FillRectangle = RADEON_FUNC(radeonFillRectangle2D); + funcs->FillTriangle = NULL; + funcs->DrawRectangle = RADEON_FUNC(radeonDrawRectangle2D); + funcs->DrawLine = RADEON_FUNC(radeonDrawLine2D); + funcs->EmitCommands = NULL; + } + + state->set = rdev->drawing_mask; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + r100_set_source( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MASK) + r100_set_source_mask( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA) + r100_set_blend_function( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_COLOR) + r100_set_blitting_color( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + r100_set_src_colorkey( rdrv, rdev, state ); + + r100_set_blittingflags( rdrv, rdev, state ); + + if (RADEON_BLIT_3D()) { + funcs->Blit = r100Blit3D; + funcs->StretchBlit = r100StretchBlit; + funcs->TextureTriangles = r100TextureTriangles; + funcs->EmitCommands = r100EmitCommands3D; + } else { + funcs->Blit = RADEON_FUNC(radeonBlit2D); + funcs->StretchBlit = NULL; + funcs->TextureTriangles = NULL; + funcs->EmitCommands = NULL; + } + + state->set = (accel & DFXL_TEXTRIANGLES) + ? : (rdev->blitting_mask & ~DFXL_TEXTRIANGLES); + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void r200SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + rdev->set &= ~state->mod_hw; + if (DFB_BLITTING_FUNCTION( accel )) { + if ((rdev->accel ^ accel) & DFXL_TEXTRIANGLES) + rdev->set &= ~SMF_BLITTING_FLAGS; + } + + rdev->accel = accel; + + r200_set_destination( rdrv, rdev, state ); + r200_set_clip( rdrv, rdev, state ); + r200_set_render_options( rdrv, rdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + r200_set_drawing_color( rdrv, rdev, state ); + + if (state->drawingflags & DSDRAW_BLEND) + r200_set_blend_function( rdrv, rdev, state ); + + r200_set_drawingflags( rdrv, rdev, state ); + + if (RADEON_DRAW_3D()) { + funcs->FillRectangle = r200FillRectangle3D; + funcs->FillTriangle = r200FillTriangle; + funcs->DrawRectangle = r200DrawRectangle3D; + funcs->DrawLine = r200DrawLine3D; + funcs->EmitCommands = r200EmitCommands3D; + } else { + funcs->FillRectangle = RADEON_FUNC(radeonFillRectangle2D); + funcs->FillTriangle = NULL; + funcs->DrawRectangle = RADEON_FUNC(radeonDrawRectangle2D); + funcs->DrawLine = RADEON_FUNC(radeonDrawLine2D); + funcs->EmitCommands = NULL; + } + + state->set = rdev->drawing_mask; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + r200_set_source( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MASK) + r200_set_source_mask( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA) + r200_set_blend_function( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_COLOR) + r200_set_blitting_color( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + r200_set_src_colorkey( rdrv, rdev, state ); + + r200_set_blittingflags( rdrv, rdev, state ); + + if (RADEON_BLIT_3D()) { + funcs->Blit = r200Blit3D; + funcs->StretchBlit = r200StretchBlit; + funcs->TextureTriangles = r200TextureTriangles; + funcs->EmitCommands = r200EmitCommands3D; + } else { + funcs->Blit = RADEON_FUNC(radeonBlit2D); + funcs->StretchBlit = NULL; + funcs->TextureTriangles = NULL; + funcs->EmitCommands = NULL; + } + + state->set = (accel & DFXL_TEXTRIANGLES) + ? : (rdev->blitting_mask & ~DFXL_TEXTRIANGLES); + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void r300SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + rdev->set &= ~state->mod_hw; + if (DFB_BLITTING_FUNCTION( accel )) { + if ((rdev->accel ^ accel) & DFXL_TEXTRIANGLES) + rdev->set &= ~SMF_BLITTING_FLAGS; + } + + rdev->accel = accel; + + r300_set_destination( rdrv, rdev, state ); + r300_set_clip( rdrv, rdev, state ); + r300_set_render_options( rdrv, rdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + r300_set_drawing_color( rdrv, rdev, state ); + + if (state->drawingflags & DSDRAW_BLEND) + r300_set_blend_function( rdrv, rdev, state ); + + r300_set_drawingflags( rdrv, rdev, state ); + + if (RADEON_DRAW_3D()) { + funcs->FillRectangle = r300FillRectangle3D; + funcs->FillTriangle = r300FillTriangle; + funcs->DrawRectangle = r300DrawRectangle3D; + funcs->DrawLine = r300DrawLine3D; + funcs->EmitCommands = r300EmitCommands3D; + } else { + funcs->FillRectangle = RADEON_FUNC(radeonFillRectangle2D); + funcs->FillTriangle = NULL; + funcs->DrawRectangle = RADEON_FUNC(radeonDrawRectangle2D); + funcs->DrawLine = RADEON_FUNC(radeonDrawLine2D); + funcs->EmitCommands = NULL; + } + + state->set = rdev->drawing_mask; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + r300_set_source( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA) + r300_set_blend_function( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_COLOR) + r300_set_blitting_color( rdrv, rdev, state ); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + r300_set_src_colorkey( rdrv, rdev, state ); + + r300_set_blittingflags( rdrv, rdev, state ); + + if (RADEON_BLIT_3D()) { + funcs->Blit = r300Blit3D; + funcs->StretchBlit = r300StretchBlit; + funcs->TextureTriangles = r300TextureTriangles; + funcs->EmitCommands = r300EmitCommands3D; + } else { + funcs->Blit = RADEON_FUNC(radeonBlit2D); + funcs->StretchBlit = NULL; + funcs->TextureTriangles = NULL; + funcs->EmitCommands = NULL; + } + + state->set = (accel & DFXL_TEXTRIANGLES) + ? : (rdev->blitting_mask & ~DFXL_TEXTRIANGLES); + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + + +/* chipset detection */ + +static int +radeon_find_chipset( RadeonDriverData *rdrv, int *ret_devid, int *ret_index ) +{ + volatile u8 *mmio = rdrv->mmio_base; + unsigned int vendor_id; + unsigned int device_id; + int i; + + vendor_id = radeon_in16( mmio, CONFIG_VENDOR_ID ); + device_id = radeon_in16( mmio, CONFIG_DEVICE_ID ); + if (vendor_id != 0x1002 || !device_id) + dfb_system_get_deviceid( &vendor_id, &device_id ); + + if (vendor_id == 0x1002) { + if (ret_devid) + *ret_devid = device_id; + + for (i = 0; i < D_ARRAY_SIZE( dev_table ); i++) { + if ((unsigned int)dev_table[i].id == device_id) { + if (ret_index) + *ret_index = i; + return 1; + } + } + } + + return 0; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_ATI_RADEON: + return 1; + default: + break; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "ATI Radeon Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Claudio Ciccani" ); + + snprintf( info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL" ); + + snprintf( info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org" ); + + info->version.major = 1; + info->version.minor = 2; + + info->driver_data_size = sizeof(RadeonDriverData); + info->device_data_size = sizeof(RadeonDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonChipsetFamily chip = CHIP_UNKNOWN; + int idx; + + rdrv->device_data = (RadeonDeviceData*) device_data; + + /* gain access to memory mapped registers */ + rdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, 0x4000 ); + if (!rdrv->mmio_base) + return DFB_IO; + rdrv->mmio_size = 0x4000; + + rdrv->fb_base = dfb_gfxcard_memory_virtual( device, 0 ); + + if (radeon_find_chipset( rdrv, NULL, &idx )) + chip = dev_table[idx].chip; + + if (chip >= CHIP_R300 && !getenv( "R300_DISABLE_3D" )) { + volatile void *base; + /* increase amount of memory mapped registers */ + base = dfb_gfxcard_map_mmio( device, 0, 0x8000 ); + if (!base) { + D_ERROR( "DirectFB/Radeon: You are running a buggy version of radeonfb!\n" + " -> Please, apply the kernel patch named radeonfb-r300fix.\n" ); + D_INFO( "DirectFB/Radeon: 3D Acceleration will be disabled.\n" ); + } + else { + rdrv->mmio_base = base; + rdrv->mmio_size = 0x8000; + } + } + + /* fill function table */ + funcs->AfterSetVar = radeonAfterSetVar; + funcs->EngineReset = radeonEngineReset; + funcs->EngineSync = radeonEngineSync; + funcs->InvalidateState = radeonInvalidateState; + funcs->FlushTextureCache = radeonFlushTextureCache; +#ifdef WORDS_BIGENDIAN + funcs->SurfaceEnter = radeonSurfaceEnter; + funcs->SurfaceLeave = radeonSurfaceLeave; +#endif + + if (chip >= CHIP_R300) { + funcs->CheckState = r300CheckState; + funcs->SetState = r300SetState; + } + else if (chip >= CHIP_R200) { + funcs->CheckState = r200CheckState; + funcs->SetState = r200SetState; + } + else if (chip >= CHIP_R100) { + funcs->CheckState = r100CheckState; + funcs->SetState = r100SetState; + } + + /* primary screen */ + dfb_screens_hook_primary( device, driver_data, + &RadeonCrtc1ScreenFuncs, + &OldPrimaryScreenFuncs, + &OldPrimaryScreenDriverData ); + + /* primary layer */ + dfb_layers_hook_primary( device, driver_data, + &RadeonCrtc1LayerFuncs, + &OldPrimaryLayerFuncs, + &OldPrimaryLayerDriverData ); + + /* overlay support */ + dfb_layers_register( dfb_screens_at( DSCID_PRIMARY ), + driver_data, &RadeonOverlayFuncs ); + + if (chip != CHIP_R100) { + CoreScreen *screen; + + /* secondary screen support */ + screen = dfb_screens_register( device, driver_data, + &RadeonCrtc2ScreenFuncs ); + + /* secondary underlay support */ + dfb_layers_register( screen, driver_data, + &RadeonCrtc2LayerFuncs ); + + /* secondary overlay support */ + dfb_layers_register( screen, driver_data, + &RadeonOverlayFuncs ); + } + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = (RadeonDeviceData*) device_data; + volatile void *mmio = rdrv->mmio_base; + int dev = 0; + int idx = 0; + const char *name = "Unknown"; + + if (radeon_find_chipset( rdrv, &dev, &idx )) { + rdev->chipset = dev_table[idx].chip; + rdev->igp = dev_table[idx].igp; + name = dev_table[idx].name; + } + else { + if (!dev) { + D_ERROR( "DirectFB/Radeon: Could not detect device id!\n" + " -> Please, specify the bus location of" + " the card by using the 'busid' option.\n" ); + } + D_INFO( "DirectFB/Radeon: " + "Unknown chipset, disabling acceleration!\n" ); + } + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, + "%s (%04x)", name, dev ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "ATI" ); + + device_info->caps.flags = CCF_CLIPPING | CCF_AUXMEMORY | CCF_RENDEROPTS; + + if (rdev->chipset >= CHIP_R300) { + if (rdrv->mmio_size > 0x4000) { + device_info->caps.accel = R300_SUPPORTED_DRAWINGFUNCS | + R300_SUPPORTED_BLITTINGFUNCS; + device_info->caps.drawing = R300_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = R300_SUPPORTED_BLITTINGFLAGS; + } else { + device_info->caps.accel = RADEON_SUPPORTED_2D_DRAWINGFUNCS | + RADEON_SUPPORTED_2D_BLITTINGFUNCS; + device_info->caps.drawing = RADEON_SUPPORTED_2D_DRAWINGFLAGS; + device_info->caps.blitting = RADEON_SUPPORTED_2D_BLITTINGFLAGS; + } + } + else if (rdev->chipset >= CHIP_R200) { + device_info->caps.accel = R200_SUPPORTED_DRAWINGFUNCS | + R200_SUPPORTED_BLITTINGFUNCS; + device_info->caps.drawing = R200_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = R200_SUPPORTED_BLITTINGFLAGS; + } + else if (rdev->chipset >= CHIP_R100) { + device_info->caps.accel = R100_SUPPORTED_DRAWINGFUNCS | + R100_SUPPORTED_BLITTINGFUNCS; + device_info->caps.drawing = R100_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = R100_SUPPORTED_BLITTINGFLAGS; + } + + device_info->limits.surface_byteoffset_alignment = 32; + device_info->limits.surface_pixelpitch_alignment = 64; + device_info->limits.surface_bytepitch_alignment = 128; + + dfb_config->pollvsync_after = 1; + + /* reserve memory for YUV422 color buffer */ + rdev->yuv422_buffer = dfb_gfxcard_reserve_memory( device, 128 ); + if (rdev->yuv422_buffer == (u32)-1) { + D_ERROR( "DirectFB/Radeon: " + "couldn't reserve 128 bytes of video memory!\n" ); + return DFB_NOVIDEOMEMORY; + } + + rdev->fb_phys = dfb_gfxcard_memory_physical( device, 0 ); + + radeon_waitidle( rdrv, rdev ); + + /* get connected monitors */ + radeon_get_monitors( rdrv, rdev, &rdev->monitor1, &rdev->monitor2 ); + + /* save the following regs */ + rdev->mc_fb_location = radeon_in32( mmio, MC_FB_LOCATION ); + rdev->mc_agp_location = radeon_in32( mmio, MC_AGP_LOCATION ); + rdev->crtc_base_addr = radeon_in32( mmio, CRTC_BASE_ADDR ); + rdev->crtc2_base_addr = radeon_in32( mmio, CRTC2_BASE_ADDR ); + rdev->agp_base = radeon_in32( mmio, AGP_BASE ); + rdev->agp_cntl = radeon_in32( mmio, AGP_CNTL ); + rdev->aic_cntl = radeon_in32( mmio, AIC_CNTL ); + rdev->bus_cntl = radeon_in32( mmio, BUS_CNTL ); + rdev->fcp_cntl = radeon_in32( mmio, FCP_CNTL ); + rdev->cap0_trig_cntl = radeon_in32( mmio, CAP0_TRIG_CNTL ); + rdev->vid_buffer_control = radeon_in32( mmio, VID_BUFFER_CONTROL ); + rdev->display_test_debug_cntl = radeon_in32( mmio, DISPLAY_TEST_DEBUG_CNTL ); + rdev->surface_cntl = radeon_in32( mmio, SURFACE_CNTL ); + rdev->dp_gui_master_cntl = radeon_in32( mmio, DP_GUI_MASTER_CNTL ); + + rdev->surface_cntl_p = + rdev->surface_cntl_c = rdev->surface_cntl; + + if (rdev->igp) { + u32 tom; + /* force MC_FB_LOCATION to NB_TOM */ + tom = radeon_in32( mmio, NB_TOM ); + rdev->fb_offset = tom << 16; + rdev->fb_size = ((tom >> 16) - (tom & 0xffff) + 1) << 16; + } + else { + if (rdev->chipset >= CHIP_R300) { + rdev->fb_offset = 0; + rdev->fb_size = radeon_in32( mmio, CONFIG_MEMSIZE ); + } else { + rdev->fb_offset = radeon_in32( mmio, CONFIG_APER_0_BASE ); + rdev->fb_size = radeon_in32( mmio, CONFIG_APER_SIZE ); + } + } + + radeon_out32( mmio, MC_FB_LOCATION, (rdev->fb_offset>>16) | + ((rdev->fb_offset + rdev->fb_size - 1) & 0xffff0000) ); + + D_DEBUG( "DirectFB/Radeon: " + "Framebuffer located at 0x%08x:0x%08x.\n", + rdev->fb_offset, rdev->fb_offset + rdev->fb_size - 1 ); + + if (dfb_system_auxram_length()) { + rdev->agp_offset = (rdev->fb_offset + rdev->fb_size) & 0xffc00000; + rdev->agp_size = dfb_system_auxram_length(); + + /* enable AGP support */ + radeon_out32( mmio, AIC_CNTL, rdev->aic_cntl & ~PCIGART_TRANSLATE_EN ); + radeon_out32( mmio, AGP_BASE, dfb_system_aux_memory_physical( 0 ) ); + radeon_out32( mmio, AGP_CNTL, rdev->agp_cntl | 0x000e0000 ); + radeon_out32( mmio, BUS_CNTL, rdev->bus_cntl & ~BUS_MASTER_DIS ); + + radeon_out32( mmio, MC_AGP_LOCATION, (rdev->agp_offset>>16) | + ((rdev->agp_offset + rdev->agp_size - 1) & 0xffff0000) ); + + D_DEBUG( "DirectFB/Radeon: " + "AGP Aperture located at 0x%08x:0x%08x.\n", + rdev->agp_offset, rdev->agp_offset + rdev->agp_size - 1 ); + } + + radeon_out32( mmio, CRTC_BASE_ADDR, rdev->fb_offset ); + radeon_out32( mmio, DISP_MERGE_CNTL, 0xffff0000 ); + if (rdev->chipset != CHIP_R100) { + radeon_out32( mmio, CRTC2_BASE_ADDR, rdev->fb_offset ); + radeon_out32( mmio, DISP2_MERGE_CNTL, 0xffff0000 ); + } + + radeon_out32( mmio, FCP_CNTL, FCP0_SRC_GND ); + radeon_out32( mmio, CAP0_TRIG_CNTL, 0 ); + radeon_out32( mmio, VID_BUFFER_CONTROL, 0x00010001 ); + radeon_out32( mmio, DISPLAY_TEST_DEBUG_CNTL, 0 ); + + radeon_reset( rdrv, rdev ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = (RadeonDeviceData*) device_data; + volatile u8 *mmio = rdrv->mmio_base; + + D_DEBUG( "DirectFB/Radeon: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/Radeon: %9d radeon_waitfifo calls\n", + rdev->waitfifo_calls ); + D_DEBUG( "DirectFB/Radeon: %9d register writes (radeon_waitfifo sum)\n", + rdev->waitfifo_sum ); + D_DEBUG( "DirectFB/Radeon: %9d FIFO wait cycles (depends on CPU)\n", + rdev->fifo_waitcycles ); + D_DEBUG( "DirectFB/Radeon: %9d IDLE wait cycles (depends on CPU)\n", + rdev->idle_waitcycles ); + D_DEBUG( "DirectFB/Radeon: %9d FIFO space cache hits(depends on CPU)\n", + rdev->fifo_cache_hits ); + D_DEBUG( "DirectFB/Radeon: Conclusion:\n" ); + D_DEBUG( "DirectFB/Radeon: Average register writes/radeon_waitfifo call:%.2f\n", + rdev->waitfifo_sum / (float)rdev->waitfifo_calls ); + D_DEBUG( "DirectFB/Radeon: Average wait cycles/radeon_waitfifo call: %.2f\n", + rdev->fifo_waitcycles / (float)rdev->waitfifo_calls ); + D_DEBUG( "DirectFB/Radeon: Average fifo space cache hits: %02d%%\n", + (int)(100 * rdev->fifo_cache_hits / (float)rdev->waitfifo_calls) ); + + radeon_reset( rdrv, rdev ); + + /* restore previously saved regs */ + radeon_out32( mmio, MC_FB_LOCATION, rdev->mc_fb_location ); + radeon_out32( mmio, MC_AGP_LOCATION, rdev->mc_agp_location ); + radeon_out32( mmio, CRTC_BASE_ADDR, rdev->crtc_base_addr ); + radeon_out32( mmio, CRTC2_BASE_ADDR, rdev->crtc2_base_addr ); + radeon_out32( mmio, AGP_CNTL, rdev->agp_cntl ); + radeon_out32( mmio, AGP_BASE, rdev->agp_base ); + radeon_out32( mmio, AIC_CNTL, rdev->aic_cntl ); + radeon_out32( mmio, BUS_CNTL, rdev->bus_cntl ); + radeon_out32( mmio, FCP_CNTL, rdev->fcp_cntl ); + radeon_out32( mmio, CAP0_TRIG_CNTL, rdev->cap0_trig_cntl ); + radeon_out32( mmio, VID_BUFFER_CONTROL, rdev->vid_buffer_control ); + radeon_out32( mmio, DISPLAY_TEST_DEBUG_CNTL, rdev->display_test_debug_cntl ); + radeon_out32( mmio, SURFACE_CNTL, rdev->surface_cntl ); + + radeon_waitfifo( rdrv, rdev, 3 ); + radeon_out32( mmio, SC_TOP_LEFT, 0 ); + radeon_out32( mmio, DEFAULT_SC_BOTTOM_RIGHT, DEFAULT_SC_RIGHT_MAX | + DEFAULT_SC_BOTTOM_MAX ); + radeon_out32( mmio, DP_GUI_MASTER_CNTL, rdev->dp_gui_master_cntl ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, rdrv->mmio_base, rdrv->mmio_size ); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon.h b/Source/DirectFB/gfxdrivers/radeon/radeon.h new file mode 100755 index 0000000..037c892 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_H__ +#define __RADEON_H__ + +#include + +#include +#include +#include +#include + + +typedef enum { + CHIP_UNKNOWN = 0, + CHIP_R100, + CHIP_RV100, + CHIP_RS100, + CHIP_RV200, + CHIP_RS200, + CHIP_RS250, + CHIP_R200, + CHIP_RV250, + CHIP_RV280, + CHIP_RS300, + CHIP_RS350, + CHIP_R300, + CHIP_R350, + CHIP_RV350, + CHIP_RV380, + CHIP_R420, + CHIP_RV410, + CHIP_RS400, +} RadeonChipsetFamily; + +typedef enum { + MT_NONE = 0, + MT_CRT = 1, + MT_DFP = 2, + MT_LCD = 3, + MT_CTV = 4, + MT_STV = 5 +} RadeonMonitorType; + +typedef struct { + /* validated flags */ + StateModificationFlags set; + /* current function */ + DFBAccelerationMask accel; + /* mask of currently supported drawing functions */ + DFBAccelerationMask drawing_mask; + /* mask of currently supported blitting functions */ + DFBAccelerationMask blitting_mask; + + unsigned long fb_phys; + u32 fb_offset; + u32 fb_size; + u32 agp_offset; + u32 agp_size; + + DFBSurfacePixelFormat dst_format; + u32 dst_offset; + u32 dst_offset_cb; + u32 dst_offset_cr; + u32 dst_pitch; + DFBBoolean dst_422; + + DFBSurfacePixelFormat src_format; + u32 src_offset; + u32 src_offset_cb; + u32 src_offset_cr; + u32 src_pitch; + u32 src_width; + u32 src_height; + u32 src_mask; + + DFBSurfacePixelFormat msk_format; + u32 msk_offset; + u32 msk_pitch; + u32 msk_width; + u32 msk_height; + + DFBRegion clip; + + float color[4]; + u32 y_cop; + u32 cb_cop; + u32 cr_cop; + + DFBSurfaceRenderOptions render_options; + DFBSurfaceDrawingFlags drawingflags; + DFBSurfaceBlittingFlags blittingflags; + + const s32 *matrix; + DFBBoolean affine_matrix; + + /* chipset identified */ + RadeonChipsetFamily chipset; + DFBBoolean igp; + + /* connected monitors */ + RadeonMonitorType monitor1; + RadeonMonitorType monitor2; + + /* saved registers */ + u32 mc_fb_location; + u32 mc_agp_location; + u32 crtc_base_addr; + u32 crtc2_base_addr; + u32 agp_base; + u32 agp_cntl; + u32 aic_cntl; + u32 bus_cntl; + u32 fcp_cntl; + u32 cap0_trig_cntl; + u32 vid_buffer_control; + u32 display_test_debug_cntl; + u32 surface_cntl; + u32 dp_gui_master_cntl; + + /* recorded registers */ + u32 surface_cntl_p; + u32 surface_cntl_c; + u32 gui_master_cntl; + u32 rb3d_cntl; + u32 rb3d_blend; + + /* faked texture for YUV422 drawing functions */ + u32 yuv422_buffer; + + /* vertex buffer */ + u32 vb[1024]; + u32 vb_size; + u32 vb_count; + u32 vb_type; + + /* for fifo/performance monitoring */ + unsigned int fifo_space; + + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; +} RadeonDeviceData; + +typedef struct { + RadeonDeviceData *device_data; + + u8 *fb_base; + volatile u8 *mmio_base; + unsigned int mmio_size; +} RadeonDriverData; + + +extern void radeon_reset( RadeonDriverData *rdrv, RadeonDeviceData *rdev ); + +extern ScreenFuncs RadeonCrtc1ScreenFuncs; +extern ScreenFuncs OldPrimaryScreenFuncs; +extern void *OldPrimaryScreenDriverData; + +extern DisplayLayerFuncs RadeonCrtc1LayerFuncs; +extern DisplayLayerFuncs OldPrimaryLayerFuncs; +extern void *OldPrimaryLayerDriverData; + +extern DisplayLayerFuncs RadeonOverlayFuncs; + +extern ScreenFuncs RadeonCrtc2ScreenFuncs; + +extern DisplayLayerFuncs RadeonCrtc2LayerFuncs; + + +/* utility function */ +static __inline__ u32 f2d( float f ) +{ + union { float f; u32 d; } tmp; + tmp.f = f; + return tmp.d; +} + +static __inline__ float d2f( u32 d ) +{ + union { float f; u32 d; } tmp; + tmp.d = d; + return tmp.f; +} + +#define RADEON_TRANSFORM(x, y, retx, rety, m, affine) \ + do { \ + float _x, _y, _w; \ + if (affine) { \ + _x = ((x) * m[0] + (y) * m[1] + m[2]) / 65536.f; \ + _y = ((x) * m[3] + (y) * m[4] + m[5]) / 65536.f; \ + } \ + else { \ + _w = ((x) * m[6] + (y) * m[7] + m[8]); \ + _x = ((x) * m[0] + (y) * m[1] + m[2]) / _w; \ + _y = ((x) * m[3] + (y) * m[4] + m[5]) / _w; \ + } \ + retx = _x; rety = _y; \ + } while(0) + + +#endif /* __RADEON_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_2d.c b/Source/DirectFB/gfxdrivers/radeon/radeon_2d.c new file mode 100755 index 0000000..acee7aa --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_2d.c @@ -0,0 +1,397 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" +#include "radeon_2d.h" + + +static void +radeonDoFillRectangle2D( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + DFBRectangle *rect ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 2 ); + + radeon_out32( mmio, DST_Y_X, (rect->y << 16) | + (rect->x & 0x3fff) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | + (rect->w & 0x3fff) ); +} + +bool radeonFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + radeonDoFillRectangle2D( rdrv, rdev, rect ); + + return true; +} + +bool radeonFillRectangle2D_420( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + + /* Fill Luma plane */ + radeonDoFillRectangle2D( rdrv, rdev, rect ); + + /* Scale coordinates */ + rect->x /= 2; + rect->y /= 2; + rect->w = (rect->w+1) >> 1; + rect->h = (rect->h+1) >> 1; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1)/2 << 16) | + ((clip->x2+1)/2 & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cb_cop ); + + /* Fill Cb plane */ + radeonDoFillRectangle2D( rdrv, rdev, rect ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cr ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cr_cop ); + + /* Fill Cr plane */ + radeonDoFillRectangle2D( rdrv, rdev, rect ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1) << 16) | + ((clip->x2+1) & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->y_cop ); + + return true; +} + +static void +radeonDoDrawRectangle2D( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + DFBRectangle *rect ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 7 ); + + /* left line */ + radeon_out32( mmio, DST_Y_X, (rect->y << 16) | (rect->x & 0x3fff) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | 1 ); + /* top line */ + radeon_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | (rect->w & 0xffff) ); + /* bottom line */ + radeon_out32( mmio, DST_Y_X, ((rect->y+rect->h-1) << 16) | (rect->x & 0x3fff) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, (1 << 16) | (rect->w & 0xffff) ); + /* right line */ + radeon_out32( mmio, DST_Y_X, (rect->y << 16) | ((rect->x+rect->w-1) & 0x3fff) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, (rect->h << 16) | 1 ); +} + +bool radeonDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + radeonDoDrawRectangle2D( rdrv, rdev, rect ); + + return true; +} + +bool radeonDrawRectangle2D_420( void *drv, void *dev, DFBRectangle *rect ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + + /* Fill Luma plane */ + radeonDoDrawRectangle2D( rdrv, rdev, rect ); + + /* Scale coordinates */ + rect->x /= 2; + rect->y /= 2; + rect->w >>= 1; + rect->h >>= 1; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1)/2 << 16) | + ((clip->x2+1)/2 & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cb_cop ); + + /* Fill Cb plane */ + radeonDoDrawRectangle2D( rdrv, rdev, rect ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cr ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cr_cop ); + + /* Fill Cr plane */ + radeonDoDrawRectangle2D( rdrv, rdev, rect ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1) << 16) | + ((clip->x2+1) & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->y_cop ); + + return true; +} + +static void +radeonDoDrawLine2D( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + DFBRegion *line ) +{ + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 2 ); + + radeon_out32( mmio, DST_LINE_START, (line->y1 << 16) | + (line->x1 & 0xffff) ); + radeon_out32( mmio, DST_LINE_END, (line->y2 << 16) | + (line->x2 & 0xffff) ); +} + +bool radeonDrawLine2D( void *drv, void *dev, DFBRegion *line ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->dst_422) { + line->x1 /= 2; + line->x2 = (line->x2+1) / 2; + } + + radeonDoDrawLine2D( rdrv, rdev, line ); + + return true; +} + +bool radeonDrawLine2D_420( void *drv, void *dev, DFBRegion *line ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + + line->x1 &= ~1; + line->y1 &= ~1; + line->x2 &= ~1; + line->y2 &= ~1; + + /* Fill Luma plane */ + radeonDoDrawLine2D( rdrv, rdev, line ); + + /* Scale coordinates */ + line->x1 /= 2; + line->y1 /= 2; + line->x2 /= 2; + line->y2 /= 2; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1)/2 << 16) | + ((clip->x2+1)/2 & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cb_cop ); + + /* Fill Cb plane */ + radeonDoDrawLine2D( rdrv, rdev, line ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cr ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->cr_cop ); + + /* Fill Cr plane */ + radeonDoDrawLine2D( rdrv, rdev, line ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 5 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1) << 16) | + ((clip->x2+1) & 0xffff) ); + radeon_out32( mmio, DP_BRUSH_FRGD_CLR, rdev->y_cop ); + + return true; +} + +static void +radeonDoBlit2D( RadeonDriverData *rdrv, RadeonDeviceData *rdev, + int sx, int sy, int dx, int dy, int w, int h ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 dir = 0; + + /* check which blitting direction should be used */ + if (sx <= dx) { + sx += w-1; + dx += w-1; + } else + dir |= DST_X_LEFT_TO_RIGHT; + + if (sy <= dy) { + sy += h-1; + dy += h-1; + } else + dir |= DST_Y_TOP_TO_BOTTOM; + + radeon_waitfifo( rdrv, rdev, 4 ); + + radeon_out32( mmio, DP_CNTL, dir ); + radeon_out32( mmio, SRC_Y_X, (sy << 16) | (sx & 0x3fff) ); + radeon_out32( mmio, DST_Y_X, (dy << 16) | (dx & 0x3fff) ); + radeon_out32( mmio, DST_HEIGHT_WIDTH, (h << 16) | (w & 0x3fff) ); +} + +bool radeonBlit2D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + + if (rdev->dst_422) { + sr->x /= 2; + sr->w = (sr->w+1) >> 1; + dx /= 2; + } + + radeonDoBlit2D( rdrv, rdev, sr->x, sr->y, dx, dy, sr->w, sr->h ); + + return true; +} + +bool radeonBlit2D_420( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) drv; + RadeonDeviceData *rdev = (RadeonDeviceData*) dev; + DFBRegion *clip = &rdev->clip; + volatile u8 *mmio = rdrv->mmio_base; + + /* Blit Luma plane */ + radeonDoBlit2D( rdrv, rdev, sr->x, sr->y, dx, dy, sr->w, sr->h ); + + /* Scale coordinates */ + sr->x /= 2; + sr->y /= 2; + sr->w = (sr->w+1) >> 1; + sr->h = (sr->h+1) >> 1; + dx /= 2; + dy /= 2; + + /* Prepare Cb plane */ + radeon_waitfifo( rdrv, rdev, 6 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cb ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch/2 ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset_cb ); + radeon_out32( mmio, SRC_PITCH, rdev->src_pitch/2 ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1/2 << 16) | + (clip->x1/2 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1/2) << 16) | + ((clip->x2+1/2) & 0xffff) ); + + /* Blit Cb plane */ + radeonDoBlit2D( rdrv, rdev, sr->x, sr->y, dx, dy, sr->w, sr->h ); + + /* Prepare Cr plane */ + radeon_waitfifo( rdrv, rdev, 2 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset_cr ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset_cr ); + + /* Blit Cr plane */ + radeonDoBlit2D( rdrv, rdev, sr->x, sr->y, dx, dy, sr->w, sr->h ); + + /* Reset */ + radeon_waitfifo( rdrv, rdev, 6 ); + radeon_out32( mmio, DST_OFFSET, rdev->dst_offset ); + radeon_out32( mmio, DST_PITCH, rdev->dst_pitch ); + radeon_out32( mmio, SRC_OFFSET, rdev->src_offset ); + radeon_out32( mmio, SRC_PITCH, rdev->src_pitch ); + radeon_out32( mmio, SC_TOP_LEFT, (clip->y1 << 16) | + (clip->x1 & 0xffff) ); + radeon_out32( mmio, SC_BOTTOM_RIGHT, ((clip->y2+1) << 16) | + ((clip->x2+1) & 0xffff) ); + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_2d.h b/Source/DirectFB/gfxdrivers/radeon/radeon_2d.h new file mode 100755 index 0000000..9277f85 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_2d.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_2D_H__ +#define __RADEON_2D_H__ + +bool radeonFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ); +bool radeonFillRectangle2D_420( void *drv, void *dev, DFBRectangle *rect ); + +bool radeonDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ); +bool radeonDrawRectangle2D_420( void *drv, void *dev, DFBRectangle *rect ); + +bool radeonDrawLine2D( void *drv, void *dev, DFBRegion *line ); +bool radeonDrawLine2D_420( void *drv, void *dev, DFBRegion *line ); + +bool radeonBlit2D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ); +bool radeonBlit2D_420( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ); + +#endif /* __RADEON_2D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_3d.h b/Source/DirectFB/gfxdrivers/radeon/radeon_3d.h new file mode 100755 index 0000000..0504dbc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_3d.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_3D_H__ +#define __RADEON_3D_H__ + +/* R100 Functions */ +bool r100FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r100FillTriangle( void *drv, void *dev, DFBTriangle *tri ); + +bool r100DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r100DrawLine3D( void *drv, void *dev, DFBRegion *line ); + +bool r100Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ); + +bool r100StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +bool r100TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ); + +void r100EmitCommands3D( void *drv, void *dev ); + +/* R200 Functions */ +bool r200FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r200FillTriangle( void *drv, void *dev, DFBTriangle *tri ); + +bool r200DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r200DrawLine3D( void *drv, void *dev, DFBRegion *line ); + +bool r200Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ); + +bool r200StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +bool r200TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ); + +void r200EmitCommands3D( void *drv, void *dev ); + +/* R300 Functions */ +bool r300FillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r300FillTriangle( void *drv, void *dev, DFBTriangle *tri ); + +bool r300DrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool r300DrawLine3D( void *drv, void *dev, DFBRegion *line ); + +bool r300Blit3D( void *drv, void *dev, DFBRectangle *sr, int dx, int dy ); + +bool r300StretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +bool r300TextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ); + +void r300EmitCommands3D( void *drv, void *dev ); + + +#endif /* __RADEON_3D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_chipsets.h b/Source/DirectFB/gfxdrivers/radeon/radeon_chipsets.h new file mode 100755 index 0000000..52f38f1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_chipsets.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_CHIPSETS_H__ +#define __RADEON_CHIPSETS_H__ + +static const struct { + u16 id; + u16 chip; + bool igp; + const char *name; +} dev_table[] = { + { 0x5144, CHIP_R100 , false, "Radeon" }, + { 0x5145, CHIP_R100 , false, "Radeon" }, + { 0x5146, CHIP_R100 , false, "Radeon" }, + { 0x5147, CHIP_R100 , false, "Radeon" }, + { 0x5159, CHIP_RV100, false, "Radeon VE/7000" }, + { 0x515a, CHIP_RV100, false, "Radeon VE/7000" }, + { 0x4c59, CHIP_RV100, false, "Radeon Mobility M6" }, + { 0x4c5a, CHIP_RV100, false, "Radeon Mobility M6" }, + { 0x4c57, CHIP_RV200, false, "Radeon Mobility M7" }, + { 0x4c58, CHIP_RV200, false, "FireGL Mobility 7800 M7" }, + { 0x5157, CHIP_RV200, false, "Radeon 7500" }, + { 0x5158, CHIP_RV200, false, "Radeon 7500" }, + { 0x4136, CHIP_RS100, true , "Radeon IGP320" }, + { 0x4336, CHIP_RS100, true , "Radeon IGP320M" }, + { 0x4137, CHIP_RS200, true , "Radeon IGP330/340/350" }, + { 0x4337, CHIP_RS200, true , "Radeon IGP330M/340M/350M" }, + { 0x4237, CHIP_RS250, true , "Radeon 7000 IGP" }, + { 0x4437, CHIP_RS250, true , "Radeon Mobility 7000 IGP" }, + { 0x514c, CHIP_R200 , false, "Radeon 8500" }, + { 0x4242, CHIP_R200 , false, "Radeon 8500 AIW" }, + { 0x4243, CHIP_R200 , false, "Radeon 8500 AIW" }, + { 0x514d, CHIP_R200 , false, "Radeon 9100" }, + { 0x5148, CHIP_R200 , false, "FireGL 8700/8800" }, + { 0x4966, CHIP_RV250, false, "Radeon 9000 PRO" }, + { 0x4967, CHIP_RV250, false, "Radeon 9000" }, + { 0x4c66, CHIP_RV250, false, "Radeon Mobility 9000 M9" }, + { 0x4c67, CHIP_RV250, false, "Radeon Mobility 9000 M9" }, + { 0x4c64, CHIP_RV250, false, "FireGL Mobility 9000 M9" }, + { 0x5960, CHIP_RV280, false, "Radeon 9200 PRO" }, + { 0x5961, CHIP_RV280, false, "Radeon 9200" }, + { 0x5962, CHIP_RV280, false, "Radeon 9200" }, + { 0x5964, CHIP_RV280, false, "Radeon 9200 SE" }, + { 0x5c61, CHIP_RV280, false, "Radeon Mobility 9200 M9+" }, + { 0x5c63, CHIP_RV280, false, "Radeon Mobility 9200 M9+" }, + { 0x5834, CHIP_RS300, true , "Radeon 9100 IGP" }, + { 0x5835, CHIP_RS300, true , "Radeon Mobility 9100 IGP" }, + { 0x7834, CHIP_RS350, true , "Radeon 9100 PRO IGP" }, + { 0x7835, CHIP_RS350, true , "Radeon Mobility 9200 IGP" }, + { 0x4144, CHIP_R300 , false, "Radeon 9500" }, + { 0x4145, CHIP_R300 , false, "Radeon 9500" }, + { 0x4146, CHIP_R300 , false, "Radeon 9600 TX" }, + { 0x4147, CHIP_R300 , false, "FireGL Z1" }, + { 0x4e44, CHIP_R300 , false, "Radeon 9700 PRO" }, + { 0x4e45, CHIP_R300 , false, "Radeon 9700/9500PRO" }, + { 0x4e46, CHIP_R300 , false, "Radeon 9600 TX" }, + { 0x4e47, CHIP_R300 , false, "FireGL X1" }, + { 0x4150, CHIP_RV350, false, "Radeon 9600" }, + { 0x4151, CHIP_RV350, false, "Radeon 9600 SE" }, + { 0x4152, CHIP_RV350, false, "Radeon 9600 XT" }, + { 0x4153, CHIP_RV350, false, "Radeon 9600" }, + { 0x4154, CHIP_RV350, false, "FireGL T2" }, + { 0x4156, CHIP_RV350, false, "FireGL RV360" }, + { 0x4e50, CHIP_RV350, false, "Radeon Mobility 9600/9700 M10/M11" }, + { 0x4e51, CHIP_RV350, false, "Radeon Mobility 9600 M10" }, + { 0x4e52, CHIP_RV350, false, "Radeon Mobility 9600 M11" }, + { 0x4e53, CHIP_RV350, false, "Radeon Mobility 9600 M10" }, + { 0x4e54, CHIP_RV350, false, "FireGL Mobility T2 M10" }, + { 0x4e56, CHIP_RV350, false, "FireGL Mobility T2e M11" }, + { 0x4155, CHIP_RV350, false, "Radeon 9650" }, + { 0x4148, CHIP_R350 , false, "Radeon 9800 SE" }, + { 0x4149, CHIP_R350 , false, "Radeon 9800" }, + { 0x414a, CHIP_R350 , false, "Radeon 9800" }, + { 0x414b, CHIP_R350 , false, "FireGL X2" }, + { 0x4e48, CHIP_R350 , false, "Radeon 9800 PRO" }, + { 0x4e49, CHIP_R350 , false, "Radeon 9800" }, + { 0x4e4b, CHIP_R350 , false, "FireGL X2" }, + { 0x4e4a, CHIP_R350 , false, "Radeon 9800 XT" }, + { 0x3e50, CHIP_RV380, false, "Radeon X600" }, + { 0x3e54, CHIP_RV380, false, "FireGL V3200" }, + { 0x3150, CHIP_RV380, false, "Radeon Mobility X600 M24" }, + { 0x3152, CHIP_RV380, false, "Radeon Mobility X300 M24" }, + { 0x3154, CHIP_RV380, false, "FireGL M24 GL" }, + { 0x5b60, CHIP_RV380, false, "Radeon X300" }, + { 0x5b62, CHIP_RV380, false, "Radeon X600" }, + { 0x5b63, CHIP_RV380, false, "Radeon X550" }, + { 0x5b64, CHIP_RV380, false, "FireGL V3100" }, + { 0x5b65, CHIP_RV380, false, "FireMV 2200 PCIE" }, + { 0x5460, CHIP_RV380, false, "Radeon Mobility X300 M22" }, + { 0x5462, CHIP_RV380, false, "Radeon Mobility X600 SE M24C" }, + { 0x5464, CHIP_RV380, false, "FireGL M22 GL" }, + { 0x5a41, CHIP_RS400, false, "Radeon XPRESS 200" }, + { 0x5a42, CHIP_RS400, false, "Radeon XPRESS 200M" }, + { 0x5a61, CHIP_RS400, false, "Radeon XPRESS 200" }, + { 0x5a62, CHIP_RS400, false, "Radeon XPRESS 200M" }, + { 0x5954, CHIP_RS400, false, "Radeon XPRESS 200" }, + { 0x5955, CHIP_RS400, false, "Radeon XPRESS 200M" }, + { 0x5974, CHIP_RS400, false, "Radeon XPRESS 200" }, + { 0x5975, CHIP_RS400, false, "Radeon XPRESS 200M" }, + { 0x5e48, CHIP_RV410, false, "FireGL V5000" }, + { 0x564a, CHIP_RV410, false, "Mobility FireGL V5000 M26" }, + { 0x564b, CHIP_RV410, false, "Mobility FireGL V5000 M26" }, + { 0x564f, CHIP_RV410, false, "Mobility Radeon X700 XL M26" }, + { 0x5652, CHIP_RV410, false, "Mobility Radeon X700 M26" }, + { 0x5653, CHIP_RV410, false, "Mobility Radeon X700 M26" }, + { 0x5e4b, CHIP_RV410, false, "Radeon X700 PRO" }, + { 0x5e4a, CHIP_RV410, false, "Radeon X700 XT" }, + { 0x5e4d, CHIP_RV410, false, "Radeon X700" }, + { 0x5e4c, CHIP_RV410, false, "Radeon X700 SE" }, + { 0x5e4f, CHIP_RV410, false, "Radeon X700 SE" }, + { 0x4a48, CHIP_R420 , false, "Radeon X800" }, + { 0x4a49, CHIP_R420 , false, "Radeon X800 PRO" }, + { 0x4a4a, CHIP_R420 , false, "Radeon X800 SE" }, + { 0x4a4b, CHIP_R420 , false, "Radeon X800" }, + { 0x4a4c, CHIP_R420 , false, "Radeon X800" }, + { 0x4a4d, CHIP_R420 , false, "FireGL X3" }, + { 0x4a4e, CHIP_R420 , false, "Radeon Mobility 9800 M18" }, + { 0x4a50, CHIP_R420 , false, "Radeon X800 XT" }, + { 0x4a4f, CHIP_R420 , false, "Radeon X800 SE" }, + { 0x4a54, CHIP_R420 , false, "Radeon AIW X800" }, + { 0x5548, CHIP_R420 , false, "Radeon X800" }, + { 0x5549, CHIP_R420 , false, "Radeon X800 PRO" }, + { 0x554a, CHIP_R420 , false, "Radeon X800 LE" }, + { 0x554b, CHIP_R420 , false, "Radeon X800 SE" }, + { 0x5551, CHIP_R420 , false, "FireGL V5100" }, + { 0x5552, CHIP_R420 , false, "FireGL Unknown" }, + { 0x5554, CHIP_R420 , false, "FireGL Unknown" }, + { 0x5d57, CHIP_R420 , false, "Radeon X800 XT" }, + { 0x5550, CHIP_R420 , false, "FireGL V7100" }, + { 0x5d49, CHIP_R420 , false, "Mobility FireGL V5100 M28" }, + { 0x5d4a, CHIP_R420 , false, "Mobility Radeon X800 M28" }, + { 0x5d48, CHIP_R420 , false, "Mobility Radeon X800 XT M28" }, + { 0x554f, CHIP_R420 , false, "Radeon X800" }, + { 0x554d, CHIP_R420 , false, "Radeon X800 XL" }, + { 0x554e, CHIP_R420 , false, "Radeon X800 SE" }, + { 0x554c, CHIP_R420 , false, "Radeon X800 XTP" }, + { 0x5d4c, CHIP_R420 , false, "Radeon X850" }, + { 0x5d50, CHIP_R420 , false, "Radeon Unknown R480" }, + { 0x5d4e, CHIP_R420 , false, "Radeon X850 SE" }, + { 0x5d4f, CHIP_R420 , false, "Radeon X850 PRO" }, + { 0x5d52, CHIP_R420 , false, "Radeon X850 XT" }, + { 0x5d4d, CHIP_R420 , false, "Radeon X850 XT PE" }, + { 0x4b4b, CHIP_R420 , false, "Radeon X850 PRO" }, + { 0x4b4a, CHIP_R420 , false, "Radeon X850 SE" }, + { 0x4b49, CHIP_R420 , false, "Radeon X850 XT" }, + { 0x4b4c, CHIP_R420 , false, "Radeon X850 XT PE" } +}; + +#endif /* __RADEON_CHIPSETS_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_crtc1.c b/Source/DirectFB/gfxdrivers/radeon/radeon_crtc1.c new file mode 100755 index 0000000..c4b1610 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_crtc1.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" + + + +/*************************** CRTC1 Screen functions **************************/ + +static DFBResult +crtc1WaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + volatile u8 *mmio = rdrv->mmio_base; + int i; + + if (dfb_config->pollvsync_none) + return DFB_OK; + + radeon_out32( mmio, GEN_INT_STATUS, + (radeon_in32( mmio, GEN_INT_STATUS ) & ~VSYNC_INT) | VSYNC_INT_AK ); + + for (i = 0; i < 2000000; i++) { + struct timespec t = { 0, 10000 }; + + if (radeon_in32( mmio, GEN_INT_STATUS ) & VSYNC_INT) + break; + nanosleep( &t, NULL ); + } + + return DFB_OK; +} + +ScreenFuncs RadeonCrtc1ScreenFuncs = { + .WaitVSync = crtc1WaitVSync +}; + +ScreenFuncs OldPrimaryScreenFuncs; +void *OldPrimaryScreenDriverData; + + +/*************************** CRTC1 Layer functions **************************/ + +#define CRTC1_SUPPORTED_OPTIONS ( DLOP_ALPHACHANNEL ) + +static DFBResult +crtc1InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + DFBResult ret; + + ret = OldPrimaryLayerFuncs.InitLayer( layer, + OldPrimaryLayerDriverData, + layer_data, description, + config, adjustment ); + + description->caps |= DLCAPS_ALPHACHANNEL; + + return ret; +} + +static DFBResult +crtc1TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfig layer_config; + CoreLayerRegionConfigFlags fail = 0; + DFBResult ret; + + layer_config = *config; + layer_config.options &= ~CRTC1_SUPPORTED_OPTIONS; + + ret = OldPrimaryLayerFuncs.TestRegion( layer, + OldPrimaryLayerDriverData, + layer_data, &layer_config, &fail ); + + if (config->options & ~CRTC1_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + if (config->options & DLOP_ALPHACHANNEL && config->format != DSPF_ARGB) + fail |= CLRCF_OPTIONS; + + if (failed) + *failed = fail; + + return fail ? DFB_UNSUPPORTED : DFB_OK; +} + +static DFBResult +crtc1SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + + if (updated & ~CLRCF_OPTIONS) { + return OldPrimaryLayerFuncs.SetRegion( layer, + OldPrimaryLayerDriverData, + layer_data, region_data, + config, updated, surface, palette, lock ); + } + + return DFB_OK; +} + +DisplayLayerFuncs RadeonCrtc1LayerFuncs = { + .InitLayer = crtc1InitLayer, + .TestRegion = crtc1TestRegion, + .SetRegion = crtc1SetRegion +}; + +DisplayLayerFuncs OldPrimaryLayerFuncs; +void *OldPrimaryLayerDriverData; + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_crtc2.c b/Source/DirectFB/gfxdrivers/radeon/radeon_crtc2.c new file mode 100755 index 0000000..bcae981 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_crtc2.c @@ -0,0 +1,1011 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" + + +typedef struct { + CoreLayerRegionConfig config; + CorePalette *palette; + DFBColorAdjustment adjustment; + + unsigned int pll_max_freq; + unsigned int pll_min_freq; + unsigned int pll_ref_div; + unsigned int pll_ref_clk; + + struct { + unsigned int size; + u8 r[256]; + u8 g[256]; + u8 b[256]; + } lut; + + struct { + u32 rCRTC2_GEN_CNTL; + u32 rFP2_GEN_CNTL; + u32 rDAC_CNTL2; + u32 rTV_DAC_CNTL; + u32 rDISP_OUTPUT_CNTL; + u32 rDISP_HW_DEBUG; + u32 rCRTC2_OFFSET_CNTL; + } save; + + struct { + u32 rCRTC2_GEN_CNTL; + u32 rDAC_CNTL2; + u32 rTV_DAC_CNTL; + u32 rDISP_OUTPUT_CNTL; + u32 rDISP_HW_DEBUG; + u32 rCRTC2_H_TOTAL_DISP; + u32 rCRTC2_H_SYNC_STRT_WID; + u32 rCRTC2_V_TOTAL_DISP; + u32 rCRTC2_V_SYNC_STRT_WID; + u32 rCRTC2_BASE_ADDR; + u32 rCRTC2_OFFSET; + u32 rCRTC2_OFFSET_CNTL; + u32 rCRTC2_PITCH; + u32 rFP2_GEN_CNTL; + u32 rFP2_H_SYNC_STRT_WID; + u32 rFP2_V_SYNC_STRT_WID; + u32 rP2PLL_REF_DIV; + u32 rP2PLL_DIV_0; + u32 rHTOTAL2_CNTL; + } regs; +} RadeonCrtc2LayerData; + +static VideoMode* crtc2_find_mode ( RadeonDriverData *drv, + int xres, + int yres ); +static bool crtc2_calc_regs ( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ); +static void crtc2_set_regs ( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2 ); +static void crtc2_calc_palette ( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2, + CoreLayerRegionConfig *config, + DFBColorAdjustment *adjustment, + CorePalette *palette ); +static void crtc2_set_palette ( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2 ); + +/*************************** CRTC2 Screen functions **************************/ + +static DFBResult +crtc2InitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + /* Set the screen capabilities. */ + description->caps = DSCCAPS_VSYNC | DSCCAPS_POWER_MANAGEMENT; + + /* Set the screen name. */ + snprintf( description->name, + DFB_SCREEN_DESC_NAME_LENGTH, "Radeon CRTC2" ); + + return DFB_OK; +} + +static DFBResult +crtc2SetPowerMode( CoreScreen *screen, + void *driver_data, + void *screen_data, + DFBScreenPowerMode mode ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + volatile u8 *mmio = rdrv->mmio_base; + u32 crtc2_gen_cntl; + + crtc2_gen_cntl = radeon_in32( mmio, CRTC2_GEN_CNTL ); + crtc2_gen_cntl &= ~(CRTC2_HSYNC_DIS | CRTC2_VSYNC_DIS | CRTC2_DISP_DIS); + + switch (mode) { + case DSPM_OFF: + crtc2_gen_cntl |= CRTC2_HSYNC_DIS | + CRTC2_VSYNC_DIS | + CRTC2_DISP_DIS; + break; + case DSPM_SUSPEND: + crtc2_gen_cntl |= CRTC2_VSYNC_DIS | + CRTC2_DISP_DIS; + break; + case DSPM_STANDBY: + crtc2_gen_cntl |= CRTC2_HSYNC_DIS | + CRTC2_DISP_DIS; + break; + case DSPM_ON: + break; + default: + D_DEBUG( "unknown power mode" ); + return DFB_INVARG; + } + + radeon_out32( mmio, CRTC2_GEN_CNTL, crtc2_gen_cntl ); + + return DFB_OK; +} + +static DFBResult +crtc2WaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + volatile u8 *mmio = rdrv->mmio_base; + int i; + + if (dfb_config->pollvsync_none) + return DFB_OK; + + radeon_out32( mmio, GEN_INT_STATUS, + (radeon_in32( mmio, GEN_INT_STATUS ) & ~VSYNC2_INT) | VSYNC2_INT_AK ); + + for (i = 0; i < 2000000; i++) { + struct timespec t = { 0, 10000 }; + + if (radeon_in32( mmio, GEN_INT_STATUS ) & VSYNC2_INT) + break; + nanosleep( &t, NULL ); + } + + return DFB_OK; +} + +static DFBResult +crtc2GetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + volatile u8 *mmio = rdrv->mmio_base; + unsigned int xres; + unsigned int yres; + + xres = ((radeon_in32( mmio, CRTC2_H_TOTAL_DISP ) >> 16) + 1) * 8; + yres = ((radeon_in32( mmio, CRTC2_V_TOTAL_DISP ) >> 16) + 1); + + D_DEBUG( "DirectFB/Radeon/CRTC2: " + "detected screen size %dx%d.\n", xres, yres ); + + if (xres <= 1 || yres <= 1) { + VideoMode *mode = dfb_system_modes(); + + if (!mode) { + D_WARN( "no default video mode" ); + return DFB_UNSUPPORTED; + } + xres = mode->xres; + yres = mode->yres; + } + + *ret_width = xres; + *ret_height = yres; + + return DFB_OK; +} + +ScreenFuncs RadeonCrtc2ScreenFuncs = { + .InitScreen = crtc2InitScreen, + .SetPowerMode = crtc2SetPowerMode, + .WaitVSync = crtc2WaitVSync, + .GetScreenSize = crtc2GetScreenSize +}; + +/**************************** CRTC2 Layer functions **************************/ + +#define CRTC2_SUPPORTED_OPTIONS ( DLOP_ALPHACHANNEL ) + +static int +crtc2LayerDataSize( void ) +{ + return sizeof(RadeonCrtc2LayerData); +} + +static DFBResult +crtc2InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonCrtc2LayerData *rcrtc2 = (RadeonCrtc2LayerData*) layer_data; + volatile u8 *mmio = rdrv->mmio_base; + VideoMode *mode; + + mode = dfb_system_modes(); + if (!mode) { + D_BUG( "no default video mode" ); + return DFB_FAILURE; + } + + /* Fill layer description. */ + description->caps = DLCAPS_SURFACE | DLCAPS_BRIGHTNESS | + DLCAPS_CONTRAST | DLCAPS_SATURATION | + DLCAPS_ALPHACHANNEL; + + description->type = DLTF_GRAPHICS; + + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Radeon CRTC2's Underlay" ); + + /* Set default configuration. */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = mode->xres; + config->height = mode->yres; + config->pixelformat = DSPF_RGB16; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* Set default color adjustment. */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | + DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + + /* Set PLL coefficients (should be done by reading the BIOS). */ + rcrtc2->pll_max_freq = 35000; + rcrtc2->pll_min_freq = 12000; + rcrtc2->pll_ref_div = 60; + rcrtc2->pll_ref_clk = 2700; + + /* Save common registers. */ + rcrtc2->save.rCRTC2_GEN_CNTL = radeon_in32( mmio, CRTC2_GEN_CNTL ); + rcrtc2->save.rFP2_GEN_CNTL = radeon_in32( mmio, FP2_GEN_CNTL ); + rcrtc2->save.rDAC_CNTL2 = radeon_in32( mmio, DAC_CNTL2 ); + rcrtc2->save.rTV_DAC_CNTL = radeon_in32( mmio, TV_DAC_CNTL ); + rcrtc2->save.rDISP_OUTPUT_CNTL = radeon_in32( mmio, DISP_OUTPUT_CNTL ); + rcrtc2->save.rDISP_HW_DEBUG = radeon_in32( mmio, DISP_HW_DEBUG ); + rcrtc2->save.rCRTC2_OFFSET_CNTL = radeon_in32( mmio, CRTC2_OFFSET_CNTL ); + + return DFB_OK; +} + +static DFBResult +crtc2TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + CoreLayerRegionConfigFlags fail = 0; + + /* check for unsupported options */ + if (config->options & ~CRTC2_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + if (config->options & DLOP_ALPHACHANNEL && config->format != DSPF_ARGB) + fail |= CLRCF_OPTIONS; + + /* check for unsupported buffermode */ + switch (config->buffermode) { + case DLBM_FRONTONLY: + case DLBM_BACKSYSTEM: + case DLBM_BACKVIDEO: + case DLBM_TRIPLE: + break; + + default: + fail |= CLRCF_BUFFERMODE; + break; + } + + /* check for unsupported pixelformat */ + switch (config->format) { + case DSPF_LUT8: + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + default: + fail |= CLRCF_FORMAT; + break; + } + + /* check for unsupported size */ + if (!crtc2_find_mode( rdrv, config->width, config->height )) + fail |= CLRCF_WIDTH | CLRCF_HEIGHT; + + if (failed) + *failed = fail; + + return fail ? DFB_UNSUPPORTED : DFB_OK; +} + +static DFBResult +crtc2AddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = rdrv->device_data; + + if (!rdev->monitor2) { + D_ERROR( "DirectFB/Radeon/CRTC2: " + "no secondary monitor connected!\n" ); + return DFB_IO; + } + + return DFB_OK; +} + +static DFBResult +crtc2SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonCrtc2LayerData *rcrtc2 = (RadeonCrtc2LayerData*) layer_data; + + rcrtc2->config = *config; + rcrtc2->palette = palette; + + updated &= CLRCF_WIDTH | CLRCF_HEIGHT | + CLRCF_FORMAT | CLRCF_SURFACE | CLRCF_PALETTE; + + if (updated & ~CLRCF_PALETTE) { + if (!crtc2_calc_regs( rdrv, rcrtc2, &rcrtc2->config, surface, lock )) + return DFB_UNSUPPORTED; + + crtc2_set_regs( rdrv, rcrtc2 ); + } + + if (updated) { + crtc2_calc_palette( rdrv, rcrtc2, &rcrtc2->config, + &rcrtc2->adjustment, rcrtc2->palette ); + crtc2_set_palette( rdrv, rcrtc2 ); + } + + return DFB_OK; +} + +static DFBResult +crtc2RemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonCrtc2LayerData *rcrtc2 = (RadeonCrtc2LayerData*) layer_data; + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitidle( rdrv, rdrv->device_data ); + + radeon_out32( mmio, CRTC2_GEN_CNTL, rcrtc2->save.rCRTC2_GEN_CNTL ); + radeon_out32( mmio, FP2_GEN_CNTL, rcrtc2->save.rFP2_GEN_CNTL ); + radeon_out32( mmio, DAC_CNTL2, rcrtc2->save.rDAC_CNTL2 ); + radeon_out32( mmio, TV_DAC_CNTL, rcrtc2->save.rTV_DAC_CNTL ); + radeon_out32( mmio, DISP_OUTPUT_CNTL, rcrtc2->save.rDISP_OUTPUT_CNTL ); + radeon_out32( mmio, DISP_HW_DEBUG, rcrtc2->save.rDISP_HW_DEBUG ); + radeon_out32( mmio, CRTC2_OFFSET_CNTL, rcrtc2->save.rCRTC2_OFFSET_CNTL ); + + return DFB_OK; +} + +static DFBResult +crtc2FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = rdrv->device_data; + RadeonCrtc2LayerData *rcrtc2 = (RadeonCrtc2LayerData*) layer_data; + volatile u8 *mmio = rdrv->mmio_base; + + if (lock->phys - lock->offset == rdev->fb_phys) + rcrtc2->regs.rCRTC2_BASE_ADDR = rdev->fb_offset; + else + rcrtc2->regs.rCRTC2_BASE_ADDR = rdev->agp_offset; + + rcrtc2->regs.rCRTC2_OFFSET = lock->offset; + + radeon_waitidle( rdrv, rdrv->device_data ); + + radeon_out32( mmio, CRTC2_BASE_ADDR, rcrtc2->regs.rCRTC2_BASE_ADDR ); + radeon_out32( mmio, CRTC2_OFFSET, rcrtc2->regs.rCRTC2_OFFSET ); + + dfb_surface_flip( surface, false ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + return DFB_OK; +} + +static DFBResult +crtc2SetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonCrtc2LayerData *rcrtc2 = (RadeonCrtc2LayerData*) layer_data; + + if (adj->flags & DCAF_BRIGHTNESS) { + if (adj->brightness == 0x8000) { + rcrtc2->adjustment.flags &= ~DCAF_BRIGHTNESS; + } else { + rcrtc2->adjustment.flags |= DCAF_BRIGHTNESS; + rcrtc2->adjustment.brightness = adj->brightness; + } + } + if (adj->flags & DCAF_CONTRAST) { + if (adj->contrast == 0x8000) { + rcrtc2->adjustment.flags &= ~DCAF_CONTRAST; + } else { + rcrtc2->adjustment.flags |= DCAF_CONTRAST; + rcrtc2->adjustment.contrast = adj->contrast; + } + } + if (adj->flags & DCAF_SATURATION) { + if (adj->saturation == 0x8000) { + rcrtc2->adjustment.flags &= ~DCAF_SATURATION; + } else { + rcrtc2->adjustment.flags |= DCAF_SATURATION; + rcrtc2->adjustment.saturation = adj->saturation; + } + } + + crtc2_calc_palette( rdrv, rcrtc2, &rcrtc2->config, + &rcrtc2->adjustment, rcrtc2->palette ); + crtc2_set_palette( rdrv, rcrtc2 ); + + return DFB_OK; +} + +DisplayLayerFuncs RadeonCrtc2LayerFuncs = { + .LayerDataSize = crtc2LayerDataSize, + .InitLayer = crtc2InitLayer, + .TestRegion = crtc2TestRegion, + .AddRegion = crtc2AddRegion, + .SetRegion = crtc2SetRegion, + .RemoveRegion = crtc2RemoveRegion, + .FlipRegion = crtc2FlipRegion, + .SetColorAdjustment = crtc2SetColorAdjustment +}; + +/************************** CRTC2 internal functions *************************/ + +static VideoMode* +crtc2_find_mode( RadeonDriverData *rdrv, + int xres, + int yres ) +{ + VideoMode *modes = dfb_system_modes(); + VideoMode *mode; + + for (mode = modes; mode; mode = mode->next) { + if (mode->xres == xres && mode->yres == yres) + return mode; + } + + return NULL; +} + +static void +crtc2_calc_pllregs( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2, + unsigned int freq ) +{ + struct { + int divider; + int bitvalue; + } *post_div, post_divs[] = { + { 1, 0 }, /* VCLK_SRC */ + { 2, 1 }, /* VCLK_SRC/2 */ + { 4, 2 }, /* VCLK_SRC/4 */ + { 8, 3 }, /* VCLK_SRC/8 */ + { 3, 4 }, /* VCLK_SRC/3 */ + { 6, 6 }, /* VCLK_SRC/6 */ + { 12, 7 }, /* VCLK_SRC/12 */ + { 0, 0 } + }; + u32 pll_output_freq_2 = 0; + u32 feedback_div_2; + + if (freq > rcrtc2->pll_max_freq) + freq = rcrtc2->pll_max_freq; + if (freq*12 < rcrtc2->pll_min_freq) + freq = rcrtc2->pll_min_freq/12; + + for (post_div = &post_divs[0]; post_div->divider; ++post_div) { + pll_output_freq_2 = post_div->divider * freq; + if (pll_output_freq_2 >= rcrtc2->pll_min_freq && + pll_output_freq_2 <= rcrtc2->pll_max_freq) + break; + } + + if (!post_div->divider) { + pll_output_freq_2 = freq; + post_div = &post_divs[0]; + } + + feedback_div_2 = rcrtc2->pll_ref_div * pll_output_freq_2; + feedback_div_2 += rcrtc2->pll_ref_clk/2; + feedback_div_2 /= rcrtc2->pll_ref_clk; + + D_DEBUG( "DirectFB/Radeon/CRTC2: " + "DotCLock=%d OutputFreq=%d FeedbackDiv=%d PostDiv=%d.\n", + freq, pll_output_freq_2, feedback_div_2, post_div->divider ); + + rcrtc2->regs.rP2PLL_REF_DIV = rcrtc2->pll_ref_div; + rcrtc2->regs.rP2PLL_DIV_0 = feedback_div_2 | (post_div->bitvalue << 16); + rcrtc2->regs.rHTOTAL2_CNTL = 0; +} + +static bool +crtc2_calc_regs( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock ) +{ + RadeonDeviceData *rdev = rdrv->device_data; + VideoMode *mode; + u32 format = 0; + + int h_total, h_sync_start, h_sync_end, h_sync_wid; + int v_total, v_sync_start, v_sync_end, v_sync_wid; + + + mode = crtc2_find_mode( rdrv, config->width, config->height ); + if (!mode) { + D_BUG( "unexpected error while searching video mode" ); + return false; + } + + switch (config->format) { + case DSPF_LUT8: + case DSPF_RGB332: + format = DST_8BPP; + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + format = DST_15BPP; + break; + case DSPF_RGB16: + format = DST_16BPP; + break; + case DSPF_RGB24: + format = DST_24BPP; + break; + case DSPF_RGB32: + case DSPF_ARGB: + format = DST_32BPP; + break; + default: + D_BUG( "unexpected pixelformat" ); + return false; + } + + h_sync_start = mode->xres + mode->right_margin; + h_sync_end = h_sync_start + mode->hsync_len; + h_total = h_sync_end + mode->left_margin; + h_sync_wid = (h_sync_end - h_sync_start) / 8; + h_sync_wid = CLAMP( h_sync_wid, 1, 0x3f ); + h_sync_start = h_sync_start - 8; + + v_sync_start = mode->yres + mode->lower_margin; + v_sync_end = v_sync_start + mode->vsync_len; + v_total = v_sync_end + mode->upper_margin; + v_sync_wid = v_sync_end - v_sync_start; + v_sync_wid = CLAMP( v_sync_wid, 1, 0x1f ); + + D_DEBUG( "DirectFB/Radeon/CRTC2: \n" + "\t\thSyncStart:%d hSyncEnd:%d hTotal:%d hSyncWid:%d\n" + "\t\tvSyncStart:%d vSyncEnd:%d vTotal:%d vSyncWid:%d\n", + h_sync_start, h_sync_end, h_total, h_sync_wid, + v_sync_start, v_sync_end, v_total, v_sync_wid ); + + rcrtc2->regs.rCRTC2_GEN_CNTL = CRTC2_EN | CRTC2_CRT2_ON | (format << 8); + if (mode->laced) + rcrtc2->regs.rCRTC2_GEN_CNTL |= CRTC2_INTERLACE_EN; + if (mode->doubled) + rcrtc2->regs.rCRTC2_GEN_CNTL |= CRTC2_DBL_SCAN_EN; + if (mode->sync_on_green) + rcrtc2->regs.rCRTC2_GEN_CNTL |= CRTC2_CSYNC_EN; + + rcrtc2->regs.rDAC_CNTL2 = rcrtc2->save.rDAC_CNTL2 | DAC2_DAC2_CLK_SEL; + rcrtc2->regs.rTV_DAC_CNTL = 0x00280203; + rcrtc2->regs.rDISP_OUTPUT_CNTL = rcrtc2->save.rDISP_OUTPUT_CNTL; + rcrtc2->regs.rDISP_HW_DEBUG = rcrtc2->save.rDISP_HW_DEBUG; + + if (rdev->chipset == CHIP_UNKNOWN || + rdev->chipset == CHIP_R200 || + rdev->chipset >= CHIP_R300) + { + rcrtc2->regs.rDISP_OUTPUT_CNTL &= ~(DISP_DAC_SOURCE_MASK | + DISP_DAC2_SOURCE_MASK); + + /* If primary monitor is a TV monitor, + * reverse the DAC source to control it using the CRTC2. */ + if (rdev->monitor1 == MT_CTV || rdev->monitor1 == MT_STV) + rcrtc2->regs.rDISP_OUTPUT_CNTL |= DISP_DAC2_SOURCE_CRTC2; + else + rcrtc2->regs.rDISP_OUTPUT_CNTL |= DISP_DAC_SOURCE_CRTC2; + } + else { + if (rdev->monitor1 == MT_CTV || rdev->monitor1 == MT_STV) { + rcrtc2->regs.rDISP_HW_DEBUG &= ~CRT2_DISP1_SEL; + rcrtc2->regs.rDAC_CNTL2 &= ~DAC2_DAC_CLK_SEL; + } + else { + rcrtc2->regs.rDISP_HW_DEBUG |= CRT2_DISP1_SEL; + rcrtc2->regs.rDAC_CNTL2 |= DAC2_DAC_CLK_SEL; + } + } + + rcrtc2->regs.rCRTC2_H_TOTAL_DISP = ((h_total/8 - 1) & 0x3ff) | + ((mode->xres/8 - 1) << 16); + rcrtc2->regs.rCRTC2_H_SYNC_STRT_WID = (h_sync_start & 0x1fff) | + ((h_sync_wid & 0x3f) << 16); + if (!mode->hsync_high) + rcrtc2->regs.rCRTC2_H_SYNC_STRT_WID |= CRTC2_H_SYNC_POL; + + rcrtc2->regs.rCRTC2_V_TOTAL_DISP = ((v_total - 1) & 0xffff) | + ((mode->yres - 1) << 16); + rcrtc2->regs.rCRTC2_V_SYNC_STRT_WID = ((v_sync_start - 1) & 0xfff) | + ((v_sync_wid & 0x1f) << 16); + if (!mode->vsync_high) + rcrtc2->regs.rCRTC2_V_SYNC_STRT_WID |= CRTC2_V_SYNC_POL; + + if (lock->phys - lock->offset == rdev->fb_phys) + rcrtc2->regs.rCRTC2_BASE_ADDR = rdev->fb_offset; + else + rcrtc2->regs.rCRTC2_BASE_ADDR = rdev->agp_offset; + + rcrtc2->regs.rCRTC2_OFFSET = lock->offset; + + rcrtc2->regs.rCRTC2_OFFSET_CNTL = rcrtc2->save.rCRTC2_OFFSET_CNTL; + rcrtc2->regs.rCRTC2_OFFSET_CNTL &= ~CRTC_TILE_EN; + rcrtc2->regs.rCRTC2_OFFSET_CNTL |= CRTC_HSYNC_EN; + + rcrtc2->regs.rCRTC2_PITCH = (lock->pitch / + DFB_BYTES_PER_PIXEL(surface->config.format)) >> 3; + rcrtc2->regs.rCRTC2_PITCH |= rcrtc2->regs.rCRTC2_PITCH << 16; + + if (rdev->monitor2 == MT_DFP) { + rcrtc2->regs.rCRTC2_GEN_CNTL &= ~CRTC2_CRT2_ON; + rcrtc2->regs.rFP2_GEN_CNTL = rcrtc2->save.rFP2_GEN_CNTL | FP2_ON; + + if (rdev->chipset == CHIP_UNKNOWN || + rdev->chipset == CHIP_R200 || + rdev->chipset >= CHIP_R300) + { + rcrtc2->regs.rFP2_GEN_CNTL &= ~(R200_FP2_SOURCE_SEL_MASK | + FP2_DVO_RATE_SEL_SDR); + rcrtc2->regs.rFP2_GEN_CNTL |= R200_FP2_SOURCE_SEL_CRTC2 | FP2_DVO_EN; + } + else { + rcrtc2->regs.rFP2_GEN_CNTL &= ~FP2_SRC_SEL_MASK; + rcrtc2->regs.rFP2_GEN_CNTL |= FP2_SRC_SEL_CRTC2; + } + + rcrtc2->regs.rFP2_H_SYNC_STRT_WID = rcrtc2->regs.rCRTC2_H_SYNC_STRT_WID; + rcrtc2->regs.rFP2_V_SYNC_STRT_WID = rcrtc2->regs.rCRTC2_V_SYNC_STRT_WID; + } + else { + rcrtc2->regs.rFP2_GEN_CNTL = rcrtc2->save.rFP2_GEN_CNTL; + rcrtc2->regs.rFP2_H_SYNC_STRT_WID = 0; + rcrtc2->regs.rFP2_V_SYNC_STRT_WID = 0; + } + + crtc2_calc_pllregs( rdrv, rcrtc2, 100000000 / mode->pixclock ); + + return true; +} + +static void +crtc2_set_regs ( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2 ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 tmp; + + /* Lock the card during mode switching. */ + dfb_gfxcard_lock( GDLF_WAIT | GDLF_SYNC ); + + radeon_out32( mmio, CRTC2_GEN_CNTL, + rcrtc2->regs.rCRTC2_GEN_CNTL | CRTC2_DISP_DIS ); + + radeon_out32( mmio, DAC_CNTL2, rcrtc2->regs.rDAC_CNTL2 ); + radeon_out32( mmio, TV_DAC_CNTL, rcrtc2->regs.rTV_DAC_CNTL ); + radeon_out32( mmio, DISP_OUTPUT_CNTL, rcrtc2->regs.rDISP_OUTPUT_CNTL ); + radeon_out32( mmio, DISP_HW_DEBUG, rcrtc2->regs.rDISP_HW_DEBUG ); + + radeon_out32( mmio, CRTC2_H_TOTAL_DISP, rcrtc2->regs.rCRTC2_H_TOTAL_DISP ); + radeon_out32( mmio, CRTC2_H_SYNC_STRT_WID, rcrtc2->regs.rCRTC2_H_SYNC_STRT_WID ); + + radeon_out32( mmio, CRTC2_V_TOTAL_DISP, rcrtc2->regs.rCRTC2_V_TOTAL_DISP ); + radeon_out32( mmio, CRTC2_V_SYNC_STRT_WID, rcrtc2->regs.rCRTC2_V_SYNC_STRT_WID ); + + radeon_out32( mmio, CRTC2_BASE_ADDR, rcrtc2->regs.rCRTC2_BASE_ADDR ); + radeon_out32( mmio, CRTC2_OFFSET, rcrtc2->regs.rCRTC2_OFFSET ); + radeon_out32( mmio, CRTC2_OFFSET_CNTL, rcrtc2->regs.rCRTC2_OFFSET_CNTL ); + radeon_out32( mmio, CRTC2_PITCH, rcrtc2->regs.rCRTC2_PITCH ); + + radeon_out32( mmio, FP2_GEN_CNTL, rcrtc2->regs.rFP2_GEN_CNTL ); + radeon_out32( mmio, FP2_H_SYNC_STRT_WID, rcrtc2->regs.rFP2_H_SYNC_STRT_WID ); + radeon_out32( mmio, FP2_V_SYNC_STRT_WID, rcrtc2->regs.rFP2_V_SYNC_STRT_WID ); + + tmp = radeon_inpll( mmio, PIXCLKS_CNTL) & ~PIX2CLK_SRC_SEL_MASK; + radeon_outpll( mmio, PIXCLKS_CNTL, tmp | PIX2CLK_SRC_SEL_CPUCLK ); + + tmp = radeon_inpll( mmio, P2PLL_CNTL ); + radeon_outpll( mmio, P2PLL_CNTL, tmp | P2PLL_RESET | + P2PLL_ATOMIC_UPDATE_EN | + P2PLL_VGA_ATOMIC_UPDATE_EN ); + + tmp = radeon_inpll( mmio, P2PLL_REF_DIV ) & ~P2PLL_REF_DIV_MASK; + radeon_outpll( mmio, P2PLL_REF_DIV, tmp | rcrtc2->regs.rP2PLL_REF_DIV ); + + tmp = radeon_inpll( mmio, P2PLL_DIV_0 ) & ~P2PLL_FB0_DIV_MASK; + radeon_outpll( mmio, P2PLL_DIV_0, tmp | rcrtc2->regs.rP2PLL_DIV_0 ); + + tmp = radeon_inpll( mmio, P2PLL_DIV_0 ) & ~P2PLL_POST0_DIV_MASK; + radeon_outpll( mmio, P2PLL_DIV_0, tmp | rcrtc2->regs.rP2PLL_DIV_0 ); + + while (radeon_inpll( mmio, P2PLL_REF_DIV ) & P2PLL_ATOMIC_UPDATE_R); + + radeon_outpll( mmio, P2PLL_REF_DIV, + radeon_inpll( mmio, P2PLL_REF_DIV ) | P2PLL_ATOMIC_UPDATE_W ); + + for (tmp = 0; tmp < 1000; tmp++) { + if (!(radeon_inpll( mmio, P2PLL_REF_DIV ) & P2PLL_ATOMIC_UPDATE_R)) + break; + } + + radeon_outpll( mmio, HTOTAL2_CNTL, rcrtc2->regs.rHTOTAL2_CNTL ); + + tmp = radeon_inpll( mmio, P2PLL_CNTL ); + radeon_outpll( mmio, P2PLL_CNTL, tmp & ~(P2PLL_RESET | P2PLL_SLEEP | + P2PLL_ATOMIC_UPDATE_EN | + P2PLL_VGA_ATOMIC_UPDATE_EN) ); + + usleep( 5000 ); + + tmp = radeon_inpll( mmio, PIXCLKS_CNTL ) & ~PIX2CLK_SRC_SEL_MASK; + radeon_outpll( mmio, PIXCLKS_CNTL, tmp | PIX2CLK_SRC_SEL_P2PLLCLK ); + + radeon_out32( mmio, CRTC2_GEN_CNTL, rcrtc2->regs.rCRTC2_GEN_CNTL ); + + dfb_gfxcard_unlock(); +} + +static inline u8 +calc_gamma( float n, float d ) +{ + int ret; + + ret = 255.0 * n / d + 0.5; + if (ret > 255) + ret = 255; + else if (ret < 0) + ret = 0; + + return ret; +} + +static void +crtc2_calc_palette( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2, + CoreLayerRegionConfig *config, + DFBColorAdjustment *adjustment, + CorePalette *palette ) +{ + unsigned int i; + int r, g, b; + + switch (config->format) { + case DSPF_LUT8: + rcrtc2->lut.size = MAX( palette->num_entries, 256 ); + for (i = 0; i < rcrtc2->lut.size; i++) { + rcrtc2->lut.r[i] = palette->entries[i].r; + rcrtc2->lut.g[i] = palette->entries[i].g; + rcrtc2->lut.b[i] = palette->entries[i].b; + } + break; + case DSPF_RGB332: + rcrtc2->lut.size = 256; + for (i = 0, r = 0; r < 8; r++) { + for (g = 0; g < 8; g++) { + for (b = 0; b < 4; b++) { + rcrtc2->lut.r[i] = calc_gamma( r, 7 ); + rcrtc2->lut.g[i] = calc_gamma( g, 7 ); + rcrtc2->lut.b[i] = calc_gamma( b, 3 ); + i++; + } + } + } + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + rcrtc2->lut.size = 32; + for (i = 0; i < 32; i++) { + rcrtc2->lut.r[i] = + rcrtc2->lut.g[i] = + rcrtc2->lut.b[i] = calc_gamma( i, 31 ); + } + break; + case DSPF_RGB16: + rcrtc2->lut.size = 64; + for (i = 0; i < 64; i++) { + rcrtc2->lut.r[i] = + rcrtc2->lut.b[i] = calc_gamma( i/2, 31 ); + rcrtc2->lut.g[i] = calc_gamma( i, 63 ); + } + break; + default: + rcrtc2->lut.size = 256; + for (i = 0; i < 256; i++) { + rcrtc2->lut.r[i] = + rcrtc2->lut.b[i] = + rcrtc2->lut.g[i] = i; + } + break; + } + + if (adjustment->flags & DCAF_BRIGHTNESS) { + int brightness = (adjustment->brightness >> 8) - 128; + + for (i = 0; i < rcrtc2->lut.size; i++) { + r = rcrtc2->lut.r[i] + brightness; + g = rcrtc2->lut.g[i] + brightness; + b = rcrtc2->lut.b[i] + brightness; + rcrtc2->lut.r[i] = CLAMP( r, 0, 255 ); + rcrtc2->lut.g[i] = CLAMP( g, 0, 255 ); + rcrtc2->lut.b[i] = CLAMP( b, 0, 255 ); + } + } + + if (adjustment->flags & DCAF_CONTRAST) { + int contrast = adjustment->contrast; + + for (i = 0; i < rcrtc2->lut.size; i++) { + r = rcrtc2->lut.r[i] * contrast / 0x8000; + g = rcrtc2->lut.g[i] * contrast / 0x8000; + b = rcrtc2->lut.b[i] * contrast / 0x8000; + rcrtc2->lut.r[i] = CLAMP( r, 0, 255 ); + rcrtc2->lut.g[i] = CLAMP( g, 0, 255 ); + rcrtc2->lut.b[i] = CLAMP( b, 0, 255 ); + } + } + + if (adjustment->flags & DCAF_SATURATION) { + int saturation = adjustment->saturation >> 8; + + for (i = 0; i < rcrtc2->lut.size; i++) { + if (saturation > 128) { + float gray = ((float)saturation - 128.0)/128.0; + float color = 1.0 - gray; + + r = (((float)rcrtc2->lut.r[i] - 128.0 * gray)/color); + g = (((float)rcrtc2->lut.g[i] - 128.0 * gray)/color); + b = (((float)rcrtc2->lut.b[i] - 128.0 * gray)/color); + } + else { + float color = (float)saturation/128.0; + float gray = 1.0 - color; + + r = (((float)rcrtc2->lut.r[i] * color) + (128.0 * gray)); + g = (((float)rcrtc2->lut.g[i] * color) + (128.0 * gray)); + b = (((float)rcrtc2->lut.b[i] * color) + (128.0 * gray)); + } + rcrtc2->lut.r[i] = CLAMP( r, 0, 255 ); + rcrtc2->lut.g[i] = CLAMP( g, 0, 255 ); + rcrtc2->lut.b[i] = CLAMP( b, 0, 255 ); + } + } +} + +static void +crtc2_set_palette( RadeonDriverData *rdrv, + RadeonCrtc2LayerData *rcrtc2 ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 tmp; + int i, j; + + if (!rcrtc2->lut.size) { + D_WARN( "palette is empty" ); + return; + } + + dfb_gfxcard_lock( GDLF_WAIT | GDLF_SYNC ); + + tmp = radeon_in32( mmio, DAC_CNTL2 ); + radeon_out32( mmio, DAC_CNTL2, tmp | DAC2_PALETTE_ACC_CTL ); + + j = 256 / rcrtc2->lut.size; + for (i = 0; i < rcrtc2->lut.size; i++) { + radeon_out32( mmio, PALETTE_INDEX, i*j ); + radeon_out32( mmio, PALETTE_DATA, (rcrtc2->lut.b[i] ) | + (rcrtc2->lut.g[i] << 8) | + (rcrtc2->lut.r[i] << 16) ); + } + + radeon_out32( mmio, DAC_CNTL2, tmp ); + + dfb_gfxcard_unlock(); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_mmio.h b/Source/DirectFB/gfxdrivers/radeon/radeon_mmio.h new file mode 100755 index 0000000..cdfa1f7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_mmio.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_MMIO_H__ +#define __RADEON_MMIO_H__ + +#include +#include + +#include "radeon.h" + + +static __inline__ void +radeon_out8( volatile u8 *mmioaddr, u32 reg, u8 value ) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static __inline__ void +radeon_out16( volatile u8 *mmioaddr, u32 reg, u32 value ) +{ +#ifdef __powerpc__ + asm volatile( "sthbrx %0,%1,%2;eieio" + :: "r" (value), "b"(reg), "r" (mmioaddr) : "memory" ); +#else + *((volatile u16*)(mmioaddr+reg)) = value; +#endif +} + +static __inline__ void +radeon_out32( volatile u8 *mmioaddr, u32 reg, u32 value ) +{ +#ifdef __powerpc__ + asm volatile( "stwbrx %0,%1,%2;eieio" + :: "r" (value), "b"(reg), "r" (mmioaddr) : "memory" ); +#else + *((volatile u32*)(mmioaddr+reg)) = value; +#endif +} + +static __inline__ u8 +radeon_in8( volatile u8 *mmioaddr, u32 reg ) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static __inline__ u16 +radeon_in16( volatile u8 *mmioaddr, u32 reg ) +{ +#ifdef __powerpc__ + u32 value; + asm volatile( "lhbrx %0,%1,%2;eieio" + : "=r" (value) : "b" (reg), "r" (mmioaddr) ); + return value; +#else + return *((volatile u16*)(mmioaddr+reg)); +#endif +} + +static __inline__ u32 +radeon_in32( volatile u8 *mmioaddr, u32 reg ) +{ +#ifdef __powerpc__ + u32 value; + asm volatile( "lwbrx %0,%1,%2;eieio" + : "=r" (value) : "b" (reg), "r" (mmioaddr) ); + return value; +#else + return *((volatile u32*)(mmioaddr+reg)); +#endif +} + + +static __inline__ void +radeon_outpll( volatile u8 *mmioaddr, u32 addr, u32 value ) +{ + radeon_out8( mmioaddr, CLOCK_CNTL_INDEX, (addr & 0x3f) | PLL_WR_EN ); + radeon_out32( mmioaddr, CLOCK_CNTL_DATA, value ); +} + +static __inline__ u32 +radeon_inpll( volatile u8 *mmioaddr, u32 addr ) +{ + radeon_out8( mmioaddr, CLOCK_CNTL_INDEX, addr & 0x3f ); + return radeon_in32( mmioaddr, CLOCK_CNTL_DATA ); +} + + +static inline bool +radeon_waitfifo( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + unsigned int space ) +{ + int waitcycles = 0; + + rdev->waitfifo_sum += space; + rdev->waitfifo_calls++; + + if (rdev->fifo_space < space ) { + do { + rdev->fifo_space = radeon_in32( rdrv->mmio_base, RBBM_STATUS ); + rdev->fifo_space &= RBBM_FIFOCNT_MASK; + if (++waitcycles > 10000000) { + radeon_reset( rdrv, rdev ); + D_BREAK( "FIFO timed out" ); + return false; + } + } while (rdev->fifo_space < space); + + rdev->fifo_waitcycles += waitcycles; + } else + rdev->fifo_cache_hits++; + + rdev->fifo_space -= space; + + return true; +} + +static inline bool +radeon_waitidle( RadeonDriverData *rdrv, RadeonDeviceData *rdev ) +{ + int waitcycles = 0; + int status; + + if (!radeon_waitfifo( rdrv, rdev, 64 )) + return false; + + do { + status = radeon_in32( rdrv->mmio_base, RBBM_STATUS ); + if (++waitcycles > 10000000) { + radeon_reset( rdrv, rdev ); + D_BREAK( "Engine timed out" ); + return false; + } + } while (status & RBBM_ACTIVE); + + rdev->fifo_space = status & RBBM_FIFOCNT_MASK; + rdev->idle_waitcycles += waitcycles; + + return true; +} + + +#endif /* __RADEON_MMIO_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_overlay.c b/Source/DirectFB/gfxdrivers/radeon/radeon_overlay.c new file mode 100755 index 0000000..bdcaabe --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_overlay.c @@ -0,0 +1,983 @@ +/* + * Copyright (C) 2006 Claudio Ciccani + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +#include "radeon.h" +#include "radeon_regs.h" +#include "radeon_mmio.h" + + +typedef struct { + CoreLayerRegionConfig config; + float brightness; + float contrast; + float saturation; + float hue; + int field; + int level; + + CoreScreen *screen; + int crtc2; + + CoreSurface *surface; + CoreSurfaceBufferLock *lock; + + /* overlay registers */ + struct { + u32 H_INC; + u32 STEP_BY; + u32 Y_X_START; + u32 Y_X_END; + u32 V_INC; + u32 P1_BLANK_LINES_AT_TOP; + u32 P23_BLANK_LINES_AT_TOP; + u32 VID_BUF_PITCH0_VALUE; + u32 VID_BUF_PITCH1_VALUE; + u32 P1_X_START_END; + u32 P2_X_START_END; + u32 P3_X_START_END; + u32 BASE_ADDR; + u32 VID_BUF0_BASE_ADRS; + u32 VID_BUF1_BASE_ADRS; + u32 VID_BUF2_BASE_ADRS; + u32 VID_BUF3_BASE_ADRS; + u32 VID_BUF4_BASE_ADRS; + u32 VID_BUF5_BASE_ADRS; + u32 P1_V_ACCUM_INIT; + u32 P23_V_ACCUM_INIT; + u32 P1_H_ACCUM_INIT; + u32 P23_H_ACCUM_INIT; + u32 VID_KEY_CLR_LOW; + u32 VID_KEY_CLR_HIGH; + u32 GRPH_KEY_CLR_LOW; + u32 GRPH_KEY_CLR_HIGH; + u32 KEY_CNTL; + u32 MERGE_CNTL; + u32 SCALE_CNTL; + } regs; +} RadeonOverlayLayerData; + +static void ovl_calc_regs ( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ); +static void ovl_set_regs ( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl ); +static void ovl_calc_buffers ( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ); +static void ovl_set_buffers ( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl ); +static void ovl_set_colorkey ( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreLayerRegionConfig *config ); +static void ovl_set_adjustment( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + float brightness, + float contrast, + float saturation, + float hue ); + +#define OVL_SUPPORTED_OPTIONS \ + ( DLOP_DST_COLORKEY | DLOP_OPACITY | DLOP_DEINTERLACING ) + +/**********************/ + +static int +ovlLayerDataSize( void ) +{ + return sizeof(RadeonOverlayLayerData); +} + +static DFBResult +ovlInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + volatile u8 *mmio = rdrv->mmio_base; + DFBScreenDescription dsc; + + dfb_screen_get_info( layer->screen, NULL, &dsc ); + if (strstr( dsc.name, "CRTC2" )) + rovl->crtc2 = 1; + + rovl->level = 1; + + /* fill layer description */ + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | + DLCAPS_SATURATION | DLCAPS_HUE | + DLCAPS_DST_COLORKEY | DLCAPS_OPACITY | + DLCAPS_DEINTERLACING | DLCAPS_LEVELS; + + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, + "Radeon CRTC%c's Overlay", rovl->crtc2 ? '2' : '1' ); + + /* set default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* set default color adjustment */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | + DCAF_SATURATION | DCAF_HUE; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + + /* reset overlay */ + radeon_out32( mmio, OV0_SCALE_CNTL, SCALER_SOFT_RESET ); + radeon_out32( mmio, OV0_AUTO_FLIP_CNTL, 0 ); + radeon_out32( mmio, OV0_DEINTERLACE_PATTERN, 0 ); + radeon_out32( mmio, OV0_EXCLUSIVE_HORZ, 0 ); + radeon_out32( mmio, OV0_FILTER_CNTL, FILTER_HARDCODED_COEF ); + radeon_out32( mmio, OV0_TEST, 0 ); + + /* reset color adjustments */ + ovl_set_adjustment( rdrv, rovl, 0, 0, 0, 0 ); + + return DFB_OK; +} + +static DFBResult +ovlTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + CoreLayerRegionConfigFlags fail = 0; + + /* check for unsupported options */ + if (config->options & ~OVL_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + if (rovl->level == -1) { + if (config->options & ~DLOP_DEINTERLACING) + fail |= CLRCF_OPTIONS; + } + else { + if (config->options & DLOP_OPACITY && + config->options & (DLOP_SRC_COLORKEY | DLOP_DST_COLORKEY)) + fail |= CLRCF_OPTIONS; + } + + /* check buffermode */ + switch (config->buffermode) { + case DLBM_FRONTONLY: + case DLBM_BACKSYSTEM: + case DLBM_BACKVIDEO: + case DLBM_TRIPLE: + break; + + default: + fail |= CLRCF_BUFFERMODE; + break; + } + + /* check pixel format */ + switch (config->format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + break; + + default: + fail |= CLRCF_FORMAT; + break; + } + + /* check width */ + if (config->width > 2048 || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 2048 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ovlAddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = rdrv->device_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + if (rovl->crtc2 && !rdev->monitor2) { + D_ERROR( "DirectFB/Radeon/Overlay: " + "no secondary monitor connected!\n" ); + return DFB_IO; + } + + return DFB_OK; +} + +static DFBResult +ovlSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + /* save configuration */ + rovl->config = *config; + rovl->surface = surface; + rovl->screen = layer->screen; + + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | + CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS | CLRCF_OPACITY)) + { + ovl_calc_regs( rdrv, rovl, surface, &rovl->config, lock ); + ovl_set_regs( rdrv, rovl ); + } + + if (updated & (CLRCF_SRCKEY | CLRCF_DSTKEY)) + ovl_set_colorkey( rdrv, rovl, &rovl->config ); + + rovl->lock = lock; + + return DFB_OK; +} + +static DFBResult +ovlFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + dfb_surface_flip( surface, false ); + + ovl_calc_buffers( rdrv, rovl, surface, &rovl->config, lock ); + ovl_set_buffers( rdrv, rovl ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + rovl->lock = lock; + + return DFB_OK; +} + +static DFBResult +ovlSetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + if (adj->flags & DCAF_BRIGHTNESS) + rovl->brightness = (float)(adj->brightness-0x8000) / 65535.0; + + if (adj->flags & DCAF_CONTRAST) + rovl->contrast = (float)adj->contrast / 32768.0; + + if (adj->flags & DCAF_SATURATION) + rovl->saturation = (float)adj->saturation / 32768.0; + + if (adj->flags & DCAF_HUE) + rovl->hue = (float)(adj->hue-0x8000) * 3.1416 / 65535.0; + + ovl_set_adjustment( rdrv, rovl, rovl->brightness, rovl->contrast, + rovl->saturation, rovl->hue ); + + return DFB_OK; +} + +static DFBResult +ovlSetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + rovl->field = field; + + if (rovl->surface) { + ovl_calc_buffers( rdrv, rovl, rovl->surface, &rovl->config, rovl->lock ); + ovl_set_buffers( rdrv, rovl ); + } + + return DFB_OK; +} + +static DFBResult +ovlGetLevel( CoreLayer *layer, + void *driver_data, + void *layer_data, + int *level ) +{ + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + *level = rovl->level; + + return DFB_OK; +} + +static DFBResult +ovlSetLevel( CoreLayer *layer, + void *driver_data, + void *layer_data, + int level ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonOverlayLayerData *rovl = (RadeonOverlayLayerData*) layer_data; + + if (!rovl->surface) + return DFB_UNSUPPORTED; + + switch (level) { + case -1: + case 1: + rovl->level = level; + ovl_calc_regs( rdrv, rovl, rovl->surface, &rovl->config, rovl->lock ); + ovl_set_regs( rdrv, rovl ); + break; + default: + return DFB_UNSUPPORTED; + } + + return DFB_OK; +} + +static DFBResult +ovlRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + RadeonDriverData *rdrv = (RadeonDriverData*) driver_data; + RadeonDeviceData *rdev = rdrv->device_data; + + /* disable overlay */ + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( rdrv->mmio_base, OV0_SCALE_CNTL, 0 ); + + return DFB_OK; +} + + +DisplayLayerFuncs RadeonOverlayFuncs = { + .LayerDataSize = ovlLayerDataSize, + .InitLayer = ovlInitLayer, + .TestRegion = ovlTestRegion, + .AddRegion = ovlAddRegion, + .SetRegion = ovlSetRegion, + .RemoveRegion = ovlRemoveRegion, + .FlipRegion = ovlFlipRegion, + .SetColorAdjustment = ovlSetColorAdjustment, + .SetInputField = ovlSetInputField, + .GetLevel = ovlGetLevel, + .SetLevel = ovlSetLevel +}; + + +/*** Internal Functions ***/ + +static void +ovl_calc_coordinates( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreSurface *surface, + CoreLayerRegionConfig *config ) +{ + RadeonDeviceData *rdev = rdrv->device_data; + DFBRectangle source = config->source; + DFBRectangle dest = config->dest; + u32 ecp_div = 0; + u32 h_inc; + u32 h_inc2; + u32 v_inc; + u32 step_by; + u32 tmp; + int xres; + int yres; + + dfb_screen_get_screen_size( rovl->screen, &xres, &yres ); + + if (dest.w > (source.w << 4)) + dest.w = source.w << 4; + + if (dest.h > (source.h << 4)) + dest.h = source.h << 4; + + if (dest.x < 0) { + source.w += dest.x * source.w / dest.w; + dest.w += dest.x; + dest.x = 0; + } + + if (dest.y < 0) { + source.h += dest.y * source.h / dest.h; + dest.h += dest.y; + dest.y = 0; + } + + if ((dest.x + dest.w) > xres) { + source.w = (xres - dest.x) * source.w / dest.w; + dest.w = xres - dest.x; + } + + if ((dest.y + dest.h) > yres) { + source.h = (yres - dest.y) * source.h / dest.h; + dest.h = yres - dest.y; + } + + if (dest.w < 1 || dest.h < 1 || source.w < 1 || source.h < 1) { + config->opacity = 0; + return; + } + + if (config->options & DLOP_DEINTERLACING) + source.h /= 2; + + tmp = radeon_in32( rdrv->mmio_base, + rovl->crtc2 ? CRTC2_GEN_CNTL : CRTC_GEN_CNTL ); + + if (tmp & CRTC_DBL_SCAN_EN) { + dest.y *= 2; + dest.h *= 2; + } + + if (tmp & CRTC_INTERLACE_EN) { + dest.y /= 2; + dest.h /= 2; + } + + /* FIXME: We need to know the VideoMode of the current screen. */ +#if 0 + if ((100000000 / mode->pixclock) >= 17500) + ecp_div = 1; +#endif + + h_inc = (source.w << (12 + ecp_div)) / dest.w; + v_inc = (source.h << 20) / dest.h; + + for (step_by = 1; h_inc >= (2 << 12);) { + step_by++; + h_inc >>= 1; + } + + switch (surface->config.format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + h_inc2 = h_inc; + break; + default: + h_inc2 = h_inc >> 1; + break; + } + + rovl->regs.V_INC = v_inc; + rovl->regs.H_INC = h_inc | (h_inc2 << 16); + rovl->regs.STEP_BY = step_by | (step_by << 8); + + /* compute values for horizontal accumulators */ + tmp = 0x00028000 + (h_inc << 3); + rovl->regs.P1_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0xf0000000); + tmp = 0x00028000 + (h_inc2 << 3); + rovl->regs.P23_H_ACCUM_INIT = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); + + /* compute values for vertical accumulators */ + tmp = 0x00018000; + rovl->regs.P1_V_ACCUM_INIT = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | + (OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + tmp = 0x00018000; + rovl->regs.P23_V_ACCUM_INIT = ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | + (OV0_P23_MAX_LN_IN_PER_LN_OUT & 1); + + if (!rovl->crtc2) { + if (rdev->chipset < CHIP_R300 && + rdev->chipset != CHIP_R200 && + rdev->chipset != CHIP_UNKNOWN) + dest.x += 8; + } + + /* compute destination coordinates */ + rovl->regs.Y_X_START = (dest.x & 0xffff) | (dest.y << 16); + rovl->regs.Y_X_END = ((dest.x + dest.w - 1) & 0xffff) | + ((dest.y + dest.h - 1) << 16); + + /* compute source coordinates */ + rovl->regs.P1_BLANK_LINES_AT_TOP = P1_BLNK_LN_AT_TOP_M1_MASK | + ((source.h - 1) << 16); + rovl->regs.P1_X_START_END = (source.w - 1) & 0xffff; + + if (DFB_PLANAR_PIXELFORMAT( surface->config.format )) { + rovl->regs.P23_BLANK_LINES_AT_TOP = P23_BLNK_LN_AT_TOP_M1_MASK | + ((source.h/2 - 1) << 16); + rovl->regs.P2_X_START_END = (source.w/2 - 1) & 0xffff; + rovl->regs.P3_X_START_END = rovl->regs.P2_X_START_END; + } + else { + rovl->regs.P23_BLANK_LINES_AT_TOP = P23_BLNK_LN_AT_TOP_M1_MASK | + ((source.h - 1) << 16); + rovl->regs.P2_X_START_END = rovl->regs.P1_X_START_END; + rovl->regs.P3_X_START_END = rovl->regs.P1_X_START_END; + } +} + +static void +ovl_calc_buffers( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ) +{ + RadeonDeviceData *rdev = rdrv->device_data; + DFBRectangle source = config->source; + u32 offsets[3] = { 0, 0, 0 }; + u32 pitch = lock->pitch; + int even = 0; + int cropleft; + int croptop; + + if (config->options & DLOP_DEINTERLACING) { + source.y /= 2; + source.h /= 2; + pitch *= 2; + even = rovl->field; + } + + cropleft = source.x; + croptop = source.y; + + if (config->dest.x < 0) + cropleft += -config->dest.x * source.w / config->dest.w; + + if (config->dest.y < 0) + croptop += -config->dest.y * source.h / config->dest.h; + + if (DFB_PLANAR_PIXELFORMAT( surface->config.format )) { + cropleft &= ~31; + croptop &= ~1; + + offsets[0] = lock->offset; + offsets[1] = offsets[0] + surface->config.size.h * lock->pitch; + offsets[2] = offsets[1] + surface->config.size.h/2 * lock->pitch/2; + offsets[0] += croptop * pitch + cropleft; + offsets[1] += croptop/2 * pitch/2 + cropleft/2; + offsets[2] += croptop/2 * pitch/2 + cropleft/2; + + if (even) { + offsets[0] += lock->pitch; + offsets[1] += lock->pitch/2; + offsets[2] += lock->pitch/2; + } + + if (surface->config.format == DSPF_YV12) { + u32 tmp = offsets[1]; + offsets[1] = offsets[2]; + offsets[2] = tmp; + } + } + else { + offsets[0] = lock->offset + croptop * pitch + + cropleft * DFB_BYTES_PER_PIXEL( surface->config.format ); + if (even) + offsets[0] += lock->pitch; + + offsets[1] = + offsets[2] = offsets[0]; + } + + if (lock->phys - lock->offset == rdev->fb_phys) + rovl->regs.BASE_ADDR = rdev->fb_offset; + else + rovl->regs.BASE_ADDR = rdev->agp_offset; + + rovl->regs.VID_BUF0_BASE_ADRS = (offsets[0] & VIF_BUF0_BASE_ADRS_MASK); + rovl->regs.VID_BUF1_BASE_ADRS = (offsets[1] & VIF_BUF1_BASE_ADRS_MASK) | + VIF_BUF1_PITCH_SEL; + rovl->regs.VID_BUF2_BASE_ADRS = (offsets[2] & VIF_BUF2_BASE_ADRS_MASK) | + VIF_BUF2_PITCH_SEL; + rovl->regs.VID_BUF3_BASE_ADRS = (offsets[0] & VIF_BUF3_BASE_ADRS_MASK); + rovl->regs.VID_BUF4_BASE_ADRS = (offsets[1] & VIF_BUF4_BASE_ADRS_MASK) | + VIF_BUF4_PITCH_SEL; + rovl->regs.VID_BUF5_BASE_ADRS = (offsets[2] & VIF_BUF5_BASE_ADRS_MASK) | + VIF_BUF5_PITCH_SEL; + rovl->regs.VID_BUF_PITCH0_VALUE = pitch; + rovl->regs.VID_BUF_PITCH1_VALUE = pitch/2; +} + +static void +ovl_calc_regs( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreSurface *surface, + CoreLayerRegionConfig *config, + CoreSurfaceBufferLock *lock ) +{ + rovl->regs.SCALE_CNTL = 0; + + /* Configure coordinates */ + ovl_calc_coordinates( rdrv, rovl, surface, config ); + + /* Configure buffers */ + ovl_calc_buffers( rdrv, rovl, surface, config, lock ); + + /* Configure scaler */ + if (rovl->level == -1) { + rovl->regs.KEY_CNTL = GRAPHIC_KEY_FN_FALSE | + VIDEO_KEY_FN_FALSE | + CMP_MIX_AND; + rovl->regs.MERGE_CNTL = DISP_ALPHA_MODE_PER_PIXEL | + 0x00ff0000 | /* graphic alpha */ + 0xff000000; /* overlay alpha */ + } + else if (config->options & DLOP_OPACITY) { + rovl->regs.KEY_CNTL = GRAPHIC_KEY_FN_TRUE | + VIDEO_KEY_FN_TRUE | + CMP_MIX_AND; + rovl->regs.MERGE_CNTL = DISP_ALPHA_MODE_GLOBAL | + 0x00ff0000 | + (config->opacity << 24); + } + else { + rovl->regs.KEY_CNTL = CMP_MIX_AND; + + if (config->options & DLOP_SRC_COLORKEY) + rovl->regs.KEY_CNTL |= VIDEO_KEY_FN_NE; + else + rovl->regs.KEY_CNTL |= VIDEO_KEY_FN_TRUE; + + if (config->options & DLOP_DST_COLORKEY) + rovl->regs.KEY_CNTL |= GRAPHIC_KEY_FN_EQ; + else + rovl->regs.KEY_CNTL |= GRAPHIC_KEY_FN_TRUE; + + rovl->regs.MERGE_CNTL = 0xffff0000; + } + + if (config->opacity) { + rovl->regs.SCALE_CNTL = SCALER_SMART_SWITCH | + SCALER_DOUBLE_BUFFER | + SCALER_ADAPTIVE_DEINT | + (rovl->crtc2 << 14); + + if (config->source.w == config->dest.w) + rovl->regs.SCALE_CNTL |= SCALER_HORZ_PICK_NEAREST; + if (config->source.h == config->dest.h) + rovl->regs.SCALE_CNTL |= SCALER_VERT_PICK_NEAREST; + + switch (surface->config.format) { + case DSPF_RGB555: + case DSPF_ARGB1555: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_15BPP | + SCALER_PRG_LOAD_START; + break; + case DSPF_RGB16: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_16BPP | + SCALER_PRG_LOAD_START; + break; + case DSPF_RGB32: + case DSPF_ARGB: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_32BPP | + SCALER_PRG_LOAD_START; + break; + case DSPF_UYVY: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_YVYU422; + break; + case DSPF_YUY2: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_VYUY422; + break; + case DSPF_YV12: + case DSPF_I420: + rovl->regs.SCALE_CNTL |= SCALER_SOURCE_YUV12; + break; + default: + D_BUG( "unexpected pixelformat" ); + config->opacity = 0; + return; + } + + rovl->regs.SCALE_CNTL |= SCALER_ENABLE; + } +} + +static void +ovl_set_regs( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl ) +{ + RadeonDeviceData *rdev = rdrv->device_data; + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK ); + while(!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & REG_LD_CTL_LOCK_READBACK)); + + radeon_waitfifo( rdrv, rdev, 17 ); + radeon_out32( mmio, OV0_H_INC, rovl->regs.H_INC ); + radeon_out32( mmio, OV0_STEP_BY, rovl->regs.STEP_BY ); + if (rovl->crtc2) { + radeon_out32( mmio, OV1_Y_X_START, rovl->regs.Y_X_START ); + radeon_out32( mmio, OV1_Y_X_END, rovl->regs.Y_X_END ); + } else { + radeon_out32( mmio, OV0_Y_X_START, rovl->regs.Y_X_START ); + radeon_out32( mmio, OV0_Y_X_END, rovl->regs.Y_X_END ); + } + radeon_out32( mmio, OV0_V_INC, rovl->regs.V_INC ); + radeon_out32( mmio, OV0_P1_BLANK_LINES_AT_TOP, rovl->regs.P1_BLANK_LINES_AT_TOP ); + radeon_out32( mmio, OV0_P23_BLANK_LINES_AT_TOP, rovl->regs.P23_BLANK_LINES_AT_TOP ); + radeon_out32( mmio, OV0_VID_BUF_PITCH0_VALUE, rovl->regs.VID_BUF_PITCH0_VALUE ); + radeon_out32( mmio, OV0_VID_BUF_PITCH1_VALUE, rovl->regs.VID_BUF_PITCH1_VALUE ); + radeon_out32( mmio, OV0_P1_X_START_END, rovl->regs.P1_X_START_END ); + radeon_out32( mmio, OV0_P2_X_START_END, rovl->regs.P2_X_START_END ); + radeon_out32( mmio, OV0_P3_X_START_END, rovl->regs.P3_X_START_END ); + radeon_out32( mmio, OV0_P1_V_ACCUM_INIT, rovl->regs.P1_V_ACCUM_INIT ); + radeon_out32( mmio, OV0_BASE_ADDR, rovl->regs.BASE_ADDR ); + radeon_out32( mmio, OV0_VID_BUF0_BASE_ADRS, rovl->regs.VID_BUF0_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF1_BASE_ADRS, rovl->regs.VID_BUF1_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF2_BASE_ADRS, rovl->regs.VID_BUF2_BASE_ADRS ); + + radeon_waitfifo( rdrv, rdev, 10 ); + radeon_out32( mmio, OV0_VID_BUF3_BASE_ADRS, rovl->regs.VID_BUF3_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF4_BASE_ADRS, rovl->regs.VID_BUF4_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF5_BASE_ADRS, rovl->regs.VID_BUF5_BASE_ADRS ); + radeon_out32( mmio, OV0_P1_H_ACCUM_INIT, rovl->regs.P1_H_ACCUM_INIT ); + radeon_out32( mmio, OV0_P23_V_ACCUM_INIT, rovl->regs.P23_V_ACCUM_INIT ); + radeon_out32( mmio, OV0_P23_H_ACCUM_INIT, rovl->regs.P23_H_ACCUM_INIT ); + + radeon_out32( mmio, DISP_MERGE_CNTL, rovl->regs.MERGE_CNTL ); + radeon_out32( mmio, OV0_KEY_CNTL, rovl->regs.KEY_CNTL ); + radeon_out32( mmio, OV0_SCALE_CNTL, rovl->regs.SCALE_CNTL ); + + radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 ); +} + +static void +ovl_set_buffers( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl ) +{ + RadeonDeviceData *rdev = rdrv->device_data; + volatile u8 *mmio = rdrv->mmio_base; + + radeon_waitfifo( rdrv, rdev, 1 ); + radeon_out32( mmio, OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK ); + while(!(radeon_in32( mmio, OV0_REG_LOAD_CNTL ) & REG_LD_CTL_LOCK_READBACK)); + + radeon_waitfifo( rdrv, rdev, 8 ); + radeon_out32( mmio, OV0_BASE_ADDR, rovl->regs.BASE_ADDR ); + radeon_out32( mmio, OV0_VID_BUF0_BASE_ADRS, rovl->regs.VID_BUF0_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF1_BASE_ADRS, rovl->regs.VID_BUF1_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF2_BASE_ADRS, rovl->regs.VID_BUF2_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF3_BASE_ADRS, rovl->regs.VID_BUF3_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF4_BASE_ADRS, rovl->regs.VID_BUF4_BASE_ADRS ); + radeon_out32( mmio, OV0_VID_BUF5_BASE_ADRS, rovl->regs.VID_BUF5_BASE_ADRS ); + + radeon_out32( mmio, OV0_REG_LOAD_CNTL, 0 ); +} + +static void +ovl_set_colorkey( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + CoreLayerRegionConfig *config ) +{ + volatile u8 *mmio = rdrv->mmio_base; + u32 SkeyLow, SkeyHigh; + u32 DkeyLow, DkeyHigh; + u32 tmp; + + SkeyLow = PIXEL_RGB32( config->src_key.r, + config->src_key.g, + config->src_key.b ); + SkeyHigh = SkeyLow | 0xff000000; + + tmp = radeon_in32( mmio, rovl->crtc2 ? CRTC2_GEN_CNTL : CRTC_GEN_CNTL ); + switch ((tmp >> 8) & 0xf) { + case DST_8BPP: + case DST_8BPP_RGB332: + DkeyLow = ((MAX( config->dst_key.r - 0x20, 0 ) & 0xe0) << 16) | + ((MAX( config->dst_key.g - 0x20, 0 ) & 0xe0) << 8) | + ((MAX( config->dst_key.b - 0x40, 0 ) & 0xc0) ); + break; + case DST_15BPP: + DkeyLow = ((MAX( config->dst_key.r - 0x08, 0 ) & 0xf8) << 16) | + ((MAX( config->dst_key.g - 0x08, 0 ) & 0xf8) << 8) | + ((MAX( config->dst_key.b - 0x08, 0 ) & 0xf8) ); + break; + case DST_16BPP: + DkeyLow = ((MAX( config->dst_key.r - 0x08, 0 ) & 0xf8) << 16) | + ((MAX( config->dst_key.g - 0x04, 0 ) & 0xfc) << 8) | + ((MAX( config->dst_key.b - 0x08, 0 ) & 0xf8) ); + break; + default: + DkeyLow = PIXEL_RGB32( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + break; + } + + DkeyHigh = PIXEL_RGB32( config->dst_key.r, + config->dst_key.g, + config->dst_key.b ) | 0xff000000; + + radeon_waitfifo( rdrv, rdrv->device_data, 4 ); + radeon_out32( mmio, OV0_VID_KEY_CLR_LOW, SkeyLow ); + radeon_out32( mmio, OV0_VID_KEY_CLR_HIGH, SkeyHigh ); + radeon_out32( mmio, OV0_GRPH_KEY_CLR_LOW, DkeyLow ); + radeon_out32( mmio, OV0_GRPH_KEY_CLR_HIGH, DkeyHigh ); +} + +static void +ovl_set_adjustment( RadeonDriverData *rdrv, + RadeonOverlayLayerData *rovl, + float brightness, + float contrast, + float saturation, + float hue ) +{ + volatile u8 *mmio = rdrv->mmio_base; + float HueSin, HueCos; + float Luma; + float RCb, RCr; + float GCb, GCr; + float BCb, BCr; + float AdjOff, ROff, GOff, BOff; + u32 dwLuma, dwROff, dwGOff, dwBOff; + u32 dwRCb, dwRCr; + u32 dwGCb, dwGCr; + u32 dwBCb, dwBCr; + + HueSin = sin( hue ); + HueCos = cos( hue ); + + Luma = contrast * +1.1678; + RCb = saturation * -HueSin * +1.6007; + RCr = saturation * HueCos * +1.6007; + GCb = saturation * (HueCos * -0.3929 - HueSin * -0.8154); + GCr = saturation * (HueCos * -0.3929 + HueCos * -0.8154); + BCb = saturation * HueCos * +2.0232; + BCr = saturation * HueSin * +2.0232; + + AdjOff = contrast * 1.1678 * brightness * 1023.0; + ROff = AdjOff - Luma * 64.0 - (RCb + RCr) * 512.0; + GOff = AdjOff - Luma * 64.0 - (GCb + GCr) * 512.0; + BOff = AdjOff - Luma * 64.0 - (BCb + BCr) * 512.0; + ROff = CLAMP( ROff, -2048.0, 2047.5 ); + GOff = CLAMP( GOff, -2048.0, 2047.5 ); + BOff = CLAMP( BOff, -2048.0, 2047.5 ); + dwROff = ((u32)(ROff * 2.0)) & 0x1fff; + dwGOff = ((u32)(GOff * 2.0)) & 0x1fff; + dwBOff = ((u32)(BOff * 2.0)) & 0x1fff; + + dwLuma = (((u32)(Luma * 256.0)) & 0xfff) << 20; + dwRCb = (((u32)(RCb * 256.0)) & 0xfff) << 4; + dwRCr = (((u32)(RCr * 256.0)) & 0xfff) << 20; + dwGCb = (((u32)(GCb * 256.0)) & 0xfff) << 4; + dwGCr = (((u32)(GCr * 256.0)) & 0xfff) << 20; + dwBCb = (((u32)(BCb * 256.0)) & 0xfff) << 4; + dwBCr = (((u32)(BCr * 256.0)) & 0xfff) << 20; + + radeon_waitfifo( rdrv, rdrv->device_data, 6 ); + radeon_out32( mmio, OV0_LIN_TRANS_A, dwRCb | dwLuma ); + radeon_out32( mmio, OV0_LIN_TRANS_B, dwROff | dwRCr ); + radeon_out32( mmio, OV0_LIN_TRANS_C, dwGCb | dwLuma ); + radeon_out32( mmio, OV0_LIN_TRANS_D, dwGOff | dwGCr ); + radeon_out32( mmio, OV0_LIN_TRANS_E, dwBCb | dwLuma ); + radeon_out32( mmio, OV0_LIN_TRANS_F, dwBOff | dwBCr ); +} + diff --git a/Source/DirectFB/gfxdrivers/radeon/radeon_regs.h b/Source/DirectFB/gfxdrivers/radeon/radeon_regs.h new file mode 100755 index 0000000..03e5952 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/radeon_regs.h @@ -0,0 +1,4364 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +#ifndef __RADEON_REGS_H__ +#define __RADEON_REGS_H__ + +#ifdef ROP_XOR +#undef ROP_XOR +#endif + +#ifdef ROP_COPY +#undef ROP_COPY +#endif + + + /* Registers for 2D/Video/Overlay */ +#define CONFIG_VENDOR_ID 0x0f00 /* PCI */ +#define CONFIG_DEVICE_ID 0x0f02 /* PCI */ +#define CONFIG_ADAPTER_ID 0x0f2c /* PCI */ + +#define AGP_BASE 0x0170 +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AGP_COMMAND 0x0f60 /* PCI */ +#define AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define AGP_ENABLE (1<<8) +#define AGP_PLL_CNTL 0x000b /* PLL */ +#define AGP_STATUS 0x0f5c /* PCI */ +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_FW_MODE 0x10 +# define AGP_MODE_MASK 0x17 +#define ATTRDR 0x03c1 /* VGA */ +#define ATTRDW 0x03c0 /* VGA */ +#define ATTRX 0x03c0 /* VGA */ +#define AUX_SC_CNTL 0x1660 +# define AUX1_SC_EN (1 << 0) +# define AUX1_SC_MODE_OR (0 << 1) +# define AUX1_SC_MODE_NAND (1 << 1) +# define AUX2_SC_EN (1 << 2) +# define AUX2_SC_MODE_OR (0 << 3) +# define AUX2_SC_MODE_NAND (1 << 3) +# define AUX3_SC_EN (1 << 4) +# define AUX3_SC_MODE_OR (0 << 5) +# define AUX3_SC_MODE_NAND (1 << 5) +#define AUX1_SC_BOTTOM 0x1670 +#define AUX1_SC_LEFT 0x1664 +#define AUX1_SC_RIGHT 0x1668 +#define AUX1_SC_TOP 0x166c +#define AUX2_SC_BOTTOM 0x1680 +#define AUX2_SC_LEFT 0x1674 +#define AUX2_SC_RIGHT 0x1678 +#define AUX2_SC_TOP 0x167c +#define AUX3_SC_BOTTOM 0x1690 +#define AUX3_SC_LEFT 0x1684 +#define AUX3_SC_RIGHT 0x1688 +#define AUX3_SC_TOP 0x168c +#define AUX_WINDOW_HORZ_CNTL 0x02d8 +#define AUX_WINDOW_VERT_CNTL 0x02dc + +#define BASE_CODE 0x0f0b +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c +#define BIOS_ROM 0x0f30 /* PCI */ +#define BIST 0x0f0f /* PCI */ +#define BRUSH_DATA0 0x1480 +#define BRUSH_DATA1 0x1484 +#define BRUSH_DATA10 0x14a8 +#define BRUSH_DATA11 0x14ac +#define BRUSH_DATA12 0x14b0 +#define BRUSH_DATA13 0x14b4 +#define BRUSH_DATA14 0x14b8 +#define BRUSH_DATA15 0x14bc +#define BRUSH_DATA16 0x14c0 +#define BRUSH_DATA17 0x14c4 +#define BRUSH_DATA18 0x14c8 +#define BRUSH_DATA19 0x14cc +#define BRUSH_DATA2 0x1488 +#define BRUSH_DATA20 0x14d0 +#define BRUSH_DATA21 0x14d4 +#define BRUSH_DATA22 0x14d8 +#define BRUSH_DATA23 0x14dc +#define BRUSH_DATA24 0x14e0 +#define BRUSH_DATA25 0x14e4 +#define BRUSH_DATA26 0x14e8 +#define BRUSH_DATA27 0x14ec +#define BRUSH_DATA28 0x14f0 +#define BRUSH_DATA29 0x14f4 +#define BRUSH_DATA3 0x148c +#define BRUSH_DATA30 0x14f8 +#define BRUSH_DATA31 0x14fc +#define BRUSH_DATA32 0x1500 +#define BRUSH_DATA33 0x1504 +#define BRUSH_DATA34 0x1508 +#define BRUSH_DATA35 0x150c +#define BRUSH_DATA36 0x1510 +#define BRUSH_DATA37 0x1514 +#define BRUSH_DATA38 0x1518 +#define BRUSH_DATA39 0x151c +#define BRUSH_DATA4 0x1490 +#define BRUSH_DATA40 0x1520 +#define BRUSH_DATA41 0x1524 +#define BRUSH_DATA42 0x1528 +#define BRUSH_DATA43 0x152c +#define BRUSH_DATA44 0x1530 +#define BRUSH_DATA45 0x1534 +#define BRUSH_DATA46 0x1538 +#define BRUSH_DATA47 0x153c +#define BRUSH_DATA48 0x1540 +#define BRUSH_DATA49 0x1544 +#define BRUSH_DATA5 0x1494 +#define BRUSH_DATA50 0x1548 +#define BRUSH_DATA51 0x154c +#define BRUSH_DATA52 0x1550 +#define BRUSH_DATA53 0x1554 +#define BRUSH_DATA54 0x1558 +#define BRUSH_DATA55 0x155c +#define BRUSH_DATA56 0x1560 +#define BRUSH_DATA57 0x1564 +#define BRUSH_DATA58 0x1568 +#define BRUSH_DATA59 0x156c +#define BRUSH_DATA6 0x1498 +#define BRUSH_DATA60 0x1570 +#define BRUSH_DATA61 0x1574 +#define BRUSH_DATA62 0x1578 +#define BRUSH_DATA63 0x157c +#define BRUSH_DATA7 0x149c +#define BRUSH_DATA8 0x14a0 +#define BRUSH_DATA9 0x14a4 +#define BRUSH_SCALE 0x1470 +#define BRUSH_Y_X 0x1474 +#define BUS_CNTL 0x0030 +# define BUS_MASTER_DIS (1 << 6) +# define BUS_RD_DISCARD_EN (1 << 24) +# define BUS_RD_ABORT_EN (1 << 25) +# define BUS_MSTR_DISCONNECT_EN (1 << 28) +# define BUS_WRT_BURST (1 << 29) +# define BUS_READ_BURST (1 << 30) +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define CACHE_CNTL 0x1724 +#define CACHE_LINE 0x0f0c /* PCI */ +#define CAP0_TRIG_CNTL 0x0950 /* ? */ +#define CAP1_TRIG_CNTL 0x09c0 /* ? */ +#define CAPABILITIES_ID 0x0f50 /* PCI */ +#define CAPABILITIES_PTR 0x0f34 /* PCI */ +#define CLK_PIN_CNTL 0x0001 /* PLL */ +# define SCLK_DYN_START_CNTL (1 << 15) +#define CLOCK_CNTL_DATA 0x000c +#define CLOCK_CNTL_INDEX 0x0008 +# define PLL_WR_EN (1 << 7) +# define PLL_DIV_SEL (3 << 8) +# define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLK_PWRMGT_CNTL 0x0014 +# define ENGIN_DYNCLK_MODE (1 << 12) +# define ACTIVE_HILO_LAT_MASK (3 << 13) +# define ACTIVE_HILO_LAT_SHIFT 13 +# define DISP_DYN_STOP_LAT_MASK (1 << 12) +# define DYN_STOP_MODE_MASK (7 << 21) +#define PLL_PWRMGT_CNTL 0x0015 +# define TCL_BYPASS_DISABLE (1 << 20) +#define CLR_CMP_CLR_3D 0x1a24 +#define CLR_CMP_CLR_DST 0x15c8 +#define CLR_CMP_CLR_SRC 0x15c4 +#define CLR_CMP_CNTL 0x15c0 +# define SRC_CMP_EQ_COLOR (4 << 0) +# define SRC_CMP_NEQ_COLOR (5 << 0) +# define CLR_CMP_SRC_SOURCE (1 << 24) +#define CLR_CMP_MASK 0x15cc +# define CLR_CMP_MSK 0xffffffff +#define CLR_CMP_MASK_3D 0x1A28 +#define COMMAND 0x0f04 /* PCI */ +#define COMPOSITE_SHADOW_ID 0x1a0c +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_BONDS 0x00e8 +#define CONFIG_CNTL 0x00e0 +# define CFG_ATI_REV_A11 (0 << 16) +# define CFG_ATI_REV_A12 (1 << 16) +# define CFG_ATI_REV_A13 (2 << 16) +# define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CONFIG_MEMSIZE 0x00f8 +#define CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define CONFIG_REG_1_BASE 0x010c +#define CONFIG_REG_APER_SIZE 0x0110 +#define CONFIG_XSTRAP 0x00e4 +#define CONSTANT_COLOR_C 0x1d34 +# define CONSTANT_COLOR_MASK 0x00ffffff +# define CONSTANT_COLOR_ONE 0x00ffffff +# define CONSTANT_COLOR_ZERO 0x00000000 +#define CRC_CMDFIFO_ADDR 0x0740 +#define CRC_CMDFIFO_DOUT 0x0744 +#define GRPH_BUFFER_CNTL 0x02f0 +# define GRPH_START_REQ_MASK (0x7f) +# define GRPH_START_REQ_SHIFT 0 +# define GRPH_STOP_REQ_MASK (0x7f<<8) +# define GRPH_STOP_REQ_SHIFT 8 +# define GRPH_CRITICAL_POINT_MASK (0x7f<<16) +# define GRPH_CRITICAL_POINT_SHIFT 16 +# define GRPH_CRITICAL_CNTL (1<<28) +# define GRPH_BUFFER_SIZE (1<<29) +# define GRPH_CRITICAL_AT_SOF (1<<30) +# define GRPH_STOP_CNTL (1<<31) +#define GRPH2_BUFFER_CNTL 0x03f0 +# define GRPH2_START_REQ_MASK (0x7f) +# define GRPH2_START_REQ_SHIFT 0 +# define GRPH2_STOP_REQ_MASK (0x7f<<8) +# define GRPH2_STOP_REQ_SHIFT 8 +# define GRPH2_CRITICAL_POINT_MASK (0x7f<<16) +# define GRPH2_CRITICAL_POINT_SHIFT 16 +# define GRPH2_CRITICAL_CNTL (1<<28) +# define GRPH2_BUFFER_SIZE (1<<29) +# define GRPH2_CRITICAL_AT_SOF (1<<30) +# define GRPH2_STOP_CNTL (1<<31) +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_EXT_CNTL 0x0054 +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR (1 << 3) +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define CRTC_GEN_CNTL 0x0050 +# define CRTC_DBL_SCAN_EN (1 << 0) +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN (1 << 16) +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_CSYNC_EN (1 << 27) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define CRTC_MORE_CNTL 0x27c +# define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +# define CRTC_HSYNC_EN (1 << 16) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022c +#define CRTC2_PITCH 0x032c +#define CRTC_STATUS 0x005c +# define CRTC_VBLANK_SAVE (1 << 1) +# define CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define CRTC2_STATUS 0x03fc +# define CRTC2_VBLANK_SAVE (1 << 1) +# define CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define CRTC_V_SYNC_STRT_WID 0x020c +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030c +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC2_STATUS 0x03fc +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define CUR_CLR0 0x026c +#define CUR_CLR1 0x0270 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_OFFSET 0x0260 +# define CUR_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define CUR2_HORZ_VERT_OFF 0x0368 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_OFFSET 0x0360 +# define CUR2_LOCK (1 << 31) + +#define DAC_CNTL 0x0058 +# define DAC_RANGE_CNTL (3 << 0) +# define DAC_RANGE_CNTL_MASK 0x03 +# define DAC_BLANKING (1 << 2) +# define DAC_CMP_EN (1 << 3) +# define DAC_CMP_OUTPUT (1 << 7) +# define DAC_8BIT_EN (1 << 8) +# define DAC_TVO_EN (1 << 10) +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_PDWN (1 << 15) +# define DAC_MASK_ALL (0xff << 24) +#define DAC_CNTL2 0x007c +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define DAC_EXT_CNTL 0x0280 +# define DAC_FORCE_BLANK_OFF_EN (1 << 4) +# define DAC_FORCE_DATA_EN (1 << 5) +# define DAC_FORCE_DATA_SEL_MASK (3 << 6) +# define DAC_FORCE_DATA_MASK 0x0003ff00 +# define DAC_FORCE_DATA_SHIFT 8 +#define DAC_MACRO_CNTL 0x0d04 +# define DAC_PDWN_R (1 << 16) +# define DAC_PDWN_G (1 << 17) +# define DAC_PDWN_B (1 << 18) +#define DISP_HW_DEBUG 0x0d14 +# define CRT2_DISP1_SEL (1 << 5) +#define DISP_OUTPUT_CNTL 0x0d64 +# define DISP_DAC_SOURCE_MASK 0x03 +# define DISP_DAC2_SOURCE_MASK 0x0c +# define DISP_DAC_SOURCE_CRTC2 0x01 +# define DISP_DAC2_SOURCE_CRTC2 0x04 +# define DISP_TV_SOURCE (1 << 16) +# define DISP_TV_MODE_MASK (3 << 17) +# define DISP_TV_MODE_888 (0 << 17) +# define DISP_TV_MODE_565 (1 << 17) +# define DISP_TV_YG_DITH_EN (1 << 19) +# define DISP_TV_CBB_CRR_DITH_EN (1 << 20) +# define DISP_TV_BIT_WIDTH (1 << 21) +# define DISP_TV_SYNC_MODE_MASK (3 << 22) +# define DISP_TV_SYNC_COLOR_MASK (3 << 25) +#define DAC_CRC_SIG 0x02cc +#define DAC_DATA 0x03c9 /* VGA */ +#define DAC_MASK 0x03c6 /* VGA */ +#define DAC_R_INDEX 0x03c7 /* VGA */ +#define DAC_W_INDEX 0x03c8 /* VGA */ +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH 0x16e4 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define DISP_MISC_CNTL 0x0d00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MERGE_CNTL 0x0d60 +# define DISP_ALPHA_MODE_MASK 0x03 +# define DISP_ALPHA_MODE_KEY 0 +# define DISP_ALPHA_MODE_PER_PIXEL 1 +# define DISP_ALPHA_MODE_GLOBAL 2 +# define DISP_RGB_OFFSET_EN (1<<8) +# define DISP_GRPH_ALPHA_MASK (0xff << 16) +# define DISP_OV0_ALPHA_MASK (0xff << 24) +# define DISP_LIN_TRANS_BYPASS (0x01 << 9) +#define DISP2_MERGE_CNTL 0x0d68 +# define DISP2_RGB_OFFSET_EN (1<<8) +#define DISP_LIN_TRANS_GRPH_A 0x0d80 +#define DISP_LIN_TRANS_GRPH_B 0x0d84 +#define DISP_LIN_TRANS_GRPH_C 0x0d88 +#define DISP_LIN_TRANS_GRPH_D 0x0d8c +#define DISP_LIN_TRANS_GRPH_E 0x0d90 +#define DISP_LIN_TRANS_GRPH_F 0x0d98 +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DP_BRUSH_FRGD_CLR 0x147c +#define DP_CNTL 0x16c0 +# define DST_X_LEFT_TO_RIGHT (1 << 0) +# define DST_Y_TOP_TO_BOTTOM (1 << 1) +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +# define DST_Y_MAJOR (1 << 2) +# define DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +# define DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define DP_DATATYPE 0x16c4 +# define DST_8BPP 0x00000002 +# define DST_15BPP 0x00000003 +# define DST_16BPP 0x00000004 +# define DST_24BPP 0x00000005 +# define DST_32BPP 0x00000006 +# define DST_8BPP_RGB332 0x00000007 +# define DST_8BPP_Y8 0x00000008 +# define DST_8BPP_RGB8 0x00000009 +# define DST_16BPP_VYUY422 0x0000000b +# define DST_16BPP_YVYU422 0x0000000c +# define DST_32BPP_AYUV444 0x0000000e +# define DST_16BPP_ARGB4444 0x0000000f +# define BRUSH_SOLIDCOLOR 0x00000d00 +# define SRC_MONO 0x00000000 +# define SRC_MONO_LBKGD 0x00010000 +# define SRC_DSTCOLOR 0x00030000 +# define BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define BYTE_ORDER_LSB_TO_MSB 0x40000000 +# define DP_CONVERSION_TEMP 0x80000000 +# define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_GUI_MASTER_CNTL 0x146c +# define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define GMC_SRC_CLIPPING (1 << 2) +# define GMC_DST_CLIPPING (1 << 3) +# define GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define GMC_BRUSH_8x8_COLOR (10 << 4) +# define GMC_BRUSH_1X8_COLOR (12 << 4) +# define GMC_BRUSH_SOLID_COLOR (13 << 4) +# define GMC_BRUSH_NONE (15 << 4) +# define GMC_DST_8BPP (2 << 8) +# define GMC_DST_15BPP (3 << 8) +# define GMC_DST_16BPP (4 << 8) +# define GMC_DST_24BPP (5 << 8) +# define GMC_DST_32BPP (6 << 8) +# define GMC_DST_8BPP_RGB (7 << 8) +# define GMC_DST_Y8 (8 << 8) +# define GMC_DST_RGB8 (9 << 8) +# define GMC_DST_VYUY (11 << 8) +# define GMC_DST_YVYU (12 << 8) +# define GMC_DST_AYUV444 (14 << 8) +# define GMC_DST_ARGB4444 (15 << 8) +# define GMC_DST_DATATYPE_MASK (0x0f << 8) +# define GMC_DST_DATATYPE_SHIFT 8 +# define GMC_SRC_DATATYPE_MASK (3 << 12) +# define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define GMC_SRC_DATATYPE_COLOR (3 << 12) +# define GMC_BYTE_PIX_ORDER (1 << 14) +# define GMC_BYTE_MSB_TO_LSB (0 << 14) +# define GMC_BYTE_LSB_TO_MSB (1 << 14) +# define GMC_CONVERSION_TEMP (1 << 15) +# define GMC_CONVERSION_TEMP_6500 (0 << 15) +# define GMC_CONVERSION_TEMP_9300 (1 << 15) +# define GMC_ROP3_MASK (0xff << 16) +# define GMC_ROP3_PATCOPY 0x00f00000 +# define GMC_ROP3_SRCCOPY 0x00cc0000 +# define GMC_ROP3_PATXOR 0x005a0000 +# define GMC_ROP3_XOR 0x00660000 +# define GMC_DP_SRC_SOURCE_MASK (7 << 24) +# define GMC_DP_SRC_SOURCE_MEMORY (2 << 24) +# define GMC_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define GMC_3D_FCN_EN (1 << 27) +# define GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define GMC_AUX_CLIP_DIS (1 << 29) +# define GMC_WR_MSK_DIS (1 << 30) +# define GMC_LD_BRUSH_Y_X (1 << 31) +#define DP_GUI_MASTER_CNTL_C 0x1c84 +#define DP_MIX 0x16c8 +#define DP_SRC_BKGD_CLR 0x15dc +#define DP_SRC_FRGD_CLR 0x15d8 +#define DP_WRITE_MASK 0x16cc +#define DST_BRES_DEC 0x1630 +#define DST_BRES_ERR 0x1628 +#define DST_BRES_INC 0x162c +#define DST_BRES_LNTH 0x1634 +#define DST_BRES_LNTH_SUB 0x1638 +#define DST_HEIGHT 0x1410 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_HEIGHT_WIDTH_8 0x158c +#define DST_HEIGHT_WIDTH_BW 0x15b4 +#define DST_HEIGHT_Y 0x15a0 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define DST_LINE_PATCOUNT 0x1608 +# define BRES_CNTL_SHIFT 8 +#define DST_OFFSET 0x1404 +#define DST_PITCH 0x1408 +#define DST_PITCH_OFFSET 0x142c +#define DST_PITCH_OFFSET_C 0x1c80 +# define PITCH_SHIFT 21 +# define DST_TILE_LINEAR (0 << 30) +# define DST_TILE_MACRO (1 << 30) +# define DST_TILE_MICRO (2 << 30) +# define DST_TILE_BOTH (3 << 30) +#define DST_WIDTH 0x140c +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_WIDTH_X 0x1588 +#define DST_WIDTH_X_INCY 0x159c +#define DST_X 0x141c +#define DST_X_SUB 0x15a4 +#define DST_X_Y 0x1594 +#define DST_Y 0x1420 +#define DST_Y_SUB 0x15a8 +#define DST_Y_X 0x1438 + +#define FCP_CNTL 0x0910 +# define FCP0_SRC_PCICLK 0 +# define FCP0_SRC_PCLK 1 +# define FCP0_SRC_PCLKb 2 +# define FCP0_SRC_HREF 3 +# define FCP0_SRC_GND 4 +# define FCP0_SRC_HREFb 5 +#define FLUSH_1 0x1704 +#define FLUSH_2 0x1708 +#define FLUSH_3 0x170c +#define FLUSH_4 0x1710 +#define FLUSH_5 0x1714 +#define FLUSH_6 0x1718 +#define FLUSH_7 0x171c +#define FOG_3D_TABLE_START 0x1810 +#define FOG_3D_TABLE_END 0x1814 +#define FOG_3D_TABLE_DENSITY 0x181c +#define FOG_TABLE_INDEX 0x1a14 +#define FOG_TABLE_DATA 0x1a18 +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define FP_GEN_CNTL 0x0284 +# define FP_FPON (1 << 0) +# define FP_BLANK_EN (1 << 1) +# define FP_TMDS_EN (1 << 2) +# define FP_PANEL_FORMAT (1 << 3) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define R200_FP_SOURCE_SEL_MASK (3 << 10) +# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP_SOURCE_SEL_RMX (2 << 10) +# define R200_FP_SOURCE_SEL_TRANS (3 << 10) +# define FP_SEL_CRTC1 (0 << 13) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +# define FP2_BLANK_EN (1 << 1) +# define FP2_ON (1 << 2) +# define FP2_PANEL_FORMAT (1 << 3) +# define R200_FP2_SOURCE_SEL_MASK (3 << 10) +# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP2_SOURCE_SEL_RMX (2 << 10) +# define FP2_SRC_SEL_MASK (3 << 13) +# define FP2_SRC_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +# define FP2_DVO_EN (1 << 25) +# define FP2_DVO_RATE_SEL_SDR (1 << 26) +#define FP_H_SYNC_STRT_WID 0x02c4 +#define FP2_H_SYNC_STRT_WID 0x03c4 +#define FP_HORZ_STRETCH 0x028c +#define FP_HORZ2_STRETCH 0x038c +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_V_SYNC_STRT_WID 0x02c8 +#define FP_VERT_STRETCH 0x0290 +#define FP2_V_SYNC_STRT_WID 0x03c8 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 + +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +# define VSYNC2_INT_AK (1 << 6) +# define VSYNC2_INT (1 << 6) +#define GENENB 0x03c3 /* VGA */ +#define GENFC_RD 0x03ca /* VGA */ +#define GENFC_WT 0x03da /* VGA, 0x03ba */ +#define GENMO_RD 0x03cc /* VGA */ +#define GENMO_WT 0x03c2 /* VGA */ +#define GENS0 0x03c2 /* VGA */ +#define GENS1 0x03da /* VGA, 0x03ba */ +#define GPIO_MONID 0x0068 /* DDC interface via I2C */ +#define GPIO_MONIDB 0x006c +#define GPIO_CRT2_DDC 0x006c +#define GPIO_DVI_DDC 0x0064 +#define GPIO_VGA_DDC 0x0060 +# define GPIO_A_0 (1 << 0) +# define GPIO_A_1 (1 << 1) +# define GPIO_Y_0 (1 << 8) +# define GPIO_Y_1 (1 << 9) +# define GPIO_Y_SHIFT_0 8 +# define GPIO_Y_SHIFT_1 9 +# define GPIO_EN_0 (1 << 16) +# define GPIO_EN_1 (1 << 17) +# define GPIO_MASK_0 (1 << 24) /*??*/ +# define GPIO_MASK_1 (1 << 25) /*??*/ +#define GRPH8_DATA 0x03cf /* VGA */ +#define GRPH8_IDX 0x03ce /* VGA */ +#define GUI_SCRATCH_REG0 0x15e0 +#define GUI_SCRATCH_REG1 0x15e4 +#define GUI_SCRATCH_REG2 0x15e8 +#define GUI_SCRATCH_REG3 0x15ec +#define GUI_SCRATCH_REG4 0x15f0 +#define GUI_SCRATCH_REG5 0x15f4 + +#define HEADER 0x0f0e /* PCI */ +#define HOST_DATA0 0x17c0 +#define HOST_DATA1 0x17c4 +#define HOST_DATA2 0x17c8 +#define HOST_DATA3 0x17cc +#define HOST_DATA4 0x17d0 +#define HOST_DATA5 0x17d4 +#define HOST_DATA6 0x17d8 +#define HOST_DATA7 0x17dc +#define HOST_DATA_LAST 0x17e0 +#define HOST_PATH_CNTL 0x0130 +# define HDP_SOFT_RESET (1 << 26) +#define HTOTAL_CNTL 0x0009 /* PLL */ +#define HTOTAL2_CNTL 0x002e /* PLL */ + +#define I2C_CNTL_1 0x0094 /* ? */ +#define DVI_I2C_CNTL_1 0x02e4 /* ? */ +#define INTERRUPT_LINE 0x0f3c /* PCI */ +#define INTERRUPT_PIN 0x0f3d /* PCI */ +#define IO_BASE 0x0f14 /* PCI */ + +#define LATENCY 0x0f0d /* PCI */ +#define LEAD_BRES_DEC 0x1608 +#define LEAD_BRES_LNTH 0x161c +#define LEAD_BRES_LNTH_SUB 0x1624 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) + +#define MAX_LATENCY 0x0f3f /* PCI */ +#define MC_AGP_LOCATION 0x014c +#define MC_FB_LOCATION 0x0148 +#define CRTC_BASE_ADDR 0x023c +#define CRTC2_BASE_ADDR 0x033c +#define DISPLAY_TEST_DEBUG_CNTL 0x0d10 +#define NB_TOM 0x015c +#define MCLK_CNTL 0x0012 /* PLL */ +# define FORCEON_MCLKA (1 << 16) +# define FORCEON_MCLKB (1 << 17) +# define FORCEON_YCLKA (1 << 18) +# define FORCEON_YCLKB (1 << 19) +# define FORCEON_MC (1 << 20) +# define FORCEON_AIC (1 << 21) +# define R300_DISABLE_MC_MCLKA (1 << 21) +# define R300_DISABLE_MC_MCLKB (1 << 21) +#define MCLK_MISC 0x001f /* PLL */ +# define MC_MCLK_MAX_DYN_STOP_LAT (1<<12) +# define IO_MCLK_MAX_DYN_STOP_LAT (1<<13) +# define MC_MCLK_DYN_ENABLE (1 << 14) +# define IO_MCLK_DYN_ENABLE (1 << 14) +#define MDGPIO_A_REG 0x01ac +#define MDGPIO_EN_REG 0x01b0 +#define MDGPIO_MASK 0x0198 +#define MDGPIO_Y_REG 0x01b4 +#define MEM_ADDR_CONFIG 0x0148 +#define MEM_BASE 0x0f10 /* PCI */ +#define MEM_CNTL 0x0140 +# define MEM_NUM_CHANNELS_MASK 0x01 +# define MEM_USE_B_CH_ONLY (1<<1) +# define RV100_HALF_MODE (1<<3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1<<2) +#define MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define MEM_INIT_LAT_TIMER 0x0154 +#define MEM_INTF_CNTL 0x014c +#define MEM_SDRAM_MODE_REG 0x0158 +#define MEM_STR_CNTL 0x0150 +#define MEM_VGA_RP_SEL 0x003c +#define MEM_VGA_WP_SEL 0x0038 +#define MIN_GRANT 0x0f3e /* PCI */ +#define MM_DATA 0x0004 +#define MM_INDEX 0x0000 +#define MPLL_CNTL 0x000e /* PLL */ +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define R300_MC_IND_INDEX 0x01f8 +# define R300_MC_IND_ADDR_MASK 0x3f +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +# define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +# define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define N_VIF_COUNT 0x0248 + +/* overlay */ +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001 +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002 +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004 +# define REG_LD_CTL_LOCK_READBACK 0x00000008 +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001 +# define SCALER_Y2R_TEMP 0x00000002 +# define SCALER_HORZ_PICK_NEAREST 0x00000004 +# define SCALER_VERT_PICK_NEAREST 0x00000008 +# define SCALER_SIGNED_UV 0x00000010 +# define SCALER_GAMMA_SEL_MASK 0x00000060 +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000 +# define SCALER_GAMMA_SEL_G22 0x00000020 +# define SCALER_GAMMA_SEL_G18 0x00000040 +# define SCALER_GAMMA_SEL_G14 0x00000060 +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080 +# define SCALER_SURFAC_FORMAT 0x00000f00 +# define SCALER_SOURCE_UNK0 0x00000000 /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100 /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200 /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300 +# define SCALER_SOURCE_16BPP 0x00000400 +/*# define SCALER_SOURCE_24BPP 0x00000500*/ +# define SCALER_SOURCE_32BPP 0x00000600 +# define SCALER_SOURCE_UNK3 0x00000700 /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800 /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900 /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00 +# define SCALER_SOURCE_VYUY422 0x00000B00 +# define SCALER_SOURCE_YVYU422 0x00000C00 +# define SCALER_SOURCE_UNK5 0x00000D00 /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00 /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00 /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000 +# define R200_SCALER_TEMPORAL_DEINT 0x00002000 +# define SCALER_UNKNOWN_FLAG1 0x00004000 /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000 +# define SCALER_BURST_PER_PLANE 0x007f0000 +# define SCALER_DOUBLE_BUFFER 0x01000000 +# define SCALER_UNKNOWN_FLAG3 0x02000000 /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000 /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000 +# define SCALER_PRG_LOAD_START 0x10000000 +# define SCALER_INT_EMU 0x20000000 +# define SCALER_ENABLE 0x40000000 +# define SCALER_SOFT_RESET 0x80000000 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003 +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000 +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003 +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000 +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fff +# define P1_ACTIVE_LINES_M1 0x0fff0000 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ff +# define P23_ACTIVE_LINES_M1 0x07ff0000 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001 +# define VIF_BUF0_TILE_ADRS 0x00000002 +# define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001 +# define VIF_BUF1_TILE_ADRS 0x00000002 +# define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001 +# define VIF_BUF2_TILE_ADRS 0x00000002 +# define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001 +# define VIF_BUF3_TILE_ADRS 0x00000002 +# define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001 +# define VIF_BUF4_TILE_ADRS 0x00000002 +# define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001 +# define VIF_BUF5_TILE_ADRS 0x00000002 +# define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0 +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARD_SCALE_HORZ_Y 0x00000001 +# define FILTER_HARD_SCALE_HORZ_UV 0x00000002 +# define FILTER_HARD_SCALE_VERT_Y 0x00000004 +# define FILTER_HARD_SCALE_VERT_UV 0x00000008 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +#define OV0_FOUR_TAP_COEF_0 0x04B0 +# define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_3 0x04BC +# define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_4 0x04C0 +# define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 +#define OV0_FLAG_CNTL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +# define VIDEO_KEY_FN_MASK 0x00000003 +# define VIDEO_KEY_FN_FALSE 0x00000000 +# define VIDEO_KEY_FN_TRUE 0x00000001 +# define VIDEO_KEY_FN_EQ 0x00000002 +# define VIDEO_KEY_FN_NE 0x00000003 +# define GRAPHIC_KEY_FN_MASK 0x00000030 +# define GRAPHIC_KEY_FN_FALSE 0x00000000 +# define GRAPHIC_KEY_FN_TRUE 0x00000010 +# define GRAPHIC_KEY_FN_EQ 0x00000020 +# define GRAPHIC_KEY_FN_NE 0x00000030 +# define CMP_MIX_MASK 0x00000100 +# define CMP_MIX_OR 0x00000000 +# define CMP_MIX_AND 0x00000100 +#define OV0_TEST 0x04F8 +# define OV0_SCALER_Y2R_DISABLE 0x00000001 +# define OV0_SUBPIC_ONLY 0x00000008 +# define OV0_EXTENSE 0x00000010 +# define OV0_SWAP_UV 0x00000020 +#define OV0_COL_CONV 0x04FC +# define OV0_CB_TO_B 0x0000007F +# define OV0_CB_TO_G 0x0000FF00 +# define OV0_CR_TO_G 0x00FF0000 +# define OV0_CR_TO_R 0x7F000000 +# define OV0_NEW_COL_CONV 0x80000000 +#define OV1_Y_X_START 0x0600 +#define OV1_Y_X_END 0x0604 +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_000_00F 0x0d40 +#define OV0_GAMMA_010_01F 0x0d44 +#define OV0_GAMMA_020_03F 0x0d48 +#define OV0_GAMMA_040_07F 0x0d4c +#define OV0_GAMMA_080_0BF 0x0e00 +#define OV0_GAMMA_0C0_0FF 0x0e04 +#define OV0_GAMMA_100_13F 0x0e08 +#define OV0_GAMMA_140_17F 0x0e0c +#define OV0_GAMMA_180_1BF 0x0e10 +#define OV0_GAMMA_1C0_1FF 0x0e14 +#define OV0_GAMMA_200_23F 0x0e18 +#define OV0_GAMMA_240_27F 0x0e1c +#define OV0_GAMMA_280_2BF 0x0e20 +#define OV0_GAMMA_2C0_2FF 0x0e24 +#define OV0_GAMMA_300_33F 0x0e28 +#define OV0_GAMMA_340_37F 0x0e2c +#define OV0_GAMMA_380_3BF 0x0d50 +#define OV0_GAMMA_3C0_3FF 0x0d54 + +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 + +/* subpicture */ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define P2PLL_CNTL 0x002a /* P2PLL */ +# define P2PLL_RESET (1 << 0) +# define P2PLL_SLEEP (1 << 1) +# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +# define P2PLL_FB0_DIV_MASK 0x07ff +# define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV 0x002B /* PLL */ +# define P2PLL_REF_DIV_MASK 0x03ff +# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +# define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define PALETTE_DATA 0x00b4 +#define PALETTE_30_DATA 0x00b8 +#define PALETTE_INDEX 0x00b0 +#define PCI_GART_PAGE 0x017c +#define PIXCLKS_CNTL 0x002d +# define PIX2CLK_SRC_SEL_MASK 0x03 +# define PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +# define PIX2CLK_ALWAYS_ONb (1<<6) +# define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define PIXCLK_TV_SRC_SEL (1 << 8) +# define DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +# define R300_DVOCLK_ALWAYS_ONb (1 << 10) +# define PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +# define PIXCLK_GV_ALWAYS_ONb (1 << 12) +# define PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +# define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +# define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +#define PLANE_3D_MASK_C 0x1d44 +#define PLL_TEST_CNTL 0x0013 /* PLL */ +#define PMI_CAP_ID 0x0f5c /* PCI */ +#define PMI_DATA 0x0f63 /* PCI */ +#define PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define PMI_PMC_REG 0x0f5e /* PCI */ +#define PMI_PMCSR_REG 0x0f60 /* PCI */ +#define PMI_REGISTER 0x0f5c /* PCI */ +#define PPLL_CNTL 0x0002 /* PLL */ +# define PPLL_RESET (1 << 0) +# define PPLL_SLEEP (1 << 1) +# define PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define PPLL_DIV_0 0x0004 /* PLL */ +#define PPLL_DIV_1 0x0005 /* PLL */ +#define PPLL_DIV_2 0x0006 /* PLL */ +#define PPLL_DIV_3 0x0007 /* PLL */ +# define PPLL_FB3_DIV_MASK 0x07ff +# define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_REF_DIV 0x0003 /* PLL */ +# define PPLL_REF_DIV_MASK 0x03ff +# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +/* ERT registers */ +#define TV_MASTER_CNTL 0x0800 +# define TV_MASTER_TVCLK_ALWAYS_ONb (1 << 30) +# define TV_MASTER_TV_ON (1 << 31) +#define TV_RGB_CNTL 0x0804 +# define TV_RGB_CNTL_INI 0x007b0004 +#define TV_SYNC_CNTL 0x0808 +#define TV_HTOTAL 0x080c +#define TV_HDISP 0x0810 +#define TV_HSTART 0x0818 +#define TV_HCOUNT 0x081c +#define TV_VTOTAL 0x0820 +#define TV_VDISP 0x0824 +#define TV_VCOUNT 0x0828 +#define TV_FTOTAL 0x082c +#define TV_FCOUNT 0x0830 +#define TV_FRESTART 0x0834 +#define TV_HRESTART 0x0838 +#define TV_VRESTART 0x083c +#define TV_HOST_READ_DATA 0x0840 +#define TV_HOST_WRITE_DATA 0x0844 +#define TV_HOST_RD_WT_CNTL 0x0848 +#define TV_VSCALER_CNTL1 0x084c +# define TV_VSCALER_RESTART_FIELD (1 << 29) +#define TV_TIMING_CNTL 0x0850 +#define TV_VSCALER_CNTL2 0x0854 +#define TV_Y_FALL_CNTL 0x0858 +#define TV_Y_RISE_CNTL 0x085c +#define TV_Y_SAWTOOTH_CNTL 0x0860 +#define TV_UPSAMP_AND_GAIN_CNTL 0x0864 +#define TV_GAIN_LIMIT_SETTINGS 0x0868 +#define TV_LINEAR_GAIN_SETTINGS 0x086c +#define TV_MODULATOR_CNTL1 0x0870 +#define TV_MODULATOR_CNTL2 0x0874 +#define TV_PRE_DAC_MUX_CNTL 0x0888 +# define TV_PRE_DAC_Y_RED_EN (1 << 0) +# define TV_PRE_DAC_C_GRN_EN (1 << 1) +# define TV_PRE_DAC_CMP_BLU_EN (1 << 2) +# define TV_PRE_DAC_RED_MX_FORCE_DAC_DATA (6 << 4) +# define TV_PRE_DAC_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define TV_PRE_DAC_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define TV_FORCE_DAC_DATA_SHIFT 16 +#define TV_DAC_CNTL 0x088c +# define TV_DAC_NBLANK (1 << 0) +# define TV_DAC_NHOLD (1 << 1) +# define TV_DAC_CMPOUT (1 << 5) +# define TV_DAC_BGSLEEP (1 << 6) +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define TV_CRC_CNTL 0x0890 +#define TV_UV_ADR 0x08ac +/* ERT PLL registers */ +#define TV_PLL_CNTL 0x21 +#define TV_PLL_CNTL1 0x22 +# define TV_PLL_CNTL1_TVPLL_RESET (1 << 1) +# define TV_PLL_CNTL1_TVPLL_SLEEP (1 << 3) +# define TV_PLL_CNTL1_TVPDC_SHIFT 14 +# define TV_PLL_CNTL1_TVPDC_MASK (3 << 14) +# define TV_PLL_CNTL1_TVCLK_SRC_SEL (1 << 30) + + +#define RBBM_GUICNTL 0x172c +# define HOST_DATA_SWAP_NONE (0 << 0) +# define HOST_DATA_SWAP_16BIT (1 << 0) +# define HOST_DATA_SWAP_32BIT (2 << 0) +# define HOST_DATA_SWAP_HDW (3 << 0) +#define RBBM_SOFT_RESET 0x00f0 +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_STATUS 0x0e40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RB2D_DSTCACHE_MODE 0x3428 +# define RB2D_DC_CACHE_ENABLE (0) +# define RB2D_DC_2D_CACHE_DISABLE (1) +# define RB2D_DC_3D_CACHE_DISABLE (2) +# define RB2D_DC_CACHE_DISABLE (3) +# define RB2D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +# define RB2D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +# define RB2D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +# define RB2D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +# define R200_RB2D_DC_2D_CACHE_AUTOFREE (1 << 10) +# define R200_RB2D_DC_3D_CACHE_AUTOFREE (2 << 10) +# define RB2D_DC_FORCE_RMW (1 << 16) +# define R300_RB2D_DC_ENABLE (1 << 17) +# define RB2D_DC_DISABLE_RI_FILL (1 << 24) +# define RB2D_DC_DISABLE_RI_READ (1 << 25) +# define RB2D_DC_DISABLE_MASK_CHK (1 << 26) +#define RB2D_DSTCACHE_CTLSTAT 0x342c +# define RB2D_DC_FLUSH (3 << 0) +# define RB2D_DC_FREE (3 << 2) +# define RB2D_DC_FLUSH_ALL 0xf +# define RB2D_DC_BUSY (1 << 31) +#define RB3D_DSTCACHE_MODE 0x3258 +# define RB3D_DC_CACHE_ENABLE (0) +# define RB3D_DC_2D_CACHE_DISABLE (1) +# define RB3D_DC_3D_CACHE_DISABLE (2) +# define RB3D_DC_CACHE_DISABLE (3) +# define RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +# define RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +# define RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +# define RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) +# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) +# define RB3D_DC_FORCE_RMW (1 << 16) +# define R300_RB3D_DC_ENABLE (1 << 17) +# define RB3D_DC_DISABLE_RI_FILL (1 << 24) +# define RB3D_DC_DISABLE_RI_READ (1 << 25) +# define RB3D_DC_DISABLE_MASK_CHK (1 << 26) +#define RB3D_DSTCACHE_CTLSTAT 0x325C +# define RB3D_DC_FLUSH (3 << 0) +# define RB3D_DC_FREE (3 << 2) +# define RB3D_DC_FLUSH_ALL 0xf +# define RB3D_DC_BUSY (1 << 31) +#define REG_BASE 0x0f18 /* PCI */ +#define REGPROG_INF 0x0f09 /* PCI */ +#define REVISION_ID 0x0f08 /* PCI */ + +#define SC_BOTTOM 0x164c +#define SC_BOTTOM_RIGHT 0x16f0 +#define SC_BOTTOM_RIGHT_C 0x1c8c +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_TOP_LEFT 0x16ec +#define SC_TOP_LEFT_C 0x1c88 +# define SC_SIGN_MASK_LO 0x8000 +# define SC_SIGN_MASK_HI 0x80000000 +#define SCLK_CNTL 0x000d /* PLL */ +# define SCLK_SRC_SEL_MASK 0x0007 +# define DYN_STOP_LAT_MASK 0x00007ff8 +# define CP_MAX_DYN_STOP_LAT 0x0008 +# define SCLK_FORCEON_MASK 0xffff8000 +# define SCLK_FORCE_DISP2 (1<<15) +# define SCLK_FORCE_CP (1<<16) +# define SCLK_FORCE_HDP (1<<17) +# define SCLK_FORCE_DISP1 (1<<18) +# define SCLK_FORCE_TOP (1<<19) +# define SCLK_FORCE_E2 (1<<20) +# define SCLK_FORCE_SE (1<<21) +# define SCLK_FORCE_IDCT (1<<22) +# define SCLK_FORCE_VIP (1<<23) +# define SCLK_FORCE_RE (1<<24) +# define SCLK_FORCE_PB (1<<25) +# define SCLK_FORCE_TAM (1<<26) +# define SCLK_FORCE_TDM (1<<27) +# define SCLK_FORCE_RB (1<<28) +# define SCLK_FORCE_TV_SCLK (1<<29) +# define SCLK_FORCE_SUBPIC (1<<30) +# define SCLK_FORCE_OV0 (1<<31) +# define R300_SCLK_FORCE_VAP (1<<21) +# define R300_SCLK_FORCE_SR (1<<25) +# define R300_SCLK_FORCE_PX (1<<26) +# define R300_SCLK_FORCE_TX (1<<27) +# define R300_SCLK_FORCE_US (1<<28) +# define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +# define R300_SCLK_FORCE_TCL (1<<13) +# define R300_SCLK_FORCE_CBA (1<<14) +# define R300_SCLK_FORCE_GA (1<<15) +#define SCLK_MORE_CNTL 0x0035 /* PLL */ +# define SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 +# define SCLK_MORE_FORCEON 0x0700 +#define SDRAM_MODE_REG 0x0158 +#define SEQ8_DATA 0x03c5 /* VGA */ +#define SEQ8_IDX 0x03c4 /* VGA */ +#define SNAPSHOT_F_COUNT 0x0244 +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_VIF_COUNT 0x024c +#define SRC_OFFSET 0x15ac +#define SRC_PITCH 0x15b0 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_SC_BOTTOM 0x165c +#define SRC_SC_BOTTOM_RIGHT 0x16f4 +#define SRC_SC_RIGHT 0x1654 +#define SRC_X 0x1414 +#define SRC_X_Y 0x1590 +#define SRC_Y 0x1418 +#define SRC_Y_X 0x1434 +#define STATUS 0x0f06 /* PCI */ +#define SUB_CLASS 0x0f0a /* PCI */ +#define SURFACE_CNTL 0x0b00 +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (1 << 21) +# define NONSURF_AP1_SWP_16BPP (1 << 22) +# define NONSURF_AP1_SWP_32BPP (1 << 23) +#define SURFACE0_INFO 0x0b0c +#define SURFACE0_LOWER_BOUND 0x0b04 +#define SURFACE0_UPPER_BOUND 0x0b08 +#define SURFACE1_INFO 0x0b1c +#define SURFACE1_LOWER_BOUND 0x0b14 +#define SURFACE1_UPPER_BOUND 0x0b18 +#define SURFACE2_INFO 0x0b2c +#define SURFACE2_LOWER_BOUND 0x0b24 +#define SURFACE2_UPPER_BOUND 0x0b28 +#define SURFACE3_INFO 0x0b3c +#define SURFACE3_LOWER_BOUND 0x0b34 +#define SURFACE3_UPPER_BOUND 0x0b38 +#define SURFACE4_INFO 0x0b4c +#define SURFACE4_LOWER_BOUND 0x0b44 +#define SURFACE4_UPPER_BOUND 0x0b48 +#define SURFACE5_INFO 0x0b5c +#define SURFACE5_LOWER_BOUND 0x0b54 +#define SURFACE5_UPPER_BOUND 0x0b58 +#define SURFACE6_INFO 0x0b6c +#define SURFACE6_LOWER_BOUND 0x0b64 +#define SURFACE6_UPPER_BOUND 0x0b68 +#define SURFACE7_INFO 0x0b7c +#define SURFACE7_LOWER_BOUND 0x0b74 +#define SURFACE7_UPPER_BOUND 0x0b78 +#define SW_SEMAPHORE 0x013c + +#define TEST_DEBUG_CNTL 0x0120 +#define TEST_DEBUG_MUX 0x0124 +#define TEST_DEBUG_OUT 0x012c +#define TMDS_PLL_CNTL 0x02a8 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +# define TMDS_TRANSMITTER_PLLEN 1 +# define TMDS_TRANSMITTER_PLLRST 2 +#define TRAIL_BRES_DEC 0x1614 +#define TRAIL_BRES_ERR 0x160c +#define TRAIL_BRES_INC 0x1610 +#define TRAIL_X 0x1618 +#define TRAIL_X_SUB 0x1620 + +#define VCLK_ECP_CNTL 0x0008 /* PLL */ +# define VCLK_SRC_SEL_MASK 0x03 +# define VCLK_SRC_SEL_CPUCLK 0x00 +# define VCLK_SRC_SEL_PSCANCLK 0x01 +# define VCLK_SRC_SEL_BYTECLK 0x02 +# define VCLK_SRC_SEL_PPLLCLK 0x03 +# define PIXCLK_ALWAYS_ONb (1<<6) +# define PIXCLK_DAC_ALWAYS_ONb (1<<7) +# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +#define VGA_DDA_CONFIG 0x02e8 +#define VGA_DDA_ON_OFF 0x02ec +#define VID_BUFFER_CONTROL 0x0900 +#define VIDEOMUX_CNTL 0x0190 +#define VIPH_CONTROL 0x0c40 /* ? */ + +#define WAIT_UNTIL 0x1720 +# define WAIT_CRTC_PFLIP (1 << 0) +# define R300_WAIT_2D_IDLE (1 << 0) +# define R300_WAIT_3D_IDLE (2 << 0) +# define R300_WAIT_2D_IDLECLEAN (3 << 0) +# define R300_WAIT_3D_IDLECLEAN (4 << 0) +# define WAIT_2D_IDLE (1 << 14) +# define WAIT_3D_IDLE (1 << 15) +# define WAIT_2D_IDLECLEAN (1 << 16) +# define WAIT_3D_IDLECLEAN (1 << 17) +# define WAIT_HOST_IDLECLEAN (1 << 18) + +#define ISYNC_CNTL 0x1724 +# define ISYNC_ANY2D_IDLE3D (1 << 0) +# define ISYNC_ANY3D_IDLE2D (1 << 1) +# define ISYNC_TRIG2D_IDLE3D (1 << 2) +# define ISYNC_TRIG3D_IDLE2D (1 << 3) +# define ISYNC_WAIT_IDLEGUI (1 << 4) +# define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) + +#define X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define XCLK_CNTL 0x000d /* PLL */ +#define XDLL_CNTL 0x000c /* PLL */ +#define XPLL_CNTL 0x000b /* PLL */ + + + + /* Registers for 3D/TCL */ +#define PP_BORDER_COLOR_0 0x1d40 +#define PP_BORDER_COLOR_1 0x1d44 +#define PP_BORDER_COLOR_2 0x1d48 +#define PP_CNTL 0x1c38 +# define STIPPLE_ENABLE (1 << 0) +# define SCISSOR_ENABLE (1 << 1) +# define PATTERN_ENABLE (1 << 2) +# define SHADOW_ENABLE (1 << 3) +# define TEX_ENABLE_MASK (0xf << 4) +# define TEX_0_ENABLE (1 << 4) +# define TEX_1_ENABLE (1 << 5) +# define TEX_2_ENABLE (1 << 6) +# define TEX_3_ENABLE (1 << 7) +# define TEX_BLEND_ENABLE_MASK (0xf << 12) +# define TEX_BLEND_0_ENABLE (1 << 12) +# define TEX_BLEND_1_ENABLE (1 << 13) +# define TEX_BLEND_2_ENABLE (1 << 14) +# define TEX_BLEND_3_ENABLE (1 << 15) +# define PLANAR_YUV_ENABLE (1 << 20) +# define SPECULAR_ENABLE (1 << 21) +# define FOG_ENABLE (1 << 22) +# define ALPHA_TEST_ENABLE (1 << 23) +# define ANTI_ALIAS_NONE (0 << 24) +# define ANTI_ALIAS_LINE (1 << 24) +# define ANTI_ALIAS_POLY (2 << 24) +# define ANTI_ALIAS_LINE_POLY (3 << 24) +# define BUMP_MAP_ENABLE (1 << 26) +# define BUMPED_MAP_T0 (0 << 27) +# define BUMPED_MAP_T1 (1 << 27) +# define BUMPED_MAP_T2 (2 << 27) +# define TEX_3D_ENABLE_0 (1 << 29) +# define TEX_3D_ENABLE_1 (1 << 30) +# define MC_ENABLE (1 << 31) +#define PP_FOG_COLOR 0x1c18 +# define FOG_COLOR_MASK 0x00ffffff +# define FOG_VERTEX (0 << 24) +# define FOG_TABLE (1 << 24) +# define FOG_USE_DEPTH (0 << 25) +# define FOG_USE_DIFFUSE_ALPHA (2 << 25) +# define FOG_USE_SPEC_ALPHA (3 << 25) +#define PP_LUM_MATRIX 0x1d00 +#define PP_MISC 0x1c14 +# define REF_ALPHA_MASK 0x000000ff +# define ALPHA_TEST_FAIL (0 << 8) +# define ALPHA_TEST_LESS (1 << 8) +# define ALPHA_TEST_LEQUAL (2 << 8) +# define ALPHA_TEST_EQUAL (3 << 8) +# define ALPHA_TEST_GEQUAL (4 << 8) +# define ALPHA_TEST_GREATER (5 << 8) +# define ALPHA_TEST_NEQUAL (6 << 8) +# define ALPHA_TEST_PASS (7 << 8) +# define ALPHA_TEST_OP_MASK (7 << 8) +# define CHROMA_FUNC_FAIL (0 << 16) +# define CHROMA_FUNC_PASS (1 << 16) +# define CHROMA_FUNC_NEQUAL (2 << 16) +# define CHROMA_FUNC_EQUAL (3 << 16) +# define CHROMA_KEY_NEAREST (0 << 18) +# define CHROMA_KEY_ZERO (1 << 18) +# define SHADOW_ID_AUTO_INC (1 << 20) +# define SHADOW_FUNC_EQUAL (0 << 21) +# define SHADOW_FUNC_NEQUAL (1 << 21) +# define SHADOW_PASS_1 (0 << 22) +# define SHADOW_PASS_2 (1 << 22) +# define RIGHT_HAND_CUBE_D3D (0 << 24) +# define RIGHT_HAND_CUBE_OGL (1 << 24) +#define PP_ROT_MATRIX_0 0x1d58 +#define PP_ROT_MATRIX_1 0x1d5c +#define PP_TXFILTER_0 0x1c54 +#define PP_TXFILTER_1 0x1c6c +#define PP_TXFILTER_2 0x1c84 +# define MAG_FILTER_NEAREST (0 << 0) +# define MAG_FILTER_LINEAR (1 << 0) +# define MAG_FILTER_MASK (1 << 0) +# define MIN_FILTER_NEAREST (0 << 1) +# define MIN_FILTER_LINEAR (1 << 1) +# define MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define MIN_FILTER_ANISO_NEAREST (8 << 1) +# define MIN_FILTER_ANISO_LINEAR (9 << 1) +# define MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define MIN_FILTER_MASK (15 << 1) +# define MAX_ANISO_1_TO_1 (0 << 5) +# define MAX_ANISO_2_TO_1 (1 << 5) +# define MAX_ANISO_4_TO_1 (2 << 5) +# define MAX_ANISO_8_TO_1 (3 << 5) +# define MAX_ANISO_16_TO_1 (4 << 5) +# define MAX_ANISO_MASK (7 << 5) +# define LOD_BIAS_MASK (0xff << 8) +# define LOD_BIAS_SHIFT 8 +# define MAX_MIP_LEVEL_MASK (0x0f << 16) +# define MAX_MIP_LEVEL_SHIFT 16 +# define YUV_TO_RGB (1 << 20) +# define YUV_TEMPERATURE_COOL (0 << 21) +# define YUV_TEMPERATURE_HOT (1 << 21) +# define YUV_TEMPERATURE_MASK (1 << 21) +# define WRAPEN_S (1 << 22) +# define CLAMP_S_WRAP (0 << 23) +# define CLAMP_S_MIRROR (1 << 23) +# define CLAMP_S_CLAMP_LAST (2 << 23) +# define CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define CLAMP_S_CLAMP_BORDER (4 << 23) +# define CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define CLAMP_S_CLAMP_GL (6 << 23) +# define CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define CLAMP_S_MASK (7 << 23) +# define WRAPEN_T (1 << 26) +# define CLAMP_T_WRAP (0 << 27) +# define CLAMP_T_MIRROR (1 << 27) +# define CLAMP_T_CLAMP_LAST (2 << 27) +# define CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define CLAMP_T_CLAMP_BORDER (4 << 27) +# define CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define CLAMP_T_CLAMP_GL (6 << 27) +# define CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define CLAMP_T_MASK (7 << 27) +# define BORDER_MODE_OGL (0 << 31) +# define BORDER_MODE_D3D (1 << 31) +#define PP_TXFORMAT_0 0x1c58 +#define PP_TXFORMAT_1 0x1c70 +#define PP_TXFORMAT_2 0x1c88 +# define TXFORMAT_I8 (0 << 0) +# define TXFORMAT_AI88 (1 << 0) +# define TXFORMAT_RGB332 (2 << 0) +# define TXFORMAT_ARGB1555 (3 << 0) +# define TXFORMAT_RGB565 (4 << 0) +# define TXFORMAT_ARGB4444 (5 << 0) +# define TXFORMAT_ARGB8888 (6 << 0) +# define TXFORMAT_RGBA8888 (7 << 0) +# define TXFORMAT_Y8 (8 << 0) +# define TXFORMAT_VYUY422 (10 << 0) +# define TXFORMAT_YVYU422 (11 << 0) +# define TXFORMAT_DXT1 (12 << 0) +# define TXFORMAT_DXT23 (14 << 0) +# define TXFORMAT_DXT45 (15 << 0) +# define TXFORMAT_FORMAT_MASK (31 << 0) +# define TXFORMAT_FORMAT_SHIFT 0 +# define TXFORMAT_APPLE_YUV_MODE (1 << 5) +# define TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define TXFORMAT_NON_POWER2 (1 << 7) +# define TXFORMAT_WIDTH_MASK (15 << 8) +# define TXFORMAT_WIDTH_SHIFT 8 +# define TXFORMAT_HEIGHT_MASK (15 << 12) +# define TXFORMAT_HEIGHT_SHIFT 12 +# define TXFORMAT_F5_WIDTH_MASK (15 << 16) +# define TXFORMAT_F5_WIDTH_SHIFT 16 +# define TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define TXFORMAT_F5_HEIGHT_SHIFT 20 +# define TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define TXFORMAT_ST_ROUTE_MASK (3 << 24) +# define TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +# define TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +# define TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +# define TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +# define TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +# define TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define PP_CUBIC_FACES_0 0x1d24 +#define PP_CUBIC_FACES_1 0x1d28 +#define PP_CUBIC_FACES_2 0x1d2c +# define FACE_WIDTH_1_SHIFT 0 +# define FACE_HEIGHT_1_SHIFT 4 +# define FACE_WIDTH_1_MASK (0xf << 0) +# define FACE_HEIGHT_1_MASK (0xf << 4) +# define FACE_WIDTH_2_SHIFT 8 +# define FACE_HEIGHT_2_SHIFT 12 +# define FACE_WIDTH_2_MASK (0xf << 8) +# define FACE_HEIGHT_2_MASK (0xf << 12) +# define FACE_WIDTH_3_SHIFT 16 +# define FACE_HEIGHT_3_SHIFT 20 +# define FACE_WIDTH_3_MASK (0xf << 16) +# define FACE_HEIGHT_3_MASK (0xf << 20) +# define FACE_WIDTH_4_SHIFT 24 +# define FACE_HEIGHT_4_SHIFT 28 +# define FACE_WIDTH_4_MASK (0xf << 24) +# define FACE_HEIGHT_4_MASK (0xf << 28) + +#define PP_TXOFFSET_0 0x1c5c +#define PP_TXOFFSET_1 0x1c74 +#define PP_TXOFFSET_2 0x1c8c +# define TXO_ENDIAN_NO_SWAP (0 << 0) +# define TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define TXO_ENDIAN_WORD_SWAP (2 << 0) +# define TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define TXO_MACRO_LINEAR (0 << 2) +# define TXO_MACRO_TILE (1 << 2) +# define TXO_MICRO_LINEAR (0 << 3) +# define TXO_MICRO_TILE_X2 (1 << 3) +# define TXO_MICRO_TILE_OPT (2 << 3) +# define TXO_OFFSET_MASK 0xffffffe0 +# define TXO_OFFSET_SHIFT 5 + +#define PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define PP_CUBIC_OFFSET_T0_3 0x1ddc +#define PP_CUBIC_OFFSET_T0_4 0x1de0 +#define PP_CUBIC_OFFSET_T1_0 0x1e00 +#define PP_CUBIC_OFFSET_T1_1 0x1e04 +#define PP_CUBIC_OFFSET_T1_2 0x1e08 +#define PP_CUBIC_OFFSET_T1_3 0x1e0c +#define PP_CUBIC_OFFSET_T1_4 0x1e10 +#define PP_CUBIC_OFFSET_T2_0 0x1e14 +#define PP_CUBIC_OFFSET_T2_1 0x1e18 +#define PP_CUBIC_OFFSET_T2_2 0x1e1c +#define PP_CUBIC_OFFSET_T2_3 0x1e20 +#define PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define PP_TEX_SIZE_1 0x1d0c +#define PP_TEX_SIZE_2 0x1d14 +# define TEX_USIZE_MASK (0x7ff << 0) +# define TEX_USIZE_SHIFT 0 +# define TEX_VSIZE_MASK (0x7ff << 16) +# define TEX_VSIZE_SHIFT 16 +# define SIGNED_RGB_MASK (1 << 30) +# define SIGNED_RGB_SHIFT 30 +# define SIGNED_ALPHA_MASK (1 << 31) +# define SIGNED_ALPHA_SHIFT 31 +#define PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define PP_TXCBLEND_0 0x1c60 +#define PP_TXCBLEND_1 0x1c78 +#define PP_TXCBLEND_2 0x1c90 +# define COLOR_ARG_A_SHIFT 0 +# define COLOR_ARG_A_MASK (0x1f << 0) +# define COLOR_ARG_A_ZERO (0 << 0) +# define COLOR_ARG_A_CURRENT_COLOR (2 << 0) +# define COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +# define COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +# define COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +# define COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +# define COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +# define COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +# define COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +# define COLOR_ARG_A_T0_COLOR (10 << 0) +# define COLOR_ARG_A_T0_ALPHA (11 << 0) +# define COLOR_ARG_A_T1_COLOR (12 << 0) +# define COLOR_ARG_A_T1_ALPHA (13 << 0) +# define COLOR_ARG_A_T2_COLOR (14 << 0) +# define COLOR_ARG_A_T2_ALPHA (15 << 0) +# define COLOR_ARG_A_T3_COLOR (16 << 0) +# define COLOR_ARG_A_T3_ALPHA (17 << 0) +# define COLOR_ARG_B_SHIFT 5 +# define COLOR_ARG_B_MASK (0x1f << 5) +# define COLOR_ARG_B_ZERO (0 << 5) +# define COLOR_ARG_B_CURRENT_COLOR (2 << 5) +# define COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +# define COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +# define COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +# define COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +# define COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +# define COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +# define COLOR_ARG_B_T0_COLOR (10 << 5) +# define COLOR_ARG_B_T0_ALPHA (11 << 5) +# define COLOR_ARG_B_T1_COLOR (12 << 5) +# define COLOR_ARG_B_T1_ALPHA (13 << 5) +# define COLOR_ARG_B_T2_COLOR (14 << 5) +# define COLOR_ARG_B_T2_ALPHA (15 << 5) +# define COLOR_ARG_B_T3_COLOR (16 << 5) +# define COLOR_ARG_B_T3_ALPHA (17 << 5) +# define COLOR_ARG_C_SHIFT 10 +# define COLOR_ARG_C_MASK (0x1f << 10) +# define COLOR_ARG_C_ZERO (0 << 10) +# define COLOR_ARG_C_CURRENT_COLOR (2 << 10) +# define COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +# define COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +# define COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +# define COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +# define COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +# define COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +# define COLOR_ARG_C_T0_COLOR (10 << 10) +# define COLOR_ARG_C_T0_ALPHA (11 << 10) +# define COLOR_ARG_C_T1_COLOR (12 << 10) +# define COLOR_ARG_C_T1_ALPHA (13 << 10) +# define COLOR_ARG_C_T2_COLOR (14 << 10) +# define COLOR_ARG_C_T2_ALPHA (15 << 10) +# define COLOR_ARG_C_T3_COLOR (16 << 10) +# define COLOR_ARG_C_T3_ALPHA (17 << 10) +# define COMP_ARG_A (1 << 15) +# define COMP_ARG_A_SHIFT 15 +# define COMP_ARG_B (1 << 16) +# define COMP_ARG_B_SHIFT 16 +# define COMP_ARG_C (1 << 17) +# define COMP_ARG_C_SHIFT 17 +# define BLEND_CTL_MASK (7 << 18) +# define BLEND_CTL_ADD (0 << 18) +# define BLEND_CTL_SUBTRACT (1 << 18) +# define BLEND_CTL_ADDSIGNED (2 << 18) +# define BLEND_CTL_BLEND (3 << 18) +# define BLEND_CTL_DOT3 (4 << 18) +# define SCALE_SHIFT 21 +# define SCALE_MASK (3 << 21) +# define SCALE_1X (0 << 21) +# define SCALE_2X (1 << 21) +# define SCALE_4X (2 << 21) +# define CLAMP_TX (1 << 23) +# define T0_EQ_TCUR (1 << 24) +# define T1_EQ_TCUR (1 << 25) +# define T2_EQ_TCUR (1 << 26) +# define T3_EQ_TCUR (1 << 27) +# define COLOR_ARG_MASK 0x1f +# define COMP_ARG_SHIFT 15 +#define PP_TXABLEND_0 0x1c64 +#define PP_TXABLEND_1 0x1c7c +#define PP_TXABLEND_2 0x1c94 +# define ALPHA_ARG_A_SHIFT 0 +# define ALPHA_ARG_A_MASK (0xf << 0) +# define ALPHA_ARG_A_ZERO (0 << 0) +# define ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +# define ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +# define ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +# define ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +# define ALPHA_ARG_A_T0_ALPHA (5 << 0) +# define ALPHA_ARG_A_T1_ALPHA (6 << 0) +# define ALPHA_ARG_A_T2_ALPHA (7 << 0) +# define ALPHA_ARG_A_T3_ALPHA (8 << 0) +# define ALPHA_ARG_B_SHIFT 4 +# define ALPHA_ARG_B_MASK (0xf << 4) +# define ALPHA_ARG_B_ZERO (0 << 4) +# define ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +# define ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +# define ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +# define ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +# define ALPHA_ARG_B_T0_ALPHA (5 << 4) +# define ALPHA_ARG_B_T1_ALPHA (6 << 4) +# define ALPHA_ARG_B_T2_ALPHA (7 << 4) +# define ALPHA_ARG_B_T3_ALPHA (8 << 4) +# define ALPHA_ARG_C_SHIFT 8 +# define ALPHA_ARG_C_MASK (0xf << 8) +# define ALPHA_ARG_C_ZERO (0 << 8) +# define ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +# define ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +# define ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +# define ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +# define ALPHA_ARG_C_T0_ALPHA (5 << 8) +# define ALPHA_ARG_C_T1_ALPHA (6 << 8) +# define ALPHA_ARG_C_T2_ALPHA (7 << 8) +# define ALPHA_ARG_C_T3_ALPHA (8 << 8) +# define DOT_ALPHA_DONT_REPLICATE (1 << 9) +# define ALPHA_ARG_MASK 0xf + +#define PP_TFACTOR_0 0x1c68 +#define PP_TFACTOR_1 0x1c80 +#define PP_TFACTOR_2 0x1c98 + +#define RB3D_BLENDCNTL 0x1c20 +# define COMB_FCN_MASK (3 << 12) +# define COMB_FCN_ADD_CLAMP (0 << 12) +# define COMB_FCN_ADD_NOCLAMP (1 << 12) +# define COMB_FCN_SUB_CLAMP (2 << 12) +# define COMB_FCN_SUB_NOCLAMP (3 << 12) +# define SRC_BLEND_GL_ZERO (32 << 16) +# define SRC_BLEND_GL_ONE (33 << 16) +# define SRC_BLEND_GL_SRC_COLOR (34 << 16) +# define SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +# define SRC_BLEND_GL_DST_COLOR (36 << 16) +# define SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +# define SRC_BLEND_GL_SRC_ALPHA (38 << 16) +# define SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +# define SRC_BLEND_GL_DST_ALPHA (40 << 16) +# define SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +# define SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +# define SRC_BLEND_MASK (63 << 16) +# define DST_BLEND_GL_ZERO (32 << 24) +# define DST_BLEND_GL_ONE (33 << 24) +# define DST_BLEND_GL_SRC_COLOR (34 << 24) +# define DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +# define DST_BLEND_GL_DST_COLOR (36 << 24) +# define DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +# define DST_BLEND_GL_SRC_ALPHA (38 << 24) +# define DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +# define DST_BLEND_GL_DST_ALPHA (40 << 24) +# define DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +# define DST_BLEND_MASK (63 << 24) +#define RB3D_CNTL 0x1c3c +# define ALPHA_BLEND_ENABLE (1 << 0) +# define PLANE_MASK_ENABLE (1 << 1) +# define DITHER_ENABLE (1 << 2) +# define ROUND_ENABLE (1 << 3) +# define SCALE_DITHER_ENABLE (1 << 4) +# define DITHER_INIT (1 << 5) +# define ROP_ENABLE (1 << 6) +# define STENCIL_ENABLE (1 << 7) +# define Z_ENABLE (1 << 8) +# define DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define COLOR_FORMAT_ARGB1555 (3 << 10) +# define COLOR_FORMAT_RGB565 (4 << 10) +# define COLOR_FORMAT_ARGB8888 (6 << 10) +# define COLOR_FORMAT_RGB332 (7 << 10) +# define COLOR_FORMAT_Y8 (8 << 10) +# define COLOR_FORMAT_RGB8 (9 << 10) +# define COLOR_FORMAT_YUV422_VYUY (11 << 10) +# define COLOR_FORMAT_YUV422_YVYU (12 << 10) +# define COLOR_FORMAT_AVYU (14 << 10) +# define COLOR_FORMAT_ARGB4444 (15 << 10) +# define CLRCMP_FLIP_ENABLE (1 << 14) +# define SEPARATE_ALPHA_ENABLE (1 << 16) +#define RB3D_COLOROFFSET 0x1c40 +# define COLOROFFSET_MASK 0xfffffff0 +#define RB3D_COLORPITCH 0x1c48 +# define COLORPITCH_MASK 0x000001ff8 +# define COLOR_TILE_ENABLE (1 << 16) +# define COLOR_MICROTILE_ENABLE (1 << 17) +# define COLOR_ENDIAN_NO_SWAP (0 << 18) +# define COLOR_ENDIAN_WORD_SWAP (1 << 18) +# define COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RB3D_DEPTHOFFSET 0x1c24 +#define RB3D_DEPTHPITCH 0x1c28 +# define DEPTHPITCH_MASK 0x00001ff8 +# define DEPTH_ENDIAN_NO_SWAP (0 << 18) +# define DEPTH_ENDIAN_WORD_SWAP (1 << 18) +# define DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RB3D_PLANEMASK 0x1d84 +#define RB3D_ROPCNTL 0x1d80 +# define ROP_MASK (15 << 8) +# define ROP_CLEAR (0 << 8) +# define ROP_NOR (1 << 8) +# define ROP_AND_INVERTED (2 << 8) +# define ROP_COPY_INVERTED (3 << 8) +# define ROP_AND_REVERSE (4 << 8) +# define ROP_INVERT (5 << 8) +# define ROP_XOR (6 << 8) +# define ROP_NAND (7 << 8) +# define ROP_AND (8 << 8) +# define ROP_EQUIV (9 << 8) +# define ROP_NOOP (10 << 8) +# define ROP_OR_INVERTED (11 << 8) +# define ROP_COPY (12 << 8) +# define ROP_OR_REVERSE (13 << 8) +# define ROP_OR (14 << 8) +# define ROP_SET (15 << 8) +#define RB3D_STENCILREFMASK 0x1d7c +# define STENCIL_REF_SHIFT 0 +# define STENCIL_REF_MASK (0xff << 0) +# define STENCIL_MASK_SHIFT 16 +# define STENCIL_VALUE_MASK (0xff << 16) +# define STENCIL_WRITEMASK_SHIFT 24 +# define STENCIL_WRITE_MASK (0xff << 24) +#define RB3D_ZSTENCILCNTL 0x1c2c +# define DEPTH_FORMAT_MASK (0xf << 0) +# define DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +# define DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +# define DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +# define DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +# define DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +# define DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +# define DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +# define Z_TEST_NEVER (0 << 4) +# define Z_TEST_LESS (1 << 4) +# define Z_TEST_LEQUAL (2 << 4) +# define Z_TEST_EQUAL (3 << 4) +# define Z_TEST_GEQUAL (4 << 4) +# define Z_TEST_GREATER (5 << 4) +# define Z_TEST_NEQUAL (6 << 4) +# define Z_TEST_ALWAYS (7 << 4) +# define Z_TEST_MASK (7 << 4) +# define STENCIL_TEST_NEVER (0 << 12) +# define STENCIL_TEST_LESS (1 << 12) +# define STENCIL_TEST_LEQUAL (2 << 12) +# define STENCIL_TEST_EQUAL (3 << 12) +# define STENCIL_TEST_GEQUAL (4 << 12) +# define STENCIL_TEST_GREATER (5 << 12) +# define STENCIL_TEST_NEQUAL (6 << 12) +# define STENCIL_TEST_ALWAYS (7 << 12) +# define STENCIL_TEST_MASK (0x7 << 12) +# define STENCIL_FAIL_KEEP (0 << 16) +# define STENCIL_FAIL_ZERO (1 << 16) +# define STENCIL_FAIL_REPLACE (2 << 16) +# define STENCIL_FAIL_INC (3 << 16) +# define STENCIL_FAIL_DEC (4 << 16) +# define STENCIL_FAIL_INVERT (5 << 16) +# define STENCIL_FAIL_MASK (0x7 << 16) +# define STENCIL_ZPASS_KEEP (0 << 20) +# define STENCIL_ZPASS_ZERO (1 << 20) +# define STENCIL_ZPASS_REPLACE (2 << 20) +# define STENCIL_ZPASS_INC (3 << 20) +# define STENCIL_ZPASS_DEC (4 << 20) +# define STENCIL_ZPASS_INVERT (5 << 20) +# define STENCIL_ZPASS_MASK (0x7 << 20) +# define STENCIL_ZFAIL_KEEP (0 << 24) +# define STENCIL_ZFAIL_ZERO (1 << 24) +# define STENCIL_ZFAIL_REPLACE (2 << 24) +# define STENCIL_ZFAIL_INC (3 << 24) +# define STENCIL_ZFAIL_DEC (4 << 24) +# define STENCIL_ZFAIL_INVERT (5 << 24) +# define STENCIL_ZFAIL_MASK (0x7 << 24) +# define Z_COMPRESSION_ENABLE (1 << 28) +# define FORCE_Z_DIRTY (1 << 29) +# define Z_WRITE_ENABLE (1 << 30) +#define RE_LINE_PATTERN 0x1cd0 +# define LINE_PATTERN_MASK 0x0000ffff +# define LINE_REPEAT_COUNT_SHIFT 16 +# define LINE_PATTERN_START_SHIFT 24 +# define LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +# define LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +# define LINE_PATTERN_AUTO_RESET (1 << 29) +#define RE_LINE_STATE 0x1cd4 +# define LINE_CURRENT_PTR_SHIFT 0 +# define LINE_CURRENT_COUNT_SHIFT 8 +#define RE_MISC 0x26c4 +# define STIPPLE_COORD_MASK 0x1f +# define STIPPLE_X_OFFSET_SHIFT 0 +# define STIPPLE_X_OFFSET_MASK (0x1f << 0) +# define STIPPLE_Y_OFFSET_SHIFT 8 +# define STIPPLE_Y_OFFSET_MASK (0x1f << 8) +# define STIPPLE_LITTLE_BIT_ORDER (0 << 16) +# define STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RE_SOLID_COLOR 0x1c1c +#define RE_POINTSIZE 0x2648 +# define RE_POINTSIZE_SHIFT 0 +# define RE_MAXPOINTSIZE_SHIFT 16 +#define RE_TOP_LEFT 0x26c0 +# define RE_LEFT_SHIFT 0 +# define RE_TOP_SHIFT 16 +#define RE_BOTTOM_RIGHT 0x1c44 +# define RE_RIGHT_SHIFT 0 +# define RE_BOTTOM_SHIFT 16 + +#define SE_CNTL 0x1c4c +# define FFACE_CULL_CW (0 << 0) +# define FFACE_CULL_CCW (1 << 0) +# define FFACE_CULL_DIR_MASK (1 << 0) +# define BFACE_CULL (0 << 1) +# define BFACE_SOLID (3 << 1) +# define FFACE_CULL (0 << 3) +# define FFACE_SOLID (3 << 3) +# define FFACE_CULL_MASK (3 << 3) +# define BADVTX_CULL_DISABLE (1 << 5) +# define FLAT_SHADE_VTX_0 (0 << 6) +# define FLAT_SHADE_VTX_1 (1 << 6) +# define FLAT_SHADE_VTX_2 (2 << 6) +# define FLAT_SHADE_VTX_LAST (3 << 6) +# define DIFFUSE_SHADE_SOLID (0 << 8) +# define DIFFUSE_SHADE_FLAT (1 << 8) +# define DIFFUSE_SHADE_GOURAUD (2 << 8) +# define DIFFUSE_SHADE_MASK (3 << 8) +# define ALPHA_SHADE_SOLID (0 << 10) +# define ALPHA_SHADE_FLAT (1 << 10) +# define ALPHA_SHADE_GOURAUD (2 << 10) +# define ALPHA_SHADE_MASK (3 << 10) +# define SPECULAR_SHADE_SOLID (0 << 12) +# define SPECULAR_SHADE_FLAT (1 << 12) +# define SPECULAR_SHADE_GOURAUD (2 << 12) +# define SPECULAR_SHADE_MASK (3 << 12) +# define FOG_SHADE_SOLID (0 << 14) +# define FOG_SHADE_FLAT (1 << 14) +# define FOG_SHADE_GOURAUD (2 << 14) +# define FOG_SHADE_MASK (3 << 14) +# define ZBIAS_ENABLE_POINT (1 << 16) +# define ZBIAS_ENABLE_LINE (1 << 17) +# define ZBIAS_ENABLE_TRI (1 << 18) +# define WIDELINE_ENABLE (1 << 20) +# define VPORT_XY_XFORM_ENABLE (1 << 24) +# define VPORT_Z_XFORM_ENABLE (1 << 25) +# define VTX_PIX_CENTER_D3D (0 << 27) +# define VTX_PIX_CENTER_OGL (1 << 27) +# define ROUND_MODE_TRUNC (0 << 28) +# define ROUND_MODE_ROUND (1 << 28) +# define ROUND_MODE_ROUND_EVEN (2 << 28) +# define ROUND_MODE_ROUND_ODD (3 << 28) +# define ROUND_PREC_16TH_PIX (0 << 30) +# define ROUND_PREC_8TH_PIX (1 << 30) +# define ROUND_PREC_4TH_PIX (2 << 30) +# define ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +# define R200_STIPPLE_ENABLE 0x1 +# define R200_SCISSOR_ENABLE 0x2 +# define R200_PATTERN_ENABLE 0x4 +# define R200_PERSPECTIVE_ENABLE 0x8 +# define R200_POINT_SMOOTH 0x20 +# define R200_VTX_STQ0_D3D 0x00010000 +# define R200_VTX_STQ1_D3D 0x00040000 +# define R200_VTX_STQ2_D3D 0x00100000 +# define R200_VTX_STQ3_D3D 0x00400000 +# define R200_VTX_STQ4_D3D 0x01000000 +# define R200_VTX_STQ5_D3D 0x04000000 +#define SE_CNTL_STATUS 0x2140 +# define VC_NO_SWAP (0 << 0) +# define VC_16BIT_SWAP (1 << 0) +# define VC_32BIT_SWAP (2 << 0) +# define VC_HALF_DWORD_SWAP (3 << 0) +# define TCL_BYPASS (1 << 8) +#define SE_COORD_FMT 0x1c50 +# define VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +# define VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +# define VTX_ST0_NONPARAMETRIC (1 << 8) +# define VTX_ST1_NONPARAMETRIC (1 << 9) +# define VTX_ST2_NONPARAMETRIC (1 << 10) +# define VTX_ST3_NONPARAMETRIC (1 << 11) +# define VTX_W0_NORMALIZE (1 << 12) +# define VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +# define VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +# define VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +# define VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +# define VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +# define TEX1_W_ROUTING_USE_W0 (0 << 26) +# define TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define SE_LINE_WIDTH 0x1db8 +#define SE_TCL_LIGHT_MODEL_CTL 0x226c +# define LIGHTING_ENABLE (1 << 0) +# define LIGHT_IN_MODELSPACE (1 << 1) +# define LOCAL_VIEWER (1 << 2) +# define NORMALIZE_NORMALS (1 << 3) +# define RESCALE_NORMALS (1 << 4) +# define SPECULAR_LIGHTS (1 << 5) +# define DIFFUSE_SPECULAR_COMBINE (1 << 6) +# define LIGHT_ALPHA (1 << 7) +# define LOCAL_LIGHT_VEC_GL (1 << 8) +# define LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +# define LM_SOURCE_STATE_PREMULT 0 +# define LM_SOURCE_STATE_MULT 1 +# define LM_SOURCE_VERTEX_DIFFUSE 2 +# define LM_SOURCE_VERTEX_SPECULAR 3 +# define EMISSIVE_SOURCE_SHIFT 16 +# define AMBIENT_SOURCE_SHIFT 18 +# define DIFFUSE_SOURCE_SHIFT 20 +# define SPECULAR_SOURCE_SHIFT 22 +#define SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define SE_TCL_MATRIX_SELECT_0 0x225c +# define MODELVIEW_0_SHIFT 0 +# define MODELVIEW_1_SHIFT 4 +# define MODELVIEW_2_SHIFT 8 +# define MODELVIEW_3_SHIFT 12 +# define IT_MODELVIEW_0_SHIFT 16 +# define IT_MODELVIEW_1_SHIFT 20 +# define IT_MODELVIEW_2_SHIFT 24 +# define IT_MODELVIEW_3_SHIFT 28 +#define SE_TCL_MATRIX_SELECT_1 0x2260 +# define MODELPROJECT_0_SHIFT 0 +# define MODELPROJECT_1_SHIFT 4 +# define MODELPROJECT_2_SHIFT 8 +# define MODELPROJECT_3_SHIFT 12 +# define TEXMAT_0_SHIFT 16 +# define TEXMAT_1_SHIFT 20 +# define TEXMAT_2_SHIFT 24 +# define TEXMAT_3_SHIFT 28 + + +#define SE_TCL_OUTPUT_VTX_FMT 0x2254 +# define TCL_VTX_W0 (1 << 0) +# define TCL_VTX_FP_DIFFUSE (1 << 1) +# define TCL_VTX_FP_ALPHA (1 << 2) +# define TCL_VTX_PK_DIFFUSE (1 << 3) +# define TCL_VTX_FP_SPEC (1 << 4) +# define TCL_VTX_FP_FOG (1 << 5) +# define TCL_VTX_PK_SPEC (1 << 6) +# define TCL_VTX_ST0 (1 << 7) +# define TCL_VTX_ST1 (1 << 8) +# define TCL_VTX_Q1 (1 << 9) +# define TCL_VTX_ST2 (1 << 10) +# define TCL_VTX_Q2 (1 << 11) +# define TCL_VTX_ST3 (1 << 12) +# define TCL_VTX_Q3 (1 << 13) +# define TCL_VTX_Q0 (1 << 14) +# define TCL_VTX_WEIGHT_COUNT_SHIFT 15 +# define TCL_VTX_NORM0 (1 << 18) +# define TCL_VTX_XY1 (1 << 27) +# define TCL_VTX_Z1 (1 << 28) +# define TCL_VTX_W1 (1 << 29) +# define TCL_VTX_NORM1 (1 << 30) +# define TCL_VTX_Z0 (1 << 31) + +#define SE_TCL_OUTPUT_VTX_SEL 0x2258 +# define TCL_COMPUTE_XYZW (1 << 0) +# define TCL_COMPUTE_DIFFUSE (1 << 1) +# define TCL_COMPUTE_SPECULAR (1 << 2) +# define TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +# define TCL_FORCE_INORDER_PROC (1 << 4) +# define TCL_TEX_INPUT_TEX_0 0 +# define TCL_TEX_INPUT_TEX_1 1 +# define TCL_TEX_INPUT_TEX_2 2 +# define TCL_TEX_INPUT_TEX_3 3 +# define TCL_TEX_COMPUTED_TEX_0 8 +# define TCL_TEX_COMPUTED_TEX_1 9 +# define TCL_TEX_COMPUTED_TEX_2 10 +# define TCL_TEX_COMPUTED_TEX_3 11 +# define TCL_TEX_0_OUTPUT_SHIFT 16 +# define TCL_TEX_1_OUTPUT_SHIFT 20 +# define TCL_TEX_2_OUTPUT_SHIFT 24 +# define TCL_TEX_3_OUTPUT_SHIFT 28 + +#define SE_TCL_PER_LIGHT_CTL_0 0x2270 +# define LIGHT_0_ENABLE (1 << 0) +# define LIGHT_0_ENABLE_AMBIENT (1 << 1) +# define LIGHT_0_ENABLE_SPECULAR (1 << 2) +# define LIGHT_0_IS_LOCAL (1 << 3) +# define LIGHT_0_IS_SPOT (1 << 4) +# define LIGHT_0_DUAL_CONE (1 << 5) +# define LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +# define LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +# define LIGHT_0_SHIFT 0 +# define LIGHT_1_ENABLE (1 << 16) +# define LIGHT_1_ENABLE_AMBIENT (1 << 17) +# define LIGHT_1_ENABLE_SPECULAR (1 << 18) +# define LIGHT_1_IS_LOCAL (1 << 19) +# define LIGHT_1_IS_SPOT (1 << 20) +# define LIGHT_1_DUAL_CONE (1 << 21) +# define LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +# define LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +# define LIGHT_1_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_1 0x2274 +# define LIGHT_2_SHIFT 0 +# define LIGHT_3_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_2 0x2278 +# define LIGHT_4_SHIFT 0 +# define LIGHT_5_SHIFT 16 +#define SE_TCL_PER_LIGHT_CTL_3 0x227c +# define LIGHT_6_SHIFT 0 +# define LIGHT_7_SHIFT 16 + +#define SE_TCL_SHININESS 0x2250 + +#define SE_TCL_TEXTURE_PROC_CTL 0x2268 +# define TEXGEN_TEXMAT_0_ENABLE (1 << 0) +# define TEXGEN_TEXMAT_1_ENABLE (1 << 1) +# define TEXGEN_TEXMAT_2_ENABLE (1 << 2) +# define TEXGEN_TEXMAT_3_ENABLE (1 << 3) +# define TEXMAT_0_ENABLE (1 << 4) +# define TEXMAT_1_ENABLE (1 << 5) +# define TEXMAT_2_ENABLE (1 << 6) +# define TEXMAT_3_ENABLE (1 << 7) +# define TEXGEN_INPUT_MASK 0xf +# define TEXGEN_INPUT_TEXCOORD_0 0 +# define TEXGEN_INPUT_TEXCOORD_1 1 +# define TEXGEN_INPUT_TEXCOORD_2 2 +# define TEXGEN_INPUT_TEXCOORD_3 3 +# define TEXGEN_INPUT_OBJ 4 +# define TEXGEN_INPUT_EYE 5 +# define TEXGEN_INPUT_EYE_NORMAL 6 +# define TEXGEN_INPUT_EYE_REFLECT 7 +# define TEXGEN_INPUT_EYE_NORMALIZED 8 +# define TEXGEN_0_INPUT_SHIFT 16 +# define TEXGEN_1_INPUT_SHIFT 20 +# define TEXGEN_2_INPUT_SHIFT 24 +# define TEXGEN_3_INPUT_SHIFT 28 + +#define SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +# define UCP_IN_CLIP_SPACE (1 << 0) +# define UCP_IN_MODEL_SPACE (1 << 1) +# define UCP_ENABLE_0 (1 << 2) +# define UCP_ENABLE_1 (1 << 3) +# define UCP_ENABLE_2 (1 << 4) +# define UCP_ENABLE_3 (1 << 5) +# define UCP_ENABLE_4 (1 << 6) +# define UCP_ENABLE_5 (1 << 7) +# define TCL_FOG_MASK (3 << 8) +# define TCL_FOG_DISABLE (0 << 8) +# define TCL_FOG_EXP (1 << 8) +# define TCL_FOG_EXP2 (2 << 8) +# define TCL_FOG_LINEAR (3 << 8) +# define RNG_BASED_FOG (1 << 10) +# define LIGHT_TWOSIDE (1 << 11) +# define BLEND_OP_COUNT_MASK (7 << 12) +# define BLEND_OP_COUNT_SHIFT 12 +# define POSITION_BLEND_OP_ENABLE (1 << 16) +# define NORMAL_BLEND_OP_ENABLE (1 << 17) +# define VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) +# define VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +# define VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) +# define VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +# define VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) +# define VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +# define VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) +# define VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +# define VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +# define CULL_FRONT_IS_CW (0 << 28) +# define CULL_FRONT_IS_CCW (1 << 28) +# define CULL_FRONT (1 << 29) +# define CULL_BACK (1 << 30) +# define FORCE_W_TO_ONE (1 << 31) + +#define SE_VPORT_XSCALE 0x1d98 +#define SE_VPORT_XOFFSET 0x1d9c +#define SE_VPORT_YSCALE 0x1da0 +#define SE_VPORT_YOFFSET 0x1da4 +#define SE_VPORT_ZSCALE 0x1da8 +#define SE_VPORT_ZOFFSET 0x1dac +#define SE_ZBIAS_FACTOR 0x1db0 +#define SE_ZBIAS_CONSTANT 0x1db4 + +#define SE_VTX_FMT 0x2080 +# define SE_VTX_FMT_XY 0x00000000 +# define SE_VTX_FMT_W0 0x00000001 +# define SE_VTX_FMT_FPCOLOR 0x00000002 +# define SE_VTX_FMT_FPALPHA 0x00000004 +# define SE_VTX_FMT_PKCOLOR 0x00000008 +# define SE_VTX_FMT_FPSPEC 0x00000010 +# define SE_VTX_FMT_FPFOG 0x00000020 +# define SE_VTX_FMT_PKSPEC 0x00000040 +# define SE_VTX_FMT_ST0 0x00000080 +# define SE_VTX_FMT_ST1 0x00000100 +# define SE_VTX_FMT_Q1 0x00000200 +# define SE_VTX_FMT_ST2 0x00000400 +# define SE_VTX_FMT_Q2 0x00000800 +# define SE_VTX_FMT_ST3 0x00001000 +# define SE_VTX_FMT_Q3 0x00002000 +# define SE_VTX_FMT_Q0 0x00004000 +# define SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define SE_VTX_FMT_N0 0x00040000 +# define SE_VTX_FMT_XY1 0x08000000 +# define SE_VTX_FMT_Z1 0x10000000 +# define SE_VTX_FMT_W1 0x20000000 +# define SE_VTX_FMT_N1 0x40000000 +# define SE_VTX_FMT_Z 0x80000000 + +#define SE_VF_CNTL 0x2084 +# define VF_PRIM_TYPE_POINT_LIST 1 +# define VF_PRIM_TYPE_LINE_LIST 2 +# define VF_PRIM_TYPE_LINE_STRIP 3 +# define VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define VF_PRIM_TYPE_POINT_LIST_3 9 +# define VF_PRIM_TYPE_LINE_LIST_3 10 +# define VF_PRIM_TYPE_SPIRIT_LIST 11 +# define VF_PRIM_TYPE_LINE_LOOP 12 +# define VF_PRIM_TYPE_QUAD_LIST 13 +# define VF_PRIM_TYPE_QUAD_STRIP 14 +# define VF_PRIM_TYPE_POLYGON 15 +# define VF_PRIM_WALK_STATE (0<<4) +# define VF_PRIM_WALK_INDEX (1<<4) +# define VF_PRIM_WALK_LIST (2<<4) +# define VF_PRIM_WALK_DATA (3<<4) +# define VF_COLOR_ORDER_RGBA (1<<6) +# define VF_RADEON_MODE (1<<8) +# define VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define VF_PROG_STREAM_ENA (1<<10) +# define VF_INDEX_SIZE_SHIFT 11 +# define VF_NUM_VERTICES_SHIFT 16 + +#define SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE 0x00000001 +# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +# define R200_VAP_FORCE_W_TO_ONE 0x00010000 +# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_VPORT_X_SCALE_ENA 0x00000001 +# define R200_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_VTX_XY_FMT 0x00000100 +# define R200_VTX_Z_FMT 0x00000200 +# define R200_VTX_W0_FMT 0x00000400 +# define R200_VTX_W0_NORMALIZE 0x00000800 +# define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +# define R200_VC_NO_SWAP (0 << 0) +# define R200_VC_16BIT_SWAP (1 << 0) +# define R200_VC_32BIT_SWAP (2 << 0) +# define R200_TCL_BYPASS (1 << 8) +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXFILTER_1 0x2c20 +# define R200_MAG_FILTER_NEAREST (0 << 0) +# define R200_MAG_FILTER_LINEAR (1 << 0) +# define R200_MAG_FILTER_MASK (1 << 0) +# define R200_MIN_FILTER_NEAREST (0 << 1) +# define R200_MIN_FILTER_LINEAR (1 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define R200_MIN_FILTER_MASK (15 << 1) +# define R200_MAX_ANISO_1_TO_1 (0 << 5) +# define R200_MAX_ANISO_2_TO_1 (1 << 5) +# define R200_MAX_ANISO_4_TO_1 (2 << 5) +# define R200_MAX_ANISO_8_TO_1 (3 << 5) +# define R200_MAX_ANISO_16_TO_1 (4 << 5) +# define R200_MAX_ANISO_MASK (7 << 5) +# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define R200_MAX_MIP_LEVEL_SHIFT 16 +# define R200_YUV_TO_RGB (1 << 20) +# define R200_YUV_TEMPERATURE_COOL (0 << 21) +# define R200_YUV_TEMPERATURE_HOT (1 << 21) +# define R200_YUV_TEMPERATURE_MASK (1 << 21) +# define R200_WRAPEN_S (1 << 22) +# define R200_CLAMP_S_WRAP (0 << 23) +# define R200_CLAMP_S_MIRROR (1 << 23) +# define R200_CLAMP_S_CLAMP_LAST (2 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define R200_CLAMP_S_CLAMP_GL (6 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define R200_CLAMP_S_MASK (7 << 23) +# define R200_WRAPEN_T (1 << 26) +# define R200_CLAMP_T_WRAP (0 << 27) +# define R200_CLAMP_T_MIRROR (1 << 27) +# define R200_CLAMP_T_CLAMP_LAST (2 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define R200_CLAMP_T_CLAMP_GL (6 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define R200_CLAMP_T_MASK (7 << 27) +# define R200_KILL_LT_ZERO (1 << 30) +# define R200_BORDER_MODE_OGL (0 << 31) +# define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_PP_TXFORMAT_1 0x2c24 +# define R200_TXFORMAT_I8 (0 << 0) +# define R200_TXFORMAT_AI88 (1 << 0) +# define R200_TXFORMAT_RGB332 (2 << 0) +# define R200_TXFORMAT_ARGB1555 (3 << 0) +# define R200_TXFORMAT_RGB565 (4 << 0) +# define R200_TXFORMAT_ARGB4444 (5 << 0) +# define R200_TXFORMAT_ARGB8888 (6 << 0) +# define R200_TXFORMAT_RGBA8888 (7 << 0) +# define R200_TXFORMAT_Y8 (8 << 0) +# define R200_TXFORMAT_AVYU (9 << 0) +# define R200_TXFORMAT_VYUY422 (10 << 0) +# define R200_TXFORMAT_YVYU422 (11 << 0) +# define R200_TXFORMAT_DXT1 (12 << 0) +# define R200_TXFORMAT_DXT23 (14 << 0) +# define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_FORMAT_MASK (31 << 0) +# define R200_TXFORMAT_FORMAT_SHIFT 0 +# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define R200_TXFORMAT_NON_POWER2 (1 << 7) +# define R200_TXFORMAT_WIDTH_MASK (15 << 8) +# define R200_TXFORMAT_WIDTH_SHIFT 8 +# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +# define R200_TXFORMAT_HEIGHT_SHIFT 12 +# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXFORMAT_X_1 0x2c28 +#define R200_DEPTH_LOG2_MASK (0xf << 0) +#define R200_DEPTH_LOG2_SHIFT 0 +#define R200_VOLUME_FILTER_SHIFT 4 +#define R200_VOLUME_FILTER_MASK (1 << 4) +#define R200_VOLUME_FILTER_NEAREST (0 << 4) +#define R200_VOLUME_FILTER_LINEAR (1 << 4) +#define R200_WRAPEN_Q (1 << 8) +#define R200_CLAMP_Q_WRAP (0 << 9) +#define R200_CLAMP_Q_MIRROR (1 << 9) +#define R200_CLAMP_Q_CLAMP_LAST (2 << 9) +#define R200_CLAMP_Q_MIRROR_CLAMP_LAST (3 << 9) +#define R200_CLAMP_Q_CLAMP_BORDER (4 << 9) +#define R200_CLAMP_Q_MIRROR_CLAMP_BORDER (5 << 9) +#define R200_CLAMP_Q_CLAMP_GL (6 << 9) +#define R200_CLAMP_Q_MIRROR_CLAMP_GL (7 << 9) +#define R200_CLAMP_Q_MASK (7 << 9) +#define R200_MIN_MIP_LEVEL_MASK (0xff << 12) +#define R200_MIN_MIP_LEVEL_SHIFT 12 +#define R200_TEXCOORD_NONPROJ (0 << 16) +#define R200_TEXCOORD_CUBIC_ENV (1 << 16) +#define R200_TEXCOORD_VOLUME (2 << 16) +#define R200_TEXCOORD_PROJ (3 << 16) +#define R200_TEXCOORD_DEPTH (4 << 16) +#define R200_TEXCOORD_1D_PROJ (5 << 16) +#define R200_TEXCOORD_1D (6 << 16) +#define R200_TEXCOORD_ZERO (7 << 16) +#define R200_TEXCOORD_MASK (7 << 16) +#define R200_LOD_BIAS_MASK (0xfff80000) +#define R200_LOD_BIAS_SHIFT 19 +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXSIZE_1 0x2c2c +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXPITCH_1 0x2c30 +#define R200_PP_BORDER_COLOR_0 0x2c14 +#define R200_PP_BORDER_COLOR_1 0x2c34 +#define R200_PP_TXOFFSET_0 0x2d00 +#define R200_PP_TXOFFSET_1 0x2d18 +# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R200_TXO_OFFSET_MASK 0xffffffe0 +# define R200_TXO_OFFSET_SHIFT 5 + + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +#define R200_PP_TXCBLEND_1 0x2f10 +# define R200_TXC_ARG_A_ZERO (0) +# define R200_TXC_ARG_A_CURRENT_COLOR (2) +# define R200_TXC_ARG_A_CURRENT_ALPHA (3) +# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +# define R200_TXC_ARG_A_SPECULAR_COLOR (6) +# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +# define R200_TXC_ARG_A_TFACTOR_COLOR (8) +# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +# define R200_TXC_ARG_A_R0_COLOR (10) +# define R200_TXC_ARG_A_R0_ALPHA (11) +# define R200_TXC_ARG_A_R1_COLOR (12) +# define R200_TXC_ARG_A_R1_ALPHA (13) +# define R200_TXC_ARG_A_R2_COLOR (14) +# define R200_TXC_ARG_A_R2_ALPHA (15) +# define R200_TXC_ARG_A_R3_COLOR (16) +# define R200_TXC_ARG_A_R3_ALPHA (17) +# define R200_TXC_ARG_A_R4_COLOR (18) +# define R200_TXC_ARG_A_R4_ALPHA (19) +# define R200_TXC_ARG_A_R5_COLOR (20) +# define R200_TXC_ARG_A_R5_ALPHA (21) +# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +# define R200_TXC_ARG_A_MASK (31 << 0) +# define R200_TXC_ARG_A_SHIFT 0 +# define R200_TXC_ARG_B_ZERO (0 << 5) +# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +# define R200_TXC_ARG_B_R0_COLOR (10 << 5) +# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +# define R200_TXC_ARG_B_R1_COLOR (12 << 5) +# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +# define R200_TXC_ARG_B_R2_COLOR (14 << 5) +# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +# define R200_TXC_ARG_B_R3_COLOR (16 << 5) +# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +# define R200_TXC_ARG_B_R4_COLOR (18 << 5) +# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +# define R200_TXC_ARG_B_R5_COLOR (20 << 5) +# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +# define R200_TXC_ARG_B_MASK (31 << 5) +# define R200_TXC_ARG_B_SHIFT 5 +# define R200_TXC_ARG_C_ZERO (0 << 10) +# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +# define R200_TXC_ARG_C_R0_COLOR (10 << 10) +# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +# define R200_TXC_ARG_C_R1_COLOR (12 << 10) +# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +# define R200_TXC_ARG_C_R2_COLOR (14 << 10) +# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +# define R200_TXC_ARG_C_R3_COLOR (16 << 10) +# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +# define R200_TXC_ARG_C_R4_COLOR (18 << 10) +# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +# define R200_TXC_ARG_C_R5_COLOR (20 << 10) +# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +# define R200_TXC_ARG_C_MASK (31 << 10) +# define R200_TXC_ARG_C_SHIFT 10 +# define R200_TXC_COMP_ARG_A (1 << 16) +# define R200_TXC_COMP_ARG_A_SHIFT (16) +# define R200_TXC_BIAS_ARG_A (1 << 17) +# define R200_TXC_SCALE_ARG_A (1 << 18) +# define R200_TXC_NEG_ARG_A (1 << 19) +# define R200_TXC_COMP_ARG_B (1 << 20) +# define R200_TXC_COMP_ARG_B_SHIFT (20) +# define R200_TXC_BIAS_ARG_B (1 << 21) +# define R200_TXC_SCALE_ARG_B (1 << 22) +# define R200_TXC_NEG_ARG_B (1 << 23) +# define R200_TXC_COMP_ARG_C (1 << 24) +# define R200_TXC_COMP_ARG_C_SHIFT (24) +# define R200_TXC_BIAS_ARG_C (1 << 25) +# define R200_TXC_SCALE_ARG_C (1 << 26) +# define R200_TXC_NEG_ARG_C (1 << 27) +# define R200_TXC_OP_MADD (0 << 28) +# define R200_TXC_OP_CND0 (2 << 28) +# define R200_TXC_OP_LERP (3 << 28) +# define R200_TXC_OP_DOT3 (4 << 28) +# define R200_TXC_OP_DOT4 (5 << 28) +# define R200_TXC_OP_CONDITIONAL (6 << 28) +# define R200_TXC_OP_DOT2_ADD (7 << 28) +# define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +#define R200_PP_TXCBLEND2_1 0x2f14 +# define R200_TXC_TFACTOR_SEL_SHIFT 0 +# define R200_TXC_TFACTOR_SEL_MASK 0x7 +# define R200_TXC_TFACTOR1_SEL_SHIFT 4 +# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXC_SCALE_SHIFT 8 +# define R200_TXC_SCALE_MASK (7 << 8) +# define R200_TXC_SCALE_1X (0 << 8) +# define R200_TXC_SCALE_2X (1 << 8) +# define R200_TXC_SCALE_4X (2 << 8) +# define R200_TXC_SCALE_8X (3 << 8) +# define R200_TXC_SCALE_INV2 (5 << 8) +# define R200_TXC_SCALE_INV4 (6 << 8) +# define R200_TXC_SCALE_INV8 (7 << 8) +# define R200_TXC_CLAMP_SHIFT 12 +# define R200_TXC_CLAMP_MASK (3 << 12) +# define R200_TXC_CLAMP_WRAP (0 << 12) +# define R200_TXC_CLAMP_0_1 (1 << 12) +# define R200_TXC_CLAMP_8_8 (2 << 12) +# define R200_TXC_OUTPUT_REG_MASK (7 << 16) +# define R200_TXC_OUTPUT_REG_NONE (0 << 16) +# define R200_TXC_OUTPUT_REG_R0 (1 << 16) +# define R200_TXC_OUTPUT_REG_R1 (2 << 16) +# define R200_TXC_OUTPUT_REG_R2 (3 << 16) +# define R200_TXC_OUTPUT_REG_R3 (4 << 16) +# define R200_TXC_OUTPUT_REG_R4 (5 << 16) +# define R200_TXC_OUTPUT_REG_R5 (6 << 16) +# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +# define R200_TXC_OUTPUT_MASK_RG (1 << 20) +# define R200_TXC_OUTPUT_MASK_RB (2 << 20) +# define R200_TXC_OUTPUT_MASK_R (3 << 20) +# define R200_TXC_OUTPUT_MASK_GB (4 << 20) +# define R200_TXC_OUTPUT_MASK_G (5 << 20) +# define R200_TXC_OUTPUT_MASK_B (6 << 20) +# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +# define R200_TXC_REPL_NORMAL 0 +# define R200_TXC_REPL_RED 1 +# define R200_TXC_REPL_GREEN 2 +# define R200_TXC_REPL_BLUE 3 +# define R200_TXC_REPL_ARG_A_SHIFT 26 +# define R200_TXC_REPL_ARG_A_MASK (3 << 26) +# define R200_TXC_REPL_ARG_B_SHIFT 28 +# define R200_TXC_REPL_ARG_B_MASK (3 << 28) +# define R200_TXC_REPL_ARG_C_SHIFT 30 +# define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +#define R200_PP_TXABLEND_1 0x2f18 +# define R200_TXA_ARG_A_ZERO (0) +# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +# define R200_TXA_ARG_A_SPECULAR_BLUE (7) +# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +# define R200_TXA_ARG_A_TFACTOR_BLUE (9) +# define R200_TXA_ARG_A_R0_ALPHA (10) +# define R200_TXA_ARG_A_R0_BLUE (11) +# define R200_TXA_ARG_A_R1_ALPHA (12) +# define R200_TXA_ARG_A_R1_BLUE (13) +# define R200_TXA_ARG_A_R2_ALPHA (14) +# define R200_TXA_ARG_A_R2_BLUE (15) +# define R200_TXA_ARG_A_R3_ALPHA (16) +# define R200_TXA_ARG_A_R3_BLUE (17) +# define R200_TXA_ARG_A_R4_ALPHA (18) +# define R200_TXA_ARG_A_R4_BLUE (19) +# define R200_TXA_ARG_A_R5_ALPHA (20) +# define R200_TXA_ARG_A_R5_BLUE (21) +# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +# define R200_TXA_ARG_A_MASK (31 << 0) +# define R200_TXA_ARG_A_SHIFT 0 +# define R200_TXA_ARG_B_ZERO (0 << 5) +# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +# define R200_TXA_ARG_B_R0_BLUE (11 << 5) +# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +# define R200_TXA_ARG_B_R1_BLUE (13 << 5) +# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +# define R200_TXA_ARG_B_R2_BLUE (15 << 5) +# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +# define R200_TXA_ARG_B_R3_BLUE (17 << 5) +# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +# define R200_TXA_ARG_B_R4_BLUE (19 << 5) +# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +# define R200_TXA_ARG_B_R5_BLUE (21 << 5) +# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +# define R200_TXA_ARG_B_MASK (31 << 5) +# define R200_TXA_ARG_B_SHIFT 5 +# define R200_TXA_ARG_C_ZERO (0 << 10) +# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +# define R200_TXA_ARG_C_R0_BLUE (11 << 10) +# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +# define R200_TXA_ARG_C_R1_BLUE (13 << 10) +# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +# define R200_TXA_ARG_C_R2_BLUE (15 << 10) +# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +# define R200_TXA_ARG_C_R3_BLUE (17 << 10) +# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +# define R200_TXA_ARG_C_R4_BLUE (19 << 10) +# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +# define R200_TXA_ARG_C_R5_BLUE (21 << 10) +# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +# define R200_TXA_ARG_C_MASK (31 << 10) +# define R200_TXA_ARG_C_SHIFT 10 +# define R200_TXA_COMP_ARG_A (1 << 16) +# define R200_TXA_COMP_ARG_A_SHIFT (16) +# define R200_TXA_BIAS_ARG_A (1 << 17) +# define R200_TXA_SCALE_ARG_A (1 << 18) +# define R200_TXA_NEG_ARG_A (1 << 19) +# define R200_TXA_COMP_ARG_B (1 << 20) +# define R200_TXA_COMP_ARG_B_SHIFT (20) +# define R200_TXA_BIAS_ARG_B (1 << 21) +# define R200_TXA_SCALE_ARG_B (1 << 22) +# define R200_TXA_NEG_ARG_B (1 << 23) +# define R200_TXA_COMP_ARG_C (1 << 24) +# define R200_TXA_COMP_ARG_C_SHIFT (24) +# define R200_TXA_BIAS_ARG_C (1 << 25) +# define R200_TXA_SCALE_ARG_C (1 << 26) +# define R200_TXA_NEG_ARG_C (1 << 27) +# define R200_TXA_OP_MADD (0 << 28) +# define R200_TXA_OP_CND0 (2 << 28) +# define R200_TXA_OP_LERP (3 << 28) +# define R200_TXA_OP_CONDITIONAL (6 << 28) +# define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +#define R200_PP_TXABLEND2_1 0x2f1c +# define R200_TXA_TFACTOR_SEL_SHIFT 0 +# define R200_TXA_TFACTOR_SEL_MASK 0x7 +# define R200_TXA_TFACTOR1_SEL_SHIFT 4 +# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXA_SCALE_SHIFT 8 +# define R200_TXA_SCALE_MASK (7 << 8) +# define R200_TXA_SCALE_1X (0 << 8) +# define R200_TXA_SCALE_2X (1 << 8) +# define R200_TXA_SCALE_4X (2 << 8) +# define R200_TXA_SCALE_8X (3 << 8) +# define R200_TXA_SCALE_INV2 (5 << 8) +# define R200_TXA_SCALE_INV4 (6 << 8) +# define R200_TXA_SCALE_INV8 (7 << 8) +# define R200_TXA_CLAMP_SHIFT 12 +# define R200_TXA_CLAMP_MASK (3 << 12) +# define R200_TXA_CLAMP_WRAP (0 << 12) +# define R200_TXA_CLAMP_0_1 (1 << 12) +# define R200_TXA_CLAMP_8_8 (2 << 12) +# define R200_TXA_OUTPUT_REG_MASK (7 << 16) +# define R200_TXA_OUTPUT_REG_NONE (0 << 16) +# define R200_TXA_OUTPUT_REG_R0 (1 << 16) +# define R200_TXA_OUTPUT_REG_R1 (2 << 16) +# define R200_TXA_OUTPUT_REG_R2 (3 << 16) +# define R200_TXA_OUTPUT_REG_R3 (4 << 16) +# define R200_TXA_OUTPUT_REG_R4 (5 << 16) +# define R200_TXA_OUTPUT_REG_R5 (6 << 16) +# define R200_TXA_DOT_ALPHA (1 << 20) +# define R200_TXA_REPL_NORMAL 0 +# define R200_TXA_REPL_RED 1 +# define R200_TXA_REPL_GREEN 2 +# define R200_TXA_REPL_ARG_A_SHIFT 26 +# define R200_TXA_REPL_ARG_A_MASK (3 << 26) +# define R200_TXA_REPL_ARG_B_SHIFT 28 +# define R200_TXA_REPL_ARG_B_MASK (3 << 28) +# define R200_TXA_REPL_ARG_C_SHIFT 30 +# define R200_TXA_REPL_ARG_C_MASK (3 << 30) +#define R200_RB3D_BLENDCOLOR 0x3218 /* ARGB 8888 */ +#define R200_RB3D_ABLENDCNTL 0x321C /* see BLENDCNTL */ +#define R200_RB3D_CBLENDCNTL 0x3220 /* see BLENDCNTL */ + +#define R200_SE_VTX_FMT_0 0x2088 +# define R200_VTX_XY 0 /* always have xy */ +# define R200_VTX_Z0 (1<<0) +# define R200_VTX_W0 (1<<1) +# define R200_VTX_WEIGHT_COUNT_SHIFT (2) +# define R200_VTX_PV_MATRIX_SEL (1<<5) +# define R200_VTX_N0 (1<<6) +# define R200_VTX_POINT_SIZE (1<<7) +# define R200_VTX_DISCRETE_FOG (1<<8) +# define R200_VTX_SHININESS_0 (1<<9) +# define R200_VTX_SHININESS_1 (1<<10) +# define R200_VTX_COLOR_NOT_PRESENT 0 +# define R200_VTX_PK_RGBA 1 +# define R200_VTX_FP_RGB 2 +# define R200_VTX_FP_RGBA 3 +# define R200_VTX_COLOR_MASK 3 +# define R200_VTX_COLOR_0_SHIFT 11 +# define R200_VTX_COLOR_1_SHIFT 13 +# define R200_VTX_COLOR_2_SHIFT 15 +# define R200_VTX_COLOR_3_SHIFT 17 +# define R200_VTX_COLOR_4_SHIFT 19 +# define R200_VTX_COLOR_5_SHIFT 21 +# define R200_VTX_COLOR_6_SHIFT 23 +# define R200_VTX_COLOR_7_SHIFT 25 +# define R200_VTX_XY1 (1<<28) +# define R200_VTX_Z1 (1<<29) +# define R200_VTX_W1 (1<<30) +# define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +# define R200_OUTPUT_XYZW (1<<0) +# define R200_OUTPUT_COLOR_0 (1<<8) +# define R200_OUTPUT_COLOR_1 (1<<9) +# define R200_OUTPUT_TEX_0 (1<<16) +# define R200_OUTPUT_TEX_1 (1<<17) +# define R200_OUTPUT_TEX_2 (1<<18) +# define R200_OUTPUT_TEX_3 (1<<19) +# define R200_OUTPUT_TEX_4 (1<<20) +# define R200_OUTPUT_TEX_5 (1<<21) +# define R200_OUTPUT_TEX_MASK (0x3f<<16) +# define R200_OUTPUT_DISCRETE_FOG (1<<24) +# define R200_OUTPUT_PT_SIZE (1<<25) +# define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + + + /* R300 3D registers */ +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 +# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 +# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 +# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 +# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 +# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 +# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 +# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 +# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 + + +#define R300_MC_INIT_GFX_LAT_TIMER 0x154 +# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 +# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 +# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 +# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 +# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 +# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 +# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 +# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 + +/* +This file contains registers and constants for the R300. They have been +found mostly by examining command buffers captured using glxtest, as well +as by extrapolating some known registers and constants from the R200. + +I am fairly certain that they are correct unless stated otherwise in comments. +*/ + +#define R300_SE_VPORT_XSCALE 0x1D98 +#define R300_SE_VPORT_XOFFSET 0x1D9C +#define R300_SE_VPORT_YSCALE 0x1DA0 +#define R300_SE_VPORT_YOFFSET 0x1DA4 +#define R300_SE_VPORT_ZSCALE 0x1DA8 +#define R300_SE_VPORT_ZOFFSET 0x1DAC + +/* BEGIN: Wild guesses */ +#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 +# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ + +#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 +/* END */ + +#define R300_SE_VTE_CNTL 0x20b0 +# define R300_VPORT_X_SCALE_ENA 0x00000001 +# define R300_VPORT_X_OFFSET_ENA 0x00000002 +# define R300_VPORT_Y_SCALE_ENA 0x00000004 +# define R300_VPORT_Y_OFFSET_ENA 0x00000008 +# define R300_VPORT_Z_SCALE_ENA 0x00000010 +# define R300_VPORT_Z_OFFSET_ENA 0x00000020 +# define R300_VTX_XY_FMT 0x00000100 +# define R300_VTX_Z_FMT 0x00000200 +# define R300_VTX_W0_FMT 0x00000400 +# define R300_VTX_W0_NORMALIZE 0x00000800 +# define R300_VTX_ST_DENORMALIZED 0x00001000 + +/* BEGIN: Vertex data assembly - lots of uncertainties */ +/* gap */ +/* Where do we get our vertex data? +// +// Vertex data either comes either from immediate mode registers or from +// vertex arrays. +// There appears to be no mixed mode (though we can force the pitch of +// vertex arrays to 0, effectively reusing the same element over and over +// again). +// +// Immediate mode is controlled by the INPUT_CNTL registers. I am not sure +// if these registers influence vertex array processing. +// +// Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. +// +// In both cases, vertex attributes are then passed through INPUT_ROUTE. + +// Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data +// into the vertex processor's input registers. +// The first word routes the first input, the second word the second, etc. +// The corresponding input is routed into the register with the given index. +// The list is ended by a word with INPUT_ROUTE_END set. +// +// Always set COMPONENTS_4 in immediate mode. */ + +#define R300_VAP_INPUT_ROUTE_0_0 0x2150 +# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) +# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) +# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) +# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) +# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ +# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 +# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ +# define R300_VAP_INPUT_ROUTE_END (1 << 13) +# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ +#define R300_VAP_INPUT_ROUTE_0_1 0x2154 +#define R300_VAP_INPUT_ROUTE_0_2 0x2158 +#define R300_VAP_INPUT_ROUTE_0_3 0x215C +#define R300_VAP_INPUT_ROUTE_0_4 0x2160 +#define R300_VAP_INPUT_ROUTE_0_5 0x2164 +#define R300_VAP_INPUT_ROUTE_0_6 0x2168 +#define R300_VAP_INPUT_ROUTE_0_7 0x216C + +/* gap */ +/* Notes: +// - always set up to produce at least two attributes: +// if vertex program uses only position, fglrx will set normal, too +// - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */ +#define R300_VAP_INPUT_CNTL_0 0x2180 +# define R300_INPUT_CNTL_0_COLOR 0x00000001 +#define R300_VAP_INPUT_CNTL_1 0x2184 +# define R300_INPUT_CNTL_POS 0x00000001 +# define R300_INPUT_CNTL_NORMAL 0x00000002 +# define R300_INPUT_CNTL_COLOR 0x00000004 +# define R300_INPUT_CNTL_TC0 0x00000400 +# define R300_INPUT_CNTL_TC1 0x00000800 +# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ +# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ +# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ +# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ +# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ +# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ + +/* gap */ +/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 +// are set to a swizzling bit pattern, other words are 0. +// +// In immediate mode, the pattern is always set to xyzw. In vertex array +// mode, the swizzling pattern is e.g. used to set zw components in texture +// coordinates with only tweo components. */ +#define R300_VAP_INPUT_ROUTE_1_0 0x21E0 +# define R300_INPUT_ROUTE_SELECT_X 0 +# define R300_INPUT_ROUTE_SELECT_Y 1 +# define R300_INPUT_ROUTE_SELECT_Z 2 +# define R300_INPUT_ROUTE_SELECT_W 3 +# define R300_INPUT_ROUTE_SELECT_ZERO 4 +# define R300_INPUT_ROUTE_SELECT_ONE 5 +# define R300_INPUT_ROUTE_SELECT_MASK 7 +# define R300_INPUT_ROUTE_X_SHIFT 0 +# define R300_INPUT_ROUTE_Y_SHIFT 3 +# define R300_INPUT_ROUTE_Z_SHIFT 6 +# define R300_INPUT_ROUTE_W_SHIFT 9 +# define R300_INPUT_ROUTE_ENABLE (15 << 12) +#define R300_VAP_INPUT_ROUTE_1_1 0x21E4 +#define R300_VAP_INPUT_ROUTE_1_2 0x21E8 +#define R300_VAP_INPUT_ROUTE_1_3 0x21EC +#define R300_VAP_INPUT_ROUTE_1_4 0x21F0 +#define R300_VAP_INPUT_ROUTE_1_5 0x21F4 +#define R300_VAP_INPUT_ROUTE_1_6 0x21F8 +#define R300_VAP_INPUT_ROUTE_1_7 0x21FC + +/* END */ + +/* gap */ +/* BEGIN: Upload vertex program and data +// The programmable vertex shader unit has a memory bank of unknown size +// that can be written to in 16 byte units by writing the address into +// UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). +// +// Pointers into the memory bank are always in multiples of 16 bytes. +// +// The memory bank is divided into areas with fixed meaning. +// +// Starting at address UPLOAD_PROGRAM: Vertex program instructions. +// Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), +// whereas the difference between known addresses suggests size 512. +// +// Starting at address UPLOAD_PARAMETERS: Vertex program parameters. +// Native reported limits and the VPI layout suggest size 256, whereas +// difference between known addresses suggests size 512. +// +// At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the +// floating point pointsize. The exact purpose of this state is uncertain, +// as there is also the R300_RE_POINTSIZE register. +// +// Multiple vertex programs and parameter sets can be loaded at once, +// which could explain the size discrepancy. */ +#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 +# define R300_PVS_UPLOAD_PROGRAM 0x00000000 +# define R300_PVS_UPLOAD_PARAMETERS 0x00000200 +# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 +/* gap */ +#define R300_VAP_PVS_UPLOAD_DATA 0x2208 +/* END */ + +/* gap */ +/* I do not know the purpose of this register. However, I do know that +// it is set to 221C_CLEAR for clear operations and to 221C_NORMAL +// for normal rendering. */ +#define R300_VAP_UNKNOWN_221C 0x221C +# define R300_221C_NORMAL 0x00000000 +# define R300_221C_CLEAR 0x0001C000 + +/* gap */ +/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between +// rendering commands and overwriting vertex program parameters. +// Therefore, I suspect writing zero to 0x2284 synchronizes the engine and +// avoids bugs caused by still running shaders reading bad data from memory. */ +#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ + +/* Absolutely no clue what this register is about. */ +#define R300_VAP_UNKNOWN_2288 0x2288 +# define R300_2288_R300 0x00750000 /* -- nh */ +# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ + +/* gap */ +/* Addresses are relative to the vertex program instruction area of the +// memory bank. PROGRAM_END points to the last instruction of the active +// program +// +// The meaning of the two UNKNOWN fields is obviously not known. However, +// experiments so far have shown that both *must* point to an instruction +// inside the vertex program, otherwise the GPU locks up. +// fglrx usually sets CNTL_3_UNKNOWN to the end of the program and +// CNTL_1_UNKNOWN points to instruction where last write to position takes place. +// Most likely this is used to ignore rest of the program in cases where group of verts arent visible. +// For some reason this "section" is sometimes accepted other instruction that have +// no relationship with position calculations. +*/ +#define R300_VAP_PVS_CNTL_1 0x22D0 +# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 +# define R300_PVS_CNTL_1_POS_END_SHIFT 10 +# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 +/* Addresses are relative the the vertex program parameters area. */ +#define R300_VAP_PVS_CNTL_2 0x22D4 +# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 +# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 +#define R300_VAP_PVS_CNTL_3 0x22D8 +# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 +# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 + +/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for +// immediate vertices */ +#define R300_VAP_VTX_COLOR_R 0x2464 +#define R300_VAP_VTX_COLOR_G 0x2468 +#define R300_VAP_VTX_COLOR_B 0x246C +#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ +#define R300_VAP_VTX_POS_0_Y_1 0x2494 +#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ +#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ +#define R300_VAP_VTX_POS_0_Y_2 0x24A4 +#define R300_VAP_VTX_POS_0_Z_2 0x24A8 +#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ + +/* gap */ + +/* These are values from r300_reg/r300_reg.h - they are known to be correct + and are here so we can use one register file instead of several + - Vladimir */ +#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 +# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) +# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) + +#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 + /* each of the following is 3 bits wide, specifies number + of components */ +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 + +/* UNK30 seems to enables point to quad transformation on textures + (or something closely related to that). + This bit is rather fatal at the time being due to lackings at pixel shader side */ +#define R300_GB_ENABLE 0x4008 +# define R300_GB_POINT_STUFF_ENABLE (1<<0) +# define R300_GB_LINE_STUFF_ENABLE (1<<1) +# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) +# define R300_GB_STENCIL_AUTO_ENABLE (1<<4) +# define R300_GB_UNK30 (1<<30) + /* each of the following is 2 bits wide */ +#define R300_GB_TEX_REPLICATE 0 +#define R300_GB_TEX_ST 1 +#define R300_GB_TEX_STR 2 +# define R300_GB_TEX0_SOURCE_SHIFT 16 +# define R300_GB_TEX1_SOURCE_SHIFT 18 +# define R300_GB_TEX2_SOURCE_SHIFT 20 +# define R300_GB_TEX3_SOURCE_SHIFT 22 +# define R300_GB_TEX4_SOURCE_SHIFT 24 +# define R300_GB_TEX5_SOURCE_SHIFT 26 +# define R300_GB_TEX6_SOURCE_SHIFT 28 +# define R300_GB_TEX7_SOURCE_SHIFT 30 + +/* MSPOS - positions for multisample antialiasing (?) */ +#define R300_GB_MSPOS0 0x4010 + /* shifts - each of the fields is 4 bits */ +# define R300_GB_MSPOS0__MS_X0_SHIFT 0 +# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 +# define R300_GB_MSPOS0__MS_X1_SHIFT 8 +# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 +# define R300_GB_MSPOS0__MS_X2_SHIFT 16 +# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 +# define R300_GB_MSPOS0__MSBD0_Y 24 +# define R300_GB_MSPOS0__MSBD0_X 28 + +#define R300_GB_MSPOS1 0x4014 +# define R300_GB_MSPOS1__MS_X3_SHIFT 0 +# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 +# define R300_GB_MSPOS1__MS_X4_SHIFT 8 +# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 +# define R300_GB_MSPOS1__MS_X5_SHIFT 16 +# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 +# define R300_GB_MSPOS1__MSBD1 24 + + +#define R300_GB_TILE_CONFIG 0x4018 +# define R300_GB_TILE_ENABLE (1<<0) +# define R300_GB_TILE_PIPE_COUNT_RV300 0 +# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) +# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) +# define R300_GB_TILE_SIZE_8 0 +# define R300_GB_TILE_SIZE_16 (1<<4) +# define R300_GB_TILE_SIZE_32 (2<<4) +# define R300_GB_SUPER_SIZE_1 (0<<6) +# define R300_GB_SUPER_SIZE_2 (1<<6) +# define R300_GB_SUPER_SIZE_4 (2<<6) +# define R300_GB_SUPER_SIZE_8 (3<<6) +# define R300_GB_SUPER_SIZE_16 (4<<6) +# define R300_GB_SUPER_SIZE_32 (5<<6) +# define R300_GB_SUPER_SIZE_64 (6<<6) +# define R300_GB_SUPER_SIZE_128 (7<<6) +# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ +# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ +# define R300_GB_SUPER_TILE_A 0 +# define R300_GB_SUPER_TILE_B (1<<15) +# define R300_GB_SUBPIXEL_1_12 0 +# define R300_GB_SUBPIXEL_1_16 (1<<16) + +#define R300_GB_FIFO_SIZE 0x4024 + /* each of the following is 2 bits wide */ +#define R300_GB_FIFO_SIZE_32 0 +#define R300_GB_FIFO_SIZE_64 1 +#define R300_GB_FIFO_SIZE_128 2 +#define R300_GB_FIFO_SIZE_256 3 +# define R300_SC_IFIFO_SIZE_SHIFT 0 +# define R300_SC_TZFIFO_SIZE_SHIFT 2 +# define R300_SC_BFIFO_SIZE_SHIFT 4 + +# define R300_US_OFIFO_SIZE_SHIFT 12 +# define R300_US_WFIFO_SIZE_SHIFT 14 + /* the following use the same constants as above, but meaning is + is times 2 (i.e. instead of 32 words it means 64 */ +# define R300_RS_TFIFO_SIZE_SHIFT 6 +# define R300_RS_CFIFO_SIZE_SHIFT 8 +# define R300_US_RAM_SIZE_SHIFT 10 + /* watermarks, 3 bits wide */ +# define R300_RS_HIGHWATER_COL_SHIFT 16 +# define R300_RS_HIGHWATER_TEX_SHIFT 19 +# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ +# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 + +#define R300_GB_SELECT 0x401C +# define R300_GB_FOG_SELECT_C0A 0 +# define R300_GB_FOG_SELECT_C1A 1 +# define R300_GB_FOG_SELECT_C2A 2 +# define R300_GB_FOG_SELECT_C3A 3 +# define R300_GB_FOG_SELECT_1_1_W 4 +# define R300_GB_FOG_SELECT_Z 5 +# define R300_GB_DEPTH_SELECT_Z 0 +# define R300_GB_DEPTH_SELECT_1_1_W (1<<3) +# define R300_GB_W_SELECT_1_W 0 +# define R300_GB_W_SELECT_1 (1<<4) + +#define R300_GB_AA_CONFIG 0x4020 +# define R300_AA_ENABLE 0x01 +# define R300_AA_SUBSAMPLES_2 0 +# define R300_AA_SUBSAMPLES_3 (1<<1) +# define R300_AA_SUBSAMPLES_4 (2<<1) +# define R300_AA_SUBSAMPLES_6 (3<<1) + +/* END */ + +/* gap */ +/* Zero to flush caches. */ +#define R300_TX_CNTL 0x4100 + +/* The upper enable bits are guessed, based on fglrx reported limits. */ +#define R300_TX_ENABLE 0x4104 +# define R300_TX_ENABLE_0 (1 << 0) +# define R300_TX_ENABLE_1 (1 << 1) +# define R300_TX_ENABLE_2 (1 << 2) +# define R300_TX_ENABLE_3 (1 << 3) +# define R300_TX_ENABLE_4 (1 << 4) +# define R300_TX_ENABLE_5 (1 << 5) +# define R300_TX_ENABLE_6 (1 << 6) +# define R300_TX_ENABLE_7 (1 << 7) +# define R300_TX_ENABLE_8 (1 << 8) +# define R300_TX_ENABLE_9 (1 << 9) +# define R300_TX_ENABLE_10 (1 << 10) +# define R300_TX_ENABLE_11 (1 << 11) +# define R300_TX_ENABLE_12 (1 << 12) +# define R300_TX_ENABLE_13 (1 << 13) +# define R300_TX_ENABLE_14 (1 << 14) +# define R300_TX_ENABLE_15 (1 << 15) + +/* The pointsize is given in multiples of 6. The pointsize can be +// enormous: Clear() renders a single point that fills the entire +// framebuffer. */ +#define R300_RE_POINTSIZE 0x421C +# define R300_POINTSIZE_Y_SHIFT 0 +# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ +# define R300_POINTSIZE_X_SHIFT 16 +# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ +# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) + +/* The line width is given in multiples of 6. + In default mode lines are classified as vertical lines. + HO: horizontal + VE: vertical or horizontal + HO & VE: no classification +*/ +#define R300_RE_LINE_CNT 0x4234 +# define R300_LINESIZE_SHIFT 0 +# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ +# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) +# define R300_LINE_CNT_HO (1 << 16) +# define R300_LINE_CNT_VE (1 << 17) + +/* Some sort of scale or clamp value for texcoordless textures. */ +#define R300_RE_UNK4238 0x4238 + +#define R300_RE_SHADE_MODEL 0x4278 +# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa +# define R300_RE_SHADE_MODEL_FLAT 0x39595 + +/* Dangerous */ +#define R300_RE_POLYGON_MODE 0x4288 +# define R300_PM_ENABLED (1 << 0) +# define R300_PM_FRONT_POINT (0 << 0) +# define R300_PM_BACK_POINT (0 << 0) +# define R300_PM_FRONT_LINE (1 << 4) +# define R300_PM_FRONT_FILL (1 << 5) +# define R300_PM_BACK_LINE (1 << 7) +# define R300_PM_BACK_FILL (1 << 8) + +/* Not sure why there are duplicate of factor and constant values. + My best guess so far is that there are seperate zbiases for test and write. + Ordering might be wrong. + Some of the tests indicate that fgl has a fallback implementation of zbias + via pixel shaders. */ +#define R300_RE_ZBIAS_T_FACTOR 0x42A4 +#define R300_RE_ZBIAS_T_CONSTANT 0x42A8 +#define R300_RE_ZBIAS_W_FACTOR 0x42AC +#define R300_RE_ZBIAS_W_CONSTANT 0x42B0 + +/* This register needs to be set to (1<<1) for RV350 to correctly + perform depth test (see --vb-triangles in r300_demo) + Don't know about other chips. - Vladimir + This is set to 3 when GL_POLYGON_OFFSET_FILL is on. + My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT). + One to enable depth test and one for depth write. + Yet this doesnt explain why depth writes work ... + */ +#define R300_RE_OCCLUSION_CNTL 0x42B4 +# define R300_OCCLUSION_ON (1<<1) + +#define R300_RE_CULL_CNTL 0x42B8 +# define R300_CULL_FRONT (1 << 0) +# define R300_CULL_BACK (1 << 1) +# define R300_FRONT_FACE_CCW (0 << 2) +# define R300_FRONT_FACE_CW (1 << 2) + + +/* BEGIN: Rasterization / Interpolators - many guesses +// 0_UNKNOWN_18 has always been set except for clear operations. +// TC_CNT is the number of incoming texture coordinate sets (i.e. it depends +// on the vertex program, *not* the fragment program) */ +#define R300_RS_CNTL_0 0x4300 +# define R300_RS_CNTL_TC_CNT_SHIFT 2 +# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) +# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ +# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) +/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ +#define R300_RS_CNTL_1 0x4304 + +/* gap */ +/* Only used for texture coordinates. +// Use the source field to route texture coordinate input from the vertex program +// to the desired interpolator. Note that the source field is relative to the +// outputs the vertex program *actually* writes. If a vertex program only writes +// texcoord[1], this will be source index 0. +// Set INTERP_USED on all interpolators that produce data used by the +// fragment program. INTERP_USED looks like a swizzling mask, but +// I haven't seen it used that way. +// +// Note: The _UNKNOWN constants are always set in their respective register. +// I don't know if this is necessary. */ +#define R300_RS_INTERP_0 0x4310 +#define R300_RS_INTERP_1 0x4314 +# define R300_RS_INTERP_1_UNKNOWN 0x40 +#define R300_RS_INTERP_2 0x4318 +# define R300_RS_INTERP_2_UNKNOWN 0x80 +#define R300_RS_INTERP_3 0x431C +# define R300_RS_INTERP_3_UNKNOWN 0xC0 +#define R300_RS_INTERP_4 0x4320 +#define R300_RS_INTERP_5 0x4324 +#define R300_RS_INTERP_6 0x4328 +#define R300_RS_INTERP_7 0x432C +# define R300_RS_INTERP_SRC_SHIFT 2 +# define R300_RS_INTERP_SRC_MASK (7 << 2) +# define R300_RS_INTERP_USED 0x00D10000 + +/* These DWORDs control how vertex data is routed into fragment program +// registers, after interpolators. */ +#define R300_RS_ROUTE_0 0x4330 +#define R300_RS_ROUTE_1 0x4334 +#define R300_RS_ROUTE_2 0x4338 +#define R300_RS_ROUTE_3 0x433C /* GUESS */ +#define R300_RS_ROUTE_4 0x4340 /* GUESS */ +#define R300_RS_ROUTE_5 0x4344 /* GUESS */ +#define R300_RS_ROUTE_6 0x4348 /* GUESS */ +#define R300_RS_ROUTE_7 0x434C /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_0 0 +# define R300_RS_ROUTE_SOURCE_INTERP_1 1 +# define R300_RS_ROUTE_SOURCE_INTERP_2 2 +# define R300_RS_ROUTE_SOURCE_INTERP_3 3 +# define R300_RS_ROUTE_SOURCE_INTERP_4 4 +# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ +# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ +# define R300_RS_ROUTE_DEST_SHIFT 6 +# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ + +/* Special handling for color: When the fragment program uses color, +// the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the +// color register index. */ +# define R300_RS_ROUTE_0_COLOR (1 << 14) +# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 +# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ +/* As above, but for secondary color */ +# define R300_RS_ROUTE_1_COLOR1 (1 << 14) +# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 +# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) +# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) +/* END */ + +/* BEGIN: Scissors and cliprects +// There are four clipping rectangles. Their corner coordinates are inclusive. +// Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending +// on whether the pixel is inside cliprects 0-3, respectively. For example, +// if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned +// the number 3 (binary 0011). +// Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, +// the pixel is rasterized. +// +// In addition to this, there is a scissors rectangle. Only pixels inside the +// scissors rectangle are drawn. (coordinates are inclusive) +// +// For some reason, the top-left corner of the framebuffer is at (1440, 1440) +// for the purpose of clipping and scissors. */ +#define R300_RE_CLIPRECT_TL_0 0x43B0 +#define R300_RE_CLIPRECT_BR_0 0x43B4 +#define R300_RE_CLIPRECT_TL_1 0x43B8 +#define R300_RE_CLIPRECT_BR_1 0x43BC +#define R300_RE_CLIPRECT_TL_2 0x43C0 +#define R300_RE_CLIPRECT_BR_2 0x43C4 +#define R300_RE_CLIPRECT_TL_3 0x43C8 +#define R300_RE_CLIPRECT_BR_3 0x43CC +# define R300_CLIPRECT_OFFSET 1440 +# define R300_CLIPRECT_MASK 0x1FFF +# define R300_CLIPRECT_X_SHIFT 0 +# define R300_CLIPRECT_X_MASK (0x1FFF << 0) +# define R300_CLIPRECT_Y_SHIFT 13 +# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) +#define R300_RE_CLIPRECT_CNTL 0x43D0 +# define R300_CLIP_OUT (1 << 0) +# define R300_CLIP_0 (1 << 1) +# define R300_CLIP_1 (1 << 2) +# define R300_CLIP_10 (1 << 3) +# define R300_CLIP_2 (1 << 4) +# define R300_CLIP_20 (1 << 5) +# define R300_CLIP_21 (1 << 6) +# define R300_CLIP_210 (1 << 7) +# define R300_CLIP_3 (1 << 8) +# define R300_CLIP_30 (1 << 9) +# define R300_CLIP_31 (1 << 10) +# define R300_CLIP_310 (1 << 11) +# define R300_CLIP_32 (1 << 12) +# define R300_CLIP_320 (1 << 13) +# define R300_CLIP_321 (1 << 14) +# define R300_CLIP_3210 (1 << 15) + +/* gap */ +#define R300_RE_SCISSORS_TL 0x43E0 +#define R300_RE_SCISSORS_BR 0x43E4 +# define R300_SCISSORS_OFFSET 1440 +# define R300_SCISSORS_X_SHIFT 0 +# define R300_SCISSORS_X_MASK (0x1FFF << 0) +# define R300_SCISSORS_Y_SHIFT 13 +# define R300_SCISSORS_Y_MASK (0x1FFF << 13) +/* END */ + +/* BEGIN: Texture specification +// The texture specification dwords are grouped by meaning and not by texture unit. +// This means that e.g. the offset for texture image unit N is found in register +// TX_OFFSET_0 + (4*N) */ +#define R300_TX_FILTER_0 0x4400 +#define R300_TX_FILTER_1 0x4404 +# define R300_TX_REPEAT 0 +# define R300_TX_MIRRORED 1 +# define R300_TX_CLAMP 4 +# define R300_TX_CLAMP_TO_EDGE 2 +# define R300_TX_CLAMP_TO_BORDER 6 +# define R300_TX_WRAP_S_SHIFT 0 +# define R300_TX_WRAP_S_MASK (7 << 0) +# define R300_TX_WRAP_T_SHIFT 3 +# define R300_TX_WRAP_T_MASK (7 << 3) +# define R300_TX_WRAP_Q_SHIFT 6 +# define R300_TX_WRAP_Q_MASK (7 << 6) +# define R300_TX_MAG_FILTER_NEAREST (1 << 9) +# define R300_TX_MAG_FILTER_LINEAR (2 << 9) +# define R300_TX_MAG_FILTER_MASK (3 << 9) +# define R300_TX_MIN_FILTER_NEAREST (1 << 11) +# define R300_TX_MIN_FILTER_LINEAR (2 << 11) +# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) +# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) +# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) +# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) +/* NOTE: NEAREST doesnt seem to exist. + Im not seting MAG_FILTER_MASK and (3 << 11) on for all + anisotropy modes because that would void selected mag filter */ +# define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) +# define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) +# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) +# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) +# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) +# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) +# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) +# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) +# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) +# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) +# define R300_TX_MAX_ANISO_MASK (14 << 21) + +#define R300_TX_FILTER1_0 0x4440 +#define R300_TX_FILTER1_1 0x4444 +# define R300_CHROMA_KEY_MODE_DISABLE 0 +# define R300_CHROMA_KEY_FORCE 1 +# define R300_CHROMA_KEY_BLEND 2 +# define R300_MC_ROUND_NORMAL (0<<2) +# define R300_MC_ROUND_MPEG4 (1<<2) +# define R300_LOD_BIAS_MASK 0x1fff +# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) +# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) +# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) +# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) +# define R300_TX_TRI_PERF_0_8 (0<<15) +# define R300_TX_TRI_PERF_1_8 (1<<15) +# define R300_TX_TRI_PERF_1_4 (2<<15) +# define R300_TX_TRI_PERF_3_8 (3<<15) +# define R300_ANISO_THRESHOLD_MASK (7<<17) + +#define R300_TX_SIZE_0 0x4480 +#define R300_TX_SIZE_1 0x4484 +# define R300_TX_WIDTH_SHIFT 0 +# define R300_TX_WIDTH_MASK (2047 << 0) +# define R300_TX_HEIGHT_SHIFT 11 +# define R300_TX_HEIGHT_MASK (2047 << 11) +# define R300_TX_UNK23 (1 << 23) +# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ +# define R300_TX_SIZE_MASK (15 << 26) +# define R300_TX_SIZE_PROJECTED (1<<30) +# define R300_TX_SIZE_TXPITCH_EN (1<<31) + +#define R300_TX_FORMAT_0 0x44C0 +#define R300_TX_FORMAT_1 0x44C4 + /* The interpretation of the format word by Wladimir van der Laan */ + /* The X, Y, Z and W refer to the layout of the components. + They are given meanings as R, G, B and Alpha by the swizzle + specification */ +# define R300_TX_FORMAT_X8 0x0 +# define R300_TX_FORMAT_X16 0x1 +# define R300_TX_FORMAT_Y4X4 0x2 +# define R300_TX_FORMAT_Y8X8 0x3 +# define R300_TX_FORMAT_Y16X16 0x4 +# define R300_TX_FORMAT_Z3Y3X2 0x5 +# define R300_TX_FORMAT_Z5Y6X5 0x6 +# define R300_TX_FORMAT_Z6Y5X5 0x7 +# define R300_TX_FORMAT_Z11Y11X10 0x8 +# define R300_TX_FORMAT_Z10Y11X11 0x9 +# define R300_TX_FORMAT_W4Z4Y4X4 0xA +# define R300_TX_FORMAT_W1Z5Y5X5 0xB +# define R300_TX_FORMAT_W8Z8Y8X8 0xC +# define R300_TX_FORMAT_W2Z10Y10X10 0xD +# define R300_TX_FORMAT_W16Z16Y16X16 0xE +# define R300_TX_FORMAT_DXT1 0xF +# define R300_TX_FORMAT_DXT3 0x10 +# define R300_TX_FORMAT_DXT5 0x11 +# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ + /* 0x16 - some 16 bit green format.. ?? */ +# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ +# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) + /* gap */ + /* Floating point formats */ + /* Note - hardware supports both 16 and 32 bit floating point */ +# define R300_TX_FORMAT_FL_I16 0x18 +# define R300_TX_FORMAT_FL_I16A16 0x19 +# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A +# define R300_TX_FORMAT_FL_I32 0x1B +# define R300_TX_FORMAT_FL_I32A32 0x1C +# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D + /* alpha modes, convenience mostly */ + /* if you have alpha, pick constant appropriate to the + number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ +# define R300_TX_FORMAT_ALPHA_1CH 0x000 +# define R300_TX_FORMAT_ALPHA_2CH 0x200 +# define R300_TX_FORMAT_ALPHA_4CH 0x600 +# define R300_TX_FORMAT_ALPHA_NONE 0xA00 + /* Swizzling */ + /* constants */ +# define R300_TX_FORMAT_X 0 +# define R300_TX_FORMAT_Y 1 +# define R300_TX_FORMAT_Z 2 +# define R300_TX_FORMAT_W 3 +# define R300_TX_FORMAT_ZERO 4 +# define R300_TX_FORMAT_ONE 5 +# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_B_SHIFT 18 +# define R300_TX_FORMAT_G_SHIFT 15 +# define R300_TX_FORMAT_R_SHIFT 12 +# define R300_TX_FORMAT_A_SHIFT 9 + /* Convenience macro to take care of layout and swizzling */ +# define R300_EASY_TXFORMAT(B, G, R, A, FMT) (\ + ((R300_TX_FORMAT_##B)< + * + * Graphics driver for ATI Radeon cards written by + * Claudio Ciccani . + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __RADEON_STATE_H__ +#define __RADEON_STATE_H__ + +#include + +/* R100 state funcs */ +void r100_restore ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev ); +void r100_set_destination ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_source ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_source_mask ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_clip ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_drawing_color ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_src_colorkey ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_drawingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r100_set_blittingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); + +/* R200 state funcs */ +void r200_restore ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev ); +void r200_set_destination ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_source ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_source_mask ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_clip ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_drawing_color ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_src_colorkey ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_drawingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r200_set_blittingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); + +/* R300 state funcs */ +void r300_restore ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev ); +void r300_set_destination ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_source ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_clip3d ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + const DFBRegion *clip ); +void r300_set_clip ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_drawing_color ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_blitting_color( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_src_colorkey ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_blend_function( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_render_options( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_drawingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); +void r300_set_blittingflags ( RadeonDriverData *rdrv, + RadeonDeviceData *rdev, + CardState *state ); + + +#define RADEON_IS_SET( flag ) \ + ((rdev->set & SMF_##flag) == SMF_##flag) + +#define RADEON_SET( flag ) \ + rdev->set |= SMF_##flag + +#define RADEON_UNSET( flag ) \ + rdev->set &= ~(SMF_##flag) + + +static inline u32 +radeon_buffer_offset( RadeonDeviceData *rdev, CoreSurfaceBufferLock *lock ) +{ + if (lock->phys - lock->offset == rdev->fb_phys) + return lock->offset + rdev->fb_offset; + + return lock->offset + rdev->agp_offset; +} + + +#endif /* __RADEON_STATE_H__ */ diff --git a/Source/DirectFB/gfxdrivers/radeon/vertex_shader.h b/Source/DirectFB/gfxdrivers/radeon/vertex_shader.h new file mode 100755 index 0000000..4fd0fd2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/radeon/vertex_shader.h @@ -0,0 +1,83 @@ +#ifndef __VERTEX_SHADER_H__ +#define __VERTEX_SHADER_H__ + +#define VSF_FLAG_X 1 +#define VSF_FLAG_Y 2 +#define VSF_FLAG_Z 4 +#define VSF_FLAG_W 8 +#define VSF_FLAG_XYZ (VSF_FLAG_X | VSF_FLAG_Y | VSF_FLAG_Z) +#define VSF_FLAG_ALL 0xf +#define VSF_FLAG_NONE 0 + +#define VSF_OUT_CLASS_TMP 0 +#define VSF_OUT_CLASS_ADDR 1 +#define VSF_OUT_CLASS_RESULT 2 + + +/* first CARD32 of an instruction */ + +/* possible operations: + DOT, MUL, ADD, MAD, FRC, MAX, MIN, SGE, SLT, EXP, LOG, LIT, POW, RCP, RSQ, EX2, + LG2, MAD_2 */ + +#define MAKE_VSF_OP(op, out_reg_index, out_reg_fields, class) \ + ((op) \ + | ((out_reg_index) << R300_VPI_OUT_REG_INDEX_SHIFT) \ + | ((out_reg_fields) << 20) \ + | ( (class) << 8 ) ) + +#define EASY_VSF_OP(op, out_reg_index, out_reg_fields, class) \ + MAKE_VSF_OP(R300_VPI_OUT_OP_##op, out_reg_index, VSF_FLAG_##out_reg_fields, VSF_OUT_CLASS_##class) \ + +/* according to Nikolai, the subsequent 3 CARD32 are sources, use same define for each */ + +#define VSF_IN_CLASS_TMP 0 +#define VSF_IN_CLASS_ATTR 1 +#define VSF_IN_CLASS_PARAM 2 +#define VSF_IN_CLASS_NONE 9 + +#define VSF_IN_COMPONENT_X 0 +#define VSF_IN_COMPONENT_Y 1 +#define VSF_IN_COMPONENT_Z 2 +#define VSF_IN_COMPONENT_W 3 +#define VSF_IN_COMPONENT_ZERO 4 +#define VSF_IN_COMPONENT_ONE 5 + +#define MAKE_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \ + ( ((in_reg_index)<, + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE__MMIO_H__ +#define __SAVAGE__MMIO_H__ + +#include + +typedef u8 uint8; +typedef u16 uint16; +typedef u32 uint32; + +typedef s8 sint8; +typedef s16 sint16; +typedef s32 sint32; + +#if 0 + +static inline void +savage_out32(volatile uint8 *mmioaddr, uint32 reg, uint32 value) +{ + *((uint32*)(mmioaddr+reg)) = value; +} + +static inline volatile uint32 +savage_in32(volatile uint8 *mmioaddr, uint32 reg) +{ + return *((uint32*)(mmioaddr+reg)); +} + +static inline void +savage_out16(volatile uint8 *mmioaddr, uint32 reg, uint16 value) +{ + *((uint16*)(mmioaddr+reg)) = value; +} + +#else + +#define savage_out32(mmio, reg, value) (*((volatile uint32 *) ((mmio)+(reg))) = (uint32)(value)) +#define savage_in32(mmio, reg) (*((volatile uint32 *) ((mmio)+(reg)))) +#define savage_out16(mmio, reg, value) (*((volatile uint16 *) ((mmio)+(reg))) = (uint16)(value)) + +#endif + +#if 0 + +static inline void +vga_out8(volatile uint8 *mmioaddr, uint16 reg, uint8 value) +{ + *((uint8*)(mmioaddr+0x8000+reg)) = value; +} + +static inline void +vga_out16(volatile uint8 *mmioaddr, uint16 reg, uint16 value) +{ + *((uint8*)(mmioaddr+0x8000+reg)) = value; +} + +static inline volatile uint8 +vga_in8(volatile uint8 *mmioaddr, uint16 reg) +{ + return *((uint8*)(mmioaddr+0x8000+reg)); +} + +#else + +#define vga_out8(mmio, reg, value) (*((volatile uint8 *) ((mmio)+0x8000+(reg))) = (uint8)(value)) +#define vga_out16(mmio, reg, value) (*((volatile uint16 *) ((mmio)+0x8000+(reg))) = (uint16)(value)) +#define vga_in8(mmio, reg) (*((volatile uint8 *) ((mmio)+0x8000+(reg)))) + +#endif + +#endif /* __SAVAGE__MMIO_H__ */ diff --git a/Source/DirectFB/gfxdrivers/savage/savage.c b/Source/DirectFB/gfxdrivers/savage/savage.c new file mode 100755 index 0000000..dffb8e3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage.c @@ -0,0 +1,346 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä , + Claudio Ciccani and + Alex Song . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( savage ) + +#include "savage.h" +#include "savage3d.h" +#include "savage4.h" +#include "savage2000.h" +#include "savage_bci.h" + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + return 1; + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + return 1; + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Savage Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + /* some defaults, each driver has it's own version */ + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (SavageDriverData); + info->device_data_size = sizeof (SavageDeviceData); + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + savage3d_get_info( device, info ); + break; + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + savage4_get_info( device, info ); + break; + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + savage2000_get_info( device, info ); + break; + } +} + + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + + sdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!sdrv->mmio_base) + return DFB_IO; + + sdrv->bci_base = (volatile u32*)(sdrv->mmio_base + BCI_BUFFER_OFFSET); + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + return savage3d_init_driver( device, funcs, driver_data ); + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + return savage4_init_driver( device, funcs, driver_data ); + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + return savage2000_init_driver( device, funcs, driver_data ); + } + + return DFB_BUG; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + SavageDeviceData *sdev = (SavageDeviceData*) device_data; + volatile u8 *mmio = sdrv->mmio_base; + + /* use polling for syncing, artefacts occur otherwise */ + dfb_config->pollvsync_after = 1; + + sdev->accel_id = dfb_gfxcard_get_accelerator( device ); + + switch (sdev->accel_id) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + savage3d_init_device( device, device_info, + driver_data, device_data ); + break; + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + savage4_init_device( device, device_info, + driver_data, device_data ); + break; + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + savage2000_init_device( device, device_info, + driver_data, device_data ); + break; + default: + D_BUG("unexpected accelerator id"); + return DFB_BUG; + } + + /* Turn on 16-bit register access. */ + + vga_out8( mmio, 0x3d4, 0x31); + vga_out8( mmio, 0x3d5, 0x0c); + + /* Set stride to use GBD. */ + + vga_out8( mmio, 0x3d4, 0x50); + vga_out8( mmio, 0x3d5, vga_in8( mmio, 0x3d5 ) | 0xC1); + + /* Enable 2D engine. */ + + vga_out8( mmio, 0x3d4, 0x40 ); + vga_out8( mmio, 0x3d5, 0x01 ); + + + savage_out32( mmio, MONO_PAT_0, ~0 ); + savage_out32( mmio, MONO_PAT_1, ~0 ); + + /* Setup plane masks */ + savage_out32( mmio, 0x8128, ~0 ); /* enable all write planes */ + savage_out32( mmio, 0x812C, ~0 ); /* enable all read planes */ + savage_out16( mmio, 0x8134, 0x27 ); + savage_out16( mmio, 0x8136, 0x07 ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + SavageDeviceData *sdev = (SavageDeviceData*) device_data; + + (void) sdev; + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + savage3d_close_device( device, driver_data, device_data ); + break; + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + savage4_close_device( device, driver_data, device_data ); + break; + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + savage2000_close_device( device, driver_data, device_data ); + break; + } + + D_DEBUG( "DirectFBSavage: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFBSavage: %9d savage_waitfifo calls\n", + sdev->waitfifo_calls ); + D_DEBUG( "DirectFBSavage: %9d savage_waitidle calls\n", + sdev->waitidle_calls ); + D_DEBUG( "DirectFBSavage: %9d register writes (savage_waitfifo sum)\n", + sdev->waitfifo_sum ); + D_DEBUG( "DirectFBSavage: %9d FIFO wait cycles (depends on CPU)\n", + sdev->fifo_waitcycles ); + D_DEBUG( "DirectFBSavage: %9d IDLE wait cycles (depends on CPU)\n", + sdev->idle_waitcycles ); + D_DEBUG( "DirectFBSavage: %9d FIFO space cache hits(depends on CPU)\n", + sdev->fifo_cache_hits ); + D_DEBUG( "DirectFBSavage: Conclusion:\n" ); + D_DEBUG( "DirectFBSavage: Average register writes/savage_waitfifo " + "call: %.2f\n", + sdev->waitfifo_sum/(float)(sdev->waitfifo_calls) ); + D_DEBUG( "DirectFBSavage: Average wait cycles/savage_waitfifo call:" + " %.2f\n", + sdev->fifo_waitcycles/(float)(sdev->waitfifo_calls) ); + D_DEBUG( "DirectFBSavage: Average wait cycles/savage_waitidle call:" + " %.2f\n", + sdev->idle_waitcycles/(float)(sdev->waitidle_calls) ); + D_DEBUG( "DirectFBSavage: Average fifo space cache hits: %02d%%\n", + (int)(100 * sdev->fifo_cache_hits/ + (float)(sdev->waitfifo_calls)) ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_SAVAGE3D: /* Savage3D series */ + case FB_ACCEL_SAVAGE3D_MV: + case FB_ACCEL_SAVAGE_MX_MV: + case FB_ACCEL_SAVAGE_MX: + case FB_ACCEL_SAVAGE_IX_MV: + case FB_ACCEL_SAVAGE_IX: + savage3d_close_driver( device, driver_data ); + break; + + case FB_ACCEL_SAVAGE4: /* Savage4 series */ + case FB_ACCEL_PROSAVAGE_PM: + case FB_ACCEL_PROSAVAGE_KM: + case FB_ACCEL_S3TWISTER_P: + case FB_ACCEL_S3TWISTER_K: + savage4_close_driver( device, driver_data ); + break; + + case FB_ACCEL_SAVAGE2000: /* Savage 2000 */ + savage2000_close_driver( device, driver_data ); + break; + } + + dfb_gfxcard_unmap_mmio( device, sdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/savage/savage.h b/Source/DirectFB/gfxdrivers/savage/savage.h new file mode 100755 index 0000000..2b9b7c8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage.h @@ -0,0 +1,145 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE_H__ +#define __SAVAGE_H__ + +#include + +#define SRC_BASE 0xa4d4 +#define DEST_BASE 0xa4d8 +#define CLIP_L_R 0xa4dc +#define CLIP_T_B 0xa4e0 +#define DEST_SRC_STR 0xa4e4 +#define MONO_PAT_0 0xa4e8 +#define MONO_PAT_1 0xa4ec + + +#define BCI_BUFFER_OFFSET 0x10000 + +#define MAXFIFO 0x7f00 + +typedef struct { + unsigned int accel_id; + + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int waitidle_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; + + unsigned int fifo_space; + + unsigned int bci_ptr; +} SavageDeviceData; + +typedef struct { + volatile u8 *mmio_base; + volatile u32 *bci_base; +} SavageDriverData; + + +#if 0 +typedef struct S3SAVDRAWCTRLtag { + hwUI32 uED:1; // Enable Dithering + hwUI32 uUVO:1; // UV Offset Enable (add 0.5 to u and v + hwUI32 uBCM:2; // Backface Cull Mode + // 00 - reserved + // 01 - disable culling + // 10 - cull clockwise + // 11 - cull counterclockwise + hwUI32 uTVC:1; // vertex counter reset 1 - reset it + hwUI32 uSM:1; // Shade Mode 0 - gouraud, 1 - flat (color at vertex 0) + hwUI32 uESS:1; // Enable Specular + hwUI32 uDABM:3; // Destination Alpha Blend Mode look below + hwUI32 uSABM:3; // Source Alpha Blend Mode look below + hwUI32 uReserved1:1; + hwUI32 uATC:3; // Alpha Test Compare look below + hwUI32 uEAT:1; // Enable Alpha Test + hwUI32 uAlphaRef:8; // Alpha Reference Value + hwUI32 uTBC:3; // Texture Blending Control (look below) + hwUI32 uFDW:1; // Flush Destination Writes + hwUI32 uFZW:1; // Flush Z Writes + hwUI32 uIM:1; // Interpolaton Mode 1 - linear color and fog interpolation +} S3SAVDRAWCTRL, *PS3SAVDRAWCTRL; +#endif + +#define DRAWCTRL_ENABLE_DITHERING 0x00000001 +#define DRAWCTRL_ENABLE_UV_OFFSET 0x00000002 +#define DRAWCTRL_CULL_REVERSED 0x00000000 +#define DRAWCTRL_CULL_NONE 0x00000004 +#define DRAWCTRL_CULL_CLOCKWISE 0x00000008 +#define DRAWCTRL_CULL_COUNTERCLOCKWISE 0x0000000C +#define DRAWCTRL_VERTEX_COUNTER_RESET 0x00000010 +#define DRAWCTRL_SHADE_GOURAUD 0x00000000 +#define DRAWCTRL_SHADE_FLAT 0x00000020 +#define DRAWCTRL_ENABLE_SPECULAR 0x00000040 +#define DRAWCTRL_ENABLE_ALPHA_TEST 0x00020000 +#define DRAWCTRL_FLUSH_DESTINATION_WRITES 0x20000000 +#define DRAWCTRL_FLUSH_Z_WRITES 0x40000000 +#define DRAWCTRL_COLOR_AND_FOG_INTERPOLATION 0x80000000 + +#define DRAWCTRL_DABM_ZERO (0 << 7) +#define DRAWCTRL_DABM_ONE (1 << 7) +#define DRAWCTRL_DABM_SOURCE_COLOR (2 << 7) +#define DRAWCTRL_DABM_ONE_MINUS_SOURCE_COLOR (3 << 7) +#define DRAWCTRL_DABM_SOURCE_ALPHA (4 << 7) +#define DRAWCTRL_DABM_ONE_MINUS_SOURCE_ALPHA (5 << 7) +#define DRAWCTRL_DABM_6 (6 << 7) +#define DRAWCTRL_DABM_7 (7 << 7) + +#define DRAWCTRL_SABM_ZERO (0 << 10) +#define DRAWCTRL_SABM_ONE (1 << 10) +#define DRAWCTRL_SABM_DEST_COLOR (2 << 10) +#define DRAWCTRL_SABM_ONE_MINUS_DEST_COLOR (3 << 10) +#define DRAWCTRL_SABM_SOURCE_ALPHA (4 << 10) +#define DRAWCTRL_SABM_ONE_MINUS_SOURCE_ALPHA (5 << 10) +#define DRAWCTRL_SABM_6 (6 << 10) +#define DRAWCTRL_SABM_7 (7 << 10) + +#define DRAWCTRL_ATC_NEVER (0 << 14) +#define DRAWCTRL_ATC_LESS (1 << 14) +#define DRAWCTRL_ATC_EQUAL (2 << 14) +#define DRAWCTRL_ATC_LEQUAL (3 << 14) +#define DRAWCTRL_ATC_GREATER (4 << 14) +#define DRAWCTRL_ATC_NOTEQUAL (5 << 14) +#define DRAWCTRL_ATC_GEQUAL (6 << 14) +#define DRAWCTRL_ATC_ALWAYS (7 << 14) + +#define DRAWCTRL_TBC_DECAL (0 << 26) +#define DRAWCTRL_TBC_MODULATE (1 << 26) +#define DRAWCTRL_TBC_DECALALPHA (2 << 26) +#define DRAWCTRL_TBC_MODULATEALPHA (3 << 26) +#define DRAWCTRL_TBC_4 (4 << 26) +#define DRAWCTRL_TBC_5 (5 << 26) +#define DRAWCTRL_TBC_COPY (6 << 26) +#define DRAWCTRL_TBC_7 (7 << 26) + + +#endif diff --git a/Source/DirectFB/gfxdrivers/savage/savage2000.c b/Source/DirectFB/gfxdrivers/savage/savage2000.c new file mode 100755 index 0000000..0f06ed1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage2000.c @@ -0,0 +1,199 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#include "savage.h" +#include "savage2000.h" +#include "mmio.h" + + +/* state validation */ + + +/* required implementations */ + +static DFBResult savage2000EngineSync( void *drv, void *dev ) +{ + Savage2000DriverData *sdrv = (Savage2000DriverData*) drv; + Savage2000DeviceData *sdev = (Savage2000DeviceData*) dev; + + savage2000_waitidle( sdrv, sdev ); + + return DFB_OK; +} + +#define SAVAGE2000_DRAWING_FLAGS \ + (DSDRAW_NOFX) + +#define SAVAGE2000_DRAWING_FUNCTIONS \ + (DFXL_NONE) + +#define SAVAGE2000_BLITTING_FLAGS \ + (DSBLIT_NOFX) + +#define SAVAGE2000_BLITTING_FUNCTIONS \ + (DFXL_NONE) + + +static void savage2000CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ +} + +static void savage2000SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ +} + +static bool savage2000FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + return false; +} + +static bool savage2000DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + return false; +} + +static bool savage2000DrawLine( void *drv, void *dev, DFBRegion *line ) +{ + return false; +} + +static bool savage2000FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + return false; +} + +static bool savage2000Blit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + return false; +} + +static bool savage2000StretchBlit( void *drv, void *dev, + DFBRectangle *sr, DFBRectangle *dr ) +{ + return false; +} + +/* exported symbols */ + +void +savage2000_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + info->version.major = 0; + info->version.minor = 0; + + info->driver_data_size = sizeof (Savage2000DriverData); + info->device_data_size = sizeof (Savage2000DeviceData); +} + +DFBResult +savage2000_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ) +{ + funcs->CheckState = savage2000CheckState; + funcs->SetState = savage2000SetState; + funcs->EngineSync = savage2000EngineSync; + + funcs->FillRectangle = savage2000FillRectangle; + funcs->DrawRectangle = savage2000DrawRectangle; + funcs->DrawLine = savage2000DrawLine; + funcs->FillTriangle = savage2000FillTriangle; + funcs->Blit = savage2000Blit; + funcs->StretchBlit = savage2000StretchBlit; + + return DFB_OK; +} + +DFBResult +savage2000_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Savage2000 Series" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "S3" ); + + + device_info->caps.flags = 0; + device_info->caps.accel = SAVAGE2000_DRAWING_FUNCTIONS | + SAVAGE2000_BLITTING_FUNCTIONS; + device_info->caps.drawing = SAVAGE2000_DRAWING_FLAGS; + device_info->caps.blitting = SAVAGE2000_BLITTING_FLAGS; + + device_info->limits.surface_byteoffset_alignment = 2048; + device_info->limits.surface_pixelpitch_alignment = 32; + + return DFB_OK; +} + +void +savage2000_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +void +savage2000_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} + diff --git a/Source/DirectFB/gfxdrivers/savage/savage2000.h b/Source/DirectFB/gfxdrivers/savage/savage2000.h new file mode 100755 index 0000000..de67737 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage2000.h @@ -0,0 +1,105 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE2000_H__ +#define __SAVAGE2000_H__ + +#include + +#include "savage.h" +#include "mmio.h" + +typedef struct { + SavageDeviceData s; +} Savage2000DeviceData; + +typedef struct { + SavageDriverData s; +} Savage2000DriverData; + +void +savage2000_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ); + +DFBResult +savage2000_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ); + +DFBResult +savage2000_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ); + +void +savage2000_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ); + +void +savage2000_close_driver( CoreGraphicsDevice *device, + void *driver_data ); + + +#undef FIFOSTATUS +#define FIFOSTATUS 0x48C60 + +/* Wait for fifo space */ +static inline void +savage2000_waitfifo(Savage2000DriverData *sdrv, + Savage2000DeviceData *sdev, int space) +{ + uint32 slots = MAXFIFO - space; + volatile u8 *mmio = sdrv->s.mmio_base; + + sdev->s.waitfifo_sum += space; + sdev->s.waitfifo_calls++; + + if ((savage_in32(mmio, FIFOSTATUS) & 0x000fffff) > slots) { + do { + sdev->s.fifo_waitcycles++; + } while (savage_in32(mmio, FIFOSTATUS) > slots); + } + else { + sdev->s.fifo_cache_hits++; + } +} + +/* Wait for idle accelerator */ +static inline void +savage2000_waitidle(Savage2000DriverData *sdrv, Savage2000DeviceData *sdev) +{ + sdev->s.waitidle_calls++; + + while (savage_in32(sdrv->s.mmio_base, FIFOSTATUS) & 0x009fffff) { + sdev->s.idle_waitcycles++; + } +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/savage/savage3d.c b/Source/DirectFB/gfxdrivers/savage/savage3d.c new file mode 100755 index 0000000..4117b0e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage3d.c @@ -0,0 +1,561 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include "savage.h" +#include "savage_bci.h" +#include "savage3d.h" +#include "mmio.h" +#include "savage_streams_old.h" + + + +/* required implementations */ + +static DFBResult savage3DEngineSync( void *drv, void *dev ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + savage3D_waitidle( sdrv, sdev ); + + return DFB_OK; +} + +#define SAVAGE3D_DRAWING_FLAGS \ + (DSDRAW_NOFX) + +#define SAVAGE3D_DRAWING_FUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE) + +#define SAVAGE3D_BLITTING_FLAGS \ + (DSBLIT_SRC_COLORKEY) + +#define SAVAGE3D_BLITTING_FUNCTIONS \ + (DFXL_BLIT) + + +static inline void savage3D_validate_gbd( Savage3DDriverData *sdrv, + Savage3DDeviceData *sdev, + CardState *state ) +{ + u32 BitmapDescriptor; + CoreSurface *destination; + int bpp; + + + if (sdev->v_gbd) + return; + + destination = state->destination; + bpp = DFB_BYTES_PER_PIXEL(destination->config.format); + + BitmapDescriptor = BCI_BD_BW_DISABLE | 8 | 1; + BCI_BD_SET_BPP( BitmapDescriptor, bpp * 8 ); + BCI_BD_SET_STRIDE( BitmapDescriptor, state->dst.pitch / bpp ); + + /* strange effects if we don't wait here for the Savage3D being idle */ + savage3D_waitidle( sdrv, sdev ); + + savage3D_waitfifo( sdrv, sdev, 4 ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD1 ); + BCI_SEND( state->dst.offset ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD2 ); + BCI_SEND( BitmapDescriptor ); + + sdev->v_gbd = 1; +} + +static inline void savage3D_validate_pbd( Savage3DDriverData *sdrv, + Savage3DDeviceData *sdev, + CardState *state ) +{ + u32 BitmapDescriptor; + CoreSurface *source; + int bpp; + + + if (sdev->v_pbd) + return; + + source = state->source; + bpp = DFB_BYTES_PER_PIXEL(source->config.format); + + BitmapDescriptor = BCI_BD_BW_DISABLE; + BCI_BD_SET_BPP( BitmapDescriptor, bpp * 8 ); + BCI_BD_SET_STRIDE( BitmapDescriptor, state->src.pitch / bpp ); + + + savage3D_waitfifo( sdrv, sdev, 4 ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_PBD1 ); + BCI_SEND( state->src.offset ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_PBD2 ); + BCI_SEND( BitmapDescriptor ); + + sdev->v_pbd = 1; +} + +static inline void savage3D_validate_color( Savage3DDriverData *sdrv, + Savage3DDeviceData *sdev, + CardState *state ) +{ + if (sdev->v_color) + return; + + savage3D_waitfifo( sdrv, sdev, 2 ); + + BCI_SEND( BCI_CMD_NOP | BCI_CMD_SEND_COLOR ); + + switch (state->destination->config.format) { + case DSPF_A8: + BCI_SEND( state->color.a ); + break; + case DSPF_ARGB1555: + BCI_SEND( PIXEL_ARGB1555(state->color.a, + state->color.r, + state->color.g, + state->color.b) ); + break; + case DSPF_RGB16: + BCI_SEND( PIXEL_RGB16(state->color.r, + state->color.g, + state->color.b) ); + break; + case DSPF_RGB32: + BCI_SEND( PIXEL_RGB32(state->color.r, + state->color.g, + state->color.b) ); + break; + case DSPF_ARGB: + BCI_SEND( PIXEL_ARGB(state->color.a, + state->color.r, + state->color.g, + state->color.b) ); + break; + default: + D_ONCE( "unsupported destination format" ); + break; + } + + sdev->v_color = 1; +} + +static inline void savage3D_set_clip( Savage3DDriverData *sdrv, + Savage3DDeviceData *sdev, + DFBRegion *clip ) +{ + savage3D_waitfifo( sdrv, sdev, 3 ); + + BCI_SEND( BCI_CMD_NOP | BCI_CMD_CLIP_NEW ); + + BCI_SEND( BCI_CLIP_TL( clip->y1, clip->x1 ) ); + BCI_SEND( BCI_CLIP_BR( clip->y2, clip->x2 ) ); +} + +static void savage3DCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + switch (state->destination->config.format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~SAVAGE3D_DRAWING_FLAGS) + return; + + state->accel |= SAVAGE3D_DRAWING_FUNCTIONS; + } + else { + if (state->source->config.format != state->destination->config.format) + return; + + if (state->blittingflags & ~SAVAGE3D_BLITTING_FLAGS) + return; + + state->accel |= SAVAGE3D_BLITTING_FUNCTIONS; + } +} + + +static void savage3DSetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + if (state->mod_hw) { + if (state->mod_hw & SMF_DESTINATION) + sdev->v_gbd = sdev->v_color = 0; + else if (state->mod_hw & SMF_COLOR) + sdev->v_color = 0; + + if (state->mod_hw & SMF_SOURCE) + sdev->v_pbd = 0; + } + + savage3D_validate_gbd( sdrv, sdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + savage3D_validate_color( sdrv, sdev, state ); + + state->set |= SAVAGE3D_DRAWING_FUNCTIONS; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + savage3D_validate_pbd( sdrv, sdev, state ); + + state->set |= SAVAGE3D_BLITTING_FUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function!" ); + return; + } + + if (state->mod_hw & SMF_BLITTING_FLAGS) { + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + sdev->Cmd_Src_Transparent = BCI_CMD_SRC_TRANSPARENT | + BCI_CMD_SEND_COLOR; + else + sdev->Cmd_Src_Transparent = 0; + } + + if (state->mod_hw & SMF_CLIP) + savage3D_set_clip( sdrv, sdev, &state->clip ); + + if (state->mod_hw & SMF_SRC_COLORKEY) + sdev->src_colorkey = state->src_colorkey; + + state->mod_hw = 0; +} + +static bool savage3DFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + savage3D_waitfifo( sdrv, sdev, 3 ); + + BCI_SEND( BCI_CMD_RECT | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y(rect->x, rect->y) ); + BCI_SEND( BCI_W_H(rect->w, rect->h) ); + + return true; +} + +static bool savage3DDrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + savage3D_waitfifo( sdrv, sdev, 12 ); + + /* first line */ + BCI_SEND( BCI_CMD_RECT | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y) ); + BCI_SEND( BCI_W_H( 1 , rect->h) ); + + /* second line */ + BCI_SEND( BCI_CMD_RECT | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y) ); + BCI_SEND( BCI_W_H( rect->w , 1 ) ); + + /* third line */ + BCI_SEND( BCI_CMD_RECT | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y+rect->h-1 ) ); + BCI_SEND( BCI_W_H( rect->w , 1 ) ); + + /* fourth line */ + BCI_SEND( BCI_CMD_RECT | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x+rect->w-1, rect->y ) ); + BCI_SEND( BCI_W_H( 1 , rect->h ) ); + + return true; +} + +static bool savage3DDrawLine( void *drv, void *dev, DFBRegion *line ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + int dx, dy; + int min, max, xp, yp, ym; + + + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + xp = (dx >= 0); + if (!xp) + dx = -dx; + + yp = (dy >= 0); + if (!yp) + dy = -dy; + + ym = (dy > dx); + if (ym) { + max = dy + 1; + min = dx; + } + else { + max = dx + 1; + min = dy; + } + + savage3D_waitfifo( sdrv, sdev, 4 ); + + BCI_SEND( BCI_CMD_LINE_LAST_PIXEL | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_LINE_X_Y( line->x1, line->y1 ) ); + BCI_SEND( BCI_LINE_STEPS( 2 * (min - max), 2 * min ) ); + BCI_SEND( BCI_LINE_MISC( max, ym, xp, yp, 2 * min - max ) ); + + return true; +} + +static bool savage3DFillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + return false; +} + +static bool savage3DBlit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Savage3DDriverData *sdrv = (Savage3DDriverData*) drv; + Savage3DDeviceData *sdev = (Savage3DDeviceData*) dev; + + u32 cmd = ( BCI_CMD_RECT | sdev->Cmd_Src_Transparent | + BCI_CMD_CLIP_CURRENT | BCI_CMD_DEST_GBD | + BCI_CMD_SRC_PBD_COLOR | (0xcc << 16) ); + + if (dx < rect->x) { + cmd |= BCI_CMD_RECT_XP; + } + else { + dx += rect->w - 1; + rect->x += rect->w - 1; + } + + if (dy < rect->y) { + cmd |= BCI_CMD_RECT_YP; + } + else { + dy += rect->h - 1; + rect->y += rect->h - 1; + } + + savage3D_waitfifo( sdrv, sdev, sdev->Cmd_Src_Transparent ? 5 : 4 ); + + BCI_SEND( cmd ); + + /* we always have to send the colorkey, + but at least it does not clobber the fill color */ + if (sdev->Cmd_Src_Transparent) + BCI_SEND( sdev->src_colorkey ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y ) ); + BCI_SEND( BCI_X_Y( dx, dy ) ); + BCI_SEND( BCI_W_H( rect->w, rect->h ) ); + + return true; +} + +static bool savage3DStretchBlit( void *drv, void *dev, + DFBRectangle *sr, DFBRectangle *dr ) +{ + return false; +} + +static void savage3DAfterSetVar( void *drv, void *dev ) +{ +} + +/* exported symbols */ + +void +savage3d_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (Savage3DDriverData); + info->device_data_size = sizeof (Savage3DDeviceData); +} + +DFBResult +savage3d_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ) +{ + funcs->CheckState = savage3DCheckState; + funcs->SetState = savage3DSetState; + funcs->EngineSync = savage3DEngineSync; + funcs->AfterSetVar = savage3DAfterSetVar; + + funcs->FillRectangle = savage3DFillRectangle; + funcs->DrawRectangle = savage3DDrawRectangle; + funcs->DrawLine = savage3DDrawLine; + funcs->FillTriangle = savage3DFillTriangle; + funcs->Blit = savage3DBlit; + funcs->StretchBlit = savage3DStretchBlit; + + return DFB_OK; +} + +DFBResult +savage3d_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + volatile u8 *mmio = sdrv->mmio_base; + + unsigned long cobIndex; /* size index */ + unsigned long cobSize; /* size in bytes */ + unsigned long cobOffset; /* offset in frame buffer */ + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Savage3D Series" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "S3" ); + + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = SAVAGE3D_DRAWING_FUNCTIONS | + SAVAGE3D_BLITTING_FUNCTIONS; + device_info->caps.drawing = SAVAGE3D_DRAWING_FLAGS; + device_info->caps.blitting = SAVAGE3D_BLITTING_FLAGS; + + device_info->limits.surface_byteoffset_alignment = 2048; + device_info->limits.surface_pixelpitch_alignment = 32; + + + cobIndex = 7; + cobSize = 0x400 << cobIndex; + cobOffset = dfb_gfxcard_reserve_memory( device, cobSize ); + + + /* savage_out32( 0x8504, 0x00008000 ); */ + + /* Disable BCI */ + savage_out32( mmio, 0x48C18, + savage_in32( mmio, 0x48C18 ) & 0x3FF0); + + /* Setup BCI command overflow buffer */ + savage_out32( mmio, 0x48C14, (cobOffset >> 11) | (cobIndex << 29)); + + /* Program shadow status update. */ + savage_out32( mmio, 0x48C10, 0x78207220); + savage_out32( mmio, 0x48C0C, 0); + + /* Enable BCI and command overflow buffer */ + savage_out32( mmio, 0x48C18, savage_in32( mmio, 0x48C18 ) | 0x0C); + + return DFB_OK; +} + +void +savage3d_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +void +savage3d_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} + diff --git a/Source/DirectFB/gfxdrivers/savage/savage3d.h b/Source/DirectFB/gfxdrivers/savage/savage3d.h new file mode 100755 index 0000000..d693c34 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage3d.h @@ -0,0 +1,121 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE3D_H__ +#define __SAVAGE3D_H__ + +#include + +#include "savage.h" +#include "mmio.h" + + +typedef struct { + SavageDeviceData s; + + /* state validation */ + int v_gbd; /* destination */ + int v_pbd; /* source */ + int v_color; /* opaque fill color */ + + /* saved values */ + u32 Cmd_Src_Transparent; + u32 src_colorkey; +} Savage3DDeviceData; + +typedef struct { + SavageDriverData s; +} Savage3DDriverData; + + +void +savage3d_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ); + +DFBResult +savage3d_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ); + +DFBResult +savage3d_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ); + +void +savage3d_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ); + +void +savage3d_close_driver( CoreGraphicsDevice *device, + void *driver_data ); + + +#define FIFOSTATUS 0x48C00 +#define TILEDAPERTURE0 0x48C40 +#define TILEDAPERTURE1 0x48C44 +#define TILEDAPERTURE2 0x48C48 +#define TILEDAPERTURE3 0x48C4C +#define TILEDAPERTURE4 0x48C50 +#define TILEDAPERTURE5 0x48C54 + + +/* Wait for fifo space */ +static inline void +savage3D_waitfifo(Savage3DDriverData *sdrv, Savage3DDeviceData *sdev, int space) +{ + uint32 slots = MAXFIFO - space; + volatile u8 *mmio = sdrv->s.mmio_base; + + sdev->s.waitfifo_sum += space; + sdev->s.waitfifo_calls++; + + if ((savage_in32(mmio, FIFOSTATUS) & 0x0000ffff) > slots) { + do { + sdev->s.fifo_waitcycles++; + } while ((savage_in32(mmio, FIFOSTATUS) & 0x0000ffff) > slots); + } + else { + sdev->s.fifo_cache_hits++; + } +} + +/* Wait for idle accelerator */ +static inline void +savage3D_waitidle(Savage3DDriverData *sdrv, Savage3DDeviceData *sdev) +{ + sdev->s.waitidle_calls++; + + while ((savage_in32(sdrv->s.mmio_base, FIFOSTATUS) & 0x0008ffff) != 0x80000) { + sdev->s.idle_waitcycles++; + } +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/savage/savage4.c b/Source/DirectFB/gfxdrivers/savage/savage4.c new file mode 100755 index 0000000..2026fe7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage4.c @@ -0,0 +1,599 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "savage.h" +#include "savage4.h" +#include "mmio.h" +#include "savage_bci.h" +/* + * (comment stolen from xfree86 savage driver). + * There are two different streams engines used in the Savage line. + * The old engine is in the 3D, 4, Pro, and Twister. + * The new engine is in the 2000, MX, IX, and Super. + */ +#include "savage_streams_old.h" + +/* #define SAVAGE_DEBUG */ +#ifdef SAVAGE_DEBUG +#define SVGDBG(x...) fprintf(stderr, "savage4:" x) +#else +#define SVGDBG(x...) +#endif + +/* required implementations */ + +static DFBResult savage4EngineSync( void *drv, void *dev ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + SVGDBG("savage4enginesync\n"); + savage4_waitidle( sdrv, sdev ); + + return DFB_OK; +} + +#define SAVAGE4_DRAWING_FLAGS \ + (DSDRAW_NOFX) + +#define SAVAGE4_DRAWING_FUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE) + +#define SAVAGE4_BLITTING_FLAGS \ + (DSBLIT_SRC_COLORKEY) + +#define SAVAGE4_BLITTING_FUNCTIONS \ + (DFXL_BLIT) + + +static inline void savage4_validate_gbd( Savage4DriverData *sdrv, + Savage4DeviceData *sdev, + CardState *state ) +{ + u32 BitmapDescriptor; + CoreSurface *destination; + int bpp; + + if (sdev->v_gbd) + return; + + destination = state->destination; + bpp = DFB_BYTES_PER_PIXEL(destination->config.format); + + BitmapDescriptor = BCI_BD_BW_DISABLE | 8 | 1; + BCI_BD_SET_BPP( BitmapDescriptor, bpp * 8 ); + BCI_BD_SET_STRIDE( BitmapDescriptor, state->dst.pitch / bpp ); + + /* strange effects if we don't wait here for the Savage4 being idle */ + savage4_waitidle( sdrv, sdev ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD1 ); + BCI_SEND( state->dst.offset ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD2 ); + BCI_SEND( BitmapDescriptor ); + + sdev->v_gbd = 1; +} + +static inline void savage4_validate_pbd( Savage4DriverData *sdrv, + Savage4DeviceData *sdev, + CardState *state ) +{ + u32 BitmapDescriptor; + CoreSurface *source; + int bpp; + + if (sdev->v_pbd) + return; + + source = state->source; + bpp = DFB_BYTES_PER_PIXEL(source->config.format); + + BitmapDescriptor = BCI_BD_BW_DISABLE; + BCI_BD_SET_BPP( BitmapDescriptor, bpp * 8 ); + BCI_BD_SET_STRIDE( BitmapDescriptor, state->src.pitch / bpp ); + + + savage4_waitidle( sdrv, sdev ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_PBD1 ); + BCI_SEND( state->src.offset ); + + BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_PBD2 ); + BCI_SEND( BitmapDescriptor ); + + sdev->v_pbd = 1; +} + +static inline void savage4_validate_color( Savage4DeviceData *sdev, + CardState *state ) +{ + if (sdev->v_color) + return; + + switch (state->destination->config.format) { + case DSPF_A8: + sdev->Fill_Color = state->color.a; + break; + case DSPF_ARGB1555: + sdev->Fill_Color = PIXEL_ARGB1555(state->color.a, + state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB16: + sdev->Fill_Color = PIXEL_RGB16(state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB32: + sdev->Fill_Color = PIXEL_RGB32(state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_ARGB: + sdev->Fill_Color = PIXEL_ARGB(state->color.a, + state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB332: + sdev->Fill_Color = PIXEL_RGB332(state->color.r, + state->color.g, + state->color.b); + break; + default: + D_BUG( "unexpected destination format" ); + break; + } + + sdev->v_color = 1; +} + +static inline void savage4_set_clip( Savage4DriverData *sdrv, + Savage4DeviceData *sdev, + DFBRegion *clip ) +{ + SVGDBG("savage4_set_clip x1:%i y1:%i x2:%i y2:%i\n", + clip->x1, clip->y1, clip->x2, clip->y2); + savage4_waitfifo( sdrv, sdev, 3 ); + + BCI_SEND( BCI_CMD_NOP | BCI_CMD_CLIP_NEW ); + + BCI_SEND( BCI_CLIP_TL( clip->y1, clip->x1 ) ); + BCI_SEND( BCI_CLIP_BR( clip->y2, clip->x2 ) ); +} + +static void savage4CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + SVGDBG("savage4checkstate\n"); + switch (state->destination->config.format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_RGB332: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION( accel )) { + if (state->drawingflags & ~SAVAGE4_DRAWING_FLAGS) + return; + + state->accel |= SAVAGE4_DRAWING_FUNCTIONS; + } + else { + if (state->source->config.format != state->destination->config.format) + return; + + if (state->blittingflags & ~SAVAGE4_BLITTING_FLAGS) + return; + + state->accel |= SAVAGE4_BLITTING_FUNCTIONS; + } +} + +static void savage4SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + SVGDBG("savage4setstate\n"); + if (state->mod_hw) { + if (state->mod_hw & SMF_DESTINATION) + sdev->v_gbd = sdev->v_color = 0; + else if (state->mod_hw & SMF_COLOR) + sdev->v_color = 0; + + if (state->mod_hw & SMF_SOURCE) + sdev->v_pbd = 0; + } + + savage4_validate_gbd( sdrv, sdev, state ); + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + savage4_validate_color( sdev, state ); + + state->set |= SAVAGE4_DRAWING_FUNCTIONS; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + savage4_validate_pbd( sdrv, sdev, state ); + + state->set |= SAVAGE4_BLITTING_FUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function!" ); + return; + } + + if (state->mod_hw & SMF_BLITTING_FLAGS) { + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + sdev->Cmd_Src_Transparent = BCI_CMD_SRC_TRANSPARENT | + BCI_CMD_SEND_COLOR; + else + sdev->Cmd_Src_Transparent = 0; + } + + if (state->mod_hw & SMF_CLIP) + savage4_set_clip( sdrv, sdev, &state->clip ); + + if (state->mod_hw & SMF_SRC_COLORKEY) + sdev->src_colorkey = state->src_colorkey; + + state->mod_hw = 0; +} + + +static bool savage4FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + savage4_waitfifo( sdrv, sdev, 4 ); + + BCI_SEND( BCI_CMD_RECT | BCI_CMD_SEND_COLOR | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | BCI_CMD_CLIP_CURRENT | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( sdev->Fill_Color ); + + BCI_SEND( BCI_X_Y(rect->x, rect->y) ); + BCI_SEND( BCI_W_H(rect->w, rect->h) ); + + return true; +} + +static bool savage4DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + savage4_waitfifo( sdrv, sdev, 13 ); + + /* first line */ + BCI_SEND( BCI_CMD_RECT | BCI_CMD_SEND_COLOR | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( sdev->Fill_Color ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y) ); + BCI_SEND( BCI_W_H( 1 , rect->h) ); + + /* second line */ + BCI_SEND( BCI_CMD_RECT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y) ); + BCI_SEND( BCI_W_H( rect->w , 1 ) ); + + /* third line */ + BCI_SEND( BCI_CMD_RECT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y+rect->h-1 ) ); + BCI_SEND( BCI_W_H( rect->w , 1 ) ); + + + /* fourth line */ + BCI_SEND( BCI_CMD_RECT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( BCI_X_Y( rect->x+rect->w-1, rect->y ) ); + BCI_SEND( BCI_W_H( 1 , rect->h ) ); + + return true; +} + +static bool savage4DrawLine( void *drv, void *dev, DFBRegion *line ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + int dx, dy; + int min, max, xp, yp, ym; + + + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + xp = (dx >= 0); + if (!xp) + dx = -dx; + + yp = (dy >= 0); + if (!yp) + dy = -dy; + + ym = (dy > dx); + if (ym) { + max = dy + 1; + min = dx; + } + else { + max = dx + 1; + min = dy; + } + + savage4_waitfifo( sdrv, sdev, 5 ); + + BCI_SEND( BCI_CMD_LINE_LAST_PIXEL | BCI_CMD_CLIP_CURRENT | + BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | BCI_CMD_SEND_COLOR | + BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID | (0xcc << 16) ); + + BCI_SEND( sdev->Fill_Color ); + + BCI_SEND( BCI_LINE_X_Y( line->x1, line->y1 ) ); + BCI_SEND( BCI_LINE_STEPS( 2 * (min - max), 2 * min ) ); + BCI_SEND( BCI_LINE_MISC( max, ym, xp, yp, 2 * min - max ) ); + + return true; +} + +static bool savage4FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + return false; +} + +static bool savage4Blit( void *drv, void *dev, + DFBRectangle *rect, int dx, int dy ) +{ + Savage4DriverData *sdrv = (Savage4DriverData*) drv; + Savage4DeviceData *sdev = (Savage4DeviceData*) dev; + + u32 cmd = ( BCI_CMD_RECT | sdev->Cmd_Src_Transparent | + BCI_CMD_CLIP_CURRENT | BCI_CMD_DEST_GBD | + BCI_CMD_SRC_PBD_COLOR | (0xcc << 16) ); + + SVGDBG("savage4Blit x:%i y:%i w:%i h:%i dx:%i dy:%i\n", + rect->x, rect->y, rect->w, rect->h, dx, dy); + + if (dx < rect->x && dx >= 0) { + cmd |= BCI_CMD_RECT_XP; /* left to right */ + } + else { + dx += rect->w - 1; + rect->x += rect->w - 1; + } + + if (dy < rect->y && dy >= 0) { + cmd |= BCI_CMD_RECT_YP; /* top to bottom */ + } + else { + dy += rect->h - 1; + rect->y += rect->h - 1; + } + + savage4_waitfifo( sdrv, sdev, sdev->Cmd_Src_Transparent ? 5 : 4 ); + + BCI_SEND( cmd ); + + /* we always have to send the colorkey, + but at least it does not clobber the fill color */ + if (sdev->Cmd_Src_Transparent) + BCI_SEND( sdev->src_colorkey ); + + BCI_SEND( BCI_X_Y( rect->x, rect->y ) ); + BCI_SEND( BCI_X_Y( dx, dy ) ); + BCI_SEND( BCI_W_H( rect->w, rect->h ) ); + + return true; +} + +static bool savage4StretchBlit( void *drv, void *dev, + DFBRectangle *sr, DFBRectangle *dr ) +{ + return false; +} + +static void savage4AfterSetVar( void *drv, void *dev ) +{ + SVGDBG("savage4aftersetvar\n"); +} + +/* exported symbols */ + +void +savage4_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + SVGDBG("savage4getinfo\n"); + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (Savage4DriverData); + info->device_data_size = sizeof (Savage4DeviceData); +} + +DFBResult +savage4_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ) +{ + SVGDBG("savage4initdriver\n"); + funcs->CheckState = savage4CheckState; + funcs->SetState = savage4SetState; + funcs->EngineSync = savage4EngineSync; + + funcs->AfterSetVar = savage4AfterSetVar; + + funcs->FillRectangle = savage4FillRectangle; + funcs->DrawRectangle = savage4DrawRectangle; + funcs->DrawLine = savage4DrawLine; + funcs->FillTriangle = savage4FillTriangle; + funcs->Blit = savage4Blit; + funcs->StretchBlit = savage4StretchBlit; + + /* setup primary layer functions */ +// dfb_layers_hook_primary(device, driver_data, &savagePrimaryFuncs, +// &savage_pfuncs, &savage_pdriver_data); + + /* setup secondary layer functions */ + // dfb_layers_register(device, driver_data, &savageSecondaryFuncs); + + return DFB_OK; +} + +DFBResult +savage4_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + volatile u8 *mmio = sdrv->mmio_base; + + SVGDBG("savage4initdevice\n"); + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Savage4 Series" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "S3" ); + + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = SAVAGE4_DRAWING_FUNCTIONS | + SAVAGE4_BLITTING_FUNCTIONS; + device_info->caps.drawing = SAVAGE4_DRAWING_FLAGS; + device_info->caps.blitting = SAVAGE4_BLITTING_FLAGS; + + device_info->limits.surface_byteoffset_alignment = 2048; + device_info->limits.surface_pixelpitch_alignment = 32; + + + vga_out8( mmio, 0x3d4, CR_SYSCONF ); + vga_out8( mmio, 0x3d5, CR_SYSCONF_ENABLE_2D_ENGINE_IO_ACCESS ); + + vga_out8( mmio, 0x3d4, CR_MEMCONF ); + vga_out8( mmio, 0x3d5, CR_MEMCONF_ENABLE_VGA_16BIT_IO_ACCESS | + CR_MEMCONF_ENHANCED_MODE_MEMORY_MAPPING ); + + + /* Setup plane masks */ + savage_out32( mmio, SAVAGE_2D_WRITE_MASK, ~0 ); + savage_out32( mmio, SAVAGE_2D_READ_MASK, ~0 ); + savage_out16( mmio, SAVAGE_2D_BACKGROUND_MIX, 0x03 ); + savage_out16( mmio, SAVAGE_2D_FOREGROUND_MIX, 0x27 ); + + /* Disable BCI */ + savage_out32( mmio, SAVAGE_COMMAND_OVERFLOW_BUFFER_POINTERS, + (savage_in32( mmio, 0x48C18)) & 0x3FF0); + + /* Program shadow status update */ + savage_out32( mmio, 0x48C10, 0x00700040); + + savage_out32( mmio, 0x48C0C, 0); + + /* Enable BCI without the COB */ + savage_out32( mmio, SAVAGE_COMMAND_OVERFLOW_BUFFER_POINTERS, + (savage_in32( mmio, 0x48C18)) | 0x08); + + return DFB_OK; +} + +void +savage4_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + SVGDBG("savage4closedevice\n"); +} + +void +savage4_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + SVGDBG("savage4closedriver\n"); +} +/* end of code */ diff --git a/Source/DirectFB/gfxdrivers/savage/savage4.h b/Source/DirectFB/gfxdrivers/savage/savage4.h new file mode 100755 index 0000000..ca46f9f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage4.h @@ -0,0 +1,146 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE4_H__ +#define __SAVAGE4_H__ + +#include + +#include "mmio.h" + +typedef struct { + SavageDeviceData s; + + /* state validation */ + int v_gbd; /* destination */ + int v_pbd; /* source */ + int v_color; /* opaque fill color */ + + /* saved values */ + u32 Cmd_Src_Transparent; + u32 Fill_Color; + u32 src_colorkey; +} Savage4DeviceData; + +typedef struct { + SavageDriverData s; +} Savage4DriverData; + + +void +savage4_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ); + +DFBResult +savage4_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data ); + +DFBResult +savage4_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ); + +void +savage4_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ); + +void +savage4_close_driver( CoreGraphicsDevice *device, + void *driver_data ); + + +#define CR_MEMCONF 0x31 +#define CR_MEMCONF_ENABLE_VGA_16BIT_IO_ACCESS 0x04 +#define CR_MEMCONF_ENHANCED_MODE_MEMORY_MAPPING 0x08 + +#define CR_SYSCONF 0x40 +#define CR_SYSCONF_ENABLE_2D_ENGINE_IO_ACCESS 0x01 + + +#define SAVAGE_2D_WRITE_MASK 0x8128 +#define SAVAGE_2D_READ_MASK 0x812C +#define SAVAGE_2D_BACKGROUND_MIX 0x8134 +#define SAVAGE_2D_FOREGROUND_MIX 0x8136 + + +/* Configuration/Status Registers */ + +#define SAVAGE_STATUS_WORD0 0x48C00 +#define SAVAGE_STATUS_WORD1 0x48C04 +#define SAVAGE_STATUS_WORD2 0x48C08 +#define SAVAGE_SHADOW_STATUS_ADDRESS 0x48C0C +#define SAVAGE_COMMAND_BUFFER_THRESHOLDS 0x48C10 +#define SAVAGE_COMMAND_OVERFLOW_BUFFER 0x48C14 +#define SAVAGE_COMMAND_OVERFLOW_BUFFER_POINTERS 0x48C18 +#define SAVAGE_VERTEX_BUFFER_ADDRESS 0x48C20 +#define SAVAGE_BCI_POWER_MANAGEMENT 0x48C24 +#define SAVAGE_TILED_SURFACE0 0x48C40 +#define SAVAGE_TILED_SURFACE1 0x48C44 +#define SAVAGE_TILED_SURFACE2 0x48C48 +#define SAVAGE_TILED_SURFACE3 0x48C4C +#define SAVAGE_TILED_SURFACE4 0x48C50 +#define SAVAGE_ALTERNATE_STATUS_WORD0 0x48C60 +#define SAVAGE_ALTERNATE_STATUS_WORD1 0x48C64 + + +/* Wait for fifo space */ +static inline void +savage4_waitfifo(Savage4DriverData *sdrv, Savage4DeviceData *sdev, int space) +{ + uint32 slots = MAXFIFO - space; + volatile u8 *mmio = sdrv->s.mmio_base; + + sdev->s.waitfifo_sum += space; + sdev->s.waitfifo_calls++; + + if ((savage_in32(mmio, SAVAGE_ALTERNATE_STATUS_WORD0) & 0x001fffff) > slots) { + do { + sdev->s.fifo_waitcycles++; + } while ((savage_in32(mmio, SAVAGE_ALTERNATE_STATUS_WORD0) & 0x001fffff) > slots); + } + else { + sdev->s.fifo_cache_hits++; + } +} + +/* Wait for idle accelerator */ +static inline void +savage4_waitidle(Savage4DriverData *sdrv, Savage4DeviceData *sdev) +{ + sdev->s.waitidle_calls++; + + while ((savage_in32(sdrv->s.mmio_base, SAVAGE_ALTERNATE_STATUS_WORD0) & 0x00a00000) != 0x00a00000) { + sdev->s.idle_waitcycles++; + } +} + + +#endif diff --git a/Source/DirectFB/gfxdrivers/savage/savage_bci.h b/Source/DirectFB/gfxdrivers/savage/savage_bci.h new file mode 100755 index 0000000..12ff14a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage_bci.h @@ -0,0 +1,208 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef _S3BCI_H_ +#define _S3BCI_H_ + +#define REVERSE_BYTE_ORDER32(dword) {\ + unsigned int temp; \ + dword = (temp & 0xFF) << 24; \ + dword |= (temp & 0xFF00) << 8; \ + dword |= (temp & 0xFF0000) >> 8; \ + dword |= (temp & 0xFF000000) >> 24; } + + +#define BCI_SIZE 0x4000 + +#define BCI_SEND(dw) { \ + if (sdev->s.bci_ptr == BCI_SIZE) sdev->s.bci_ptr = 0; \ + sdrv->s.bci_base[sdev->s.bci_ptr++] = (u32)(dw); \ + } + +#define BCI_SENDF(dw) { \ + if (sdev->s.bci_ptr == BCI_SIZE) sdev->s.bci_ptr = 0; \ + ((float*)sdrv->s.bci_base)[sdev->s.bci_ptr++] = (float)(dw); \ + } + + +#define BCI_CMD_NOP 0x40000000 +//#define BCI_CMD_SETREG 0x96000000 /* 8}CMD | 8}count | 16}index */ +#define BCI_CMD_RECT 0x48000000 +#define BCI_CMD_RECT_XP 0x01000000 +#define BCI_CMD_RECT_YP 0x02000000 +#define BCI_CMD_SCANLINE 0x50000000 +#define BCI_CMD_LINE 0x5C000000 +#define BCI_CMD_LINE_LAST_PIXEL 0x58000000 +#define BCI_CMD_BYTE_TEXT 0x63000000 +#define BCI_CMD_NT_BYTE_TEXT 0x67000000 +#define BCI_CMD_BIT_TEXT 0x6C000000 +#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) +#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) +#define BCI_CMD_SEND_COLOR 0x00008000 + +#define BCI_CMD_CLIP_NONE 0x00000000 +#define BCI_CMD_CLIP_CURRENT 0x00002000 +#define BCI_CMD_CLIP_LR 0x00004000 +#define BCI_CMD_CLIP_NEW 0x00006000 + +#define BCI_CMD_DEST_GBD 0x00000000 +#define BCI_CMD_DEST_PBD 0x00000800 +#define BCI_CMD_DEST_PBD_NEW 0x00000C00 +#define BCI_CMD_DEST_SBD 0x00001000 +#define BCI_CMD_DEST_SBD_NEW 0x00001400 + +#define BCI_CMD_SRC_TRANSPARENT 0x00000200 +#define BCI_CMD_SRC_SOLID 0x00000000 +#define BCI_CMD_SRC_GBD 0x00000020 +#define BCI_CMD_SRC_COLOR 0x00000040 +#define BCI_CMD_SRC_MONO 0x00000060 +#define BCI_CMD_SRC_PBD_COLOR 0x00000080 +#define BCI_CMD_SRC_PBD_MONO 0x000000A0 +#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 +#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 +#define BCI_CMD_SRC_SBD_COLOR 0x00000100 +#define BCI_CMD_SRC_SBD_MONO 0x00000120 +#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 +#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 + +#define BCI_CMD_PAT_TRANSPARENT 0x00000010 +#define BCI_CMD_PAT_NONE 0x00000000 +#define BCI_CMD_PAT_COLOR 0x00000002 +#define BCI_CMD_PAT_MONO 0x00000003 +#define BCI_CMD_PAT_PBD_COLOR 0x00000004 +#define BCI_CMD_PAT_PBD_MONO 0x00000005 +#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 +#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 +#define BCI_CMD_PAT_SBD_COLOR 0x00000008 +#define BCI_CMD_PAT_SBD_MONO 0x00000009 +#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A +#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B + +#define BCI_BD_BW_DISABLE 0x10000000 +#define BCI_BD_TILE_MASK 0x03000000 +#define BCI_BD_TILE_NONE 0x00000000 +#define BCI_BD_TILE_16 0x02000000 +#define BCI_BD_TILE_32 0x04000000 +#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) +#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) +#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) +#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) + +#define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF)) +#define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF)) +#define BCI_X_W(x, y) (((w) << 16) | ((x) & 0xFFF)) +#define BCI_CLIP_LR(l, r) (((r) << 16) | ((l) & 0xFFF)) +#define BCI_CLIP_TL(t, l) (((t) << 16) | ((l) & 0xFFF)) +#define BCI_CLIP_BR(b, r) (((b) << 16) | ((r) & 0xFFF)) + +#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) +#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) +#define BCI_LINE_MISC(maj, ym, xp, yp, err) \ +(((maj) & 0xFFF) | (((ym) & 1) << 13) | \ +(((xp) & 1) << 14) | (((yp) & 1) << 15) | \ +((err) << 16)) + + +/* definition of BCI register indices */ +#define BCI_VERTEX0 0x00 +#define BCI_VERTEX1 0x08 +#define BCI_VERTEX2 0x10 +#define BCI_TEXPALADDR 0x18 +#define BCI_COLORKEY 0x19 +#define BCI_TEXADDR 0x1A +#define BCI_TEXDESC 0x1B +#define BCI_TEXCTRL 0x1C +#define BCI_FOGTABLE 0x20 +#define BCI_FOGCTRL 0x30 +#define BCI_DRAWCTRL 0x31 +#define BCI_ZBCTRL 0x32 +#define BCI_ZBADDR 0x33 +#define BCI_DESTCTRL 0x34 +#define BCI_SCSTART 0x35 +#define BCI_SCEND 0x36 +#define BCI_ZWATER 0x37 +#define BCI_DWATER 0x38 + + + +// 8}CMD|8}count|16}skipflags +#define BCI_CMD_TRILIST 0x80000000L +#define BCI_CMD_TRISTRIP 0x82000000L +#define BCI_CMD_TRIFAN 0x84000000L +#define BCI_CMD_QUADLIST 0x86000000L +// or this one with previous commands if this vertex list +// is continuation of previous one +#define BCI_CMD_CONTINUE 0x01000000L +// set any register that has bci index 8}CMD|8}count|16}index +#define BCI_CMD_SETREG 0x96000000L +// update shadow status 8}CMD|24}tag +#define BCI_CMD_UPDSHADOW 0x98000000L + +#define BCI_CMD_WAIT 0xC0000000L +#define BCI_WAIT_3D_IDLE 0x00010000L +#define BCI_WAIT_2D_IDLE 0x00020000L +#define BCI_WAIT_PAGEFLIP 0x01000000L +#define BCI_WAIT_SCANLINE 0x02000000L + +#define BCI_SKIP_Z 0x01 +#define BCI_SKIP_W 0x02 +#define BCI_SKIP_DIFFUSE 0x04 +#define BCI_SKIP_SPECULAR 0x08 +#define BCI_SKIP_U 0x10 +#define BCI_SKIP_V 0x20 + +/* definition of BCI register indices */ +#define BCI_VERTEX0 0x00 +#define BCI_VERTEX1 0x08 +#define BCI_VERTEX2 0x10 +#define BCI_TEXPALADDR 0x18 +#define BCI_COLORKEY 0x19 +#define BCI_TEXADDR 0x1A +#define BCI_TEXDESC 0x1B +#define BCI_TEXCTRL 0x1C +#define BCI_FOGTABLE 0x20 +#define BCI_FOGCTRL 0x30 +#define BCI_DRAWCTRL 0x31 +#define BCI_ZBCTRL 0x32 +#define BCI_ZBADDR 0x33 +#define BCI_DESTCTRL 0x34 +#define BCI_SCSTART 0x35 +#define BCI_SCEND 0x36 +#define BCI_ZWATER 0x37 +#define BCI_DWATER 0x38 + +/* 2D regs */ +#define BCI_GBD1 0xE0 +#define BCI_GBD2 0xE1 +#define BCI_PBD1 0xE2 +#define BCI_PBD2 0xE3 +#define BCI_SBD1 0xE4 +#define BCI_SBD2 0xE5 + + +#endif /* _S3BCI_H_ */ diff --git a/Source/DirectFB/gfxdrivers/savage/savage_streams_old.c b/Source/DirectFB/gfxdrivers/savage/savage_streams_old.c new file mode 100755 index 0000000..72673a2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage_streams_old.c @@ -0,0 +1,916 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "savage.h" +#include "savage_streams_old.h" +#include "mmio.h" +#include "savage_bci.h" + +/* #define SAVAGE_DEBUG */ +#ifdef SAVAGE_DEBUG + #define SVGDBG(x...) fprintf(stderr, "savage_streams_old:" x) +#else + #define SVGDBG(x...) +#endif + +typedef struct { + DFBRectangle dest; + CoreLayerRegionConfig config; + int video_pitch; + + struct { + /* secondary stream registers */ + u32 SSTREAM_CTRL; + u32 SSTREAM_H_SCALE; + u32 BLEND_CTRL; + u32 SSTREAM_MULTIBUF; + u32 SSTREAM_FB_ADDR0; + u32 SSTREAM_FB_ADDR1; + u32 SSTREAM_STRIDE; + u32 SSTREAM_V_SCALE; + u32 SSTREAM_V_INIT_VALUE; + u32 SSTREAM_SRC_LINE_COUNT; + u32 SSTREAM_WIN_START; + u32 SSTREAM_WIN_SIZE; + u32 SSTREAM_FB_CB_ADDR; + u32 SSTREAM_FB_CR_ADDR; + u32 SSTREAM_CBCR_STRIDE; + u32 SSTREAM_FB_SIZE; + u32 SSTREAM_FB_ADDR2; + u32 CHROMA_KEY_CONTROL; + u32 CHROMA_KEY_UPPER_BOUND; + } regs; +} SavageSecondaryLayerData; + +typedef struct { + CoreLayerRegionConfig config; + CoreSurfaceBufferLock *lock; + bool init; + + struct { + /* primary stream registers */ + u32 PSTREAM_CTRL; + u32 PSTREAM_FB_ADDR0; + u32 PSTREAM_FB_ADDR1; + u32 PSTREAM_STRIDE; + u32 PSTREAM_WIN_START; + u32 PSTREAM_WIN_SIZE; + u32 PSTREAM_FB_SIZE; + } regs; +} SavagePrimaryLayerData; + +DisplayLayerFuncs savage_pfuncs; +void *savage_pdriver_data; + +/* function prototypes */ +static void +secondary_set_regs (SavageDriverData *sdrv, + SavageSecondaryLayerData *slay); +static void +secondary_calc_regs(SavageDriverData *sdrv, + SavageSecondaryLayerData *slay, + CoreLayer *layer, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock); + +static DFBResult +savage_secondary_calc_colorkey( SavageDriverData *sdrv, + SavageSecondaryLayerData *slay, + CoreLayerRegionConfig *config, + const DFBColorKey *key, + DFBSurfacePixelFormat format ); +static void +primary_set_regs (SavageDriverData *sdrv, + SavagePrimaryLayerData *play); +static void +primary_calc_regs (SavageDriverData *sdrv, + SavagePrimaryLayerData *play, + CoreLayer *layer, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock); + +static inline +void waitretrace (void) +{ + iopl(3); + while ((inb (0x3da) & 0x8)) + ; + + while (!(inb (0x3da) & 0x8)) + ; +} + +static void +streamOnOff(SavageDriverData * sdrv, int on) +{ + volatile u8 *mmio = sdrv->mmio_base; + + waitretrace(); + + if (on) { + vga_out8( mmio, 0x3d4, 0x23 ); + vga_out8( mmio, 0x3d5, 0x00 ); + + vga_out8( mmio, 0x3d4, 0x26 ); + vga_out8( mmio, 0x3d5, 0x00 ); + + /* turn on stream operation */ + vga_out8( mmio, 0x3d4, 0x67 ); + vga_out8( mmio, 0x3d5, 0x0c ); + } + else { + /* turn off stream operation */ + vga_out8( mmio, 0x3d4, 0x67 ); + vga_out8( mmio, 0x3d5, vga_in8( mmio, 0x3d5 ) & ~0x0c ); + } +} + +/* secondary layer functions */ +static int +savageSecondaryLayerDataSize( void ) +{ + SVGDBG("savageSecondaryLayerDataSize\n"); + return sizeof(SavageSecondaryLayerData); +} + +static DFBResult +savageSecondaryInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *default_config, + DFBColorAdjustment *default_adj ) +{ + SVGDBG("savageSecondaryInitLayer\n"); + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | + DLCAPS_OPACITY | DLCAPS_HUE | DLCAPS_SATURATION | + DLCAPS_ALPHACHANNEL | DLCAPS_SRC_COLORKEY | + DLCAPS_DST_COLORKEY; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf(description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, + "Savage Secondary Stream"); + + /* fill out the default configuration */ + default_config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + default_config->width = 640; + default_config->height = 480; + default_config->pixelformat = DSPF_YUY2; + default_config->buffermode = DLBM_FRONTONLY; + default_config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + default_adj->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | + DCAF_HUE | DCAF_SATURATION; + default_adj->brightness = 0x8000; + default_adj->contrast = 0x8000; + default_adj->hue = 0x8000; + default_adj->saturation = 0x8000; + + return DFB_OK; +} + +static DFBResult +savageSecondaryRemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + volatile u8 *mmio = sdrv->mmio_base; + + SVGDBG("savageSecondaryRemoveRegion\n"); + + /* put primary stream on top of secondary stream */ + savage_out32(mmio, SAVAGE_BLEND_CONTROL, + SAVAGE_BLEND_CONTROL_COMP_PSTREAM); + + return DFB_OK; +} + +static DFBResult +savageSecondaryTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + SVGDBG("savageSecondaryTestRegion\n"); + + /* check for unsupported options */ + /* savage only supports one option at a time */ + switch (config->options) { + case DLOP_NONE: + case DLOP_ALPHACHANNEL: + case DLOP_SRC_COLORKEY: + case DLOP_DST_COLORKEY: + case DLOP_OPACITY: + break; + default: + fail |= CLRCF_OPTIONS; + break; + } + + /* check pixel format */ + switch (config->format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + break; + default: + fail |= CLRCF_FORMAT; + } + + /* check width */ + if (config->width > 2048 || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 2048 || config->height < 1) + fail |= CLRCF_HEIGHT; + + switch (config->format) { + case DSPF_YUY2: + case DSPF_UYVY: + case DSPF_I420: + case DSPF_YV12: + /* secondary is in YUV format */ + if (config->dest.w < (config->source.w / 2)) + fail |= CLRCF_SOURCE | CLRCF_DEST; + if (config->dest.h < (config->source.h / 32)) + fail |= CLRCF_SOURCE | CLRCF_DEST; + break; + default: + /* secondary is in RGB format */ + if (config->dest.w < config->source.w) + fail |= CLRCF_SOURCE | CLRCF_DEST; + if (config->dest.h < config->source.h) + fail |= CLRCF_SOURCE | CLRCF_DEST; + break; + } + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +savageSecondarySetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + SavageSecondaryLayerData *slay = (SavageSecondaryLayerData*) layer_data; + + SVGDBG("savageSecondarySetConfiguration w:%i h:%i bpp:%i\n", + config->width, config->height, + DFB_BYTES_PER_PIXEL(config->pixelformat) * 8); + + /* remember configuration */ + slay->config = *config; + + switch (config->options & (DLOP_SRC_COLORKEY | DLOP_DST_COLORKEY)) { + case DLOP_SRC_COLORKEY: + savage_secondary_calc_colorkey(sdrv, slay, config, &config->src_key, + config->format); + break; + case DLOP_DST_COLORKEY: + savage_secondary_calc_colorkey(sdrv, slay, config, &config->dst_key, + dfb_primary_layer_pixelformat()); + break; + default: + slay->regs.CHROMA_KEY_CONTROL = 0; + slay->regs.CHROMA_KEY_UPPER_BOUND = 0; + break; + } + + secondary_calc_regs(sdrv, slay, layer, config, surface, lock); + + secondary_set_regs(sdrv, slay); + + return DFB_OK; +} + +static void +savage_secondary_calc_opacity( SavageDriverData *sdrv, + SavageSecondaryLayerData *slay, + CoreLayerRegionConfig *config ) +{ + u8 opacity = config->opacity; + + switch (opacity) { + case 0: + /* put primary stream on top of secondary stream */ + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_PSTREAM; + break; + case 0xFF: + /* put secondary stream on top of primary stream */ + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_SSTREAM; + break; + default: + /* reverse opacity */ + opacity = 7 - (opacity >> 5); + + /* for some reason opacity can not be zero */ + if (opacity == 0) + opacity = 1; + + /* dissolve primary and secondary stream */ + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_DISSOLVE | KP_KS(opacity,0); + break; + } +} + +static DFBResult +savage_secondary_calc_colorkey( SavageDriverData *sdrv, + SavageSecondaryLayerData *slay, + CoreLayerRegionConfig *config, + const DFBColorKey *key, + DFBSurfacePixelFormat format ) +{ + u32 reg; + + switch (format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + reg = 0x14000000; + break; + case DSPF_RGB24: + case DSPF_RGB32: + reg = 0x17000000; + break; + default: + return DFB_UNSUPPORTED; + } + + slay->regs.CHROMA_KEY_CONTROL = reg | (key->r << 16) | (key->g << 8) | (key->b); + slay->regs.CHROMA_KEY_UPPER_BOUND = 0x00000000 | (key->r << 16) | (key->g << 8) | (key->b); + + return DFB_OK; +} + + +static DFBResult +savageSecondaryFlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + SavageSecondaryLayerData *slay = (SavageSecondaryLayerData*) layer_data; + + SVGDBG("savageSecondaryFlipRegion\n"); + + dfb_surface_flip( surface, false ); + + secondary_calc_regs(sdrv, slay, layer, &slay->config, surface, lock); + secondary_set_regs(sdrv, slay); + + if (flags & DSFLIP_WAIT) + dfb_screen_wait_vsync( dfb_screens_at( DSCID_PRIMARY ) ); + + return DFB_OK; +} + + +static DFBResult +savageSecondarySetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + SavageSecondaryLayerData *slay = (SavageSecondaryLayerData*) layer_data; + volatile u8 *mmio = sdrv->mmio_base; + + SVGDBG("savageSecondaryColorAdjustment b:%i c:%i h:%i s:%i\n", + adj->brightness, adj->contrast, adj->hue, adj->saturation); + + if ((slay->regs.SSTREAM_FB_SIZE & 0x00400000) == 0) { + /* secondary is in YUV format */ + u32 reg; + long sat = adj->saturation * 16 / 65536; + double hue = (adj->hue - 0x8000) * 3.141592654 / 32768.0; + unsigned char hs1 = ((char)(sat * cos(hue))) & 0x1f; + unsigned char hs2 = ((char)(sat * sin(hue))) & 0x1f; + + reg = 0x80008000 | (adj->brightness >> 8) | + ((adj->contrast & 0xf800) >> 3) | (hs1 << 16) | (hs2 << 24); + + savage_out32(mmio, SAVAGE_COLOR_ADJUSTMENT, reg); + + return DFB_OK; + } + else { + /* secondary is in RGB format */ + return DFB_UNSUPPORTED; + } +} + +DisplayLayerFuncs savageSecondaryFuncs = { + .LayerDataSize = savageSecondaryLayerDataSize, + .InitLayer = savageSecondaryInitLayer, + .RemoveRegion = savageSecondaryRemoveRegion, + .TestRegion = savageSecondaryTestRegion, + .SetRegion = savageSecondarySetRegion, + .FlipRegion = savageSecondaryFlipRegion, + .SetColorAdjustment = savageSecondarySetColorAdjustment, +}; + +/* secondary internal */ +static void +secondary_set_regs(SavageDriverData *sdrv, SavageSecondaryLayerData *slay) +{ + volatile u8 *mmio = sdrv->mmio_base; + + SVGDBG("secondary_set_regs\n"); + + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_CONTROL, + slay->regs.SSTREAM_CTRL); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_HORIZONTAL_SCALING, + slay->regs.SSTREAM_H_SCALE); + savage_out32(mmio, SAVAGE_BLEND_CONTROL, + slay->regs.BLEND_CTRL); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_MULTIPLE_BUFFER_SUPPORT, + slay->regs.SSTREAM_MULTIBUF); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS0, + slay->regs.SSTREAM_FB_ADDR0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS1, + slay->regs.SSTREAM_FB_ADDR1); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS2, + slay->regs.SSTREAM_FB_ADDR2); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_SIZE, + slay->regs.SSTREAM_FB_SIZE); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_STRIDE, + slay->regs.SSTREAM_STRIDE); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_VERTICAL_SCALING, + slay->regs.SSTREAM_V_SCALE); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_SOURCE_LINE_COUNT, + slay->regs.SSTREAM_SRC_LINE_COUNT); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_VERTICAL_INITIAL_VALUE, + slay->regs.SSTREAM_V_INIT_VALUE); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_WINDOW_START, + slay->regs.SSTREAM_WIN_START); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_WINDOW_SIZE, + slay->regs.SSTREAM_WIN_SIZE); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FB_CB_ADDRESS, + slay->regs.SSTREAM_FB_CB_ADDR); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FB_CR_ADDRESS, + slay->regs.SSTREAM_FB_CR_ADDR); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_CBCR_STRIDE, + slay->regs.SSTREAM_CBCR_STRIDE); + + savage_out32(mmio, SAVAGE_CHROMA_KEY_CONTROL, + slay->regs.CHROMA_KEY_CONTROL); + savage_out32(mmio, SAVAGE_CHROMA_KEY_UPPER_BOUND, + slay->regs.CHROMA_KEY_UPPER_BOUND); + + /* Set FIFO L2 on second stream. */ + { + int pitch = slay->video_pitch; + unsigned char cr92; + + SVGDBG("FIFO L2 pitch:%i\n", pitch); + pitch = (pitch + 7) / 8; + vga_out8(mmio, 0x3d4, 0x92); + cr92 = vga_in8( mmio, 0x3d5); + vga_out8(mmio, 0x3d5, (cr92 & 0x40) | (pitch >> 8) | 0x80); + vga_out8(mmio, 0x3d4, 0x93); + vga_out8(mmio, 0x3d5, pitch); + } +} + +static void +secondary_calc_regs(SavageDriverData *sdrv, + SavageSecondaryLayerData *slay, + CoreLayer *layer, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock) +{ + DFBRectangle *source = &config->source; + DFBRectangle *dest = &config->dest; + + /* source size */ + const int src_w = source->w; + const int src_h = source->h; + /* destination size */ + const int drw_w = dest->w; + const int drw_h = dest->h; + + SVGDBG("secondary_calc_regs x:%i y:%i w:%i h:%i\n", + dest->x, dest->y, dest->w, dest->h); + SVGDBG("w:%i h:%i pitch:%i video.offset:%x\n", + source->w, source->h, lock->pitch, lock->offset); + + slay->video_pitch = 1; + slay->regs.SSTREAM_FB_SIZE = (((lock->pitch * + surface->config.size.h) / 8) - 1) & 0x003fffff; + + switch (surface->config.format) { + case DSPF_ARGB1555: + SVGDBG("secondary set to DSPF_ARGB1555\n"); + slay->regs.SSTREAM_FB_SIZE |= 0x00400000; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_KRGB16; + break; + case DSPF_RGB16: + SVGDBG("secondary set to DSPF_RGB16\n"); + slay->regs.SSTREAM_FB_SIZE |= 0x00400000; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB16; + break; + case DSPF_RGB24: + SVGDBG("secondary set to DSPF_RGB24\n"); + slay->regs.SSTREAM_FB_SIZE |= 0x00400000; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB24; + break; + case DSPF_RGB32: + SVGDBG("secondary set to DSPF_RGB32\n"); + slay->regs.SSTREAM_FB_SIZE |= 0x00400000; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB32; + break; + case DSPF_YUY2: + SVGDBG("secondary set to DSPF_YUY2\n"); + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YCbCr422; + break; + case DSPF_UYVY: + SVGDBG("secondary set to DSPF_UYVY\n"); + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_CbYCrY422; + break; + case DSPF_I420: + SVGDBG("secondary set to DSPF_I420\n"); + slay->video_pitch = 2; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YCbCr420; + slay->regs.SSTREAM_FB_CB_ADDR = lock->offset + + (surface->config.size.h * lock->pitch); + slay->regs.SSTREAM_FB_CR_ADDR = slay->regs.SSTREAM_FB_CB_ADDR + + ((surface->config.size.h * lock->pitch)/4); + slay->regs.SSTREAM_CBCR_STRIDE = ((lock->pitch/2) + & 0x00001fff); + break; + case DSPF_YV12: + SVGDBG("secondary set to DSPF_YV12\n"); + slay->video_pitch = 2; + slay->regs.SSTREAM_CTRL = SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YCbCr420; + slay->regs.SSTREAM_FB_CR_ADDR = lock->offset + + surface->config.size.h * lock->pitch; + slay->regs.SSTREAM_FB_CB_ADDR = slay->regs.SSTREAM_FB_CR_ADDR + + (surface->config.size.h * lock->pitch)/4; + slay->regs.SSTREAM_CBCR_STRIDE = ((lock->pitch/2) + & 0x00001fff); + break; + default: + D_BUG("unexpected secondary pixelformat"); + return; + } + + slay->regs.SSTREAM_CTRL |= src_w; + + switch (config->options) { + case DLOP_ALPHACHANNEL: + SVGDBG("secondary option DLOP_ALPHACHANNEL\n"); + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_ALPHA; + break; + case DLOP_SRC_COLORKEY: + SVGDBG("secondary option DLOP_SRC_COLORKEY\n"); + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_SCOLORKEY; + break; + case DLOP_DST_COLORKEY: + SVGDBG("secondary option DLOP_DST_COLORKEY\n"); + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_PCOLORKEY; + break; + case DLOP_OPACITY: + SVGDBG("secondary option DLOP_OPACITY\n"); + savage_secondary_calc_opacity( sdrv, slay, config ); + break; + case DLOP_NONE: + SVGDBG("secondary option default\n"); + slay->regs.BLEND_CTRL = SAVAGE_BLEND_CONTROL_COMP_SSTREAM; + break; + default: + D_BUG("unexcpected layer option"); + } + + slay->regs.SSTREAM_H_SCALE = ((32768 * src_w) / drw_w) & 0x0000FFFF; + slay->regs.SSTREAM_V_SCALE = ((32768 * src_h) / drw_h) & 0x000FFFFF; + slay->regs.SSTREAM_V_INIT_VALUE = 0; + slay->regs.SSTREAM_SRC_LINE_COUNT = src_h & 0x7ff; + slay->regs.SSTREAM_MULTIBUF = 0; + slay->regs.SSTREAM_FB_ADDR0 = lock->offset & 0x01ffffff; + slay->regs.SSTREAM_FB_ADDR1 = 0; + slay->regs.SSTREAM_FB_ADDR2 = 0; + slay->regs.SSTREAM_STRIDE = lock->pitch & 0x00001fff; + slay->regs.SSTREAM_WIN_START = OS_XY(dest->x, dest->y); + slay->regs.SSTREAM_WIN_SIZE = OS_WH(drw_w, drw_h); + + /* remember pitch */ + slay->video_pitch *= lock->pitch; +} + +/* primary layer functions */ +static int +savagePrimaryLayerDataSize( void ) +{ + SVGDBG("savagePrimaryLayerDataSize\n"); + return sizeof(SavagePrimaryLayerData); +} + +static DFBResult +savagePrimaryInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *default_config, + DFBColorAdjustment *default_adj ) +{ + SavagePrimaryLayerData *play = (SavagePrimaryLayerData*) layer_data; + DFBResult ret; + + SVGDBG("savagePrimaryInitLayer w:%i h:%i bpp:%i\n", + dfb_config->mode.width, dfb_config->mode.height, + dfb_config->mode.depth); + + /* call the original initialization function first */ + ret = savage_pfuncs.InitLayer (layer, driver_data, layer_data, + description, default_config, default_adj); + if (ret) + return ret; + + /* set name */ + snprintf(description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, + "Savage Primary Stream"); + + /* add support for options */ + default_config->flags |= DLCONF_OPTIONS; + default_config->options = DLOP_NONE; + + /* add capabilities */ + description->caps |= DLCAPS_SCREEN_LOCATION; + + play->init = false; + + return DFB_OK; +} + +static DFBResult +savagePrimarySetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + SavageDriverData *sdrv = (SavageDriverData*) driver_data; + SavagePrimaryLayerData *play = (SavagePrimaryLayerData*) layer_data; + DFBResult ret; + + SVGDBG("savagePrimarySetConfiguration w:%i h:%i bpp:%i\n", + config->width, config->height, + DFB_BYTES_PER_PIXEL(config->format) * 8); + + ret = savage_pfuncs.SetRegion(layer, driver_data, layer_data, region_data, + config, updated, surface, palette, lock); + if (ret != DFB_OK) + return ret; + + /* remember configuration */ + play->config = *config; + play->lock = lock; + + primary_calc_regs(sdrv, play, layer, config, surface, lock); + primary_set_regs(sdrv, play); + + return DFB_OK; +} + +DisplayLayerFuncs savagePrimaryFuncs = { + .LayerDataSize = savagePrimaryLayerDataSize, + .InitLayer = savagePrimaryInitLayer, + .SetRegion = savagePrimarySetRegion, +}; + +/* primary internal */ +static void +primary_set_regs(SavageDriverData *sdrv, SavagePrimaryLayerData *play) +{ + volatile u8 *mmio = sdrv->mmio_base; + + SVGDBG("primary_set_regs\n"); + + /* turn streams on */ + streamOnOff(sdrv, 1); + + /* setup primary stream */ + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_WINDOW_START, + play->regs.PSTREAM_WIN_START); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_WINDOW_SIZE, + play->regs.PSTREAM_WIN_SIZE); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_ADDRESS0, + play->regs.PSTREAM_FB_ADDR0); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_ADDRESS1, + play->regs.PSTREAM_FB_ADDR1); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_STRIDE, + play->regs.PSTREAM_STRIDE); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_CONTROL, + play->regs.PSTREAM_CTRL); + savage_out32(mmio, SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_SIZE, + play->regs.PSTREAM_FB_SIZE); + + if (!play->init) { + /* tweak */ + /* fifo fetch delay register */ + vga_out8( mmio, 0x3d4, 0x85 ); + SVGDBG( "cr85: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + vga_out8( mmio, 0x3d5, 0x00 ); + + /* force high priority for display channel memory */ + vga_out8( mmio, 0x3d4, 0x88 ); + SVGDBG( "cr88: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + vga_out8( mmio, 0x3d5, vga_in8( mmio, 0x3d5 ) & ~0x01 ); + + /* primary stream timeout register */ + vga_out8( mmio, 0x3d4, 0x71 ); + SVGDBG( "cr71: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + + /* secondary stream timeout register */ + vga_out8( mmio, 0x3d4, 0x73 ); + SVGDBG( "cr73: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + + /* set primary stream to use memory mapped io */ + vga_out8( mmio, 0x3d4, 0x69 ); + SVGDBG( "cr69: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + vga_out8( mmio, 0x3d5, vga_in8( mmio, 0x3d5 ) | 0x80 ); + + /* enable certain registers to be loaded on vsync */ + vga_out8( mmio, 0x3d4, 0x51 ); + SVGDBG( "cr51: 0x%02x\n", vga_in8( mmio, 0x3d5 ) ); + vga_out8( mmio, 0x3d5, vga_in8( mmio, 0x3d5 ) | 0x80 ); + + /* setup secondary stream */ + savage_out32(mmio, SAVAGE_CHROMA_KEY_CONTROL, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_CONTROL, 0); + savage_out32(mmio, SAVAGE_CHROMA_KEY_UPPER_BOUND, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_HORIZONTAL_SCALING, 0); + savage_out32(mmio, SAVAGE_COLOR_ADJUSTMENT, 0); + savage_out32(mmio, SAVAGE_BLEND_CONTROL, 1 << 24); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_MULTIPLE_BUFFER_SUPPORT, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS0, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS1, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS2, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_SIZE, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_STRIDE, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_VERTICAL_SCALING, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_SOURCE_LINE_COUNT, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_VERTICAL_INITIAL_VALUE, 0); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_WINDOW_START, + OS_XY(0xfffe, 0xfffe)); + savage_out32(mmio, SAVAGE_SECONDARY_STREAM_WINDOW_SIZE, + OS_WH(10,2)); + + play->init = true; + } +} + +static void +primary_calc_regs(SavageDriverData *sdrv, + SavagePrimaryLayerData *play, + CoreLayer *layer, + CoreLayerRegionConfig *config, + CoreSurface *surface, + CoreSurfaceBufferLock *lock) +{ + DFBRectangle *dest = &config->dest; + + SVGDBG("primary_calc_regs w:%i h:%i pitch:%i video.offset:%x\n", + surface->config.size.w, surface->config.size.h, lock->pitch, lock->offset); + + switch (surface->config.format) { + case DSPF_ARGB1555: + SVGDBG("primary set to DSPF_ARGB1555\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_KRGB16; + break; + case DSPF_RGB16: + SVGDBG("primary set to DSPF_RGB16\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB16; + break; + case DSPF_RGB24: + SVGDBG("primary set to DSPF_RGB24 (unaccelerated)\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB24; + break; + case DSPF_RGB32: + SVGDBG("primary set to DSPF_RGB32\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB32; + break; + case DSPF_ARGB: + SVGDBG("primary set to DSPF_ARGB\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_ARGB; + break; + case DSPF_RGB332: + SVGDBG("primary set to DSPF_RGB332\n"); + play->regs.PSTREAM_CTRL = SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_CLUT; + break; + default: + D_BUG("unexpected primary pixelformat"); + return; + } + + play->regs.PSTREAM_FB_ADDR0 = lock->offset & 0x01ffffff; + play->regs.PSTREAM_FB_ADDR1 = 0; + play->regs.PSTREAM_STRIDE = lock->pitch & 0x00001fff; + play->regs.PSTREAM_WIN_START = OS_XY(dest->x, dest->y); + play->regs.PSTREAM_WIN_SIZE = OS_WH(dest->w, dest->h); + play->regs.PSTREAM_FB_SIZE = (((lock->pitch * + surface->config.size.h) / 8) - 1) & 0x003fffff; +} +/* end of code */ diff --git a/Source/DirectFB/gfxdrivers/savage/savage_streams_old.h b/Source/DirectFB/gfxdrivers/savage/savage_streams_old.h new file mode 100755 index 0000000..e58cfb8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/savage/savage_streams_old.h @@ -0,0 +1,142 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __SAVAGE_STREAMS_OLD_H__ +#define __SAVAGE_STREAMS_OLD_H__ + +#include "savage.h" +#include + +extern DisplayLayerFuncs savageSecondaryFuncs; +extern DisplayLayerFuncs savagePrimaryFuncs; +extern DisplayLayerFuncs savage_pfuncs; +extern void *savage_pdriver_data; + +/* Streams Processor Registers */ +#define SAVAGE_PRIMARY_STREAM_CONTROL 0x8180 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_CLUT 0x00000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_ARGB 0x01000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_KRGB16 0x03000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB16 0x05000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB24 0x06000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSIDF_RGB32 0x07000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSFC_NOT_FILTERED 0x00000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSFC_REP_BOTH 0x10000000 +#define SAVAGE_PRIMARY_STREAM_CONTROL_PSFC_HOR_INTERPOLATE 0x20000000 + +#define SAVAGE_CHROMA_KEY_CONTROL 0x8184 + +#define SAVAGE_GENLOCK_CONTROL 0x8188 + +#define SAVAGE_SECONDARY_STREAM_CONTROL 0x8190 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_CbYCrY422 0x00000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YCbCr422 0x01000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YUV422 0x02000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_KRGB16 0x03000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_YCbCr420 0x04000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB16 0x05000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB24 0x06000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_SSIDF_RGB32 0x07000000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_H_DOWNSCALE4 0x00020000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_H_DOWNSCALE8 0x00030000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_H_DOWNSCALE16 0x00040000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_H_DOWNSCALE32 0x00050000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_H_DOWNSCALE64 0x00060000 +#define SAVAGE_SECONDARY_STREAM_CONTROL_LUMA_ONLY_INTERPOL 0x80000000 + +#define SAVAGE_CHROMA_KEY_UPPER_BOUND 0x8194 + +#define SAVAGE_SECONDARY_STREAM_HORIZONTAL_SCALING 0x8198 + +#define SAVAGE_COLOR_ADJUSTMENT 0x819C + +#define SAVAGE_BLEND_CONTROL 0x81a0 +#define SAVAGE_BLEND_CONTROL_COMP_SSTREAM 0x00000000 +#define SAVAGE_BLEND_CONTROL_COMP_PSTREAM 0x01000000 +#define SAVAGE_BLEND_CONTROL_COMP_DISSOLVE 0x02000000 +#define SAVAGE_BLEND_CONTROL_COMP_FADE 0x03000000 +#define SAVAGE_BLEND_CONTROL_COMP_ALPHA 0x04000000 +#define SAVAGE_BLEND_CONTROL_COMP_PCOLORKEY 0x05000000 +#define SAVAGE_BLEND_CONTROL_COMP_SCOLORKEY 0x06000000 +#define KP_KS(kp,ks) ((kp<<10)|(ks<<2)) + +#define SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_ADDRESS0 0x81c0 + +#define SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_ADDRESS1 0x81c4 + +#define SAVAGE_PRIMARY_STREAM_STRIDE 0x81c8 + +#define SAVAGE_SECONDARY_STREAM_MULTIPLE_BUFFER_SUPPORT 0x81cc + +#define SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS0 0x81d0 + +#define SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS1 0x81d4 + +#define SAVAGE_SECONDARY_STREAM_STRIDE 0x81d8 + +#define SAVAGE_SECONDARY_STREAM_VERTICAL_SCALING 0x81e0 + +#define SAVAGE_SECONDARY_STREAM_VERTICAL_INITIAL_VALUE 0x81e4 + +#define SAVAGE_SECONDARY_STREAM_SOURCE_LINE_COUNT 0x81e8 + +#define SAVAGE_STREAMS_FIFO 0x81ec + +#define SAVAGE_PRIMARY_STREAM_WINDOW_START 0x81f0 + +#define SAVAGE_PRIMARY_STREAM_WINDOW_SIZE 0x81f4 + +#define SAVAGE_SECONDARY_STREAM_WINDOW_START 0x81f8 + +#define SAVAGE_SECONDARY_STREAM_WINDOW_SIZE 0x81fc + +#define SAVAGE_PRIMARY_STREAM_FIFO_MONITOR0 0x8200 + +#define SAVAGE_SECONDARY_STREAM_FIFO_MONITOR0 0x8204 + +#define SAVAGE_SECONDARY_STREAM_FB_CB_ADDRESS 0x8208 + +#define SAVAGE_SECONDARY_STREAM_FB_CR_ADDRESS 0x820C + +#define SAVAGE_PRIMARY_STREAM_FIFO_MONITOR1 0x8210 + +#define SAVAGE_SECONDARY_STREAM_FIFO_MONITOR1 0x8214 + +#define SAVAGE_SECONDARY_STREAM_CBCR_STRIDE 0x8218 + +#define SAVAGE_PRIMARY_STREAM_FRAME_BUFFER_SIZE 0x8300 + +#define SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_SIZE 0x8304 + +#define SAVAGE_SECONDARY_STREAM_FRAME_BUFFER_ADDRESS2 0x8308 + +/* macros */ +#define OS_XY(x,y) (((x+1)<<16)|(y+1)) +#define OS_WH(x,y) (((x-1)<<16)|(y)) + +#endif /* __SAVAGE_STREAMS_OLD_H__ */ diff --git a/Source/DirectFB/gfxdrivers/sh772x/Makefile.am b/Source/DirectFB/gfxdrivers/sh772x/Makefile.am new file mode 100755 index 0000000..462aa03 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/Makefile.am @@ -0,0 +1,80 @@ +## Makefile.am for DirectFB/src/core/gfxcards/sh7722 + +EXTRA_DIST = \ + directfbrc.sh7722 \ + directfbrc.sh7723 \ + Makefile.kernel \ + README.sh7722 \ + kernel-module/sh772x_driver.c \ + kernel-module/sh772x_gfx.h \ + kernel-module/sh7722.c \ + kernel-module/sh7722.h \ + kernel-module/sh7723.c \ + kernel-module/sh7723.h \ + kernel-module/Makefile + +INCLUDES = \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems \ + -I$(srcdir)/kernel-module + + +lib_LTLIBRARIES = libsh7722_jpeg.la + +libsh7722_jpeg_la_SOURCES = \ + sh7722_jpeglib.c \ + sh7722_jpeglib.h + + +bin_PROGRAMS = sh7722_jpegtool + +sh7722_jpegtool_SOURCES = \ + sh7722_jpegtool.c + +sh7722_jpegtool_LDADD = \ + $(top_builddir)/src/libdirectfb.la \ + libsh7722_jpeg.la + + +sh7722_LTLIBRARIES = libdirectfb_sh7722.la + +if BUILD_STATIC +sh7722_DATA = $(sh7722_LTLIBRARIES:.la=.o) +endif + +sh7722dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_sh7722_la_SOURCES = \ + sh7722.c \ + sh7722.h \ + sh7722_blt.c \ + sh7722_blt.h \ + sh7723_blt.c \ + sh7723_blt.h \ + sh7722_jpeg.c \ + sh7722_layer.c \ + sh7722_layer.h \ + sh7722_lcd.c \ + sh7722_lcd.h \ + sh7722_multi.c \ + sh7722_multi.h \ + sh7722_regs.h \ + sh7722_screen.c \ + sh7722_screen.h \ + sh7722_types.h + +libdirectfb_sh7722_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_sh7722_la_LIBADD = \ + $(top_builddir)/src/libdirectfb.la \ + libsh7722_jpeg.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/sh772x/Makefile.in b/Source/DirectFB/gfxdrivers/sh772x/Makefile.in new file mode 100755 index 0000000..a2fcc20 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/Makefile.in @@ -0,0 +1,726 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +bin_PROGRAMS = sh7722_jpegtool$(EXEEXT) +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/sh772x +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(libdir)" "$(DESTDIR)$(sh7722dir)" \ + "$(DESTDIR)$(bindir)" "$(DESTDIR)$(sh7722dir)" +libLTLIBRARIES_INSTALL = $(INSTALL) +sh7722LTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(lib_LTLIBRARIES) $(sh7722_LTLIBRARIES) +libdirectfb_sh7722_la_DEPENDENCIES = \ + $(top_builddir)/src/libdirectfb.la libsh7722_jpeg.la +am_libdirectfb_sh7722_la_OBJECTS = sh7722.lo sh7722_blt.lo \ + sh7723_blt.lo sh7722_jpeg.lo sh7722_layer.lo sh7722_lcd.lo \ + sh7722_multi.lo sh7722_screen.lo +libdirectfb_sh7722_la_OBJECTS = $(am_libdirectfb_sh7722_la_OBJECTS) +libdirectfb_sh7722_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_sh7722_la_LDFLAGS) $(LDFLAGS) -o $@ +libsh7722_jpeg_la_LIBADD = +am_libsh7722_jpeg_la_OBJECTS = sh7722_jpeglib.lo +libsh7722_jpeg_la_OBJECTS = $(am_libsh7722_jpeg_la_OBJECTS) +binPROGRAMS_INSTALL = $(INSTALL_PROGRAM) +PROGRAMS = $(bin_PROGRAMS) +am_sh7722_jpegtool_OBJECTS = sh7722_jpegtool.$(OBJEXT) +sh7722_jpegtool_OBJECTS = $(am_sh7722_jpegtool_OBJECTS) +sh7722_jpegtool_DEPENDENCIES = $(top_builddir)/src/libdirectfb.la \ + libsh7722_jpeg.la +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_sh7722_la_SOURCES) \ + $(libsh7722_jpeg_la_SOURCES) $(sh7722_jpegtool_SOURCES) +DIST_SOURCES = $(libdirectfb_sh7722_la_SOURCES) \ + $(libsh7722_jpeg_la_SOURCES) $(sh7722_jpegtool_SOURCES) +sh7722DATA_INSTALL = $(INSTALL_DATA) +DATA = $(sh7722_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = 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clean-sh7722LTLIBRARIES ctags distclean distclean-compile \ + distclean-generic distclean-libtool distclean-tags distdir dvi \ + dvi-am html html-am info info-am install install-am \ + install-binPROGRAMS install-data install-data-am install-dvi \ + install-dvi-am install-exec install-exec-am install-html \ + install-html-am install-info install-info-am \ + install-libLTLIBRARIES install-man install-pdf install-pdf-am \ + install-ps install-ps-am install-sh7722DATA \ + install-sh7722LTLIBRARIES install-strip installcheck \ + installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-binPROGRAMS \ + uninstall-libLTLIBRARIES uninstall-sh7722DATA \ + uninstall-sh7722LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/sh772x/Makefile.kernel b/Source/DirectFB/gfxdrivers/sh772x/Makefile.kernel new file mode 100755 index 0000000..8b6be07 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/Makefile.kernel @@ -0,0 +1,61 @@ +KERNEL_VERSION ?= $(shell uname -r) +KERNEL_MODLIB ?= /lib/modules/$(KERNEL_VERSION) +KERNEL_BUILD ?= $(SYSROOT)$(KERNEL_MODLIB)/build +KERNEL_SOURCE ?= $(SYSROOT)$(KERNEL_MODLIB)/source + +ifeq ($(shell test -L $(KERNEL_BUILD) && echo yes),yes) + KERNEL_BUILD := $(SYSROOT)$(shell readlink $(KERNEL_BUILD)) +endif + +ifeq ($(shell test -L $(KERNEL_SOURCE) && echo yes),yes) + KERNEL_SOURCE := $(SYSROOT)$(shell readlink $(KERNEL_SOURCE)) +endif + +K_VERSION := $(shell echo $(KERNEL_VERSION) | cut -d . -f 1) +K_PATCHLEVEL := $(shell echo $(KERNEL_VERSION) | cut -d . -f 2) +K_SUBLEVEL := $(shell echo $(KERNEL_VERSION) | cut -d . -f 3 | cut -d '-' -f 1) + + +DESTDIR ?= $(SYSROOT) + + +ifeq ($(DEBUG_2DG),yes) + CPPFLAGS += -DSH7722GFX_DEBUG_2DG +endif + +ifeq ($(DEBUG_JPU),yes) + CPPFLAGS += -DSH7722GFX_DEBUG_JPU +endif + +ifeq ($(shell test -e $(KERNEL_BUILD)/include/linux/autoconf.h && echo yes),yes) + AUTOCONF_H = -include $(KERNEL_BUILD)/include/linux/autoconf.h +endif + +ifeq ($(shell test -e $(KERNEL_BUILD)/include/linux/config.h && echo yes),yes) + CPPFLAGS += -DHAVE_LINUX_CONFIG_H +endif + +check-version = $(shell expr \( $(K_VERSION) \* 65536 + $(K_PATCHLEVEL) \* 256 + $(K_SUBLEVEL) \) \>= \( $(1) \* 65536 + $(2) \* 256 + $(3) \)) + +.PHONY: all install clean + +all: +ifeq ($(call check-version,2,6,24),1) + $(MAKE) -C $(KERNEL_BUILD) \ + KCPPFLAGS="$(CPPFLAGS) -I`pwd`/kernel-module" \ + SUBDIRS="`pwd`/kernel-module" modules +else + $(MAKE) -C $(KERNEL_BUILD) \ + CPPFLAGS="$(CPPFLAGS) -D__KERNEL__ -I`pwd`/kernel-module -I$(KERNEL_BUILD)/include -I$(KERNEL_SOURCE)/include $(AUTOCONF_H)" \ + SUBDIRS="`pwd`/kernel-module" modules +endif + +clean: + rm -rf kernel-module/*.*o kernel-module/.*.*o* kernel-module/*.mod.c kernel-module/.tmp_versions + +install: all + install -v -m 0755 -d $(DESTDIR)/lib/modules/$(KERNEL_VERSION)/renesas + install -v -m 0644 kernel-module/sh772x_gfx.ko $(DESTDIR)/lib/modules/$(KERNEL_VERSION)/renesas/ + + +.PHONY: all clean diff --git a/Source/DirectFB/gfxdrivers/sh772x/README.sh7722 b/Source/DirectFB/gfxdrivers/sh772x/README.sh7722 new file mode 100755 index 0000000..45bbf87 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/README.sh7722 @@ -0,0 +1,172 @@ +Renesas SH7722 graphics driver +============================== + +This driver supports the SH7722 SoC from Renesas Solutions Corp. controlling +- LCDC (LCD Controller) for display +- BEU (Blit Engine Unit) for blending of planes +- TDG (2D Graphics) for accelerated operations + +It's using a kernel device called sh7722gfx which mainly does interrupt handling. + +The 2D Graphics unit supports display lists in RAM and reads them via DMA. These +lists consist of double word entries, first word designates a register, second +word contains the data to write. Once a list has been completely processed, the +hardware generates an interrupt to start the next list. + +The kernel module allocates a ring buffer for usage as a display list. The user +space prepares a block of commands and puts it into the ring buffer. If the hardware +is idle, it's started directly from user space. When a DMA completion interrupt +is received, the next block of commands is started from kernel space. If the +hardware is still running the previous block, new commands are appended to the +next one. The driver is designed to run without any locking or system calls. Only +a few interrupts happen over time depending on the operations. The hardware is not +getting idle, while commands are being sent to keep it busy. There's just a minimal +gap which is the interrupt handler setting the new start address and kicking the +hardware again. + +To build the kernel module use "make -f Makefile.kernel". You might want to set +the variables KERNEL_SOURCE, KERNEL_BUILD (if != KERNEL_SOURCE), KERNEL_VERSION +and DESTDIR. + +To run the driver you need the DevMem system module using the directfbrc.sh7722 +file (renamed to directfbrc in $prefix/etc). + + +Performance (as of 2007-09-21, multi app, 127.79 BogoMIPS) +---------------------------------------------------------- + +Only 14% CPU load with df_andi running 800x480 at 28.1 fps :) + +Benchmarking with 256x256 in 16bit mode... (16bit) + CPU load +Anti-aliased Text 3.020 secs ( 41.721 KChars/sec) [100%] +Anti-aliased Text (blend) 3.328 secs ( 10.817 KChars/sec) [100%] +Fill Rectangle 5.549 secs (* 69.681 MPixel/sec) [ 3%] +Fill Rectangle (blend) 11.873 secs (* 22.079 MPixel/sec) [ 1%] +Fill Rectangles [10] 9.384 secs (* 69.838 MPixel/sec) [ 0%] +Fill Rectangles [10] (blend) 14.836 secs (* 22.086 MPixel/sec) [ 0%] +Fill Triangles 3.024 secs (+ 50.929 MPixel/sec) [ 40%] +Fill Triangles (blend) 3.064 secs (+ 20.319 MPixel/sec) [ 8%] +Draw Rectangle 3.284 secs (* 6.942 KRects/sec) [ 26%] +Draw Rectangle (blend) 3.302 secs (* 6.268 KRects/sec) [ 25%] +Draw Lines [10] 3.238 secs (* 28.103 KLines/sec) [ 20%] +Draw Lines [10] (blend) 3.198 secs (* 27.829 KLines/sec) [ 19%] +Fill Spans 3.092 secs (* 61.466 MPixel/sec) [ 33%] +Fill Spans (blend) 3.094 secs (* 21.181 MPixel/sec) [ 11%] +Blit 10.436 secs (* 30.143 MPixel/sec) [ 2%] +Blit colorkeyed 9.333 secs (* 32.301 MPixel/sec) [ 2%] +Blit destination colorkeyed 3.763 secs ( 6.966 MPixel/sec) [ 99%] +Blit with format conversion 13.369 secs (* 22.549 MPixel/sec) [ 1%] +Blit with colorizing 4.419 secs ( 2.966 MPixel/sec) [100%] +Blit from 32bit (blend) 21.973 secs (* 13.123 MPixel/sec) [ 1%] +Blit from 32bit (blend) with colorizing 5.129 secs ( 1.277 MPixel/sec) [100%] +Stretch Blit 10.271 secs (* 33.463 MPixel/sec) [ 3%] +Stretch Blit colorkeyed 7.895 secs (* 35.159 MPixel/sec) [ 3%] + +(*) SH7722/BLT: 940 starts, 940 done, 940 interrupts, 43 wait_idle, 780 wait_next, 89 idle +(*) SH7722/BLT: 24700744 words, 26277 words/start, 277536 words/idle, 10 starts/idle + +* = accelerated ++ = half way accelerated + + +Performance (as of 2007-09-25, multi app, 127.79 BogoMIPS) +---------------------------------------------------------- + +Only 13% CPU load with df_andi running 800x480 at 28.8 fps :) +Only 46% CPU load with ClanBomber2 running 800x600 at 48 fps :) + +Benchmarking with 256x256 in 16bit mode... (16bit) + CPU load +Anti-aliased Text 3.057 secs (* 98.920 KChars/sec) [ 47%] ! +Anti-aliased Text (blend) 3.298 secs ( 10.915 KChars/sec) [100%] +Fill Rectangle 5.732 secs (* 69.743 MPixel/sec) [ 3%] +Fill Rectangle (blend) 11.571 secs (* 22.088 MPixel/sec) [ 1%] +Fill Rectangles [10] 9.384 secs (* 69.838 MPixel/sec) [ 0%] +Fill Rectangles [10] (blend) 14.836 secs (* 22.086 MPixel/sec) [ 0%] +Fill Triangles 4.176 secs (* 61.989 MPixel/sec) [ 6%] ! +Fill Triangles (blend) 8.132 secs (* 21.759 MPixel/sec) [ 2%] ! +Draw Rectangle 3.216 secs (* 6.965 KRects/sec) [ 26%] +Draw Rectangle (blend) 3.290 secs (* 6.322 KRects/sec) [ 22%] +Draw Lines [10] 3.216 secs (* 28.296 KLines/sec) [ 14%] +Draw Lines [10] (blend) 3.196 secs (* 28.160 KLines/sec) [ 14%] +Fill Spans 3.086 secs (* 61.586 MPixel/sec) [ 25%] +Fill Spans (blend) 3.092 secs (* 21.195 MPixel/sec) [ 7%] +Blit 8.692 secs (* 30.159 MPixel/sec) [ 2%] +Blit 180 4.783 secs (* 30.144 MPixel/sec) [ 2%] ! +Blit colorkeyed 11.965 secs (* 32.316 MPixel/sec) [ 2%] +Blit destination colorkeyed 3.795 secs ( 6.907 MPixel/sec) [ 99%] +Blit with format conversion 9.039 secs (* 22.476 MPixel/sec) [ 1%] +Blit with colorizing 4.414 secs ( 2.969 MPixel/sec) [100%] +Blit from 32bit (blend) 23.375 secs (* 13.177 MPixel/sec) [ 1%] +Blit from 32bit (blend) with colorizing 5.137 secs ( 1.275 MPixel/sec) [100%] +Stretch Blit 8.976 secs (* 33.495 MPixel/sec) [ 2%] +Stretch Blit colorkeyed 9.728 secs (* 35.226 MPixel/sec) [ 2%] + +(*) SH7722/BLT: 521 starts, 521 done, 521 interrupts, 45 wait_idle, 363 wait_next, 90 idle +(*) SH7722/BLT: 11511104 words, 22094 words/start, 127901 words/idle, 5 starts/idle + +* = accelerated +! = updated + + +Statistics +---------- + +The statistics at the end are more valuable when looking at one case at a time: + +Fill Rectangle 5.834 secs (* 69.647 MPixel/sec) [ 4%] + +(*) SH7722/BLT: 16 starts, 16 done, 16 interrupts, 4 wait_idle, 2 wait_next, 11 idle +(*) SH7722/BLT: 74840 words, 4677 words/start, 6803 words/idle, 1 starts/idle + +This means that while the FillRectangle() benchmark was running, the hardware +didn't get idle, which is obvious when running the benchmark for just 10 ms: + +Fill Rectangle 0.191 secs (* 68.624 MPixel/sec) [ 10%] + +(*) SH7722/BLT: 13 starts, 13 done, 13 interrupts, 4 wait_idle, 0 wait_next, 11 idle +(*) SH7722/BLT: 2840 words, 218 words/start, 258 words/idle, 1 starts/idle + +See? The same number of times becoming idle, but a few less interrupts. Don't +worry about the 191 ms the benchmark needed to complete, after 10 ms of stuffing +the display list, we need to wait until the hardware is done before measuring +the time it took and calculating the result. + +Here's FillSpans() which as opposed to FillRectangle() does a lot of small commands: + +Fill Spans 3.028 secs (* 61.467 MPixel/sec) [ 34%] + +(*) SH7722/BLT: 245 starts, 245 done, 245 interrupts, 3 wait_idle, 185 wait_next, 22 idle +(*) SH7722/BLT: 5828128 words, 23788 words/start, 264914 words/idle, 11 starts/idle + + +Example kernel log (debug mode) +------------------------------- + +0.549.014 - sh7722_reset : Resetting hardware... +0.549.046 - sh7722_reset : Initializing shared area... +0.549.748 - sh7722_reset : Clearing interrupts... +0.549.770 - sh7722_reset : Ready ( idle, hw 0- 0, next 0- 0, invalid, HC 0000000, INT 000000) +0.568.700 - sh7722_wait : Waiting..... (running, hw 0- 54, next 56- 56, invalid, HC 1010111, INT 000000) +0.573.339 - sh7722_tdg_irq : -Interrupt (running, hw 0- 54, next 56- 56, invalid, HC 0000000, INT 100100) +0.573.397 - sh7722_tdg_irq : '-> Idle. (running, hw 0- 54, next 56- 56, invalid, HC 0000000, INT 000000) +0.573.480 - sh7722_wait : ........done ( idle, hw 0- 54, next 56- 56, invalid, HC 0000000, INT 000000) +0.583.575 - sh7722_wait : Waiting..... (running, hw 56- 78, next 80- 80, invalid, HC 1010111, INT 000000) +0.588.414 - sh7722_tdg_irq : -Interrupt (running, hw 56- 78, next 80- 80, invalid, HC 0000000, INT 100100) +0.588.470 - sh7722_tdg_irq : '-> Idle. (running, hw 56- 78, next 80- 80, invalid, HC 0000000, INT 000000) +0.588.544 - sh7722_wait : ........done ( idle, hw 56- 78, next 80- 80, invalid, HC 0000000, INT 000000) +0.601.336 - sh7722_tdg_irq : -Interrupt (running, hw 80- 102, next 104- 104, invalid, HC 0000000, INT 100100) +0.601.420 - sh7722_tdg_irq : '-> Idle. (running, hw 80- 102, next 104- 104, invalid, HC 0000000, INT 000000) +0.700.117 - sh7722_tdg_irq : -Interrupt (running, hw 104- 124, next 128- 128, invalid, HC 0000000, INT 100100) +0.700.205 - sh7722_tdg_irq : '-> Idle. (running, hw 104- 124, next 128- 128, invalid, HC 0000000, INT 000000) +3.115.419 - sh7722_tdg_irq : -Interrupt (running, hw 128- 220, next 224- 224, invalid, HC 0000000, INT 100100) +3.115.506 - sh7722_tdg_irq : '-> Idle. (running, hw 128- 220, next 224- 224, invalid, HC 0000000, INT 000000) +3.151.700 - sh7722_tdg_irq : -Interrupt (running, hw 224- 324, next 328- 328, invalid, HC 0000000, INT 100100) +3.151.788 - sh7722_tdg_irq : '-> Idle. (running, hw 224- 324, next 328- 328, invalid, HC 0000000, INT 000000) +3.159.160 - sh7722_wait : Waiting..... (running, hw 328- 444, next 448-12994, valid, HC 1010111, INT 000100) +3.161.783 - sh7722_tdg_irq : -Interrupt (running, hw 328- 444, next 448-12994, valid, HC 0000000, INT 100100) +3.161.839 - sh7722_tdg_irq : '-> Start! (running, hw 448-12994, next 12996-12996, invalid, HC 0000000, INT 000000) +4.316.367 - sh7722_tdg_irq : -Interrupt (running, hw 448-12994, next 12996-12996, invalid, HC 0000000, INT 100100) +4.316.434 - sh7722_tdg_irq : '-> Idle. (running, hw 448-12994, next 12996-12996, invalid, HC 0000000, INT 000000) +4.316.505 - sh7722_wait : ........done ( idle, hw 448-12994, next 12996-12996, invalid, HC 0000000, INT 000000) diff --git a/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7722 b/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7722 new file mode 100755 index 0000000..7417294 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7722 @@ -0,0 +1,10 @@ + +system = devmem + +video-phys = f800000 # Requires 'mem=120M' kernel option!!!!! +video-length = 8388608 # 8MB of physically contiguous memory for acceleration + +mmio-phys = fd000000 # Start of 2DG register space +mmio-length = 65536 # Size of register space + +accelerator = 11591 # 0x2D47 (2DG) diff --git a/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7723 b/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7723 new file mode 100755 index 0000000..b8cb009 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/directfbrc.sh7723 @@ -0,0 +1,10 @@ + +system = devmem + +video-phys = f800000 # Requires 'mem=120M' kernel option!!!!! +video-length = 8388608 # 8MB of physically contiguous memory for acceleration + +mmio-phys = a4680000 # Start of 2DG register space +mmio-length = 65536 # Size of register space + +accelerator = 11591 # 0x2D47 (2DG) diff --git a/Source/DirectFB/gfxdrivers/sh772x/kernel-module/Makefile b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/Makefile new file mode 100755 index 0000000..d054dd5 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/Makefile @@ -0,0 +1,3 @@ +obj-m += sh772x_gfx.o + +sh772x_gfx-y += sh772x_driver.o sh7722.o sh7723.o diff --git a/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7722.c b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7722.c new file mode 100755 index 0000000..981cf69 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7722.c @@ -0,0 +1,1192 @@ +/* + * SH7722 Graphics Device + * + * Copyright (C) 2006-2008 IGEL Co.,Ltd + * + * Written by Denis Oliver Kropp + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License v2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + + +//#define SH7722GFX_DEBUG_2DG +//#define SH7722GFX_DEBUG_JPU +//#define SH7722GFX_IRQ_POLLER + + +/**********************************************************************************************************************/ + +#ifndef SH7722_BEU_IRQ +#define SH7722_BEU_IRQ 53 +#endif + +#ifndef SH7722_VEU_IRQ +#define SH7722_VEU_IRQ 54 +#endif + +#ifndef SH7722_JPU_IRQ +#define SH7722_JPU_IRQ 27 +#endif + +#ifndef SH7722_TDG_IRQ +#define SH7722_TDG_IRQ 109 +#endif + +/**********************************************************************************************************************/ + +#define ENGINE_REG_TOP 0xFD000000 +#define SH7722_VEU_BASE 0xFE920000 +#define SH7722_BEU_BASE 0xFE930000 +#define SH7722_JPU_BASE 0xFEA00000 + +#define BEM_REG(x) (*(volatile u32*)((x)+ENGINE_REG_TOP)) +#define VEU_REG(x) (*(volatile u32*)((x)+SH7722_VEU_BASE)) +#define BEU_REG(x) (*(volatile u32*)((x)+SH7722_BEU_BASE)) +#define JPU_REG(x) (*(volatile u32*)((x)+SH7722_JPU_BASE)) + +#define BEM_HC_STATUS BEM_REG(0x00000) +#define BEM_HC_RESET BEM_REG(0x00004) +#define BEM_HC_CLOCK BEM_REG(0x00008) +#define BEM_HC_INT_STATUS BEM_REG(0x00020) +#define BEM_HC_INT_MASK BEM_REG(0x00024) +#define BEM_HC_INT_CLEAR BEM_REG(0x00028) +#define BEM_HC_CACHE_FLUSH BEM_REG(0x0002C) +#define BEM_HC_DMA_ADR BEM_REG(0x00040) +#define BEM_HC_DMA_START BEM_REG(0x00044) +#define BEM_HC_DMA_STOP BEM_REG(0x00048) +#define BEM_PE_CACHE BEM_REG(0x010B0) + +#define BEVTR BEU_REG(0x0018C) + +#define JPU_JCCMD JPU_REG(0x00004) +#define JPU_JCSTS JPU_REG(0x00008) +#define JPU_JINTE JPU_REG(0x00038) +#define JPU_JINTS JPU_REG(0x0003C) +#define JPU_JCDERR JPU_REG(0x00040) +#define JPU_JCRST JPU_REG(0x00044) +#define JPU_JIFDDVSZ JPU_REG(0x000B4) +#define JPU_JIFDDHSZ JPU_REG(0x000B8) +#define JPU_JIFDDYA1 JPU_REG(0x000BC) +#define JPU_JIFDDCA1 JPU_REG(0x000C0) +#define JPU_JIFDDYA2 JPU_REG(0x000C4) +#define JPU_JIFDDCA2 JPU_REG(0x000C8) +#define JPU_JIFESYA1 JPU_REG(0x00074) +#define JPU_JIFESCA1 JPU_REG(0x00078) +#define JPU_JIFESYA2 JPU_REG(0x0007C) +#define JPU_JIFESCA2 JPU_REG(0x00080) +#define JPU_JIFEDA1 JPU_REG(0x00090) +#define JPU_JIFEDA2 JPU_REG(0x00094) + +#define VEU_VESTR VEU_REG(0x00000) +#define VEU_VESWR VEU_REG(0x00010) +#define VEU_VESSR VEU_REG(0x00014) +#define VEU_VSAYR VEU_REG(0x00018) +#define VEU_VSACR VEU_REG(0x0001c) +#define VEU_VDAYR VEU_REG(0x00034) +#define VEU_VDACR VEU_REG(0x00038) +#define VEU_VTRCR VEU_REG(0x00050) +#define VEU_VRFSR VEU_REG(0x00058) +#define VEU_VEVTR VEU_REG(0x000A4) +#define VEU_VSTAR VEU_REG(0x000b0) + +#define JINTS_MASK 0x00007C68 +#define JINTS_INS3_HEADER 0x00000008 +#define JINTS_INS5_ERROR 0x00000020 +#define JINTS_INS6_DONE 0x00000040 +#define JINTS_INS10_XFER_DONE 0x00000400 +#define JINTS_INS11_LINEBUF0 0x00000800 +#define JINTS_INS12_LINEBUF1 0x00001000 +#define JINTS_INS13_LOADED 0x00002000 +#define JINTS_INS14_RELOAD 0x00004000 + +#define JCCMD_START 0x00000001 +#define JCCMD_RESTART 0x00000002 +#define JCCMD_END 0x00000004 +#define JCCMD_RESET 0x00000080 +#define JCCMD_LCMD2 0x00000100 +#define JCCMD_LCMD1 0x00000200 +#define JCCMD_READ_RESTART 0x00000400 +#define JCCMD_WRITE_RESTART 0x00000800 + +#define VTRCR_CHRR 0x0000C000 + +/**********************************************************************************************************************/ + +#ifdef SH7722GFX_DEBUG_2DG +#define QPRINT(x...) do { \ + char buf[128]; \ + struct timeval tv; \ + do_gettimeofday( &tv ); \ + snprintf( buf, sizeof(buf), x ); \ + printk( KERN_DEBUG "%ld.%03ld.%03ld - %-17s: %s\n", \ + tv.tv_sec - base_time.tv_sec, \ + tv.tv_usec / 1000, tv.tv_usec % 1000, __FUNCTION__, buf ); \ +} while (0) +#else +#define QPRINT(x...) do {} while (0) +#endif + +#define QDUMP(msg) QPRINT( "%-12s (%s, hw %5d-%5d, next %5d-%5d, %svalid, " \ + "HC %07x, INT %06x)", msg, \ + shared->hw_running ? "running" : " idle", \ + shared->hw_start, \ + shared->hw_end, \ + shared->next_start, \ + shared->next_end, \ + shared->next_valid ? " " : "in", \ + BEM_HC_STATUS, BEM_HC_INT_STATUS ); + +/**********************************************************************************************************************/ + +#ifdef SH7722GFX_DEBUG_JPU +#define JPRINT(x...) do { \ + char buf[128]; \ + struct timeval tv; \ + do_gettimeofday( &tv ); \ + snprintf( buf, sizeof(buf), x ); \ + printk( KERN_DEBUG "%ld.%03ld.%03ld - %-17s: %s\n", \ + tv.tv_sec - base_time.tv_sec, \ + tv.tv_usec / 1000, tv.tv_usec % 1000, __FUNCTION__, buf ); \ +} while (0) +#else +#define JPRINT(x...) do {} while (0) +#endif + +/**********************************************************************************************************************/ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) +# define USE_DMA_ALLOC_COHERENT +#endif + +static DECLARE_WAIT_QUEUE_HEAD( wait_idle ); +static DECLARE_WAIT_QUEUE_HEAD( wait_next ); + +static SH772xGfxSharedArea *shared; + +static struct timeval base_time; + +static struct page *shared_page; +static unsigned int shared_order; + +#ifdef USE_DMA_ALLOC_COHERENT +static unsigned long shared_phys; +#endif + +#ifdef SH7722GFX_IRQ_POLLER +static int stop_poller; +#endif + +/**********************************************************************************************************************/ + +static DECLARE_WAIT_QUEUE_HEAD( wait_jpeg_irq ); +static DECLARE_WAIT_QUEUE_HEAD( wait_jpeg_run ); +static DECLARE_WAIT_QUEUE_HEAD( wait_jpeg_lock ); + +static struct page *jpeg_page; +static unsigned int jpeg_order; +static volatile void *jpeg_area; +static u32 jpeg_buffers; +static int jpeg_buffer; +static u32 jpeg_error; +static int jpeg_encode; +static int jpeg_reading; +static int jpeg_writing; +static int jpeg_reading_line; +static int jpeg_writing_line; +static int jpeg_height; +static int jpeg_inputheight; +static unsigned long jpeg_phys; +static int jpeg_end; +static u32 jpeg_linebufs; +static int jpeg_linebuf; +static int jpeg_line; +static int jpeg_line_veu; /* is the VEU done yet? */ +static int veu_linebuf; +static int veu_running; + +static pid_t jpeg_locked; + +/**********************************************************************************************************************/ + +static int +sh7722_reset( SH772xGfxSharedArea *shared ) +{ + int i; + + do_gettimeofday( &base_time ); + + QPRINT( "Resetting hardware..." ); + + BEM_HC_CLOCK = 0; + for (i=0; i<30000; i++); + BEM_HC_CLOCK = 0x1111; + + BEM_HC_RESET = 0x1111; + for (i=0; i<30000; i++); + BEM_HC_RESET = 0; + + + QPRINT( "Initializing shared area..." ); + + memset( (void*) shared, 0, sizeof(SH772xGfxSharedArea) ); + +#ifdef USE_DMA_ALLOC_COHERENT + shared->buffer_phys = shared_phys; +#else + shared->buffer_phys = virt_to_phys(&shared->buffer[0]); +#endif + shared->jpeg_phys = virt_to_phys(jpeg_area); + shared->magic = SH7722GFX_SHARED_MAGIC; + + + QPRINT( "Clearing interrupts..." ); + + BEM_HC_INT_CLEAR = 0x111111; + BEM_HC_INT_MASK = 0x110011; + + BEM_HC_CACHE_FLUSH = 0; + + QDUMP( "Ready" ); + + return 0; +} + +static int +sh7722_wait_idle( SH772xGfxSharedArea *shared ) +{ + int ret; + + QDUMP( "Waiting....." ); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + shared->num_wait_idle++; + + ret = wait_event_interruptible_timeout( wait_idle, !shared->hw_running, 42*HZ ); + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x, INT_STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + BEM_HC_STATUS, BEM_HC_INT_STATUS ); + } + + QDUMP( "........done" ); + + return (ret > 0) ? 0 : (ret < 0) ? ret : -ETIMEDOUT; +} + +static int +sh7722_wait_next( SH772xGfxSharedArea *shared ) +{ + int ret; + + QDUMP( "Waiting....." ); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + shared->num_wait_next++; + + ret = wait_event_interruptible_timeout( wait_next, !shared->hw_running || + shared->next_start == shared->next_end, 42*HZ ); + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x, INT_STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + BEM_HC_STATUS, BEM_HC_INT_STATUS ); + } + + QDUMP( "........done" ); + + return (ret > 0) ? 0 : (ret < 0) ? ret : -ETIMEDOUT; +} + +/**********************************************************************************************************************/ + +static int +sh7722_wait_jpeg( SH772xGfxSharedArea *shared ) +{ + int ret; + + ret = wait_event_interruptible_timeout( wait_jpeg_irq, shared->jpeg_ints, HZ ); + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (status 0x%08x, ints 0x%08x)\n", __FUNCTION__, JPU_JCSTS, JPU_JINTS ); + } + + return (ret > 0) ? 0 : (ret < 0) ? ret : -ETIMEDOUT; +} + +static int +sh7722_run_jpeg( SH772xGfxSharedArea *shared, + SH7722JPEG *jpeg ) +{ + int ret; + int encode = (jpeg->flags & SH7722_JPEG_FLAG_ENCODE) ? 1 : 0; + int convert = (jpeg->flags & SH7722_JPEG_FLAG_CONVERT) ? 1 : 0; + + JPRINT( "run JPEG called %d", jpeg->state ); + + switch (jpeg->state) { + case SH7722_JPEG_START: + JPRINT( "START (buffers: %d, flags: 0x%x)", jpeg->buffers, jpeg->flags ); + + jpeg_line = 0; + jpeg_line_veu = 0; + jpeg_end = 0; + jpeg_error = 0; + jpeg_encode = encode; + jpeg_reading = 0; + jpeg_writing = 2; + jpeg_reading_line = encode && !convert; + jpeg_writing_line = !encode; + jpeg_height = jpeg->height; + jpeg_inputheight = jpeg->inputheight; + jpeg_phys = jpeg->phys; + jpeg_linebuf = 0; + jpeg_linebufs = 0; + jpeg_buffer = 0; + jpeg_buffers = jpeg->buffers; + veu_linebuf = 0; + veu_running = 0; + + jpeg->state = SH7722_JPEG_RUN; + jpeg->error = 0; + +// if (!encode || !convert) + JPU_JCCMD = JCCMD_START; + break; + + case SH7722_JPEG_RUN: + JPRINT( "RUN (buffers: %d)", jpeg->buffers ); + + /* Validate loaded buffers. */ + jpeg_buffers |= jpeg->buffers; + break; + + default: + printk( KERN_ERR "%s: INVALID STATE %d! (status 0x%08x, ints 0x%08x)\n", + __FUNCTION__, jpeg->state, JPU_JCSTS, JPU_JINTS ); + return -EINVAL; + } + + if (encode) { + if (convert) { + if (jpeg_linebufs != 3 && !veu_running) { + JPRINT( " '-> convert start (buffers: %d, veu linebuf: %d)", jpeg_buffers, veu_linebuf ); + + veu_running = 1; + + VEU_VDAYR = veu_linebuf ? JPU_JIFESYA2 : JPU_JIFESYA1; + VEU_VDACR = veu_linebuf ? JPU_JIFESCA2 : JPU_JIFESCA1; + VEU_VESTR = 0x1; + } + } + if (jpeg_buffers && !jpeg_writing) { + JPRINT( " '-> write start (buffers: %d)", jpeg_buffers ); + + jpeg_writing = 1; + JPU_JCCMD = JCCMD_WRITE_RESTART; + } + } + else if (jpeg_buffers && !jpeg_reading) { + JPRINT( " '-> read start (buffers: %d)", jpeg_buffers ); + + jpeg_reading = 1; + JPU_JCCMD = JCCMD_READ_RESTART; + } + + ret = wait_event_interruptible_timeout( wait_jpeg_run, + jpeg_end || jpeg_error || + (jpeg_buffers != 3 && (jpeg->flags & SH7722_JPEG_FLAG_RELOAD)), 5 * HZ ); + if (ret < 0) + return ret; + + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (JCSTS 0x%08x, JINTS 0x%08x, JCRST 0x%08x)\n", __FUNCTION__, + JPU_JCSTS, JPU_JINTS, JPU_JCRST ); + return -ETIMEDOUT; + } + + if (jpeg_error) { + /* Return error. */ + jpeg->state = SH7722_JPEG_END; + jpeg->error = jpeg_error; + + JPRINT( " '-> ERROR (0x%x)", jpeg->error ); + } + else { + /* Return buffers to reload or to empty. */ + jpeg->buffers = jpeg_buffers ^ 3; + + if (jpeg_end) { + JPRINT( " '-> END" ); + + /* Return end. */ + jpeg->state = SH7722_JPEG_END; + jpeg->buffers |= 1 << jpeg_buffer; + } + else if (encode) + JPRINT( " '-> LOADED (%d)", jpeg->buffers ); + else + JPRINT( " '-> RELOAD (%d)", jpeg->buffers ); + } + + return 0; +} + +static int +sh7722_lock_jpeg( SH772xGfxSharedArea *shared ) +{ + int ret; + + if (jpeg_locked) { + ret = wait_event_interruptible_timeout( wait_jpeg_lock, !jpeg_locked, 5 * HZ ); + if (ret < 0) + return ret; + + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (status 0x%08x, ints 0x%08x)\n", __FUNCTION__, JPU_JCSTS, JPU_JINTS ); + return -ETIMEDOUT; + } + } + + jpeg_locked = current->pid; + + return 0; +} + +static int +sh7722_unlock_jpeg( SH772xGfxSharedArea *shared ) +{ + if (jpeg_locked != current->pid) + return -EIO; + + jpeg_locked = 0; + + wake_up_all( &wait_jpeg_lock ); + + return 0; +} + +/**********************************************************************************************************************/ + +static irqreturn_t +sh7722_jpu_irq( int irq, void *ctx ) +{ + u32 ints; + SH772xGfxSharedArea *shared = ctx; + + ints = JPU_JINTS; + + JPU_JINTS = ~ints & JINTS_MASK; + + if (ints & (JINTS_INS3_HEADER | JINTS_INS5_ERROR | JINTS_INS6_DONE)) + JPU_JCCMD = JCCMD_END; + + JPRINT( " ... JPU int 0x%08x (veu_linebuf:%d,jpeg_linebuf:%d,jpeg_linebufs:%d,jpeg_line:%d,jpeg_buffers:%d)", + ints, veu_linebuf, jpeg_linebuf, jpeg_linebufs, jpeg_line, jpeg_buffers ); + + if (ints) { + shared->jpeg_ints |= ints; + + wake_up_all( &wait_jpeg_irq ); + + /* Header */ + if (ints & JINTS_INS3_HEADER) { + JPRINT( " -> HEADER (%dx%d)", JPU_JIFDDHSZ, JPU_JIFDDVSZ ); + } + + /* Error */ + if (ints & JINTS_INS5_ERROR) { + jpeg_error = JPU_JCDERR; + + JPRINT( " -> ERROR 0x%08x!", jpeg_error ); + + wake_up_all( &wait_jpeg_run ); + } + + /* Done */ + if (ints & JINTS_INS6_DONE) { + jpeg_end = 1; + + JPRINT( " -> DONE" ); + + JPU_JCCMD = JCCMD_END; + + wake_up_all( &wait_jpeg_run ); + } + + /* Done */ + if (ints & JINTS_INS10_XFER_DONE) { + jpeg_end = 1; + + JPRINT( " -> XFER DONE" ); + + JPU_JCCMD = JCCMD_END; + + wake_up_all( &wait_jpeg_run ); + } + + /* Line buffer ready? FIXME: encoding */ + if (ints & (JINTS_INS11_LINEBUF0 | JINTS_INS12_LINEBUF1)) { + JPRINT( " -> LINEBUF %d", jpeg_linebuf ); + + if (jpeg_encode) { + jpeg_linebufs &= ~(1 << jpeg_linebuf); + + jpeg_linebuf = jpeg_linebuf ? 0 : 1; + + if (jpeg_linebufs) { + jpeg_reading_line = 1; /* should still be one */ + + if (!jpeg_end) + JPU_JCCMD = JCCMD_LCMD2 | JCCMD_LCMD1; + } + else { + jpeg_reading_line = 0; + } + + jpeg_line += 16; + + if (jpeg_line_veu CONVERT %d", veu_linebuf ); + + veu_running = 1; + + /* we will not update VESSR or VRFSR to prevent recalculating + * the input lines in case of partial content. + * This prevents hangups in case of program errors */ + + n = jpeg_line_veu * jpeg_inputheight; + while (n >= jpeg_height*8) { offset+=8; n -= jpeg_height*8; } + while (n >= jpeg_height) { offset++; n -= jpeg_height; } + + /* VEU_VSACR is only used for CbCr, so we can simplify a bit */ + n = (VEU_VTRCR & VTRCR_CHRR) ? 0 : 1; + + VEU_VSAYR = jpeg_phys + offset * VEU_VESWR; + VEU_VSACR = jpeg_phys + ((offset >> n) + jpeg_height) * VEU_VESWR; + + VEU_VDAYR = veu_linebuf ? JPU_JIFESYA2 : JPU_JIFESYA1; + VEU_VDACR = veu_linebuf ? JPU_JIFESCA2 : JPU_JIFESCA1; + VEU_VESTR = 0x1; + } + } + else { + jpeg_linebufs |= (1 << jpeg_linebuf); + + jpeg_linebuf = jpeg_linebuf ? 0 : 1; + + if (jpeg_linebufs != 3) { + jpeg_writing_line = 1; /* should still be one */ + + if (jpeg_line > 0 && !jpeg_end) + JPU_JCCMD = JCCMD_LCMD1 | JCCMD_LCMD2; + } + else { + jpeg_writing_line = 0; + } + + jpeg_line += 16; + + if (!veu_running && !jpeg_end && !jpeg_error) { + JPRINT( " -> CONVERT %d", veu_linebuf ); + + veu_running = 1; + + VEU_VSAYR = veu_linebuf ? JPU_JIFDDYA2 : JPU_JIFDDYA1; + VEU_VSACR = veu_linebuf ? JPU_JIFDDCA2 : JPU_JIFDDCA1; + VEU_VESTR = 0x101; + } + } + } + + /* Loaded */ + if (ints & JINTS_INS13_LOADED) { + JPRINT( " -> LOADED %d (writing: %d)", jpeg_buffer, jpeg_writing ); + + jpeg_buffers &= ~(1 << jpeg_buffer); + + jpeg_buffer = jpeg_buffer ? 0 : 1; + + jpeg_writing--; + + wake_up_all( &wait_jpeg_run ); + } + + /* Reload */ + if (ints & JINTS_INS14_RELOAD) { + JPRINT( " -> RELOAD %d", jpeg_buffer ); + + jpeg_buffers &= ~(1 << jpeg_buffer); + + jpeg_buffer = jpeg_buffer ? 0 : 1; + + if (jpeg_buffers) { + jpeg_reading = 1; /* should still be one */ + + JPU_JCCMD = JCCMD_READ_RESTART; + } + else + jpeg_reading = 0; + + wake_up_all( &wait_jpeg_run ); + } + } + + return IRQ_HANDLED; +} + +/**********************************************************************************************************************/ + +static irqreturn_t +sh7722_veu_irq( int irq, void *ctx ) +{ + u32 events = VEU_VEVTR; + + VEU_VEVTR = ~events & 0x101; + + JPRINT( " ... VEU int 0x%08x (veu_linebuf:%d,jpeg_linebuf:%d,jpeg_linebufs:%d,jpeg_line:%d)", + events, veu_linebuf, jpeg_linebuf, jpeg_linebufs, jpeg_line ); + + /* update the lines processed. + * If we have tmpphys memory, we are ready now (veu lines == height) */ + jpeg_line_veu += (VEU_VRFSR >> 16); + + if (jpeg_encode) { + /* Fill line buffers. */ + jpeg_linebufs |= 1 << veu_linebuf; + + /* Resume encoding if it was blocked. */ + if (!jpeg_reading_line && !jpeg_end && !jpeg_error && jpeg_linebufs) { + JPRINT( " -> ENCODE %d", veu_linebuf ); + jpeg_reading_line = 1; + JPU_JCCMD = JCCMD_LCMD2 | JCCMD_LCMD1; + } + + veu_linebuf = veu_linebuf ? 0 : 1; + + if( jpeg_line_veu < jpeg_height /* still some more lines to do */ + && jpeg_linebufs != 3 /* and still some place to put them */ + && !jpeg_end /* safety, should not happen */ + && !jpeg_error ) { + int offset = 0; + int n = 0; + + JPRINT( " -> CONVERT %d", veu_linebuf ); + + n = jpeg_line_veu * jpeg_inputheight; + while (n >= jpeg_height*8) { offset+=8; n -= jpeg_height*8; } + while (n >= jpeg_height) { offset++; n -= jpeg_height; } + + /* VEU_VSACR is only used for CbCr, so we can simplify a bit */ + n = (VEU_VTRCR & VTRCR_CHRR) ? 0 : 1; + + VEU_VSAYR = jpeg_phys + offset * VEU_VESWR; + VEU_VSACR = jpeg_phys + ((offset >> n) + jpeg_height) * VEU_VESWR; + + VEU_VDAYR = veu_linebuf ? JPU_JIFESYA2 : JPU_JIFESYA1; + VEU_VDACR = veu_linebuf ? JPU_JIFESCA2 : JPU_JIFESCA1; + + veu_running = 1; /* kick VEU to continue */ + VEU_VESTR = 0x1; + } + else { + veu_running = 0; + } + } + else { + /* Release line buffer. */ + jpeg_linebufs &= ~(1 << veu_linebuf); + + /* Resume decoding if it was blocked. */ + if (!jpeg_writing_line && !jpeg_end && !jpeg_error && jpeg_linebufs != 3) { + JPRINT( " -> RESUME %d", jpeg_linebuf ); + + jpeg_writing_line = 1; + + JPU_JCCMD = JCCMD_LCMD1 | JCCMD_LCMD2; + } + + veu_linebuf = veu_linebuf ? 0 : 1; + + if (jpeg_linebufs) { + JPRINT( " -> CONVERT %d", veu_linebuf ); + + veu_running = 1; /* should still be one */ + + VEU_VSAYR = veu_linebuf ? JPU_JIFDDYA2 : JPU_JIFDDYA1; + VEU_VSACR = veu_linebuf ? JPU_JIFDDCA2 : JPU_JIFDDCA1; + VEU_VESTR = 0x101; + } + else { + if (jpeg_end) + wake_up_all( &wait_jpeg_run ); + + veu_running = 0; + } + } + + return IRQ_HANDLED; +} + +/**********************************************************************************************************************/ + +static irqreturn_t +sh7722_beu_irq( int irq, void *ctx ) +{ + BEVTR = 0; + + /* Nothing here so far. But Vsync could be added. */ + + return IRQ_HANDLED; +} + +/**********************************************************************************************************************/ + +static irqreturn_t +sh7722_tdg_irq( int irq, void *ctx ) +{ + SH772xGfxSharedArea *shared = ctx; + u32 status = BEM_HC_INT_STATUS; + + if (! (status & 0x111111)) { +#ifndef SH7722GFX_IRQ_POLLER + printk( KERN_WARNING "%s: bogus interrupt, INT_STATUS 0x%08x!\n", __FUNCTION__, status ); +#endif + return IRQ_NONE; + } + + if (status & ~0x100) + QDUMP( "-Interrupt" ); + + if (status & ~0x101100) + printk( KERN_ERR "%s: error! INT_STATUS 0x%08x!\n", __FUNCTION__, status ); + + shared->num_interrupts++; + + /* Clear the interrupt. */ + BEM_HC_INT_CLEAR = status; + + if (status & 0x100010) { + if (!shared->hw_running) + printk( KERN_WARNING "%s: hw not running? INT_STATUS 0x%08x!\n", __FUNCTION__, status ); + + if (status & 0x10) { + printk( KERN_ERR "%s: RUNAWAY! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x, INT_STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + BEM_HC_STATUS, status ); + + BEM_HC_RESET = 0x1111; + } + + /* Next valid means user space is not in the process of extending the buffer. */ + if (shared->next_valid && shared->next_start != shared->next_end) { + shared->hw_start = shared->next_start; + shared->hw_end = shared->next_end; + + shared->next_start = shared->next_end = (shared->hw_end + 1 + 3) & ~3; + shared->next_valid = 0; + + shared->num_words += shared->hw_end - shared->hw_start; + + shared->num_starts++; + + QDUMP( " '-> Start!" ); + + BEM_HC_DMA_ADR = shared->buffer_phys + shared->hw_start*4; + BEM_HC_DMA_START = 1; + + wake_up_all( &wait_next ); + } + else { + shared->num_idle++; + + QDUMP( " '-> Idle." ); + + BEM_PE_CACHE = 1; + + shared->hw_running = 0; + + wake_up_all( &wait_next ); + wake_up_all( &wait_idle ); + } + + shared->num_done++; + } + + return IRQ_HANDLED; +} + +#ifdef SH7722GFX_IRQ_POLLER +static int +sh7722_tdg_irq_poller( void *arg ) +{ + daemonize( "%s", __FUNCTION__ ); + + sigfillset( ¤t->blocked ); + + while (!stop_poller) { + set_current_state( TASK_UNINTERRUPTIBLE ); + schedule_timeout( 1 ); + + sh7722_tdg_irq( SH7722_TDG_IRQ, (void*) arg ); + } + + stop_poller = 0; + + return 0; +} +#endif + +/**********************************************************************************************************************/ +/**********************************************************************************************************************/ + +static int +sh7722gfx_flush( struct file *filp, + fl_owner_t id ) +{ + if (jpeg_locked == current->pid) { + jpeg_locked = 0; + + wake_up_all( &wait_jpeg_lock ); + } + + return 0; +} + +static int +sh7722gfx_ioctl( struct inode *inode, + struct file *filp, + unsigned int cmd, + unsigned long arg ) +{ + int ret; + SH772xRegister reg; + SH7722JPEG jpeg; + + switch (cmd) { + case SH772xGFX_IOCTL_RESET: + return sh7722_reset( shared ); + + case SH772xGFX_IOCTL_WAIT_IDLE: + return sh7722_wait_idle( shared ); + + case SH772xGFX_IOCTL_WAIT_NEXT: + return sh7722_wait_next( shared ); + + case SH772xGFX_IOCTL_SETREG32: + if (copy_from_user( ®, (void*)arg, sizeof(SH772xRegister) )) + return -EFAULT; + + /* VEU, BEU, LCDC, VOU, JPEG */ + if (reg.address < 0xFE920000 || reg.address > 0xFEA102D0) + return -EACCES; + + *(volatile __u32 *) reg.address = reg.value; + + return 0; + + case SH772xGFX_IOCTL_GETREG32: + if (copy_from_user( ®, (void*)arg, sizeof(SH772xRegister) )) + return -EFAULT; + + /* VEU, BEU, LCDC, VOU, JPEG */ + if (reg.address < 0xFE920000 || reg.address > 0xFEA102D0) + return -EACCES; + + reg.value = *(volatile __u32 *) reg.address; + + if (copy_to_user( (void*)arg, ®, sizeof(SH772xRegister) )) + return -EFAULT; + + return 0; + + case SH7722GFX_IOCTL_WAIT_JPEG: + return sh7722_wait_jpeg( shared ); + + case SH7722GFX_IOCTL_RUN_JPEG: + if (copy_from_user( &jpeg, (void*)arg, sizeof(SH7722JPEG) )) + return -EFAULT; + + ret = sh7722_run_jpeg( shared, &jpeg ); + if (ret) + return ret; + + if (copy_to_user( (void*)arg, &jpeg, sizeof(SH7722JPEG) )) + return -EFAULT; + + return 0; + + case SH7722GFX_IOCTL_LOCK_JPEG: + return sh7722_lock_jpeg( shared ); + + case SH7722GFX_IOCTL_UNLOCK_JPEG: + return sh7722_unlock_jpeg( shared ); + } + + return -ENOSYS; +} + +static int +sh7722gfx_mmap( struct file *file, + struct vm_area_struct *vma ) +{ + unsigned int size; + + /* Just allow mapping at offset 0. */ + if (vma->vm_pgoff) + return -EINVAL; + + /* Check size of requested mapping. */ + size = vma->vm_end - vma->vm_start; + if (size != PAGE_ALIGN(sizeof(SH772xGfxSharedArea))) + return -EINVAL; + + /* Set reserved and I/O flag for the area. */ + vma->vm_flags |= VM_RESERVED | VM_IO; + + /* Select uncached access. */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + +#ifdef USE_DMA_ALLOC_COHERENT + return remap_pfn_range( vma, vma->vm_start, + (__u32)shared >> PAGE_SHIFT, + size, vma->vm_page_prot ); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9) + return remap_pfn_range( vma, vma->vm_start, + virt_to_phys((void*)shared) >> PAGE_SHIFT, + size, vma->vm_page_prot ); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) + return remap_page_range( vma, vma->vm_start, + virt_to_phys((void*)shared), + size, vma->vm_page_prot ); +#else + return io_remap_page_range( vma->vm_start, + virt_to_phys((void*)shared), + size, vma->vm_page_prot ); +#endif +} + +/**********************************************************************************************************************/ + +static struct file_operations sh7722gfx_fops = { + flush: sh7722gfx_flush, + ioctl: sh7722gfx_ioctl, + mmap: sh7722gfx_mmap +}; + +static struct miscdevice sh7722gfx_miscdev = { + minor: 196, // 7*7*2*2 + name: "sh772x_gfx", + fops: &sh7722gfx_fops +}; + +/**********************************************************************************************************************/ + +int +sh7722_init( void ) +{ + int i; + int ret; + + /* Register the SH7722 graphics device. */ + ret = misc_register( &sh7722gfx_miscdev ); + if (ret < 0) { + printk( KERN_ERR "%s: misc_register() for minor %d failed! (error %d)\n", + __FUNCTION__, sh7722gfx_miscdev.minor, ret ); + return ret; + } + + /* Allocate and initialize the shared area. */ +#ifdef USE_DMA_ALLOC_COHERENT + shared = dma_alloc_coherent( NULL, sizeof(SH772xGfxSharedArea), + (dma_addr_t*)&shared_phys, GFP_KERNEL ); + + printk( KERN_INFO "sh7722gfx: shared area at %p [%lx/%lx] using %d bytes\n", + shared, virt_to_phys(shared), shared_phys, sizeof(SH772xGfxSharedArea) ); + +#else + shared_order = get_order(PAGE_ALIGN(sizeof(SH772xGfxSharedArea))); + shared_page = alloc_pages( GFP_DMA | GFP_KERNEL, shared_order ); + shared = ioremap( virt_to_phys( page_address(shared_page) ), + PAGE_ALIGN(sizeof(SH772xGfxSharedArea)) ); + + for (i=0; i<1< + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License v2 + * as published by the Free Software Foundation. + */ + +#ifndef __SH7722_H__ +#define __SH7722_H__ + +int sh7722_init( void ); +void sh7722_exit( void ); + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7723.c b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7723.c new file mode 100755 index 0000000..ea64cf4 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh7723.c @@ -0,0 +1,566 @@ +/* + * SH7723 Graphics Device + * + * Copyright (C) 2006-2008 IGEL Co.,Ltd + * + * Written by Janine Kropp , + * Denis Oliver Kropp + * + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License v2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27) +#include +#endif + +#include + + +//#define SH7723GFX_DEBUG_2DG +//#define SH7723GFX_IRQ_POLLER + + +/**********************************************************************************************************************/ + +#ifndef SH7723_BEU_IRQ +#define SH7723_BEU_IRQ 53 +#endif + +#ifndef SH7723_TDG_IRQ +#define SH7723_TDG_IRQ 44 +#endif + +/**********************************************************************************************************************/ + +#define ENGINE_REG_TOP 0xA4680000 +#define SH7723_BEU_BASE 0xFE930000 + +#define M2DG_REG(x) (*(volatile u32*)((x)+ENGINE_REG_TOP)) +#define BEU_REG(x) (*(volatile u32*)((x)+SH7723_BEU_BASE)) + +#define M2DG_SCLR M2DG_REG(0x000) +#define M2DG_DLSAR M2DG_REG(0x048) + + +#define M2DG_STATUS M2DG_REG(0x004) +#define M2DG_STATUS_CLEAR M2DG_REG(0x008) +#define M2DG_INT_ENABLE M2DG_REG(0x00c) + +#define M2DG_SCLR_START 0x00000001 +#define M2DG_SCLR_RESET 0x80000000 + +#define M2DG_INT_TRAP 0x0001 +#define M2DG_INT_INTERRUPT 0x0002 +#define M2DG_INT_ERROR 0x0004 +#define M2DG_INT_ANY 0x0007 + +#define BEVTR BEU_REG(0x0018C) + +/**********************************************************************************************************************/ + +#ifdef SH7723GFX_DEBUG_2DG +#define QPRINT(x...) do { \ + char buf[128]; \ + struct timeval tv; \ + do_gettimeofday( &tv ); \ + snprintf( buf, sizeof(buf), x ); \ + printk( KERN_DEBUG "%ld.%03ld.%03ld - %-17s: %s\n", \ + tv.tv_sec - base_time.tv_sec, \ + tv.tv_usec / 1000, tv.tv_usec % 1000, __FUNCTION__, buf ); \ +} while (0) +#else +#define QPRINT(x...) do {} while (0) +#endif + +#define QDUMP(msg) QPRINT( "%-12s (%s, hw %5d-%5d, next %5d-%5d, %svalid, " \ + "STATUS 0x%07x)", msg, \ + shared->hw_running ? "running" : " idle", \ + shared->hw_start, \ + shared->hw_end, \ + shared->next_start, \ + shared->next_end, \ + shared->next_valid ? " " : "in", \ + M2DG_STATUS & M2DG_INT_ANY ); + +/**********************************************************************************************************************/ + +static DECLARE_WAIT_QUEUE_HEAD( wait_idle ); +static DECLARE_WAIT_QUEUE_HEAD( wait_next ); + +static SH772xGfxSharedArea *shared; + +static struct timeval base_time; + +#ifndef SHARED_AREA_PHYS +static struct page *shared_page; +static unsigned int shared_order; +#endif + +#ifdef SH7723GFX_IRQ_POLLER +static int stop_poller; +#endif + +/**********************************************************************************************************************/ + +static int +sh7723_reset( SH772xGfxSharedArea *shared ) +{ + do_gettimeofday( &base_time ); + + QPRINT( "Resetting hardware..." ); + + M2DG_SCLR = M2DG_SCLR_RESET; + udelay( 5 ); + M2DG_SCLR = 0; + + QPRINT( "Initializing shared area..." ); + + memset( (void*) shared, 0, sizeof(SH772xGfxSharedArea) ); + + shared->buffer_phys = virt_to_phys(&shared->buffer[0]); + shared->magic = SH7723GFX_SHARED_MAGIC; + + + QPRINT( "Clearing interrupts..." ); + + M2DG_STATUS_CLEAR = M2DG_INT_ANY; + + M2DG_INT_ENABLE = M2DG_INT_ANY; + + QDUMP( "Ready" ); + + return 0; +} + +/* copied from board-ap325rxa.c */ +#define PORT_PSCR 0xA405011E +#define PORT_PSDR 0xA405013E +#define FPGA_LCDREG 0xB4100180 +#define FPGA_BKLREG 0xB4100212 + +static int +sh7723_power_display( void ) +{ + msleep(100); + + /* ASD AP-320/325 LCD ON */ + ctrl_outw(0x0018, FPGA_LCDREG); + + /* backlight */ + ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); + ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR); + ctrl_outw(0x100, FPGA_BKLREG); + + return 0; +} + +static int +sh7723_wait_idle( SH772xGfxSharedArea *shared ) +{ + int ret; + + QDUMP( "Waiting....." ); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + shared->num_wait_idle++; + + ret = wait_event_interruptible_timeout( wait_idle, !shared->hw_running, 42*HZ ); + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + M2DG_STATUS & M2DG_INT_ANY ); + } + + QDUMP( "........done" ); + + return (ret > 0) ? 0 : (ret < 0) ? ret : -ETIMEDOUT; +} + +static int +sh7723_wait_next( SH772xGfxSharedArea *shared ) +{ + int ret; + + QDUMP( "Waiting....." ); + + /* Does not need to be atomic. There's a lock in user space, + * but anyhow, this is just for statistics. */ + shared->num_wait_next++; + + ret = wait_event_interruptible_timeout( wait_next, !shared->hw_running || + shared->next_start == shared->next_end, 42*HZ ); + if (!ret) { + printk( KERN_ERR "%s: TIMEOUT! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + M2DG_STATUS & M2DG_INT_ANY ); + } + + QDUMP( "........done" ); + + return (ret > 0) ? 0 : (ret < 0) ? ret : -ETIMEDOUT; +} + +/**********************************************************************************************************************/ + +static irqreturn_t +sh7723_beu_irq( int irq, void *ctx ) +{ + BEVTR = 0; + + /* Nothing here so far. But Vsync could be added. */ + + return IRQ_HANDLED; +} + +static irqreturn_t +sh7723_tdg_irq( int irq, void *ctx ) +{ + SH772xGfxSharedArea *shared = ctx; + u32 status = M2DG_STATUS & M2DG_INT_ANY; + + if (! (status & M2DG_INT_ANY)) { +#ifndef SH7723GFX_IRQ_POLLER + printk( KERN_WARNING "%s: bogus interrupt, STATUS 0x%08x!\n", __FUNCTION__, status ); +#endif + return IRQ_NONE; + } + +// if (status & ~0x100) + QDUMP( "-Interrupt" ); + + if (status & M2DG_INT_ERROR) + printk( KERN_ERR "%s: error! STATUS 0x%08x!\n", __FUNCTION__, status ); + + shared->num_interrupts++; + + /* Clear the interrupt. */ + M2DG_STATUS_CLEAR = status; + + if (status & (M2DG_INT_TRAP | M2DG_INT_ERROR)) { + if (!shared->hw_running) + printk( KERN_WARNING "%s: huh, hw running? STATUS 0x%08x!\n", __FUNCTION__, status ); + + if (status & M2DG_INT_ERROR) { + printk( KERN_ERR "%s: ERROR! (%srunning, hw %d-%d, next %d-%d - %svalid, " + "STATUS 0x%08x)\n", + __FUNCTION__, + shared->hw_running ? "" : "not ", + shared->hw_start, + shared->hw_end, + shared->next_start, + shared->next_end, + shared->next_valid ? "" : "not ", + status ); + + M2DG_SCLR = M2DG_SCLR_RESET; + } + + /* Next valid means user space is not in the process of extending the buffer. */ + if (shared->next_valid && shared->next_start != shared->next_end) { + shared->hw_start = shared->next_start; + shared->hw_end = shared->next_end; + + shared->next_start = shared->next_end = (shared->hw_end + 1 + 3) & ~3; + shared->next_valid = 0; + + shared->num_words += shared->hw_end - shared->hw_start; + + shared->num_starts++; + + QDUMP( " '-> Start!" ); + + M2DG_DLSAR = shared->buffer_phys + shared->hw_start*4; + M2DG_SCLR = M2DG_SCLR_START; + + wake_up_all( &wait_next ); + } + else { + shared->num_idle++; + + QDUMP( " '-> Idle." ); + +//check if needed +// BEM_PE_CACHE = 1; + + shared->hw_running = 0; + + wake_up_all( &wait_next ); + wake_up_all( &wait_idle ); + } + + shared->num_done++; + } + + return IRQ_HANDLED; +} + +#ifdef SH7723GFX_IRQ_POLLER +static int +sh7723_tdg_irq_poller( void *arg ) +{ + daemonize( "%s", __FUNCTION__ ); + + sigfillset( ¤t->blocked ); + + while (!stop_poller) { + set_current_state( TASK_UNINTERRUPTIBLE ); + schedule_timeout( 1 ); + + sh7723_tdg_irq( SH7723_TDG_IRQ, (void*) arg ); + } + + stop_poller = 0; + + return 0; +} +#endif + +/**********************************************************************************************************************/ + +static int +sh7723gfx_ioctl( struct inode *inode, + struct file *filp, + unsigned int cmd, + unsigned long arg ) +{ + SH772xRegister reg; + + switch (cmd) { + case SH772xGFX_IOCTL_RESET: + return sh7723_reset( shared ); + + case SH772xGFX_IOCTL_WAIT_IDLE: + return sh7723_wait_idle( shared ); + + case SH772xGFX_IOCTL_WAIT_NEXT: + return sh7723_wait_next( shared ); + + case SH772xGFX_IOCTL_SETREG32: + if (copy_from_user( ®, (void*)arg, sizeof(SH772xRegister) )) + return -EFAULT; + + /* BEU, LCDC, VOU, 2DG */ + if ((reg.address < 0xFE930000 || reg.address > 0xFEA102D0) && + (reg.address < 0xA4680000 || reg.address > 0xA468FFFF)) + return -EACCES; + + *(volatile __u32 *) reg.address = reg.value; + + return 0; + + case SH772xGFX_IOCTL_GETREG32: + if (copy_from_user( ®, (void*)arg, sizeof(SH772xRegister) )) + return -EFAULT; + + /* BEU, LCDC, VOU */ + if ((reg.address < 0xFE930000 || reg.address > 0xFEA102D0) && + (reg.address < 0xA4680000 || reg.address > 0xA468FFFF)) + return -EACCES; + + reg.value = *(volatile __u32 *) reg.address; + + if (copy_to_user( (void*)arg, ®, sizeof(SH772xRegister) )) + return -EFAULT; + + return 0; + + case SH772xGFX_IOCTL_POWER_DISPLAY: + return sh7723_power_display( ); + } + + return -ENOSYS; +} + +static int +sh7723gfx_mmap( struct file *file, + struct vm_area_struct *vma ) +{ + unsigned int size; + + /* Just allow mapping at offset 0. */ + if (vma->vm_pgoff) + return -EINVAL; + + /* Check size of requested mapping. */ + size = vma->vm_end - vma->vm_start; + if (size != PAGE_ALIGN(sizeof(SH772xGfxSharedArea))) + return -EINVAL; + + /* Set reserved and I/O flag for the area. */ + vma->vm_flags |= VM_RESERVED | VM_IO; + + /* Select uncached access. */ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 9) + return remap_pfn_range( vma, vma->vm_start, + virt_to_phys((void*)shared) >> PAGE_SHIFT, + size, vma->vm_page_prot ); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0) + return remap_page_range( vma, vma->vm_start, + virt_to_phys((void*)shared), + size, vma->vm_page_prot ); +#else + return io_remap_page_range( vma->vm_start, + virt_to_phys((void*)shared), + size, vma->vm_page_prot ); +#endif +} + +/**********************************************************************************************************************/ + +static struct file_operations sh7723gfx_fops = { + ioctl: sh7723gfx_ioctl, + mmap: sh7723gfx_mmap +}; + +static struct miscdevice sh7723gfx_miscdev = { + minor: 196, // 7*7*2*2 + name: "sh772x_gfx", + fops: &sh7723gfx_fops +}; + +/**********************************************************************************************************************/ + +int +sh7723_init( void ) +{ +#ifndef SHARED_AREA_PHYS + int i; +#endif + int ret; + + /* Register the SH7723 graphics device. */ + ret = misc_register( &sh7723gfx_miscdev ); + if (ret < 0) { + printk( KERN_ERR "%s: misc_register() for minor %d failed! (error %d)\n", + __FUNCTION__, sh7723gfx_miscdev.minor, ret ); + return ret; + } + + /* Allocate and initialize the shared area. */ +#ifdef SHARED_AREA_PHYS +#if SHARED_AREA_SIZE < PAGE_ALIGN(sizeof(SH772xGfxSharedArea)) +#error SHARED_AREA_SIZE < PAGE_ALIGN(sizeof(SH772xGfxSharedArea))! +#endif + shared = ioremap( SHARED_AREA_PHYS, PAGE_ALIGN(sizeof(SH772xGfxSharedArea)) ); +#else + shared_order = get_order(sizeof(SH772xGfxSharedArea)); + shared_page = alloc_pages( GFP_DMA | GFP_KERNEL, shared_order ); + shared = ioremap( virt_to_phys( page_address(shared_page) ), + PAGE_ALIGN(sizeof(SH772xGfxSharedArea)) ); + + for (i=0; i<1< + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License v2 + * as published by the Free Software Foundation. + */ + +#ifndef __SH7723_H__ +#define __SH7723_H__ + +int sh7723_init( void ); +void sh7723_exit( void ); + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_driver.c b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_driver.c new file mode 100755 index 0000000..aba270b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_driver.c @@ -0,0 +1,82 @@ +/* + * SH7722/SH7723 Graphics Device + * + * Copyright (C) 2006-2008 IGEL Co.,Ltd + * + * Written by Denis Oliver Kropp + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License v2 + * as published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "sh7722.h" +#include "sh7723.h" + + +/**********************************************************************************************************************/ + +static int sh772x_init = 0; + +/**********************************************************************************************************************/ + +static int __init +sh772x_driver_init( void ) +{ + int ret = -ENODEV; + + if ((ctrl_inl(CCN_PVR) & 0xffff00) == 0x300800) { + switch (ctrl_inl(CCN_PRR) & 0xf00) { + case 0xa00: + ret = sh7722_init(); + if (ret) + return ret; + + sh772x_init = 7722; + break; + + case 0x500: + ret = sh7723_init(); + if (ret) + return ret; + + sh772x_init = 7723; + break; + } + } + + return ret; +} + +module_init( sh772x_driver_init ); + +/**********************************************************************************************************************/ + +static void __exit +sh772x_driver_exit( void ) +{ + switch (sh772x_init) { + case 7722: + sh7722_exit(); + break; + + case 7723: + sh7723_exit(); + break; + } +} + +module_exit( sh772x_driver_exit ); + +/**********************************************************************************************************************/ + +MODULE_AUTHOR( "Denis Oliver Kropp & Janine Kropp " ); +MODULE_LICENSE( "GPL v2" ); + diff --git a/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_gfx.h b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_gfx.h new file mode 100755 index 0000000..7c1abb5 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/kernel-module/sh772x_gfx.h @@ -0,0 +1,105 @@ +#ifndef __SH772X_GFX_H__ +#define __SH772X_GFX_H__ + +#include + + +#define SH772xGFX_BUFFER_WORDS 0x1f000 /* Number of 32bit words in display list (ring buffer). */ + +#define SH7722GFX_SHARED_MAGIC 0x77220001 /* Increase if binary compatibility is broken. */ +#define SH7723GFX_SHARED_MAGIC 0x77230001 /* Increase if binary compatibility is broken. */ + +#define SH7722GFX_JPEG_RELOAD_SIZE (64 * 1024) +#define SH7722GFX_JPEG_LINEBUFFER_PITCH (2560) +#define SH7722GFX_JPEG_LINEBUFFER_HEIGHT (16) +#define SH7722GFX_JPEG_LINEBUFFER_SIZE (SH7722GFX_JPEG_LINEBUFFER_PITCH * SH7722GFX_JPEG_LINEBUFFER_HEIGHT * 2) +#define SH7722GFX_JPEG_LINEBUFFER_SIZE_Y (SH7722GFX_JPEG_LINEBUFFER_PITCH * SH7722GFX_JPEG_LINEBUFFER_HEIGHT) +#define SH7722GFX_JPEG_SIZE (SH7722GFX_JPEG_LINEBUFFER_SIZE * 2 + SH7722GFX_JPEG_RELOAD_SIZE * 2) + + +typedef volatile struct { + u32 buffer[SH772xGFX_BUFFER_WORDS]; + + + int hw_start; + int hw_end; + + int hw_running; + + + int next_start; + int next_end; + + int next_valid; + + + unsigned long buffer_phys; + + unsigned int num_words; + unsigned int num_starts; + unsigned int num_done; + unsigned int num_interrupts; + unsigned int num_wait_idle; + unsigned int num_wait_next; + unsigned int num_idle; + + u32 jpeg_ints; + unsigned long jpeg_phys; + + u32 magic; +} SH772xGfxSharedArea; + + +typedef struct { + u32 address; /* in */ + u32 value; /* in/out */ +} SH772xRegister; + + +typedef enum { + SH7722_JPEG_START, + SH7722_JPEG_RUN, + SH7722_JPEG_END +} SH7722JPEGState; + +typedef enum { + SH7722_JPEG_FLAG_RELOAD = 0x00000001, /* enable reload mode */ + SH7722_JPEG_FLAG_CONVERT = 0x00000002, /* enable conversion through VEU */ + SH7722_JPEG_FLAG_ENCODE = 0x00000004 /* set encoding mode */ +} SH7722JPEGFlags; + +typedef struct { + SH7722JPEGState state; /* starting, running or ended (done/error) */ + SH7722JPEGFlags flags; /* control decoding options */ + + u32 buffers; /* input = loaded buffers, output = buffers to reload */ + u32 error; /* valid in END state, non-zero means error */ + + unsigned long phys; /* needed in case of scaling, prevents rounding errors */ + int height; + int inputheight; +} SH7722JPEG; + + +/* Just initialization and synchronization. + * Hardware is started from user space via MMIO to DMA registers. */ +#define SH772xGFX_IOCTL_RESET _IO( 'G', 0 ) +#define SH772xGFX_IOCTL_WAIT_IDLE _IO( 'G', 1 ) +#define SH772xGFX_IOCTL_WAIT_NEXT _IO( 'G', 2 ) + +/* JPEG processing, requires programming from user space. */ +#define SH7722GFX_IOCTL_WAIT_JPEG _IO ( 'J', 0 ) +#define SH7722GFX_IOCTL_RUN_JPEG _IOWR( 'J', 1, SH7722JPEG ) +#define SH7722GFX_IOCTL_LOCK_JPEG _IO ( 'J', 2 ) +#define SH7722GFX_IOCTL_UNLOCK_JPEG _IO ( 'J', 3 ) + + +/* Register access limited to BEU, LCDC, VOU and JPU. */ +#define SH772xGFX_IOCTL_SETREG32 _IOW( 'g', 0, SH772xRegister ) +#define SH772xGFX_IOCTL_GETREG32 _IOR( 'g', 1, SH772xRegister ) + +/* Generic IOCTL to power the display, do this after programming the LCD Controller */ +#define SH772xGFX_IOCTL_POWER_DISPLAY _IO( 'k', 0 ) + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722.c new file mode 100755 index 0000000..4d09928 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722.c @@ -0,0 +1,490 @@ +#ifdef SH7722_DEBUG_DRIVER +#define DIRECT_ENABLE_DEBUG +#endif + +#include +#include + +#undef HAVE_STDLIB_H + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include + +DFB_GRAPHICS_DRIVER( sh7722 ) + + +#include "sh7722.h" +#include "sh7722_blt.h" +#include "sh7722_jpeglib.h" +#include "sh7722_layer.h" +#include "sh7722_lcd.h" +#include "sh7722_multi.h" +#include "sh7722_screen.h" + +#include "sh7723_blt.h" + +#ifdef SH772X_FBDEV_SUPPORT +#include +#include +#endif + + +D_DEBUG_DOMAIN( SH7722_Driver, "SH7722/Driver", "Renesas SH7722 Driver" ); + +/**********************************************************************************************************************/ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + return dfb_gfxcard_get_accelerator( device ) == 0x2D47; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "Renesas SH772x Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Denis & Janine Kropp" ); + + info->version.major = 0; + info->version.minor = 9; + + info->driver_data_size = sizeof(SH7722DriverData); + info->device_data_size = sizeof(SH7722DeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + DFBResult ret; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = device_data; + + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + /* Keep pointer to shared device data. */ + sdrv->dev = device_data; + + /* Keep core and device pointer. */ + sdrv->core = core; + sdrv->device = device; + + /* Open the drawing engine device. */ + sdrv->gfx_fd = direct_try_open( "/dev/sh772x_gfx", "/dev/misc/sh772x_gfx", O_RDWR, true ); + if (sdrv->gfx_fd < 0) + return DFB_INIT; + + /* Map its shared data. */ + sdrv->gfx_shared = mmap( NULL, direct_page_align( sizeof(SH772xGfxSharedArea) ), + PROT_READ | PROT_WRITE, + MAP_SHARED, sdrv->gfx_fd, 0 ); + if (sdrv->gfx_shared == MAP_FAILED) { + D_PERROR( "SH7722/Driver: Could not map shared area!\n" ); + close( sdrv->gfx_fd ); + return DFB_INIT; + } + + sdrv->mmio_base = dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!sdrv->mmio_base) { + D_PERROR( "SH7722/Driver: Could not map MMIO area!\n" ); + munmap( (void*) sdrv->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + close( sdrv->gfx_fd ); + return DFB_INIT; + } + + /* Check the magic value. */ + switch (sdrv->gfx_shared->magic) { + case SH7722GFX_SHARED_MAGIC: + sdev->sh772x = 7722; + + /* Initialize function table. */ + funcs->EngineReset = sh7722EngineReset; + funcs->EngineSync = sh7722EngineSync; + funcs->EmitCommands = sh7722EmitCommands; + funcs->CheckState = sh7722CheckState; + funcs->SetState = sh7722SetState; + funcs->FillTriangle = sh7722FillTriangle; + funcs->Blit = sh7722Blit; + funcs->StretchBlit = sh7722StretchBlit; + funcs->FlushTextureCache = sh7722FlushTextureCache; + + /* Initialize JPEG library. */ + ret = SH7722_JPEG_Initialize(); + if (ret) { + D_DERROR( ret, "SH7722/Driver: JPEG initialization failed!\n" ); + dfb_gfxcard_unmap_mmio( device, sdrv->mmio_base, -1 ); + munmap( (void*) sdrv->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + close( sdrv->gfx_fd ); + return DFB_INIT; + } + break; + + case SH7723GFX_SHARED_MAGIC: + sdev->sh772x = 7723; + + /* Initialize function table. */ + funcs->EngineReset = sh7723EngineReset; + funcs->EngineSync = sh7723EngineSync; + funcs->EmitCommands = sh7723EmitCommands; + funcs->CheckState = sh7723CheckState; + funcs->SetState = sh7723SetState; + funcs->FillRectangle = sh7723FillRectangle; + funcs->FillTriangle = sh7723FillTriangle; + funcs->DrawRectangle = sh7723DrawRectangle; + funcs->DrawLine = sh7723DrawLine; + funcs->Blit = sh7723Blit; + break; + + default: + D_ERROR( "SH772x/Driver: Magic value 0x%08x doesn't match 0x%08x or 0x%08x!\n", + sdrv->gfx_shared->magic, SH7722GFX_SHARED_MAGIC, SH7723GFX_SHARED_MAGIC ); + dfb_gfxcard_unmap_mmio( device, sdrv->mmio_base, -1 ); + munmap( (void*) sdrv->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + close( sdrv->gfx_fd ); + return DFB_INIT; + } + + + /* Get virtual address for the LCD buffer in slaves here, + master does it in driver_init_device(). */ +#ifndef SH772X_FBDEV_SUPPORT + if (!dfb_core_is_master( core )) + sdrv->lcd_virt = dfb_gfxcard_memory_virtual( device, sdev->lcd_offset ); +#endif + + + /* Register primary screen. */ + sdrv->screen = dfb_screens_register( device, driver_data, &sh7722ScreenFuncs ); + + /* Register three input system layers. */ + sdrv->input1 = dfb_layers_register( sdrv->screen, driver_data, &sh7722LayerFuncs ); + sdrv->input2 = dfb_layers_register( sdrv->screen, driver_data, &sh7722LayerFuncs ); + sdrv->input3 = dfb_layers_register( sdrv->screen, driver_data, &sh7722LayerFuncs ); + + /* Register multi window layer. */ + sdrv->multi = dfb_layers_register( sdrv->screen, driver_data, &sh7722MultiLayerFuncs ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = device_data; + + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + /* FIXME: Add a runtime option / config file. */ + sdev->lcd_format = DSPF_RGB16; + + /* Check format of LCD buffer. */ + switch (sdev->lcd_format) { + case DSPF_RGB16: + case DSPF_NV16: + break; + + default: + return DFB_UNSUPPORTED; + } + + if (sdev->sh772x == 7723) + memset( dfb_gfxcard_memory_virtual(device,0), 0, dfb_gfxcard_memory_length() ); + + /* + * Setup LCD buffer. + */ +#ifdef SH772X_FBDEV_SUPPORT + { + struct fb_fix_screeninfo fsi; + struct fb_var_screeninfo vsi; + int fbdev; + + if ((fbdev = open("/dev/fb", O_RDONLY)) < 0) { + D_ERROR( "SH7722/Driver: Can't open fbdev to get LCDC info!\n" ); + return DFB_FAILURE; + } + + if (ioctl(fbdev, FBIOGET_FSCREENINFO, &fsi) < 0) { + D_ERROR( "SH7722/Driver: FBIOGET_FSCREEINFO failed.\n" ); + close(fbdev); + return DFB_FAILURE; + } + + if (ioctl(fbdev, FBIOGET_VSCREENINFO, &vsi) < 0) { + D_ERROR( "SH7722/Driver: FBIOGET_VSCREEINFO failed.\n" ); + close(fbdev); + return DFB_FAILURE; + } + + sdev->lcd_width = vsi.xres; + sdev->lcd_height = vsi.yres; + sdev->lcd_pitch = fsi.line_length; + sdev->lcd_size = fsi.smem_len; + sdev->lcd_offset = 0; + sdev->lcd_phys = fsi.smem_start; +#if 0 + sdrv->lcd_virt = mmap(NULL, fsi.smem_len, PROT_READ | PROT_WRITE, MAP_SHARED, + fbdev, 0); + if (sdrv->lcd_virt == MAP_FAILED) { + D_PERROR( "SH7722/Driver: mapping fbdev failed.\n" ); + close(fbdev); + return DFB_FAILURE; + } + + /* Clear LCD buffer. */ + switch (sdev->lcd_format) { + case DSPF_RGB16: + memset( (void*) sdrv->lcd_virt, 0x00, sdev->lcd_height * sdev->lcd_pitch ); + break; + + case DSPF_NV16: + memset( (void*) sdrv->lcd_virt, 0x10, sdev->lcd_height * sdev->lcd_pitch ); + memset( (void*) sdrv->lcd_virt + sdev->lcd_height * sdev->lcd_pitch, 0x80, sdev->lcd_height * sdev->lcd_pitch ); + break; + + default: + D_BUG( "unsupported format" ); + return DFB_BUG; + } +#endif + + close(fbdev); + } +#else + sdev->lcd_width = SH7722_LCD_WIDTH; + sdev->lcd_height = SH7722_LCD_HEIGHT; + sdev->lcd_pitch = (DFB_BYTES_PER_LINE( sdev->lcd_format, sdev->lcd_width ) + 0xf) & ~0xf; + sdev->lcd_size = DFB_PLANE_MULTIPLY( sdev->lcd_format, sdev->lcd_height ) * sdev->lcd_pitch; + sdev->lcd_offset = dfb_gfxcard_reserve_memory( device, sdev->lcd_size ); + + if (sdev->lcd_offset < 0) { + D_ERROR( "SH7722/Driver: Allocating %d bytes for the LCD buffer failed!\n", sdev->lcd_size ); + return DFB_FAILURE; + } + + sdev->lcd_phys = dfb_gfxcard_memory_physical( device, sdev->lcd_offset ); + + /* Get virtual addresses for LCD buffer in master here, + slaves do it in driver_init_driver(). */ + sdrv->lcd_virt = dfb_gfxcard_memory_virtual( device, sdev->lcd_offset ); +#endif + + D_INFO( "SH7722/LCD: Allocated %dx%d %s Buffer (%d bytes) at 0x%08lx (%p)\n", + sdev->lcd_width, sdev->lcd_height, dfb_pixelformat_name(sdev->lcd_format), + sdev->lcd_size, sdev->lcd_phys, sdrv->lcd_virt ); + + D_ASSERT( ! (sdev->lcd_pitch & 0xf) ); + D_ASSERT( ! (sdev->lcd_phys & 0xf) ); + + /* + * Initialize hardware. + */ + + switch (sdev->sh772x) { + case 7722: + /* Reset the drawing engine. */ + sh7722EngineReset( sdrv, sdev ); + + /* Fill in the device info. */ + snprintf( device_info->name, DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "SH7722" ); + snprintf( device_info->vendor, DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Renesas" ); + + /* Set device limitations. */ + device_info->limits.surface_byteoffset_alignment = 16; + device_info->limits.surface_bytepitch_alignment = 8; + + /* Set device capabilities. */ + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = SH7722_SUPPORTED_DRAWINGFUNCTIONS | + SH7722_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = SH7722_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = SH7722_SUPPORTED_BLITTINGFLAGS; + + /* Change font format for acceleration. */ + if (!dfb_config->software_only) { + dfb_config->font_format = DSPF_ARGB; + dfb_config->font_premult = false; + } + break; + + case 7723: + /* Reset the drawing engine. */ + sh7723EngineReset( sdrv, sdev ); + + /* Fill in the device info. */ + snprintf( device_info->name, DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "SH7723" ); + snprintf( device_info->vendor, DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "Renesas" ); + + /* Set device limitations. */ + device_info->limits.surface_byteoffset_alignment = 512; + device_info->limits.surface_bytepitch_alignment = 64; + + /* Set device capabilities. */ + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = SH7723_SUPPORTED_DRAWINGFUNCTIONS | \ + SH7723_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = SH7723_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = SH7723_SUPPORTED_BLITTINGFLAGS; + + break; + + default: + D_BUG( "unexpected device" ); + return DFB_BUG; + } + + + /* Wait for idle BEU. */ + while (SH7722_GETREG32( sdrv, BSTAR ) & 1); + + /* Disable all inputs. */ + SH7722_SETREG32( sdrv, BESTR, 0 ); + + /* Disable all multi windows. */ + SH7722_SETREG32( sdrv, BMWCR0, SH7722_GETREG32( sdrv, BMWCR0 ) & ~0xf ); + +#ifndef SH772X_FBDEV_SUPPORT + /* Clear LCD buffer. */ + switch (sdev->lcd_format) { + case DSPF_RGB16: + memset( (void*) sdrv->lcd_virt, 0x00, sdev->lcd_height * sdev->lcd_pitch ); + break; + + case DSPF_NV16: + memset( (void*) sdrv->lcd_virt, 0x10, sdev->lcd_height * sdev->lcd_pitch ); + memset( (void*) sdrv->lcd_virt + sdev->lcd_height * sdev->lcd_pitch, 0x80, sdev->lcd_height * sdev->lcd_pitch ); + break; + + default: + D_BUG( "unsupported format" ); + return DFB_BUG; + } +#endif + + /* + * TODO: Make LCD Buffer format and primary BEU format runtime configurable. + */ + + /* Set output pixel format of the BEU. */ + switch (sdev->lcd_format) { + case DSPF_RGB16: + SH7722_SETREG32( sdrv, BPKFR, BPKFR_RY_RGB | WPCK_RGB16 ); + break; + + case DSPF_NV16: + SH7722_SETREG32( sdrv, BPKFR, BPKFR_RY_RGB | BPKFR_TE_ENABLED | CHDS_YCBCR422 ); + SH7722_SETREG32( sdrv, BDACR, sdev->lcd_phys + sdev->lcd_height * sdev->lcd_pitch ); + break; + + default: + D_BUG( "unsupported format" ); + return DFB_BUG; + } + + SH7722_SETREG32( sdrv, BPROCR, 0x00000000 ); + + /* Have BEU render into LCD buffer. */ + SH7722_SETREG32( sdrv, BBLCR1, MT_MEMORY ); + SH7722_SETREG32( sdrv, BDAYR, sdev->lcd_phys & 0xfffffffc ); + SH7722_SETREG32( sdrv, BDMWR, sdev->lcd_pitch & 0x0003fffc ); + +#ifndef SH772X_FBDEV_SUPPORT + /* Setup LCD controller to show the buffer. */ + sh7722_lcd_setup( sdrv, sdev->lcd_width, sdev->lcd_height, + sdev->lcd_phys, sdev->lcd_pitch, sdev->lcd_format, false ); +#endif + + /* Initialize BEU lock. */ + fusion_skirmish_init( &sdev->beu_lock, "BEU", dfb_core_world(sdrv->core) ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + SH7722DeviceData *sdev = device_data; + + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + /* Destroy BEU lock. */ + fusion_skirmish_destroy( &sdev->beu_lock ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + SH7722DriverData *sdrv = driver_data; + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + + (void) shared; + + D_DEBUG_AT( SH7722_Driver, "%s()\n", __FUNCTION__ ); + + D_INFO( "SH7722/BLT: %u starts, %u done, %u interrupts, %u wait_idle, %u wait_next, %u idle\n", + shared->num_starts, shared->num_done, shared->num_interrupts, + shared->num_wait_idle, shared->num_wait_next, shared->num_idle ); + + D_INFO( "SH7722/BLT: %u words, %u words/start, %u words/idle, %u starts/idle\n", + shared->num_words, + shared->num_words / shared->num_starts, + shared->num_words / shared->num_idle, + shared->num_starts / shared->num_idle ); + + /* Shutdown JPEG library. */ + SH7722_JPEG_Shutdown(); + + /* Unmap shared area. */ + munmap( (void*) sdrv->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + + /* Close Drawing Engine device. */ + close( sdrv->gfx_fd ); +} + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722.h new file mode 100755 index 0000000..0a80512 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722.h @@ -0,0 +1,131 @@ +#ifndef __SH7722__SH7722_H__ +#define __SH7722__SH7722_H__ + +#include + +#include + +#include "sh7722_regs.h" +#include "sh7722_types.h" + + +#define SH772X_FBDEV_SUPPORT +// #define JPU_SUPPORT + +/****************************************************************************** + * Platform specific values (FIXME: add runtime config) + */ + +#define ALGO_AP325 +#undef SH7722_ALGO_PANEL + +/* LCD Panel Configuration */ +#if defined(SH7722_ALGO_PANEL) +# define SH7722_LCD_WIDTH 640 +# define SH7722_LCD_HEIGHT 480 +#elif defined(ALGO_AP325) +# define SH7722_LCD_WIDTH 800 +# define SH7722_LCD_HEIGHT 480 +#else +# define SH7722_LCD_WIDTH 800 +# define SH7722_LCD_HEIGHT 480 +#endif + + +/****************************************************************************** + * Register access + */ + +//#define SH7722_TDG_REG_USE_IOCTLS + +#ifdef SH7722_TDG_REG_USE_IOCTLS +static inline u32 +SH7722_TDG_GETREG32( SH7722DriverData *sdrv, + u32 address ) +{ + SH772xRegister reg = { address, 0 }; + + if (ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_GETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_GETREG32( 0x%08x )\n", reg.address ); + + return reg.value; +} + +static inline void +SH7722_TDG_SETREG32( SH7722DriverData *sdrv, + u32 address, + u32 value ) +{ + SH772xRegister reg = { address, value }; + + if (ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_SETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_SETREG32( 0x%08x, 0x%08x )\n", reg.address, reg.value ); +} +#else +static inline u32 +SH7722_TDG_GETREG32( SH7722DriverData *sdrv, + u32 address ) +{ + D_ASSERT( address >= dfb_config->mmio_phys ); + D_ASSERT( address < (dfb_config->mmio_phys + dfb_config->mmio_length) ); + + return *(volatile u32*)(sdrv->mmio_base + (address - dfb_config->mmio_phys)); +} + +static inline void +SH7722_TDG_SETREG32( SH7722DriverData *sdrv, + u32 address, + u32 value ) +{ + D_ASSERT( address >= dfb_config->mmio_phys ); + D_ASSERT( address < (dfb_config->mmio_phys + dfb_config->mmio_length) ); + + *(volatile u32*)(sdrv->mmio_base + (address - dfb_config->mmio_phys)) = value; +} +#endif + + +static inline u32 +SH7722_GETREG32( SH7722DriverData *sdrv, + u32 address ) +{ + SH772xRegister reg = { address, 0 }; + + if (ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_GETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_GETREG32( 0x%08x )\n", reg.address ); + + return reg.value; +} + +static inline void +SH7722_SETREG32( SH7722DriverData *sdrv, + u32 address, + u32 value ) +{ + SH772xRegister reg = { address, value }; + + if (ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_SETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_SETREG32( 0x%08x, 0x%08x )\n", reg.address, reg.value ); +} + + +static inline void +BEU_Start( SH7722DriverData *sdrv, + SH7722DeviceData *sdev ) +{ + /* Wait for idle BEU. */ + while (SH7722_GETREG32( sdrv, BSTAR ) & 1); + + /* Start operation! */ + SH7722_SETREG32( sdrv, BESTR, (sdev->input_mask << 8) | 1 ); +} + +static inline void +BEU_Wait( SH7722DriverData *sdrv, + SH7722DeviceData *sdev ) +{ + /* Wait for idle BEU. */ + while (SH7722_GETREG32( sdrv, BSTAR ) & 1); +} + +#endif diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.c new file mode 100755 index 0000000..ec373f8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.c @@ -0,0 +1,2013 @@ +#ifdef SH7722_DEBUG_BLT +#define DIRECT_ENABLE_DEBUG +#endif + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "sh7722.h" +#include "sh7722_blt.h" + + +D_DEBUG_DOMAIN( SH7722_BLT, "SH7722/BLT", "Renesas SH7722 Drawing Engine" ); + +D_DEBUG_DOMAIN( SH7722_StartStop, "SH7722/StartStop", "Renesas SH7722 Drawing Start/Stop" ); + +/* + * State validation flags. + * + * There's no prefix because of the macros below. + */ +enum { + DEST = 0x00000001, + CLIP = 0x00000002, + DEST_CLIP = 0x00000003, + + SOURCE = 0x00000010, + MASK = 0x00000020, + + COLOR = 0x00000100, + + COLOR_KEY = 0x00001000, + COLOR_CHANGE = 0x00002000, + + BLENDING = 0x00010000, + + MATRIX = 0x00100000, + + BLIT_OP = 0x01000000, + + ALL = 0x01113133 +}; + +/* + * Map pixel formats. + */ +static int pixel_formats[DFB_NUM_PIXELFORMATS]; + +__attribute__((constructor)) static void initialization( void ) +{ + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB32) ] = 0; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_ARGB) ] = 0; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB16) ] = 1; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB555) ] = 2; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_ARGB1555)] = 3; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_ARGB4444)] = 4; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB444) ] = 4; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB18) ] = 6; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_ARGB1666)] = 6; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_ARGB6666)] = 6; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_RGB24) ] = 7; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_A1) ] = 8; + pixel_formats[DFB_PIXELFORMAT_INDEX(DSPF_A8) ] = 10; +} + +/* + * State handling macros. + */ + +#define SH7722_VALIDATE(flags) do { sdev->v_flags |= (flags); } while (0) +#define SH7722_INVALIDATE(flags) do { sdev->v_flags &= ~(flags); } while (0) + +#define SH7722_CHECK_VALIDATE(flag) do { \ + if ((sdev->v_flags & flag) != flag) \ + sh7722_validate_##flag( sdrv, sdev, state ); \ + } while (0) + +#define DUMP_INFO() D_DEBUG_AT( SH7722_BLT, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + +#define AA_COEF 133 + +/**********************************************************************************************************************/ + +static bool sh7722FillRectangle ( void *drv, void *dev, DFBRectangle *rect ); +static bool sh7722FillRectangleMatrixAA( void *drv, void *dev, DFBRectangle *rect ); + +static bool sh7722DrawRectangle ( void *drv, void *dev, DFBRectangle *rect ); +static bool sh7722DrawRectangleMatrixAA( void *drv, void *dev, DFBRectangle *rect ); + +static bool sh7722DrawLine ( void *drv, void *dev, DFBRegion *line ); +static bool sh7722DrawLineMatrix ( void *drv, void *dev, DFBRegion *line ); +static bool sh7722DrawLineAA ( void *drv, void *dev, DFBRegion *line ); + +/**********************************************************************************************************************/ + +static inline bool +check_blend_functions( const CardState *state ) +{ + switch (state->src_blend) { + case DSBF_ZERO: + case DSBF_ONE: + case DSBF_DESTCOLOR: + case DSBF_INVDESTCOLOR: + case DSBF_SRCALPHA: + case DSBF_INVSRCALPHA: + case DSBF_DESTALPHA: + case DSBF_INVDESTALPHA: + return true; + + default: + break; + } + switch (state->dst_blend) { + case DSBF_ZERO: + case DSBF_ONE: + case DSBF_SRCCOLOR: + case DSBF_INVSRCCOLOR: + case DSBF_SRCALPHA: + case DSBF_INVSRCALPHA: + case DSBF_DESTALPHA: + case DSBF_INVDESTALPHA: + return true; + + default: + break; + } + + return false; +} + +/**********************************************************************************************************************/ + +static inline bool +start_hardware( SH7722DriverData *sdrv ) +{ + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + if (shared->hw_running || !shared->next_valid || shared->next_end == shared->next_start) + return false; + + shared->hw_running = true; + shared->hw_start = shared->next_start; + shared->hw_end = shared->next_end; + + shared->next_start = shared->next_end = (shared->hw_end + 1 + 3) & ~3; + shared->next_valid = false; + + shared->num_words += shared->hw_end - shared->hw_start; + + shared->num_starts++; + + DUMP_INFO(); + + D_ASSERT( shared->buffer[shared->hw_end] == 0xF0000000 ); + + SH7722_TDG_SETREG32( sdrv, BEM_HC_DMA_ADR, shared->buffer_phys + shared->hw_start*4 ); + SH7722_TDG_SETREG32( sdrv, BEM_HC_DMA_START, 1 ); + + return true; +} + +__attribute__((noinline)) +static void +flush_prepared( SH7722DriverData *sdrv ) +{ + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + unsigned int timeout = 2; + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + D_ASSERT( sdrv->prep_num < SH772xGFX_BUFFER_WORDS ); + D_ASSERT( sdrv->prep_num <= D_ARRAY_SIZE(sdrv->prep_buf) ); + + /* Something prepared? */ + while (sdrv->prep_num) { + int next_end; + + /* Mark shared information as invalid. From this point on the interrupt handler + * will not continue with the next block, and we'll start the hardware ourself. */ + shared->next_valid = false; + + /* Check if there's enough space at the end. + * Wait until hardware has started next block before it gets too big. */ + if (shared->next_end + sdrv->prep_num >= SH772xGFX_BUFFER_WORDS || + shared->next_end - shared->next_start >= SH772xGFX_BUFFER_WORDS/4) + { + /* If there's no next block waiting, start at the beginning. */ + if (shared->next_start == shared->next_end) + shared->next_start = shared->next_end = 0; + else { + D_ASSERT( shared->buffer[shared->hw_end] == 0xF0000000 ); + + /* Mark area as valid again. */ + shared->next_valid = true; + + /* Start in case it got idle while doing the checks. */ + if (!start_hardware( sdrv )) { + /* + * Hardware has not been started (still running). + * Check for timeout. */ + if (!timeout--) { + D_ERROR( "SH7722/Blt: Timeout waiting for processing!\n" ); + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + D_ASSERT( shared->buffer[shared->hw_end] == 0xF0000000 ); + sh7722EngineReset( sdrv, sdrv->dev ); + } + + /* Wait til next block is started. */ + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_NEXT ); + } + + /* Start over with the checks. */ + continue; + } + } + + /* We are appending in case there was already a next block. */ + next_end = shared->next_end + sdrv->prep_num; + + /* Reset the timeout counter. */ + timeout = 2; + + /* While the hardware is running... */ + while (shared->hw_running) { + D_ASSERT( shared->buffer[shared->hw_end] == 0xF0000000 ); + + /* ...make sure we don't over lap with its current buffer, otherwise wait. */ + if (shared->hw_start > next_end || shared->hw_end < shared->next_start) + break; + + /* Check for timeout. */ + if (!timeout--) { + D_ERROR( "SH7722/Blt: Timeout waiting for space!\n" ); + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + D_ASSERT( shared->buffer[shared->hw_end] == 0xF0000000 ); + sh7722EngineReset( sdrv, sdrv->dev ); + } + + /* Wait til next block is started. */ + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_NEXT ); + } + + /* Copy from local to shared buffer. */ + direct_memcpy( (void*) &shared->buffer[shared->next_end], &sdrv->prep_buf[0], sdrv->prep_num * sizeof(__u32) ); + + /* Terminate the block. */ + shared->buffer[next_end] = 0xF0000000; + + /* Update next block information and mark valid. */ + shared->next_end = next_end; + shared->next_valid = true; + + /* Reset local counter. */ + sdrv->prep_num = 0; + } + + /* Start in case it is idle. */ + start_hardware( sdrv ); +} + +static inline __u32 * +start_buffer( SH7722DriverData *sdrv, + int space ) +{ + /* Check for space in local buffer. */ + if (sdrv->prep_num + space > SH7722GFX_MAX_PREPARE) { + /* Flush local buffer. */ + flush_prepared( sdrv ); + + D_ASSERT( sdrv->prep_num == 0 ); + } + + /* Return next write position. */ + return &sdrv->prep_buf[sdrv->prep_num]; +} + +static inline void +submit_buffer( SH7722DriverData *sdrv, + int entries ) +{ + D_ASSERT( sdrv->prep_num + entries <= SH7722GFX_MAX_PREPARE ); + + /* Increment next write position. */ + sdrv->prep_num += entries; +} + +/**********************************************************************************************************************/ + +static inline void +sh7722_validate_DEST_CLIP( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 10 ); + + D_DEBUG_AT( SH7722_BLT, "%s( 0x%08lx [%d] - %4d,%4d-%4dx%4d )\n", __FUNCTION__, + state->dst.phys, state->dst.pitch, DFB_RECTANGLE_VALS_FROM_REGION( &state->clip ) ); + + /* Set clip. */ + prep[0] = BEM_PE_SC0_MIN; + prep[1] = SH7722_XY( state->clip.x1, state->clip.y1 ); + + prep[2] = BEM_PE_SC0_MAX; + prep[3] = SH7722_XY( state->clip.x2, state->clip.y2 ); + + /* Only clip? */ + if (sdev->v_flags & DEST) { + submit_buffer( sdrv, 4 ); + } + else { + CoreSurface *surface = state->destination; + CoreSurfaceBuffer *buffer = state->dst.buffer; + + sdev->dst_phys = state->dst.phys; + sdev->dst_pitch = state->dst.pitch; + sdev->dst_bpp = DFB_BYTES_PER_PIXEL( buffer->format ); + sdev->dst_index = DFB_PIXELFORMAT_INDEX( buffer->format ) % DFB_NUM_PIXELFORMATS; + + /* Set destination. */ + prep[4] = BEM_PE_DST; + prep[5] = pixel_formats[sdev->dst_index]; + + prep[6] = BEM_PE_DST_BASE; + prep[7] = sdev->dst_phys; + + prep[8] = BEM_PE_DST_SIZE; + prep[9] = SH7722_XY( sdev->dst_pitch / sdev->dst_bpp, surface->config.size.h ); + + submit_buffer( sdrv, 10 ); + } + + /* Set the flags. */ + SH7722_VALIDATE( DEST_CLIP ); +} + +static inline void +sh7722_validate_SOURCE( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + CoreSurfaceBuffer *buffer = state->src.buffer; + __u32 *prep = start_buffer( sdrv, 6 ); + + sdev->src_phys = state->src.phys; + sdev->src_pitch = state->src.pitch; + sdev->src_bpp = DFB_BYTES_PER_PIXEL( buffer->format ); + sdev->src_index = DFB_PIXELFORMAT_INDEX( buffer->format ) % DFB_NUM_PIXELFORMATS; + + /* Set source. */ + prep[0] = BEM_TE_SRC; + prep[1] = pixel_formats[sdev->src_index]; + + prep[2] = BEM_TE_SRC_BASE; + prep[3] = sdev->src_phys; + + prep[4] = BEM_TE_SRC_SIZE; + prep[5] = SH7722_XY( sdev->src_pitch / sdev->src_bpp, surface->config.size.h ); + + submit_buffer( sdrv, 6 ); + + /* Set the flag. */ + SH7722_VALIDATE( SOURCE ); +} + +__attribute__((noinline)) +static void +sh7722_validate_MASK( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + CoreSurface *surface = state->source_mask; + CoreSurfaceBuffer *buffer = state->src_mask.buffer; + __u32 *prep = start_buffer( sdrv, 6 ); + + sdev->mask_phys = state->src_mask.phys; + sdev->mask_pitch = state->src_mask.pitch; + sdev->mask_format = buffer->format; + sdev->mask_index = DFB_PIXELFORMAT_INDEX( buffer->format ) % DFB_NUM_PIXELFORMATS; + sdev->mask_offset = state->src_mask_offset; + sdev->mask_flags = state->src_mask_flags; + + /* Set mask. */ + prep[0] = BEM_TE_MASK; + prep[1] = TE_MASK_ENABLE | pixel_formats[sdev->mask_index]; + + prep[2] = BEM_TE_MASK_SIZE; + prep[3] = SH7722_XY( sdev->mask_pitch / DFB_BYTES_PER_PIXEL(sdev->mask_format), surface->config.size.h ); + + prep[4] = BEM_TE_MASK_BASE; + prep[5] = sdev->mask_phys + sdev->mask_pitch * sdev->mask_offset.y + + DFB_BYTES_PER_LINE( sdev->mask_format, sdev->mask_offset.x ); + + submit_buffer( sdrv, 6 ); + + /* Set the flag. */ + SH7722_VALIDATE( MASK ); +} + +static inline void +sh7722_validate_COLOR( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 4 ); + + prep[0] = BEM_BE_COLOR1; + prep[1] = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + + prep[2] = BEM_WR_FGC; + prep[3] = prep[1]; + + submit_buffer( sdrv, 4 ); + + /* Set the flag. */ + SH7722_VALIDATE( COLOR ); +} + +__attribute__((noinline)) +static void +sh7722_validate_COLOR_KEY( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + CoreSurfaceBuffer *buffer = state->src.buffer; + __u32 *prep = start_buffer( sdrv, 4 ); + + prep[0] = BEM_PE_CKEY; + prep[1] = CKEY_EXCLUDE_ALPHA | CKEY_EXCLUDE_UNUSED | CKEY_B_ENABLE; + + prep[2] = BEM_PE_CKEY_B; + + switch (buffer->format) { + case DSPF_ARGB: + case DSPF_RGB32: + prep[3] = state->src_colorkey; + break; + + case DSPF_RGB16: + prep[3] = RGB16_TO_RGB32( state->src_colorkey ); + break; + + case DSPF_ARGB1555: + case DSPF_RGB555: + prep[3] = ARGB1555_TO_RGB32( state->src_colorkey ); + break; + + case DSPF_ARGB4444: + case DSPF_RGB444: + prep[3] = ARGB4444_TO_RGB32( state->src_colorkey ); + break; + + default: + D_BUG( "unexpected pixelformat" ); + } + + submit_buffer( sdrv, 4 ); + + /* Set the flag. */ + SH7722_VALIDATE( COLOR_KEY ); +} + +/* let compiler decide here :) */ +static void +sh7722_validate_COLOR_CHANGE( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 6 ); + + prep[0] = BEM_PE_COLORCHANGE; + prep[1] = COLORCHANGE_COMPARE_FIRST | COLORCHANGE_EXCLUDE_UNUSED; + + prep[2] = BEM_PE_COLORCHANGE_0; + prep[3] = 0xffffff; + + prep[4] = BEM_PE_COLORCHANGE_1; + prep[5] = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + + submit_buffer( sdrv, 6 ); + + /* Set the flag. */ + SH7722_VALIDATE( COLOR_CHANGE ); +} + +/* DSBF_UNKNOWN = 0 */ +/* BLE_DSTF_ZERO = 0 DSBF_ZERO = 1 */ +/* BLE_DSTF_ONE = 1 DSBF_ONE = 2 */ +/* BLE_DSTF_SRC = 2 DSBF_SRCCOLOR = 3 */ +/* BLE_DSTF_1_SRC = 3 DSBF_INVSRCCOLOR = 4 */ +/* BLE_DSTF_SRC_A = 4 DSBF_SRCALPHA = 5 */ +/* BLE_DSTF_1_SRC_A = 5 DSBF_INVSRCALPHA = 6 */ +/* BLE_DSTF_DST_A = 6 DSBF_DESTALPHA = 7 */ +/* BLE_DSTF_1_DST_A = 7 DSBF_INVDESTALPHA = 8 */ +/* DSBF_DESTCOLOR = 9 */ +/* Hey, matches!!? :-P DSBF_INVDESTCOLOR = 10 */ +/* DSBF_SRCALPHASAT = 11 */ + +static inline void +sh7722_validate_BLENDING( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 2 ); + + sdev->ble_dstf = (state->dst_blend - 1) & 7; + sdev->ble_srcf = ((state->src_blend - 1) & 7) << 4; + + prep[0] = BEM_PE_FIXEDALPHA; + prep[1] = (state->color.a << 24) | (state->color.a << 16); + + submit_buffer( sdrv, 2 ); + + /* Set the flag. */ + SH7722_VALIDATE( BLENDING ); +} + +__attribute__((noinline)) +static void +sh7722_validate_MATRIX( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 12 ); + + prep[0] = BEM_BE_MATRIX_A; + prep[1] = state->matrix[0]; + + prep[2] = BEM_BE_MATRIX_B; + prep[3] = state->matrix[1]; + + prep[4] = BEM_BE_MATRIX_C; + prep[5] = state->matrix[2]; + + prep[6] = BEM_BE_MATRIX_D; + prep[7] = state->matrix[3]; + + prep[8] = BEM_BE_MATRIX_E; + prep[9] = state->matrix[4]; + + prep[10] = BEM_BE_MATRIX_F; + prep[11] = state->matrix[5]; + + submit_buffer( sdrv, 12 ); + + /* Keep for CPU transformation of lines. */ + direct_memcpy( sdev->matrix, state->matrix, sizeof(s32) * 6 ); + + /* Set the flag. */ + SH7722_VALIDATE( MATRIX ); +} + +static inline void +sh7722_validate_BLIT_OP( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 2 ); + + prep[0] = BEM_PE_OPERATION; + prep[1] = BLE_FUNC_NONE; + + if (state->blittingflags & DSBLIT_XOR) + prep[1] |= BLE_ROP_XOR; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + prep[1] |= BLE_FUNC_AxB_plus_CxD | sdev->ble_srcf | sdev->ble_dstf; + + switch (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + case DSBLIT_BLEND_ALPHACHANNEL: + prep[1] |= BLE_SRCA_SOURCE_ALPHA; + break; + + case DSBLIT_BLEND_COLORALPHA: + prep[1] |= BLE_SRCA_FIXED; + break; + } + } + else if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) + prep[1] |= BLE_FUNC_AxB_plus_CxD | BLE_SRCA_ALPHA_CHANNEL | BLE_SRCF_SRC_A | BLE_DSTF_1_SRC_A; + + submit_buffer( sdrv, 2 ); + + /* Set the flag. */ + SH7722_VALIDATE( BLIT_OP ); +} + +/**********************************************************************************************************************/ + +__attribute__((noinline)) +static void +invalidate_ckey( SH7722DriverData *sdrv, SH7722DeviceData *sdev ) +{ + __u32 *prep = start_buffer( sdrv, 4 ); + + prep[0] = BEM_PE_CKEY; + prep[1] = 0; + + prep[2] = BEM_PE_CKEY_B; + prep[3] = 0; + + submit_buffer( sdrv, 4 ); + + sdev->ckey_b_enabled = false; + + SH7722_INVALIDATE( COLOR_KEY ); +} + +__attribute__((noinline)) +static void +invalidate_color_change( SH7722DriverData *sdrv, SH7722DeviceData *sdev ) +{ + __u32 *prep = start_buffer( sdrv, 2 ); + + prep[0] = BEM_PE_COLORCHANGE; + prep[1] = COLORCHANGE_DISABLE; + + submit_buffer( sdrv, 2 ); + + sdev->color_change_enabled = false; + + SH7722_INVALIDATE( COLOR_CHANGE ); +} + +__attribute__((noinline)) +static void +invalidate_mask( SH7722DriverData *sdrv, SH7722DeviceData *sdev ) +{ + u32 *prep = start_buffer( sdrv, 2 ); + + prep[0] = BEM_TE_MASK; + prep[1] = TE_MASK_DISABLE; + + submit_buffer( sdrv, 2 ); + + sdev->mask_enabled = false; + + SH7722_INVALIDATE( MASK ); +} + +/**********************************************************************************************************************/ + +DFBResult +sh7722EngineSync( void *drv, void *dev ) +{ + DFBResult ret = DFB_OK; + SH7722DriverData *sdrv = drv; + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + while (shared->hw_running && ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_IDLE ) < 0) { + if (errno == EINTR) + continue; + + ret = errno2result( errno ); + D_PERROR( "SH7722/BLT: SH7722GFX_IOCTL_WAIT_IDLE failed!\n" ); + + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + + break; + } + + if (ret == DFB_OK) { + D_ASSERT( !shared->hw_running ); + D_ASSERT( !shared->next_valid ); + } + + return ret; +} + +void +sh7722EngineReset( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep; + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_RESET ); + + prep = start_buffer( sdrv, 20 ); + + prep[0] = BEM_PE_OPERATION; + prep[1] = 0x00000000; + + prep[2] = BEM_PE_COLORCHANGE; + prep[3] = 0x00000000; + + prep[4] = BEM_PE_CKEY; + prep[5] = 0x00000000; + + prep[6] = BEM_PE_CKEY_B; + prep[7] = 0; + + prep[8] = BEM_PE_FIXEDALPHA; + prep[9] = 0x80000000; + + prep[10] = BEM_TE_SRC_CNV; + prep[11] = 0x00100010; /* full conversion of Ad, As, Cd and Cs */ + + prep[12] = BEM_TE_FILTER; + prep[13] = 0x00000000; /* 0 = nearest, 3 = up bilinear / down average */ + + prep[14] = BEM_PE_SC; + prep[15] = 0x00000001; /* enable clipping */ + + prep[16] = BEM_BE_ORIGIN; + prep[17] = SH7722_XY( 0, 0 ); + + prep[18] = BEM_TE_MASK_CNV; + prep[19] = 2; + + submit_buffer( sdrv, 20 ); + + sdev->ckey_b_enabled = false; + sdev->color_change_enabled = false; + sdev->mask_enabled = false; +} + +void +sh7722EmitCommands( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + flush_prepared( sdrv ); +} + +void +sh7722FlushTextureCache( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + __u32 *prep = start_buffer( sdrv, 4 ); + + D_DEBUG_AT( SH7722_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + prep[0] = BEM_PE_CACHE; + prep[1] = 2; + + prep[2] = BEM_TE_INVALID; + prep[3] = 1; + + submit_buffer( sdrv, 4 ); +} + +/**********************************************************************************************************************/ + +void +sh7722CheckState( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ) +{ + D_DEBUG_AT( SH7722_BLT, "%s( %p, 0x%08x )\n", __FUNCTION__, state, accel ); + + /* Return if the desired function is not supported at all. */ + if (accel & ~(SH7722_SUPPORTED_DRAWINGFUNCTIONS | SH7722_SUPPORTED_BLITTINGFUNCTIONS)) + return; + + /* Return if the destination format is not supported. */ + switch (state->destination->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB16: + case DSPF_ARGB1555: + case DSPF_RGB555: + case DSPF_ARGB4444: + case DSPF_RGB444: + break; + default: + return; + } + + /* Check if drawing or blitting is requested. */ + if (DFB_DRAWING_FUNCTION( accel )) { + /* Return if unsupported drawing flags are set. */ + if (state->drawingflags & ~SH7722_SUPPORTED_DRAWINGFLAGS) + return; + + /* Return if blending with unsupported blend functions is requested. */ + if (state->drawingflags & DSDRAW_BLEND) { + /* Check blend functions. */ + if (!check_blend_functions( state )) + return; + + /* XOR only without blending. */ + if (state->drawingflags & DSDRAW_XOR) + return; + } + + /* Enable acceleration of drawing functions. */ + state->accel |= SH7722_SUPPORTED_DRAWINGFUNCTIONS; + } + else { + DFBSurfaceBlittingFlags flags = state->blittingflags; + + /* Return if unsupported blitting flags are set. */ + if (flags & ~SH7722_SUPPORTED_BLITTINGFLAGS) + return; + + /* Return if the source format is not supported. */ + switch (state->source->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB16: + case DSPF_ARGB1555: + case DSPF_RGB555: + case DSPF_ARGB4444: + case DSPF_RGB444: + break; + + default: + return; + } + + /* Return if blending with unsupported blend functions is requested. */ + if (flags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + /* Check blend functions. */ + if (!check_blend_functions( state )) + return; + } + + /* XOR only without blending etc. */ + if (flags & DSBLIT_XOR && + flags & ~(DSBLIT_SRC_COLORKEY | DSBLIT_ROTATE180 | DSBLIT_XOR)) + return; + + /* Return if colorizing for non-font surfaces is requested. */ + if ((flags & DSBLIT_COLORIZE) && !(state->source->type & CSTF_FONT)) + return; + + /* Return if blending with both alpha channel and value is requested. */ + if (D_FLAGS_ARE_SET( flags, DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) + return; + + /* Mask checking. */ + if (flags & DSBLIT_SRC_MASK_ALPHA) { + if (!state->source_mask) + return; + + /* Return if the source mask format is not supported. */ + switch (state->source_mask->config.format) { + case DSPF_A1: + case DSPF_A8: + break; + + default: + return; + } + } + + /* Enable acceleration of blitting functions. */ + state->accel |= SH7722_SUPPORTED_BLITTINGFUNCTIONS; + } +} + +/* + * Make sure that the hardware is programmed for execution of 'accel' according to the 'state'. + */ +void +sh7722SetState( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + StateModificationFlags modified = state->mod_hw; + + D_DEBUG_AT( SH7722_BLT, "%s( %p, 0x%08x ) <- modified 0x%08x\n", + __FUNCTION__, state, accel, modified ); + DUMP_INFO(); + + /* + * 1) Invalidate hardware states + * + * Each modification to the hw independent state invalidates one or more hardware states. + */ + + /* Simply invalidate all? */ + if (modified == SMF_ALL) { + SH7722_INVALIDATE( ALL ); + } + else if (modified) { + /* Invalidate destination registers. */ + if (modified & SMF_DESTINATION) + SH7722_INVALIDATE( DEST ); + + /* Invalidate clipping registers. */ + if (modified & SMF_CLIP) + SH7722_INVALIDATE( CLIP ); + + /* Invalidate source registers. */ + if (modified & SMF_SOURCE) + SH7722_INVALIDATE( SOURCE | COLOR_KEY ); + else if (modified & SMF_SRC_COLORKEY) + SH7722_INVALIDATE( COLOR_KEY ); + + /* Invalidate mask registers. */ + if (modified & (SMF_SOURCE_MASK | SMF_SOURCE_MASK_VALS)) + SH7722_INVALIDATE( MASK ); + + /* Invalidate color registers. */ + if (modified & SMF_COLOR) + SH7722_INVALIDATE( BLENDING | COLOR | COLOR_CHANGE ); + else if (modified & (SMF_SRC_BLEND | SMF_SRC_BLEND)) + SH7722_INVALIDATE( BLENDING ); + + /* Invalidate matrix registers. */ + if (modified & SMF_MATRIX) + SH7722_INVALIDATE( MATRIX ); + + /* Invalidate blitting operation. */ + if (modified & SMF_BLITTING_FLAGS) + SH7722_INVALIDATE( BLIT_OP ); + } + + /* + * 2) Validate hardware states + * + * Each function has its own set of states that need to be validated. + */ + + /* Always requiring valid destination and clip. */ + SH7722_CHECK_VALIDATE( DEST_CLIP ); + + /* Use transformation matrix? */ + if (state->render_options & DSRO_MATRIX) + SH7722_CHECK_VALIDATE( MATRIX ); + + /* Depending on the function... */ + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + /* ...require valid color. */ + SH7722_CHECK_VALIDATE( COLOR ); + + /* Use blending? */ + if (state->drawingflags & DSDRAW_BLEND) { + /* need valid source and destination blend factors */ + SH7722_CHECK_VALIDATE( BLENDING ); + } + + /* Clear old ckeys */ + if (sdev->ckey_b_enabled) + invalidate_ckey( sdrv, sdev ); + + /* Clear old mask */ + if (sdev->mask_enabled) + invalidate_mask( sdrv, sdev ); + + /* Choose function. */ + switch (accel) { + case DFXL_FILLRECTANGLE: + if (state->render_options & (DSRO_MATRIX | DSRO_ANTIALIAS)) + funcs->FillRectangle = sh7722FillRectangleMatrixAA; + else + funcs->FillRectangle = sh7722FillRectangle; + break; + + case DFXL_DRAWRECTANGLE: + if (state->render_options & (DSRO_MATRIX | DSRO_ANTIALIAS)) + funcs->DrawRectangle = sh7722DrawRectangleMatrixAA; + else + funcs->DrawRectangle = sh7722DrawRectangle; + break; + + case DFXL_DRAWLINE: + if (state->render_options & DSRO_ANTIALIAS) + funcs->DrawLine = sh7722DrawLineAA; + else if (state->render_options & DSRO_MATRIX) + funcs->DrawLine = sh7722DrawLineMatrix; + else + funcs->DrawLine = sh7722DrawLine; + break; + + default: + break; + } + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = SH7722_SUPPORTED_DRAWINGFUNCTIONS; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + /* ...require valid source. */ + SH7722_CHECK_VALIDATE( SOURCE ); + + /* Use blending? */ + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + /* need valid source and destination blend factors */ + SH7722_CHECK_VALIDATE( BLENDING ); + } + + /* Use color keying? */ + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + /* Need valid color key settings (enabling). */ + SH7722_CHECK_VALIDATE( COLOR_KEY ); + + sdev->ckey_b_enabled = true; + } + /* Disable color keying? */ + else if (sdev->ckey_b_enabled) + invalidate_ckey( sdrv, sdev ); + + /* Use color change? */ + if (state->blittingflags & DSBLIT_COLORIZE) { + /* Need valid color change settings (enabling). */ + SH7722_CHECK_VALIDATE( COLOR_CHANGE ); + + sdev->color_change_enabled = true; + } + /* Disable color change? */ + else if (sdev->color_change_enabled) + invalidate_color_change( sdrv, sdev ); + + /* Use mask? */ + if (state->blittingflags & DSBLIT_SRC_MASK_ALPHA) { + /* need valid mask */ + SH7722_CHECK_VALIDATE( MASK ); + + sdev->mask_enabled = true; + } + /* Disable mask? */ + else if (sdev->mask_enabled) + invalidate_mask( sdrv, sdev ); + + SH7722_CHECK_VALIDATE( BLIT_OP ); + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = SH7722_SUPPORTED_BLITTINGFUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + sdev->dflags = state->drawingflags; + sdev->bflags = state->blittingflags; + sdev->render_options = state->render_options; + sdev->color = state->color; + + /* + * 4) Clear modification flags + * + * All flags have been evaluated in 1) and remembered for further validation. + * If the hw independent state is not modified, this function won't get called + * for subsequent rendering functions, unless they aren't defined by 3). + */ + state->mod_hw = 0; +} + +/**********************************************************************************************************************/ + +static inline void +draw_rectangle( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + int x1, int y1, + int x2, int y2, + int x3, int y3, + int x4, int y4, + bool antialias, + bool full ) +{ + u32 ctrl = antialias ? WR_CTRL_ANTIALIAS : 0; + u32 *prep = start_buffer( sdrv, full ? 24 : 12 ); + + if (antialias) { + prep[0] = BEM_WR_FGC; + prep[1] = PIXEL_ARGB( (sdev->color.a * AA_COEF) >> 8, + (sdev->color.r * AA_COEF) >> 8, + (sdev->color.g * AA_COEF) >> 8, + (sdev->color.b * AA_COEF) >> 8 ); + + prep[2] = BEM_PE_FIXEDALPHA; + prep[3] = (sdev->color.a * AA_COEF) << 16; + } + else { + prep[0] = BEM_WR_FGC; + prep[1] = PIXEL_ARGB( sdev->color.a, + sdev->color.r, + sdev->color.g, + sdev->color.b ); + + prep[2] = BEM_PE_FIXEDALPHA; + prep[3] = (sdev->color.a << 24) << (sdev->color.a << 16); + } + + prep[4] = BEM_WR_V1; + prep[5] = SH7722_XY( x1, y1 ); + + prep[6] = BEM_WR_V2; + prep[7] = SH7722_XY( x2, y2 ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) + : + (antialias ? + (BLE_FUNC_AxB_plus_CxD | + BLE_SRCF_ONE | + BLE_SRCA_FIXED | + BLE_DSTF_1_SRC_A) : BLE_FUNC_NONE + ); + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_WR_CTRL; + prep[11] = WR_CTRL_LINE | ctrl; + + if (full) { + prep[12] = BEM_WR_V2; + prep[13] = SH7722_XY( x3, y3 ); + prep[14] = BEM_WR_CTRL; + prep[15] = WR_CTRL_POLYLINE | ctrl; + + prep[16] = BEM_WR_V2; + prep[17] = SH7722_XY( x4, y4 ); + prep[18] = BEM_WR_CTRL; + prep[19] = WR_CTRL_POLYLINE | ctrl; + + prep[20] = BEM_WR_V2; + prep[21] = SH7722_XY( x1, y1 ); + prep[22] = BEM_WR_CTRL; + prep[23] = WR_CTRL_POLYLINE | ctrl; + + submit_buffer( sdrv, 24 ); + } + else { + prep[7] = SH7722_XY( x3, y3 ); + prep[11] |= WR_CTRL_ENDPOINT; + + submit_buffer( sdrv, 12 ); + } +} + +/* + * Render a filled rectangle using the current hardware state. + */ +static bool +sh7722FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 8 ); + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + prep[0] = BEM_BE_V1; + prep[1] = SH7722_XY( rect->x, rect->y ); + + prep[2] = BEM_BE_V2; + prep[3] = SH7722_XY( rect->w, rect->h ); + + prep[4] = BEM_PE_OPERATION; + prep[5] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[5] |= BLE_ROP_XOR; + + prep[6] = BEM_BE_CTRL; + prep[7] = BE_CTRL_RECTANGLE | BE_CTRL_SCANMODE_LINE; + + submit_buffer( sdrv, 8 ); + + return true; +} + +/* + * This version sends a quadrangle to have all four edges transformed. + */ +static bool +sh7722FillRectangleMatrixAA( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + + if (sdev->render_options & DSRO_ANTIALIAS) { + int x1 = rect->x; + int y1 = rect->y; + int x2 = rect->x + rect->w; + int y2 = rect->y; + int x3 = rect->x + rect->w; + int y3 = rect->y + rect->h; + int x4 = rect->x; + int y4 = rect->y + rect->h; + + if (sdev->render_options & DSRO_MATRIX) { + int t; + + t = ((x1 * sdev->matrix[0]) + + (y1 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y1 = ((x1 * sdev->matrix[3]) + + (y1 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x1 = t; + + t = ((x2 * sdev->matrix[0]) + + (y2 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y2 = ((x2 * sdev->matrix[3]) + + (y2 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x2 = t; + + t = ((x3 * sdev->matrix[0]) + + (y3 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y3 = ((x3 * sdev->matrix[3]) + + (y3 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x3 = t; + + t = ((x4 * sdev->matrix[0]) + + (y4 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y4 = ((x4 * sdev->matrix[3]) + + (y4 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x4 = t; + } + + prep = start_buffer( sdrv, 28 ); + + prep[0] = BEM_WR_FGC; + prep[1] = PIXEL_ARGB( (sdev->color.a * AA_COEF) >> 8, + (sdev->color.r * AA_COEF) >> 8, + (sdev->color.g * AA_COEF) >> 8, + (sdev->color.b * AA_COEF) >> 8 ); + + prep[2] = BEM_PE_FIXEDALPHA; + prep[3] = (sdev->color.a * AA_COEF) << 16; + + prep[4] = BEM_WR_V1; + prep[5] = SH7722_XY( x1, y1 ); + + prep[6] = BEM_WR_V2; + prep[7] = SH7722_XY( x2, y2 ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) + : + (BLE_FUNC_AxB_plus_CxD | + BLE_SRCF_ONE | + BLE_SRCA_FIXED | + BLE_DSTF_1_SRC_A); + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_WR_CTRL; + prep[11] = WR_CTRL_LINE | WR_CTRL_ANTIALIAS; + + if (rect->h > 1 && rect->w > 1) { + prep[12] = BEM_WR_V2; + prep[13] = SH7722_XY( x3, y3 ); + prep[14] = BEM_WR_CTRL; + prep[15] = WR_CTRL_POLYLINE | WR_CTRL_ANTIALIAS; + + prep[16] = BEM_WR_V2; + prep[17] = SH7722_XY( x4, y4 ); + prep[18] = BEM_WR_CTRL; + prep[19] = WR_CTRL_POLYLINE | WR_CTRL_ANTIALIAS; + + prep[20] = BEM_WR_V2; + prep[21] = SH7722_XY( x1, y1 ); + prep[22] = BEM_WR_CTRL; + prep[23] = WR_CTRL_POLYLINE | WR_CTRL_ANTIALIAS; + + prep[24] = BEM_WR_FGC; + prep[25] = PIXEL_ARGB( sdev->color.a, + sdev->color.r, + sdev->color.g, + sdev->color.b ); + + prep[26] = BEM_PE_FIXEDALPHA; + prep[27] = (sdev->color.a << 24) << (sdev->color.a << 16); + + submit_buffer( sdrv, 28 ); + } + else { + prep[7] = SH7722_XY( x3, y3 ); + prep[11] |= WR_CTRL_ENDPOINT; + + prep[12] = BEM_WR_FGC; + prep[13] = PIXEL_ARGB( sdev->color.a, + sdev->color.r, + sdev->color.g, + sdev->color.b ); + + prep[14] = BEM_PE_FIXEDALPHA; + prep[15] = (sdev->color.a << 24) << (sdev->color.a << 16); + + submit_buffer( sdrv, 16 ); + } + } + + + prep = start_buffer( sdrv, 12 ); + + prep[0] = BEM_BE_V1; + prep[1] = SH7722_XY( rect->x, rect->y ); + + prep[2] = BEM_BE_V2; + prep[3] = SH7722_XY( rect->x, rect->y + rect->h ); + + prep[4] = BEM_BE_V3; + prep[5] = SH7722_XY( rect->x + rect->w, rect->y ); + + prep[6] = BEM_BE_V4; + prep[7] = SH7722_XY( rect->x + rect->w, rect->y + rect->h ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_BE_CTRL; + + if (sdev->render_options & DSRO_MATRIX) + prep[11] = BE_CTRL_QUADRANGLE | BE_CTRL_SCANMODE_4x4 | + BE_CTRL_MATRIX | BE_CTRL_FIXMODE_16_16;// | BE_CTRL_ORIGIN; + else + prep[11] = BE_CTRL_QUADRANGLE | BE_CTRL_SCANMODE_LINE; + + submit_buffer( sdrv, 12 ); + + return true; +} + +/* + * Render a filled triangle using the current hardware state. + */ +bool +sh7722FillTriangle( void *drv, void *dev, DFBTriangle *tri ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep; + + D_DEBUG_AT( SH7722_BLT, "%s( %d,%d - %d,%d - %d,%d )\n", __FUNCTION__, + tri->x1, tri->y1, tri->x2, tri->y2, tri->x3, tri->y3 ); + DUMP_INFO(); + + + if (sdev->render_options & DSRO_ANTIALIAS) { + int x1, y1; + int x2, y2; + int x3, y3; + + if (sdev->render_options & DSRO_MATRIX) { + x1 = ((tri->x1 * sdev->matrix[0]) + + (tri->y1 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y1 = ((tri->x1 * sdev->matrix[3]) + + (tri->y1 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + + x2 = ((tri->x2 * sdev->matrix[0]) + + (tri->y2 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y2 = ((tri->x2 * sdev->matrix[3]) + + (tri->y2 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + + x3 = ((tri->x3 * sdev->matrix[0]) + + (tri->y3 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y3 = ((tri->x3 * sdev->matrix[3]) + + (tri->y3 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + } + else { + x1 = tri->x1; + y1 = tri->y1; + x2 = tri->x2; + y2 = tri->y2; + x3 = tri->x3; + y3 = tri->y3; + } + + prep = start_buffer( sdrv, 24 ); + + prep[0] = BEM_WR_FGC; + prep[1] = PIXEL_ARGB( (sdev->color.a * AA_COEF) >> 8, + (sdev->color.r * AA_COEF) >> 8, + (sdev->color.g * AA_COEF) >> 8, + (sdev->color.b * AA_COEF) >> 8 ); + + prep[2] = BEM_PE_FIXEDALPHA; + prep[3] = (sdev->color.a * AA_COEF) << 16; + + prep[4] = BEM_WR_V1; + prep[5] = SH7722_XY( x1, y1 ); + + prep[6] = BEM_WR_V2; + prep[7] = SH7722_XY( x2, y2 ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) + : + (BLE_FUNC_AxB_plus_CxD | + BLE_SRCF_ONE | + BLE_SRCA_FIXED | + BLE_DSTF_1_SRC_A); + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_WR_CTRL; + prep[11] = WR_CTRL_LINE | WR_CTRL_ANTIALIAS; + + prep[12] = BEM_WR_V2; + prep[13] = SH7722_XY( x3, y3 ); + prep[14] = BEM_WR_CTRL; + prep[15] = WR_CTRL_POLYLINE | WR_CTRL_ANTIALIAS; + + prep[16] = BEM_WR_V2; + prep[17] = SH7722_XY( x1, y1 ); + prep[18] = BEM_WR_CTRL; + prep[19] = WR_CTRL_POLYLINE | WR_CTRL_ANTIALIAS; + + prep[20] = BEM_WR_FGC; + prep[21] = PIXEL_ARGB( sdev->color.a, + sdev->color.r, + sdev->color.g, + sdev->color.b ); + + prep[22] = BEM_PE_FIXEDALPHA; + prep[23] = (sdev->color.a << 24) << (sdev->color.a << 16); + + submit_buffer( sdrv, 24 ); + } + + + prep = start_buffer( sdrv, 12 ); + + prep[0] = BEM_BE_V1; + prep[1] = SH7722_XY( tri->x1, tri->y1 ); + + prep[2] = BEM_BE_V2; + prep[3] = SH7722_XY( tri->x2, tri->y2 ); + + prep[4] = BEM_BE_V3; + prep[5] = SH7722_XY( tri->x3, tri->y3 ); + + prep[6] = BEM_BE_V4; + prep[7] = SH7722_XY( tri->x3, tri->y3 ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_BE_CTRL; + prep[11] = BE_CTRL_QUADRANGLE | BE_CTRL_SCANMODE_LINE; + + if (sdev->render_options & DSRO_MATRIX) + prep[11] |= BE_CTRL_MATRIX | BE_CTRL_FIXMODE_16_16;// | BE_CTRL_ORIGIN; + + submit_buffer( sdrv, 12 ); + + return true; +} + +/* + * Render rectangle outlines using the current hardware state. + */ +static bool +sh7722DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 20 ); + + int x1 = rect->x; + int y1 = rect->y; + int x2 = rect->x + rect->w; + int y2 = rect->y + rect->h; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + prep[0] = BEM_WR_V1; + prep[1] = (y1 << 16) | x1; + + prep[2] = BEM_WR_V2; + prep[3] = (y1 << 16) | x2; + + prep[4] = BEM_PE_OPERATION; + prep[5] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[5] |= BLE_ROP_XOR; + + prep[6] = BEM_WR_CTRL; + prep[7] = WR_CTRL_LINE; + + if (rect->h > 1 && rect->w > 1) { + prep[8] = BEM_WR_V2; + prep[9] = (y2 << 16) | x2; + prep[10] = BEM_WR_CTRL; + prep[11] = WR_CTRL_POLYLINE; + + prep[12] = BEM_WR_V2; + prep[13] = (y2 << 16) | x1; + prep[14] = BEM_WR_CTRL; + prep[15] = WR_CTRL_POLYLINE; + + prep[16] = BEM_WR_V2; + prep[17] = (y1 << 16) | x1; + prep[18] = BEM_WR_CTRL; + prep[19] = WR_CTRL_POLYLINE; + + submit_buffer( sdrv, 20 ); + } + else { + prep[3] = (y2 << 16) | x2; + prep[7] |= WR_CTRL_ENDPOINT; + + submit_buffer( sdrv, 8 ); + } + + return true; +} + +static bool +sh7722DrawRectangleMatrixAA( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + + int x1 = rect->x; + int y1 = rect->y; + int x2 = rect->x + rect->w; + int y2 = rect->y; + int x3 = rect->x + rect->w; + int y3 = rect->y + rect->h; + int x4 = rect->x; + int y4 = rect->y + rect->h; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + if (sdev->render_options & DSRO_MATRIX) { + int t; + + t = ((x1 * sdev->matrix[0]) + + (y1 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y1 = ((x1 * sdev->matrix[3]) + + (y1 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x1 = t; + + t = ((x2 * sdev->matrix[0]) + + (y2 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y2 = ((x2 * sdev->matrix[3]) + + (y2 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x2 = t; + + t = ((x3 * sdev->matrix[0]) + + (y3 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y3 = ((x3 * sdev->matrix[3]) + + (y3 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x3 = t; + + t = ((x4 * sdev->matrix[0]) + + (y4 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y4 = ((x4 * sdev->matrix[3]) + + (y4 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + x4 = t; + } + + if (sdev->render_options & DSRO_ANTIALIAS) + draw_rectangle( sdrv, sdev, x1, y1, x2, y2, x3, y3, x4, y4, true, rect->h > 1 && rect->w > 1 ); + + draw_rectangle( sdrv, sdev, x1, y1, x2, y2, x3, y3, x4, y4, false, rect->h > 1 && rect->w > 1 ); + + return true; +} + +/* + * Render a line using the current hardware state. + */ +static bool +sh7722DrawLine( void *drv, void *dev, DFBRegion *line ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 8 ); + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d -> %d, %d )\n", __FUNCTION__, + DFB_REGION_VALS( line ) ); + DUMP_INFO(); + + prep[0] = BEM_WR_V1; + prep[1] = SH7722_XY( line->x1, line->y1 ); + + prep[2] = BEM_WR_V2; + prep[3] = SH7722_XY( line->x2, line->y2 ); + + prep[4] = BEM_PE_OPERATION; + prep[5] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[5] |= BLE_ROP_XOR; + + prep[6] = BEM_WR_CTRL; + prep[7] = WR_CTRL_LINE | WR_CTRL_ENDPOINT; + + submit_buffer( sdrv, 8 ); + + return true; +} + +static bool +sh7722DrawLineMatrix( void *drv, void *dev, DFBRegion *line ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 8 ); + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d -> %d, %d )\n", __FUNCTION__, + DFB_REGION_VALS( line ) ); + DUMP_INFO(); + + int x1 = ((line->x1 * sdev->matrix[0]) + + (line->y1 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + int y1 = ((line->x1 * sdev->matrix[3]) + + (line->y1 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + + int x2 = ((line->x2 * sdev->matrix[0]) + + (line->y2 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + int y2 = ((line->x2 * sdev->matrix[3]) + + (line->y2 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + + prep[0] = BEM_WR_V1; + prep[1] = SH7722_XY( x1, y1 ); + + prep[2] = BEM_WR_V2; + prep[3] = SH7722_XY( x2, y2 ); + + prep[4] = BEM_PE_OPERATION; + prep[5] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[5] |= BLE_ROP_XOR; + + prep[6] = BEM_WR_CTRL; + prep[7] = WR_CTRL_LINE | WR_CTRL_ENDPOINT; + + submit_buffer( sdrv, 8 ); + + return true; +} + +static bool +sh7722DrawLineAA( void *drv, void *dev, DFBRegion *line ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 24 ); + int x1, y1; + int x2, y2; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d -> %d, %d )\n", __FUNCTION__, + DFB_REGION_VALS( line ) ); + DUMP_INFO(); + + if (sdev->render_options & DSRO_MATRIX) { + x1 = ((line->x1 * sdev->matrix[0]) + + (line->y1 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y1 = ((line->x1 * sdev->matrix[3]) + + (line->y1 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + + x2 = ((line->x2 * sdev->matrix[0]) + + (line->y2 * sdev->matrix[1]) + sdev->matrix[2]) >> 16; + y2 = ((line->x2 * sdev->matrix[3]) + + (line->y2 * sdev->matrix[4]) + sdev->matrix[5]) >> 16; + } + else { + x1 = line->x1; + y1 = line->y1; + x2 = line->x2; + y2 = line->y2; + } + + prep[0] = BEM_WR_FGC; + prep[1] = PIXEL_ARGB( (sdev->color.a * AA_COEF) >> 8, + (sdev->color.r * AA_COEF) >> 8, + (sdev->color.g * AA_COEF) >> 8, + (sdev->color.b * AA_COEF) >> 8 ); + + prep[2] = BEM_PE_FIXEDALPHA; + prep[3] = (sdev->color.a * AA_COEF) << 16; + + prep[4] = BEM_WR_V1; + prep[5] = SH7722_XY( x1, y1 ); + + prep[6] = BEM_WR_V2; + prep[7] = SH7722_XY( x2, y2 ); + + prep[8] = BEM_PE_OPERATION; + prep[9] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) + : + (BLE_FUNC_AxB_plus_CxD | + BLE_SRCF_ONE | + BLE_SRCA_FIXED | + BLE_DSTF_1_SRC_A); + + if (sdev->dflags & DSDRAW_XOR) + prep[9] |= BLE_ROP_XOR; + + prep[10] = BEM_WR_CTRL; + prep[11] = WR_CTRL_LINE | WR_CTRL_ENDPOINT | WR_CTRL_ANTIALIAS; + + + + prep[12] = BEM_WR_FGC; + prep[13] = PIXEL_ARGB( sdev->color.a, + sdev->color.r, + sdev->color.g, + sdev->color.b ); + + prep[14] = BEM_PE_FIXEDALPHA; + prep[15] = (sdev->color.a << 24) | (sdev->color.a << 16); + + prep[16] = BEM_WR_V1; + prep[17] = SH7722_XY( x1, y1 ); + + prep[18] = BEM_WR_V2; + prep[19] = SH7722_XY( x2, y2 ); + + prep[20] = BEM_PE_OPERATION; + prep[21] = (sdev->dflags & DSDRAW_BLEND) ? (BLE_FUNC_AxB_plus_CxD | + sdev->ble_srcf | + BLE_SRCA_FIXED | + sdev->ble_dstf) : BLE_FUNC_NONE; + + if (sdev->dflags & DSDRAW_XOR) + prep[21] |= BLE_ROP_XOR; + + prep[22] = BEM_WR_CTRL; + prep[23] = WR_CTRL_LINE | WR_CTRL_ENDPOINT; + + + submit_buffer( sdrv, 24 ); + + return true; +} + +/* + * Common implementation for Blit() and StretchBlit(). + */ +static inline bool +sh7722DoBlit( SH7722DriverData *sdrv, SH7722DeviceData *sdev, + DFBRectangle *rect, int x, int y, int w, int h ) +{ + int num = 8; + __u32 *prep = start_buffer( sdrv, 12 ); + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d -> %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ), x, y, w, h ); + DUMP_INFO(); + + prep[0] = BEM_BE_SRC_LOC; + + /* Stencil mode needs a workaround, because the hardware always adds the source location. */ + if (sdev->bflags & DSBLIT_SRC_MASK_ALPHA && sdev->mask_flags & DSMF_STENCIL) + prep[1] = SH7722_XY( 0, 0 ); + else + prep[1] = SH7722_XY( rect->x, rect->y ); + + prep[2] = BEM_BE_SRC_SIZE; + prep[3] = SH7722_XY( rect->w, rect->h ); + + prep[4] = BEM_BE_V1; + prep[5] = SH7722_XY( x, y ); + + prep[6] = BEM_BE_V2; + prep[7] = SH7722_XY( w, h ); + + /* Stencil mode needs a workaround, because the hardware always adds the source location. */ + if (sdev->bflags & DSBLIT_SRC_MASK_ALPHA && sdev->mask_flags & DSMF_STENCIL) { + prep[num++] = BEM_TE_SRC_BASE; + prep[num++] = sdev->src_phys + sdev->src_pitch * rect->y + sdev->src_bpp * rect->x; + + SH7722_INVALIDATE( SOURCE ); + } + + prep[num++] = BEM_BE_CTRL; + prep[num++] = BE_CTRL_RECTANGLE | BE_CTRL_TEXTURE | BE_CTRL_SCANMODE_LINE; + + if (sdev->bflags & DSBLIT_ROTATE180) + prep[num-1] |= BE_FLIP_BOTH; + else if (rect->w == w && rect->h == h) /* No blit direction handling for StretchBlit(). */ + prep[num-1] |= BE_CTRL_BLTDIR_AUTOMATIC; + + submit_buffer( sdrv, num ); + + return true; +} + +/* + * This version sends a quadrangle to have all four edges transformed. + */ +__attribute__((noinline)) +static bool +sh7722DoBlitM( SH7722DriverData *sdrv, SH7722DeviceData *sdev, + DFBRectangle *rect, int x1, int y1, int x2, int y2 ) +{ + int num = 12; + __u32 *prep = start_buffer( sdrv, 16 ); + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d -> %d, %d - %d, %d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ), x1, y1, x2, y2 ); + DUMP_INFO(); + + prep[0] = BEM_BE_SRC_LOC; + + /* Stencil mode needs a workaround, because the hardware always adds the source location. */ + if (sdev->bflags & DSBLIT_SRC_MASK_ALPHA && sdev->mask_flags & DSMF_STENCIL) + prep[1] = SH7722_XY( 0, 0 ); + else + prep[1] = SH7722_XY( rect->x, rect->y ); + + prep[2] = BEM_BE_SRC_SIZE; + prep[3] = SH7722_XY( rect->w, rect->h ); + + prep[4] = BEM_BE_V1; + prep[5] = SH7722_XY( x1, y1 ); + + prep[6] = BEM_BE_V2; + prep[7] = SH7722_XY( x1, y2 ); + + prep[8] = BEM_BE_V3; + prep[9] = SH7722_XY( x2, y1 ); + + prep[10] = BEM_BE_V4; + prep[11] = SH7722_XY( x2, y2 ); + + /* Stencil mode needs a workaround, because the hardware always adds the source location. */ + if (sdev->bflags & DSBLIT_SRC_MASK_ALPHA && sdev->mask_flags & DSMF_STENCIL) { + prep[num++] = BEM_TE_SRC_BASE; + prep[num++] = sdev->src_phys + sdev->src_pitch * rect->y + sdev->src_bpp * rect->x; + + SH7722_INVALIDATE( SOURCE ); + } + + prep[num++] = BEM_BE_CTRL; + prep[num++] = BE_CTRL_QUADRANGLE | BE_CTRL_TEXTURE | BE_CTRL_SCANMODE_4x4 | + BE_CTRL_MATRIX | BE_CTRL_FIXMODE_16_16;// | BE_CTRL_ORIGIN; + + if (sdev->bflags & DSBLIT_ROTATE180) + prep[num-1] |= BE_FLIP_BOTH; + + submit_buffer( sdrv, num ); + + return true; +} + +/* + * Blit a rectangle using the current hardware state. + */ +bool +sh7722Blit( void *drv, void *dev, DFBRectangle *rect, int x, int y ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d -> %d, %d )\n", + __FUNCTION__, DFB_RECTANGLE_VALS( rect ), x, y ); + + if (sdev->render_options & DSRO_MATRIX) + return sh7722DoBlitM( sdrv, sdev, rect, DFB_REGION_VALS_FROM_RECTANGLE_VALS( x, y, rect->w, rect->h ) ); + + return sh7722DoBlit( sdrv, sdev, rect, x, y, rect->w, rect->h ); +} + +/* + * StretchBlit a rectangle using the current hardware state. + */ +bool +sh7722StretchBlit( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + + D_DEBUG_AT( SH7722_BLT, "%s( %d, %d - %dx%d -> %d, %d - %dx%d )\n", + __FUNCTION__, DFB_RECTANGLE_VALS( srect ), DFB_RECTANGLE_VALS( drect ) ); + + if (sdev->render_options & DSRO_MATRIX) + return sh7722DoBlitM( sdrv, sdev, srect, DFB_REGION_VALS_FROM_RECTANGLE( drect ) ); + + return sh7722DoBlit( sdrv, sdev, srect, drect->x, drect->y, drect->w, drect->h ); +} + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.h new file mode 100755 index 0000000..00934bf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_blt.h @@ -0,0 +1,214 @@ +#ifndef __SH7722_BLT_H__ +#define __SH7722_BLT_H__ + +#include + +#include "sh7722_types.h" + + + +#define SH7722_SUPPORTED_DRAWINGFLAGS (DSDRAW_BLEND | \ + DSDRAW_XOR) + +#define SH7722_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_FILLTRIANGLE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_DRAWLINE) + +#define SH7722_SUPPORTED_BLITTINGFLAGS (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_SRC_COLORKEY | \ + DSBLIT_ROTATE180 | \ + DSBLIT_COLORIZE | \ + DSBLIT_XOR | \ + DSBLIT_SRC_MASK_ALPHA) + +#define SH7722_SUPPORTED_BLITTINGFUNCTIONS (DFXL_BLIT | \ + DFXL_STRETCHBLIT) + + +DFBResult sh7722EngineSync ( void *drv, void *dev ); + +void sh7722EngineReset ( void *drv, void *dev ); +void sh7722FlushTextureCache( void *drv, void *dev ); + +void sh7722EmitCommands ( void *drv, void *dev ); + +void sh7722CheckState ( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ); + +void sh7722SetState ( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ); + +bool sh7722FillTriangle ( void *drv, void *dev, DFBTriangle *tri ); +bool sh7722Blit ( void *drv, void *dev, DFBRectangle *rect, int x, int y ); +bool sh7722StretchBlit ( void *drv, void *dev, DFBRectangle *srect, DFBRectangle *drect ); + + + +#define SH7722_S16S16(h,l) ((u32)((((u16)(h)) << 16) | ((u16)(l)))) + +#define SH7722_XY(x,y) SH7722_S16S16(y,x) + +#define SH7722_TDG_BASE 0xFD000000 + +#define BEM_HC_DMA_ADR (SH7722_TDG_BASE + 0x00040) +#define BEM_HC_DMA_START (SH7722_TDG_BASE + 0x00044) + +#define BEM_WR_CTRL (0x00400) +#define BEM_WR_V1 (0x00410) +#define BEM_WR_V2 (0x00414) +#define BEM_WR_FGC (0x00420) + +#define BEM_BE_CTRL (0x00800) +#define BEM_BE_V1 (0x00810) +#define BEM_BE_V2 (0x00814) +#define BEM_BE_V3 (0x00818) +#define BEM_BE_V4 (0x0081C) +#define BEM_BE_COLOR1 (0x00820) +#define BEM_BE_SRC_LOC (0x00830) +#define BEM_BE_SRC_SIZE (0x00834) +#define BEM_BE_MATRIX_A (0x00850) +#define BEM_BE_MATRIX_B (0x00854) +#define BEM_BE_MATRIX_C (0x00858) +#define BEM_BE_MATRIX_D (0x0085C) +#define BEM_BE_MATRIX_E (0x00860) +#define BEM_BE_MATRIX_F (0x00864) +#define BEM_BE_ORIGIN (0x00870) +#define BEM_BE_SC_MIN (0x00880) +#define BEM_BE_SC_MAX (0x00884) + +#define BEM_TE_SRC (0x00C00) +#define BEM_TE_SRC_BASE (0x00C04) +#define BEM_TE_SRC_SIZE (0x00C08) +#define BEM_TE_SRC_CNV (0x00C0C) +#define BEM_TE_MASK (0x00C10) +#define BEM_TE_MASK_BASE (0x00C14) +#define BEM_TE_MASK_SIZE (0x00C18) +#define BEM_TE_MASK_CNV (0x00C1C) +#define BEM_TE_ALPHA (0x00C28) +#define BEM_TE_FILTER (0x00C30) +#define BEM_TE_INVALID (0x00C40) + +#define BEM_PE_DST (0x01000) +#define BEM_PE_DST_BASE (0x01004) +#define BEM_PE_DST_SIZE (0x01008) +#define BEM_PE_SC (0x0100C) +#define BEM_PE_SC0_MIN (0x01010) +#define BEM_PE_SC0_MAX (0x01014) +#define BEM_PE_CKEY (0x01040) +#define BEM_PE_CKEY_B (0x01044) +#define BEM_PE_CKEY_A (0x01048) +#define BEM_PE_COLORCHANGE (0x01050) +#define BEM_PE_ALPHA (0x01058) +#define BEM_PE_COLORCHANGE_0 (0x01060) +#define BEM_PE_COLORCHANGE_1 (0x01064) +#define BEM_PE_OPERATION (0x01080) +#define BEM_PE_FIXEDALPHA (0x01084) +#define BEM_PE_OFFSET (0x01088) +#define BEM_PE_MASK (0x01094) +#define BEM_PE_CACHE (0x010B0) + +/* + * BEM_BE_CTRL + */ +#define BE_FLIP_NONE 0x00000000 +#define BE_FLIP_HORIZONTAL 0x01000000 +#define BE_FLIP_VERTICAL 0x02000000 +#define BE_FLIP_BOTH 0x03000000 + +#define BE_CTRL_FIXMODE_20_12 0x00000000 +#define BE_CTRL_FIXMODE_16_16 0x00100000 +#define BE_CTRL_CLIP 0x00080000 +#define BE_CTRL_ORIGIN 0x00040000 +#define BE_CTRL_ZOOM 0x00020000 +#define BE_CTRL_MATRIX 0x00010000 + +#define BE_CTRL_SCANMODE_LINE 0x00000000 +#define BE_CTRL_SCANMODE_4x4 0x00001000 +#define BE_CTRL_SCANMODE_8x4 0x00002000 + +#define BE_CTRL_BLTDIR_FORWARD 0x00000000 +#define BE_CTRL_BLTDIR_BACKWARD 0x00000100 +#define BE_CTRL_BLTDIR_AUTOMATIC 0x00000200 + +#define BE_CTRL_TEXTURE 0x00000020 +#define BE_CTRL_QUADRANGLE 0x00000002 +#define BE_CTRL_RECTANGLE 0x00000001 + +/* + * BEM_PE_OPERATION + */ +#define BLE_FUNC_NONE 0x00000000 +#define BLE_FUNC_AxB_plus_CxD 0x10000000 +#define BLE_FUNC_CxD_minus_AxB 0x20000000 +#define BLE_FUNC_AxB_minus_CxD 0x30000000 + +#define BLE_ROP_XOR 0x01660000 + +#define BLE_SRCA_FIXED 0x00000000 +#define BLE_SRCA_SOURCE_ALPHA 0x00001000 +#define BLE_SRCA_ALPHA_CHANNEL 0x00002000 + +#define BLE_DSTA_FIXED 0x00000000 +#define BLE_DSTA_DEST_ALPHA 0x00000100 + +#define BLE_SRCF_ZERO 0x00000000 +#define BLE_SRCF_ONE 0x00000010 +#define BLE_SRCF_DST 0x00000020 +#define BLE_SRCF_1_DST 0x00000030 +#define BLE_SRCF_SRC_A 0x00000040 +#define BLE_SRCF_1_SRC_A 0x00000050 +#define BLE_SRCF_DST_A 0x00000060 +#define BLE_SRCF_1_DST_A 0x00000070 + +#define BLE_DSTO_DST 0x00000000 +#define BLE_DSTO_OFFSET 0x00000008 + +#define BLE_DSTF_ZERO 0x00000000 +#define BLE_DSTF_ONE 0x00000001 +#define BLE_DSTF_SRC 0x00000002 +#define BLE_DSTF_1_SRC 0x00000003 +#define BLE_DSTF_SRC_A 0x00000004 +#define BLE_DSTF_1_SRC_A 0x00000005 +#define BLE_DSTF_DST_A 0x00000006 +#define BLE_DSTF_1_DST_A 0x00000007 + +/* + * BEM_PE_CKEY + */ +#define CKEY_EXCLUDE_UNUSED 0x00100000 +#define CKEY_EXCLUDE_ALPHA 0x00010000 +#define CKEY_A_ENABLE 0x00000100 +#define CKEY_B_ENABLE 0x00000001 + +/* + * BEM_PE_COLORCHANGE + */ +#define COLORCHANGE_DISABLE 0x00000000 +#define COLORCHANGE_COMPARE_FIRST 0x0000000b +#define COLORCHANGE_EXCLUDE_UNUSED 0x00010000 + +/* + * BEM_PE_MASK + */ +#define PE_MASK_DISABLE 0x00000000 +#define PE_MASK_COLOR 0x00000001 +#define PE_MASK_ALPHA 0x00000080 + +/* + * BEM_TE_MASK + */ +#define TE_MASK_DISABLE 0x00000000 +#define TE_MASK_ENABLE 0x00010000 + +/* + * BEM_WR_CTRL + */ +#define WR_CTRL_LINE 0x00000002 +#define WR_CTRL_POLYLINE 0x00000003 +#define WR_CTRL_ANTIALIAS 0x00020100 +#define WR_CTRL_ENDPOINT 0x00001000 + +#endif diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeg.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeg.c new file mode 100755 index 0000000..9208890 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeg.c @@ -0,0 +1,395 @@ +#ifdef SH7722_DEBUG_JPEG +#define DIRECT_ENABLE_DEBUG +#endif + +#include +#include + +#undef HAVE_STDLIB_H + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "sh7722.h" +#include "sh7722_jpeglib.h" + +D_DEBUG_DOMAIN( SH7722_JPEG, "SH7722/JPEG", "SH7722 JPEG Processing Unit" ); + +/**********************************************************************************************************************/ + +static DFBResult +Probe( IDirectFBImageProvider_ProbeContext *ctx ); + +static DFBResult +Construct( IDirectFBImageProvider *thiz, + ... ); + +#include + +DIRECT_INTERFACE_IMPLEMENTATION( IDirectFBImageProvider, SH7722_JPEG ) + +/* + * private data struct of IDirectFBImageProvider_SH7722_JPEG + */ +typedef struct { + int ref; /* reference counter */ + + SH7722_JPEG_context info; + + CoreDFB *core; + + IDirectFBDataBuffer *buffer; + DirectStream *stream; + + DIRenderCallback render_callback; + void *render_callback_context; +} IDirectFBImageProvider_SH7722_JPEG_data; + +/**********************************************************************************************************************/ + +static void +IDirectFBImageProvider_SH7722_JPEG_Destruct( IDirectFBImageProvider *thiz ) +{ + IDirectFBImageProvider_SH7722_JPEG_data *data = thiz->priv; + + data->buffer->Release( data->buffer ); + + DIRECT_DEALLOCATE_INTERFACE( thiz ); +} + +static DirectResult +IDirectFBImageProvider_SH7722_JPEG_AddRef( IDirectFBImageProvider *thiz ) +{ + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG) + + data->ref++; + + return DFB_OK; +} + +static DirectResult +IDirectFBImageProvider_SH7722_JPEG_Release( IDirectFBImageProvider *thiz ) +{ + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG) + + if (--data->ref == 0) + IDirectFBImageProvider_SH7722_JPEG_Destruct( thiz ); + + return DFB_OK; +} + +static DFBResult +IDirectFBImageProvider_SH7722_JPEG_RenderTo( IDirectFBImageProvider *thiz, + IDirectFBSurface *destination, + const DFBRectangle *dest_rect ) +{ + DFBResult ret; + DFBRegion clip; + DFBRectangle rect; + IDirectFBSurface_data *dst_data; + CoreSurface *dst_surface; + CoreSurfaceBufferLock lock; + + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG); + + if (!data->buffer) + return DFB_BUFFEREMPTY; + + DIRECT_INTERFACE_GET_DATA_FROM(destination, dst_data, IDirectFBSurface); + + dst_surface = dst_data->surface; + if (!dst_surface) + return DFB_DESTROYED; + + dfb_region_from_rectangle( &clip, &dst_data->area.current ); + + if (dest_rect) { + if (dest_rect->w < 1 || dest_rect->h < 1) + return DFB_INVARG; + + rect.x = dest_rect->x + dst_data->area.wanted.x; + rect.y = dest_rect->y + dst_data->area.wanted.y; + rect.w = dest_rect->w; + rect.h = dest_rect->h; + } + else + rect = dst_data->area.wanted; + + if (!dfb_rectangle_region_intersects( &rect, &clip )) + return DFB_OK; + + ret = dfb_surface_lock_buffer( dst_surface, CSBR_BACK, CSAID_GPU, CSAF_WRITE, &lock ); + if (ret) + return ret; + + ret = SH7722_JPEG_Decode( &data->info, &rect, &clip, dst_surface->config.format, + lock.phys, lock.addr, lock.pitch, dst_surface->config.size.w, dst_surface->config.size.h ); + + dfb_surface_unlock_buffer( dst_surface, &lock ); + + return ret; +} + +static DFBResult +IDirectFBImageProvider_SH7722_JPEG_SetRenderCallback( IDirectFBImageProvider *thiz, + DIRenderCallback callback, + void *context ) +{ + DIRECT_INTERFACE_GET_DATA (IDirectFBImageProvider_SH7722_JPEG) + + data->render_callback = callback; + data->render_callback_context = context; + + return DFB_OK; +} + +static DFBResult +IDirectFBImageProvider_SH7722_JPEG_GetSurfaceDescription( IDirectFBImageProvider *thiz, + DFBSurfaceDescription *desc ) +{ + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG) + + if (!data->buffer) + return DFB_BUFFEREMPTY; + + desc->flags = DSDESC_WIDTH | DSDESC_HEIGHT | DSDESC_PIXELFORMAT; + desc->height = data->info.height; + desc->width = data->info.width; + desc->pixelformat = data->info.mode420 ? DSPF_NV12 : DSPF_NV16; + + return DFB_OK; +} + +static DFBResult +IDirectFBImageProvider_SH7722_JPEG_GetImageDescription( IDirectFBImageProvider *thiz, + DFBImageDescription *desc ) +{ + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG) + + if (!desc) + return DFB_INVARG; + + if (!data->buffer) + return DFB_BUFFEREMPTY; + + desc->caps = DICAPS_NONE; + + return DFB_OK; +} + +static DFBResult +IDirectFBImageProvider_SH7722_JPEG_WriteBack( IDirectFBImageProvider *thiz, + IDirectFBSurface *surface, + const DFBRectangle *src_rect, + const char *filename ) +{ + DFBResult ret; + DFBRegion clip; + DFBRectangle rect; + IDirectFBSurface_data *src_data; + CoreSurface *src_surface; + CoreSurfaceBufferLock lock; + DFBDimension jpeg_size; + + CoreSurface *tmp_surface; + CoreSurfaceBufferLock tmp_lock; + int tmp_pitch; + unsigned int tmp_phys; + + DIRECT_INTERFACE_GET_DATA(IDirectFBImageProvider_SH7722_JPEG) + + if (!surface || !filename) + return DFB_INVARG; + + DIRECT_INTERFACE_GET_DATA_FROM(surface, src_data, IDirectFBSurface); + + D_DEBUG_AT( SH7722_JPEG, "%s - surface %p, rect %p to file %s\n", + __FUNCTION__, surface, src_rect, filename ); + + src_surface = src_data->surface; + if (!src_surface) + return DFB_DESTROYED; + + switch (src_surface->config.format) { + case DSPF_NV12: + case DSPF_NV16: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_RGB24: + break; + + default: + /* FIXME: implement fallback */ + D_UNIMPLEMENTED(); + return DFB_UNIMPLEMENTED; + } + + dfb_region_from_rectangle( &clip, &src_data->area.current ); + + if (src_rect) { + if (src_rect->w < 1 || src_rect->h < 1) + return DFB_INVARG; + + rect.x = src_rect->x + src_data->area.wanted.x; + rect.y = src_rect->y + src_data->area.wanted.y; + rect.w = src_rect->w; + rect.h = src_rect->h; + } + else + rect = src_data->area.wanted; + + if (!dfb_rectangle_region_intersects( &rect, &clip )) + return DFB_INVAREA; + + jpeg_size.w = src_surface->config.size.w; + jpeg_size.h = src_surface->config.size.h; + + /* it would be great if we had intermediate storage, since + * this prevents handling the encoding in 16-line chunks, + * causing scaling artefacts at the border of these chunks */ + + tmp_pitch = (jpeg_size.w + 3) & ~3; + ret = dfb_surface_create_simple( data->core, tmp_pitch, jpeg_size.h, + DSPF_NV16, DSCAPS_VIDEOONLY, + CSTF_NONE, 0, 0, &tmp_surface ); + if( ret ) { + /* too bad, we proceed without */ + D_DEBUG_AT( SH7722_JPEG, "%s - failed to create intermediate storage: %d\n", + __FUNCTION__, ret ); + tmp_surface = 0; + tmp_phys = 0; + } + else { + /* lock it to get the address */ + ret = dfb_surface_lock_buffer( tmp_surface, CSBR_FRONT, CSAID_GPU, CSAF_READ | CSAF_WRITE, &tmp_lock ); + if (ret) { + D_DEBUG_AT( SH7722_JPEG, "%s - failed to lock intermediate storage: %d\n", + __FUNCTION__, ret ); + dfb_surface_unref( tmp_surface ); + tmp_surface = 0; + tmp_phys = 0; + } + else { + tmp_phys = tmp_lock.phys; + D_DEBUG_AT( SH7722_JPEG, "%s - surface locked at %x\n", __FUNCTION__, tmp_phys ); + } + } + + ret = dfb_surface_lock_buffer( src_surface, CSBR_FRONT, CSAID_GPU, CSAF_READ, &lock ); + if ( ret == DFB_OK ) { + ret = SH7722_JPEG_Encode( filename, &rect, src_surface->config.format, lock.phys, lock.pitch, + jpeg_size.w, jpeg_size.h, tmp_phys ); + + dfb_surface_unlock_buffer( src_surface, &lock ); + } + + if( tmp_surface ) { + /* unlock and release the created surface */ + dfb_surface_unlock_buffer( tmp_surface, &tmp_lock ); + dfb_surface_unref( tmp_surface ); + } + + return ret; +} + +/**********************************************************************************************************************/ + +static DFBResult +Probe( IDirectFBImageProvider_ProbeContext *ctx ) +{ + SH7722DeviceData *sdev = dfb_gfxcard_get_device_data(); + +#ifndef JPU_SUPPORT + return DFB_UNSUPPORTED; +#endif + + if (sdev->sh772x != 7722) + return DFB_UNSUPPORTED; + + /* Called with NULL when used for encoding. */ + if (!ctx) + return DFB_OK; + + if (ctx->header[0] == 0xff && ctx->header[1] == 0xd8 && ctx->filename) + return DFB_OK; + + return DFB_UNSUPPORTED; +} + +static DFBResult +Construct( IDirectFBImageProvider *thiz, + ... ) +{ + DFBResult ret; + IDirectFBDataBuffer *buffer; + CoreDFB *core; + va_list tag; + + DIRECT_ALLOCATE_INTERFACE_DATA(thiz, IDirectFBImageProvider_SH7722_JPEG); + + va_start( tag, thiz ); + buffer = va_arg( tag, IDirectFBDataBuffer * ); + core = va_arg( tag, CoreDFB * ); + va_end( tag ); + + data->ref = 1; + data->buffer = buffer; + data->core = core; + + if (buffer) { + IDirectFBDataBuffer_File_data *file_data; + + ret = buffer->AddRef( buffer ); + if (ret) { + DIRECT_DEALLOCATE_INTERFACE(thiz); + return ret; + } + + DIRECT_INTERFACE_GET_DATA_FROM( buffer, file_data, IDirectFBDataBuffer_File ); + + data->stream = file_data->stream; + + ret = SH7722_JPEG_Open( file_data->stream, &data->info ); + if (ret) { + buffer->Release( buffer ); + DIRECT_DEALLOCATE_INTERFACE(thiz); + return ret; + } + } + + thiz->AddRef = IDirectFBImageProvider_SH7722_JPEG_AddRef; + thiz->Release = IDirectFBImageProvider_SH7722_JPEG_Release; + thiz->RenderTo = IDirectFBImageProvider_SH7722_JPEG_RenderTo; + thiz->SetRenderCallback = IDirectFBImageProvider_SH7722_JPEG_SetRenderCallback; + thiz->GetImageDescription = IDirectFBImageProvider_SH7722_JPEG_GetImageDescription; + thiz->GetSurfaceDescription = IDirectFBImageProvider_SH7722_JPEG_GetSurfaceDescription; + thiz->WriteBack = IDirectFBImageProvider_SH7722_JPEG_WriteBack; + + return DFB_OK; +} + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.c new file mode 100755 index 0000000..6d88da8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.c @@ -0,0 +1,1654 @@ +#ifdef SH7722_DEBUG_JPEG +#define DIRECT_ENABLE_DEBUG +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef STANDALONE +#include "sh7722_jpeglib_standalone.h" +#else +#undef HAVE_STDLIB_H +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#endif + +#include +#include + +#include + +#include "sh7722_jpeglib.h" +#include "sh7722_regs.h" + + +D_DEBUG_DOMAIN( SH7722_JPEG, "SH7722/JPEG", "SH7722 JPEG Processing Unit" ); + +/**********************************************************************************************************************/ + +/* + * private data struct of SH7722_JPEG + */ +typedef struct { + int ref_count; + + int gfx_fd; + SH772xGfxSharedArea *gfx_shared; + + unsigned long jpeg_phys; + unsigned long jpeg_lb1; + unsigned long jpeg_lb2; + + volatile void *jpeg_virt; + + unsigned long mmio_phys; + volatile void *mmio_base; +} SH7722_JPEG_data; + +/**********************************************************************************************************************/ + +#if 1 +static inline u32 +SH7722_GETREG32( SH7722_JPEG_data *data, + u32 address ) +{ + SH772xRegister reg = { address, 0 }; + + if (ioctl( data->gfx_fd, SH772xGFX_IOCTL_GETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_GETREG32( 0x%08x )\n", reg.address ); + + return reg.value; +} + +static inline void +SH7722_SETREG32( SH7722_JPEG_data *data, + u32 address, + u32 value ) +{ + SH772xRegister reg = { address, value }; + + if (ioctl( data->gfx_fd, SH772xGFX_IOCTL_SETREG32, ® ) < 0) + D_PERROR( "SH772xGFX_IOCTL_SETREG32( 0x%08x, 0x%08x )\n", reg.address, reg.value ); +} +#else +static inline u32 +SH7722_GETREG32( SH7722_JPEG_data *data, + u32 address ) +{ + D_ASSERT( address >= data->mmio_phys ); + D_ASSERT( address < (data->mmio_phys + data->mmio_length) ); + + return *(volatile u32*)(data->mmio_base + (address - data->mmio_phys)); +} + +static inline void +SH7722_SETREG32( SH7722_JPEG_data *data, + u32 address, + u32 value ) +{ + D_ASSERT( address >= data->mmio_phys ); + D_ASSERT( address < (data->mmio_phys + data->mmio_length) ); + + *(volatile u32*)(data->mmio_base + (address - data->mmio_phys)) = value; +} +#endif + +static inline int +coded_data_amount( SH7722_JPEG_data *data ) +{ + return (SH7722_GETREG32(data, JCDTCU) << 16) | (SH7722_GETREG32(data, JCDTCM) << 8) | SH7722_GETREG32(data, JCDTCD); +} + +/**********************************************************************************************************************/ + +static DirectResult +DecodeHW( SH7722_JPEG_data *data, + SH7722_JPEG_context *info, + const DFBRectangle *rect, + const DFBRegion *clip, + DFBSurfacePixelFormat format, + unsigned long phys, + int pitch, + unsigned int width, + unsigned int height ) +{ + DirectResult ret; + unsigned int len; + int i; + int cw, ch; + bool reload = false; + SH772xGfxSharedArea *shared = data->gfx_shared; + SH7722JPEG jpeg; + u32 vtrcr = 0; + u32 vswpout = 0; + DirectStream *stream = info->stream; + + D_ASSERT( data != NULL ); + DFB_RECTANGLE_ASSERT( rect ); + DFB_REGION_ASSERT( clip ); + + cw = clip->x2 - clip->x1 + 1; + ch = clip->y2 - clip->y1 + 1; + + if (cw < 1 || ch < 1) + return DR_INVAREA; + + D_DEBUG_AT( SH7722_JPEG, "%s( %p, 0x%08lx|%d [%dx%d] %s )\n", __FUNCTION__, + data, phys, pitch, info->width, info->height, + dfb_pixelformat_name(format) ); + + D_DEBUG_AT( SH7722_JPEG, " -> %d,%d - %4dx%4d [clip %d,%d - %4dx%4d]\n", + DFB_RECTANGLE_VALS( rect ), DFB_RECTANGLE_VALS_FROM_REGION( clip ) ); + + /* + * Kernel based state machine + * + * Execution enters the kernel and only returns to user space for + * - end of decoding + * - error in decoding + * - reload requested + * + * TODO + * - finish clipping (maybe not all is possible without tricky code) + * - modify state machine to be used by Construct(), GetSurfaceDescription() and RenderTo() to avoid redundancy + * - check return code and length from GetData() + */ + + /* No cropping of top or left edge :( */ + if (clip->x1 > rect->x || clip->y1 > rect->y) { + D_UNIMPLEMENTED(); + return DR_UNIMPLEMENTED; + } + + /* Init VEU transformation control (format conversion). */ + if (!info->mode420) + vtrcr |= (1 << 14); + + switch (format) { + case DSPF_NV12: + vswpout = 0x70; + break; + + case DSPF_NV16: + vswpout = 0x70; + vtrcr |= (1 << 22); + break; + + case DSPF_RGB16: + vswpout = 0x60; + vtrcr |= (6 << 16) | 2; + break; + + case DSPF_RGB32: + vswpout = 0x40; + vtrcr |= (19 << 16) | 2; + break; + + case DSPF_RGB24: + vswpout = 0x70; + vtrcr |= (21 << 16) | 2; + break; + + default: + D_BUG( "unexpected format %s", dfb_pixelformat_name(format) ); + return DR_BUG; + } + + /* Calculate destination base address. */ + phys += DFB_BYTES_PER_LINE(format, rect->x) + rect->y * pitch; + jpeg.phys = phys; + + D_DEBUG_AT( SH7722_JPEG, " -> locking JPU...\n" ); + + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_LOCK_JPEG )) { + ret = errno2result( errno ); + D_PERROR( "SH7722/JPEG: Could not lock JPEG engine!\n" ); + return ret; + } + + D_DEBUG_AT( SH7722_JPEG, " -> loading...\n" ); + + /* Fill first reload buffer. */ + ret = direct_stream_read( stream, SH7722GFX_JPEG_RELOAD_SIZE, (void*) data->jpeg_virt, &len ); + if (ret) { + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + D_DERROR( ret, "SH7722/JPEG: Could not fill first reload buffer!\n" ); + return DR_IO; + } + + D_DEBUG_AT( SH7722_JPEG, " -> setting...\n" ); + + /* Initialize JPEG state. */ + jpeg.state = SH7722_JPEG_START; + jpeg.flags = 0; + jpeg.buffers = 1; + + /* Enable reload if buffer was filled completely (coded data length >= one reload buffer). */ + if (len == SH7722GFX_JPEG_RELOAD_SIZE) { + jpeg.flags |= SH7722_JPEG_FLAG_RELOAD; + + reload = true; + } + + /* Program JPU from RESET. */ + SH7722_SETREG32( data, JCCMD, JCCMD_RESET ); + SH7722_SETREG32( data, JCMOD, JCMOD_INPUT_CTRL | JCMOD_DSP_DECODE ); + SH7722_SETREG32( data, JIFCNT, JIFCNT_VJSEL_JPU ); + SH7722_SETREG32( data, JIFECNT, JIFECNT_SWAP_4321 ); + SH7722_SETREG32( data, JIFDSA1, data->jpeg_phys ); + SH7722_SETREG32( data, JIFDSA2, data->jpeg_phys + SH7722GFX_JPEG_RELOAD_SIZE ); + SH7722_SETREG32( data, JIFDDRSZ, len & 0x00FFFF00 ); + + if (info->width == cw && info->height == ch && rect->w == cw && rect->h == ch && + (( info->mode420 && format == DSPF_NV12) || + (!info->mode420 && format == DSPF_NV16))) + { + /* Setup JPU for decoding in frame mode (directly to surface). */ + SH7722_SETREG32( data, JINTE, JINTS_INS5_ERROR | JINTS_INS6_DONE | + (reload ? JINTS_INS14_RELOAD : 0) ); + SH7722_SETREG32( data, JIFDCNT, JIFDCNT_SWAP_4321 | (reload ? JIFDCNT_RELOAD_ENABLE : 0) ); + + SH7722_SETREG32( data, JIFDDYA1, phys ); + SH7722_SETREG32( data, JIFDDCA1, phys + pitch * height ); + SH7722_SETREG32( data, JIFDDMW, pitch ); + } + else { + jpeg.flags |= SH7722_JPEG_FLAG_CONVERT; + + /* Setup JPU for decoding in line buffer mode. */ + SH7722_SETREG32( data, JINTE, JINTS_INS5_ERROR | JINTS_INS6_DONE | + JINTS_INS11_LINEBUF0 | JINTS_INS12_LINEBUF1 | + (reload ? JINTS_INS14_RELOAD : 0) ); + SH7722_SETREG32( data, JIFDCNT, JIFDCNT_LINEBUF_MODE | (SH7722GFX_JPEG_LINEBUFFER_HEIGHT << 16) | + JIFDCNT_SWAP_4321 | (reload ? JIFDCNT_RELOAD_ENABLE : 0) ); + + SH7722_SETREG32( data, JIFDDYA1, data->jpeg_lb1 ); + SH7722_SETREG32( data, JIFDDCA1, data->jpeg_lb1 + SH7722GFX_JPEG_LINEBUFFER_SIZE_Y ); + SH7722_SETREG32( data, JIFDDYA2, data->jpeg_lb2 ); + SH7722_SETREG32( data, JIFDDCA2, data->jpeg_lb2 + SH7722GFX_JPEG_LINEBUFFER_SIZE_Y ); + SH7722_SETREG32( data, JIFDDMW, SH7722GFX_JPEG_LINEBUFFER_PITCH ); + + /* Setup VEU for conversion/scaling (from line buffer to surface). */ + SH7722_SETREG32( data, VEU_VBSRR, 0x00000100 ); + SH7722_SETREG32( data, VEU_VESTR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VESWR, SH7722GFX_JPEG_LINEBUFFER_PITCH ); + SH7722_SETREG32( data, VEU_VESSR, (info->height << 16) | info->width ); + SH7722_SETREG32( data, VEU_VBSSR, 16 ); + SH7722_SETREG32( data, VEU_VEDWR, pitch ); + SH7722_SETREG32( data, VEU_VDAYR, phys ); + SH7722_SETREG32( data, VEU_VDACR, phys + pitch * height ); + SH7722_SETREG32( data, VEU_VTRCR, vtrcr ); + + SH7722_SETREG32( data, VEU_VRFCR, (((info->height << 12) / rect->h) << 16) | + ((info->width << 12) / rect->w) ); + SH7722_SETREG32( data, VEU_VRFSR, (ch << 16) | cw ); + + SH7722_SETREG32( data, VEU_VENHR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VFMCR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VAPCR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VSWPR, 0x00000007 | vswpout ); + SH7722_SETREG32( data, VEU_VEIER, 0x00000101 ); + } + + D_DEBUG_AT( SH7722_JPEG, " -> starting...\n" ); + + /* Clear interrupts in shared flags. */ + shared->jpeg_ints = 0; + + /* State machine. */ + while (true) { + /* Run the state machine. */ + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_RUN_JPEG, &jpeg ) < 0) { + ret = errno2result( errno ); + + D_PERROR( "SH7722/JPEG: SH7722GFX_IOCTL_RUN_JPEG failed!\n" ); + break; + } + + D_ASSERT( jpeg.state != SH7722_JPEG_START ); + + /* Handle end (or error). */ + if (jpeg.state == SH7722_JPEG_END) { + if (jpeg.error) { + D_ERROR( "SH7722/JPEG: ERROR 0x%x!\n", jpeg.error ); + ret = DR_IO; + } + + break; + } + + /* Check for reload requests. */ + for (i=1; i<=2; i++) { + if (jpeg.buffers & i) { + if (jpeg.flags & SH7722_JPEG_FLAG_RELOAD) { + D_ASSERT( reload ); + + ret = direct_stream_read( stream, SH7722GFX_JPEG_RELOAD_SIZE, + (void*) data->jpeg_virt + + SH7722GFX_JPEG_RELOAD_SIZE * (i-1), &len ); + if (ret) { + D_DERROR( ret, "SH7722/JPEG: Could not refill %s reload buffer!\n", + i == 1 ? "first" : "second" ); + jpeg.buffers &= ~i; + jpeg.flags &= ~SH7722_JPEG_FLAG_RELOAD; + } + else if (len < SH7722GFX_JPEG_RELOAD_SIZE) + jpeg.flags &= ~SH7722_JPEG_FLAG_RELOAD; + } + else + jpeg.buffers &= ~i; + } + } + } + + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + + return ret; +} + +static int calculate_scaling( int input, int output ) +{ + int frac = 0; + int mant = 0; + + if( input == output ) { /* no scaling, done */ + return 0; + } + + mant = input / output; + frac = ((input * 4096 / output) & ~7) - mant * 4096; + + if( input < output ) { /* upscaling */ + if( input*8 < output ) /* out-of-range */ + return -1; + + while( output > 1 + (int)((input-1)*4096/frac) ) { + frac -= 8; + } + } + else { /* downscaling */ + int a,size,pmant; + + if( output*16 < input ) /* out-of-range */ + return -1; + + while(1) { + pmant = "1122333344444444"[mant] - '0'; + a = mant * 4096 + frac; + size = (2*(input-1)*pmant)/(2*pmant); + size = (((size-1) * 4096 * pmant) + a) / a; + + if( output <= size ) + break; + + if( frac ) + frac -= 8; + else { + mant--; + frac = 0xff8; + } + } + } + + return (mant << 12) + frac; +} + +static DirectResult +EncodeHW( SH7722_JPEG_data *data, + const char *filename, + const DFBRectangle *rect, + DFBSurfacePixelFormat format, + unsigned long phys, + int pitch, + unsigned int width, + unsigned int height, + unsigned long tmpphys ) +{ + DirectResult ret; + int i, fd; + int written = 0; + SH772xGfxSharedArea *shared = data->gfx_shared; + u32 vtrcr = 0; + u32 vswpin = 0; + bool mode420 = false; + SH7722JPEG jpeg; + + int horizontalscaling = 0; + int verticalscaling = 0; + + int clipwidth, clipheight; + DFBRectangle cliprect; + + /* VEU has cliprequirement of 4 bytes, input and output must be 4 pixel aligned. + * We have to be careful with scaling: take clipped output and input */ + + cliprect.h = (rect->h + 0x3) & ~0x3; + cliprect.w = (rect->w + 0x3) & ~0x3; + clipheight = (height + 0x3) & ~0x3; + clipwidth = (width + 0x3) & ~0x3; + + D_ASSERT( data != NULL ); + DFB_RECTANGLE_ASSERT( rect ); + + D_DEBUG_AT( SH7722_JPEG, "%s( %p, 0x%08lx|%d [%dx%d] %s )\n", __FUNCTION__, + data, phys, pitch, width, height, + dfb_pixelformat_name(format) ); + + D_DEBUG_AT( SH7722_JPEG, " -> %d,%d - %4dx%4d (at %lx)\n", + DFB_RECTANGLE_VALS( rect ), tmpphys ); + + /* JPU input is 16x16 to 2560x1920 */ + if (width < 16 || width > 2560 || height < 16 || height > 1920) + return DR_INVAREA; + + if (rect->w < 1 || rect->h < 1) + return DR_INVAREA; + + horizontalscaling = calculate_scaling( cliprect.w, clipwidth ); + verticalscaling = calculate_scaling( cliprect.h, clipheight ); + if( !tmpphys ) { + /* we don't have enough memory, so we do it in 16 pixel steps */ + int h = ((rect->h * SH7722GFX_JPEG_LINEBUFFER_HEIGHT / height) + 0x3) & ~0x3; + verticalscaling = calculate_scaling( h, SH7722GFX_JPEG_LINEBUFFER_HEIGHT ); + } + + /* scaling out-of-range? */ + if( horizontalscaling == -1 || verticalscaling == -1 ) + return DR_INVAREA; + + /* + * Kernel based state machine + * + * Execution enters the kernel and only returns to user space for + * - end of encoding + * - error in encoding + * - buffer loaded + * + * TODO + * - finish clipping (maybe not all is possible without tricky code) + */ + + /* Init VEU transformation control (format conversion). */ + if (format == DSPF_NV12) + mode420 = true; + else + vtrcr |= (1 << 22); + + switch (format) { + case DSPF_NV12: + vswpin = 0x07; + break; + + case DSPF_NV16: + vswpin = 0x07; + vtrcr |= (1 << 14); + break; + + case DSPF_RGB16: + vswpin = 0x06; + vtrcr |= (3 << 8) | 3; + break; + + case DSPF_RGB32: + vswpin = 0x04; + vtrcr |= (0 << 8) | 3; + break; + + case DSPF_RGB24: + vswpin = 0x07; + vtrcr |= (2 << 8) | 3; + break; + + default: + D_BUG( "unexpected format %s", dfb_pixelformat_name(format) ); + return DR_BUG; + } + + /* Calculate source base address. */ + /* TODO: NV12 input with offset. Colour will be off.. */ + phys += DFB_BYTES_PER_LINE(format, rect->x) + rect->y * pitch; + jpeg.phys = phys; + + D_DEBUG_AT( SH7722_JPEG, " -> locking JPU...\n" ); + + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_LOCK_JPEG )) { + ret = errno2result( errno ); + D_PERROR( "SH7722/JPEG: Could not lock JPEG engine!\n" ); + return ret; + } + + D_DEBUG_AT( SH7722_JPEG, " -> opening '%s' for writing...\n", filename ); + + fd = open( filename, O_WRONLY | O_CREAT | O_TRUNC, 0644 ); + if (fd < 0) { + ret = errno2result( errno ); + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + D_PERROR( "SH7722/JPEG: Failed to open '%s' for writing!\n", filename ); + return ret; + } + + D_DEBUG_AT( SH7722_JPEG, " -> setting...\n" ); + + /* Initialize JPEG state. */ + jpeg.state = SH7722_JPEG_START; + jpeg.flags = SH7722_JPEG_FLAG_ENCODE; + jpeg.buffers = 3; + + /* Always enable reload mode. */ + jpeg.flags |= SH7722_JPEG_FLAG_RELOAD; + + /* Program JPU from RESET. */ + SH7722_SETREG32( data, JCCMD, JCCMD_RESET ); + SH7722_SETREG32( data, JCMOD, JCMOD_INPUT_CTRL | JCMOD_DSP_ENCODE | (mode420 ? 2 : 1) ); + + SH7722_SETREG32( data, JCQTN, 0x14 ); + SH7722_SETREG32( data, JCHTN, 0x3C ); + SH7722_SETREG32( data, JCDRIU, 0x02 ); + SH7722_SETREG32( data, JCDRID, 0x00 ); + SH7722_SETREG32( data, JCHSZU, width >> 8 ); + SH7722_SETREG32( data, JCHSZD, width & 0xff ); + SH7722_SETREG32( data, JCVSZU, height >> 8 ); + SH7722_SETREG32( data, JCVSZD, height & 0xff ); + SH7722_SETREG32( data, JIFCNT, JIFCNT_VJSEL_JPU ); + SH7722_SETREG32( data, JIFDCNT, JIFDCNT_SWAP_4321 ); + SH7722_SETREG32( data, JIFEDA1, data->jpeg_phys ); + SH7722_SETREG32( data, JIFEDA2, data->jpeg_phys + SH7722GFX_JPEG_RELOAD_SIZE ); + SH7722_SETREG32( data, JIFEDRSZ, SH7722GFX_JPEG_RELOAD_SIZE ); + SH7722_SETREG32( data, JIFESHSZ, clipwidth ); + SH7722_SETREG32( data, JIFESVSZ, clipheight ); + + if (width == rect->w && height == rect->h && (format == DSPF_NV12 || format == DSPF_NV16)) + { + D_DEBUG_AT( SH7722_JPEG, " -> no VEU needed\n" ); + + /* no scaling, and supported format - so no VEU needed */ + /* Setup JPU for encoding in frame mode (directly from surface). */ + SH7722_SETREG32( data, JINTE, JINTS_INS10_XFER_DONE | JINTS_INS13_LOADED ); + SH7722_SETREG32( data, JIFECNT, JIFECNT_SWAP_4321 | JIFECNT_RELOAD_ENABLE | (mode420 ? 1 : 0) ); + + SH7722_SETREG32( data, JIFESYA1, phys ); + SH7722_SETREG32( data, JIFESCA1, phys + pitch * height ); + SH7722_SETREG32( data, JIFESMW, pitch ); + } + else { + /* Setup JPU for encoding in line buffer mode. */ + jpeg.flags |= SH7722_JPEG_FLAG_CONVERT; + jpeg.height = height; + jpeg.inputheight = rect->h; + + SH7722_SETREG32( data, JINTE, JINTS_INS11_LINEBUF0 | JINTS_INS12_LINEBUF1 | + JINTS_INS10_XFER_DONE | JINTS_INS13_LOADED ); + + if( tmpphys ) { + /* we have enough memory, so we just read one big "line" */ + SH7722_SETREG32( data, JIFECNT, JIFECNT_LINEBUF_MODE | (height << 16) | + JIFECNT_SWAP_4321 | JIFECNT_RELOAD_ENABLE | (mode420 ? 1 : 0) ); + SH7722_SETREG32( data, JIFESYA1, tmpphys ); + SH7722_SETREG32( data, JIFESCA1, tmpphys + clipwidth * height ); /* Y is 8bpp */ + SH7722_SETREG32( data, JIFESMW, clipwidth ); + } + else { + SH7722_SETREG32( data, JIFECNT, JIFECNT_LINEBUF_MODE | (SH7722GFX_JPEG_LINEBUFFER_HEIGHT << 16) | + JIFECNT_SWAP_4321 | JIFECNT_RELOAD_ENABLE | (mode420 ? 1 : 0) ); + + SH7722_SETREG32( data, JIFESYA1, data->jpeg_lb1 ); + SH7722_SETREG32( data, JIFESCA1, data->jpeg_lb1 + SH7722GFX_JPEG_LINEBUFFER_SIZE_Y ); + SH7722_SETREG32( data, JIFESMW, SH7722GFX_JPEG_LINEBUFFER_PITCH ); + } + SH7722_SETREG32( data, JIFESYA2, data->jpeg_lb2 ); + SH7722_SETREG32( data, JIFESCA2, data->jpeg_lb2 + SH7722GFX_JPEG_LINEBUFFER_SIZE_Y ); + + /* we will not use the VEU in burst mode since we cannot program the + * destination addresses intermediately in line mode. */ + SH7722_SETREG32( data, VEU_VBSRR, 0x00000100 ); + SH7722_SETREG32( data, VEU_VESTR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VSAYR, phys ); + SH7722_SETREG32( data, VEU_VSACR, phys + pitch * height ); + SH7722_SETREG32( data, VEU_VESWR, pitch ); + + if( tmpphys ) { + SH7722_SETREG32( data, VEU_VESSR, (cliprect.h << 16) | cliprect.w ); + SH7722_SETREG32( data, VEU_VEDWR, clipwidth ); + SH7722_SETREG32( data, VEU_VDAYR, tmpphys ); + SH7722_SETREG32( data, VEU_VDACR, tmpphys + clipwidth * height ); + SH7722_SETREG32( data, VEU_VRFSR, (clipheight << 16) | clipwidth ); + } + else { + int h = ((rect->h * SH7722GFX_JPEG_LINEBUFFER_HEIGHT / height) + 0x3) & ~0x3; + SH7722_SETREG32( data, VEU_VESSR, (h << 16) | cliprect.w ); + SH7722_SETREG32( data, VEU_VEDWR, SH7722GFX_JPEG_LINEBUFFER_PITCH ); + SH7722_SETREG32( data, VEU_VDAYR, data->jpeg_lb1 ); + SH7722_SETREG32( data, VEU_VDACR, data->jpeg_lb1 + SH7722GFX_JPEG_LINEBUFFER_SIZE_Y ); + SH7722_SETREG32( data, VEU_VRFSR, (SH7722GFX_JPEG_LINEBUFFER_HEIGHT << 16) | clipwidth ); + } + SH7722_SETREG32( data, VEU_VRFCR, (verticalscaling << 16) | horizontalscaling ); + SH7722_SETREG32( data, VEU_VTRCR, vtrcr ); + SH7722_SETREG32( data, VEU_VENHR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VFMCR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VAPCR, 0x00000000 ); + SH7722_SETREG32( data, VEU_VSWPR, 0x00000070 | vswpin ); + SH7722_SETREG32( data, VEU_VEIER, 0x00000101 ); + } + + /* Init quantization tables. */ + SH7722_SETREG32( data, JCQTBL0( 0), 0x100B0B0E ); + SH7722_SETREG32( data, JCQTBL0( 1), 0x0C0A100E ); + SH7722_SETREG32( data, JCQTBL0( 2), 0x0D0E1211 ); + SH7722_SETREG32( data, JCQTBL0( 3), 0x10131828 ); + SH7722_SETREG32( data, JCQTBL0( 4), 0x1A181616 ); + SH7722_SETREG32( data, JCQTBL0( 5), 0x18312325 ); + SH7722_SETREG32( data, JCQTBL0( 6), 0x1D283A33 ); + SH7722_SETREG32( data, JCQTBL0( 7), 0x3D3C3933 ); + SH7722_SETREG32( data, JCQTBL0( 8), 0x38374048 ); + SH7722_SETREG32( data, JCQTBL0( 9), 0x5C4E4044 ); + SH7722_SETREG32( data, JCQTBL0(10), 0x57453738 ); + SH7722_SETREG32( data, JCQTBL0(11), 0x506D5157 ); + SH7722_SETREG32( data, JCQTBL0(12), 0x5F626768 ); + SH7722_SETREG32( data, JCQTBL0(13), 0x673E4D71 ); + SH7722_SETREG32( data, JCQTBL0(14), 0x79706478 ); + SH7722_SETREG32( data, JCQTBL0(15), 0x5C656763 ); + + SH7722_SETREG32( data, JCQTBL1( 0), 0x11121218 ); + SH7722_SETREG32( data, JCQTBL1( 1), 0x15182F1A ); + SH7722_SETREG32( data, JCQTBL1( 2), 0x1A2F6342 ); + SH7722_SETREG32( data, JCQTBL1( 3), 0x38426363 ); + SH7722_SETREG32( data, JCQTBL1( 4), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1( 5), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1( 6), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1( 7), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1( 8), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1( 9), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(10), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(11), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(12), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(13), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(14), 0x63636363 ); + SH7722_SETREG32( data, JCQTBL1(15), 0x63636363 ); + + /* Init huffman tables. */ + SH7722_SETREG32( data, JCHTBD0(0), 0x00010501 ); + SH7722_SETREG32( data, JCHTBD0(1), 0x01010101 ); + SH7722_SETREG32( data, JCHTBD0(2), 0x01000000 ); + SH7722_SETREG32( data, JCHTBD0(3), 0x00000000 ); + SH7722_SETREG32( data, JCHTBD0(4), 0x00010203 ); + SH7722_SETREG32( data, JCHTBD0(5), 0x04050607 ); + SH7722_SETREG32( data, JCHTBD0(6), 0x08090A0B ); + + SH7722_SETREG32( data, JCHTBD1(0), 0x00030101 ); + SH7722_SETREG32( data, JCHTBD1(1), 0x01010101 ); + SH7722_SETREG32( data, JCHTBD1(2), 0x01010100 ); + SH7722_SETREG32( data, JCHTBD1(3), 0x00000000 ); + SH7722_SETREG32( data, JCHTBD1(4), 0x00010203 ); + SH7722_SETREG32( data, JCHTBD1(5), 0x04050607 ); + SH7722_SETREG32( data, JCHTBD1(6), 0x08090A0B ); + + SH7722_SETREG32( data, JCHTBA0( 0), 0x00020103 ); + SH7722_SETREG32( data, JCHTBA0( 1), 0x03020403 ); + SH7722_SETREG32( data, JCHTBA0( 2), 0x05050404 ); + SH7722_SETREG32( data, JCHTBA0( 3), 0x0000017D ); + SH7722_SETREG32( data, JCHTBA0( 4), 0x01020300 ); + SH7722_SETREG32( data, JCHTBA0( 5), 0x04110512 ); + SH7722_SETREG32( data, JCHTBA0( 6), 0x21314106 ); + SH7722_SETREG32( data, JCHTBA0( 7), 0x13516107 ); + SH7722_SETREG32( data, JCHTBA0( 8), 0x22711432 ); + SH7722_SETREG32( data, JCHTBA0( 9), 0x8191A108 ); + SH7722_SETREG32( data, JCHTBA0(10), 0x2342B1C1 ); + SH7722_SETREG32( data, JCHTBA0(11), 0x1552D1F0 ); + SH7722_SETREG32( data, JCHTBA0(12), 0x24336272 ); + SH7722_SETREG32( data, JCHTBA0(13), 0x82090A16 ); + SH7722_SETREG32( data, JCHTBA0(14), 0x1718191A ); + SH7722_SETREG32( data, JCHTBA0(15), 0x25262728 ); + SH7722_SETREG32( data, JCHTBA0(16), 0x292A3435 ); + SH7722_SETREG32( data, JCHTBA0(17), 0x36373839 ); + SH7722_SETREG32( data, JCHTBA0(18), 0x3A434445 ); + SH7722_SETREG32( data, JCHTBA0(19), 0x46474849 ); + SH7722_SETREG32( data, JCHTBA0(20), 0x4A535455 ); + SH7722_SETREG32( data, JCHTBA0(21), 0x56575859 ); + SH7722_SETREG32( data, JCHTBA0(22), 0x5A636465 ); + SH7722_SETREG32( data, JCHTBA0(23), 0x66676869 ); + SH7722_SETREG32( data, JCHTBA0(24), 0x6A737475 ); + SH7722_SETREG32( data, JCHTBA0(25), 0x76777879 ); + SH7722_SETREG32( data, JCHTBA0(26), 0x7A838485 ); + SH7722_SETREG32( data, JCHTBA0(27), 0x86878889 ); + SH7722_SETREG32( data, JCHTBA0(28), 0x8A929394 ); + SH7722_SETREG32( data, JCHTBA0(29), 0x95969798 ); + SH7722_SETREG32( data, JCHTBA0(30), 0x999AA2A3 ); + SH7722_SETREG32( data, JCHTBA0(31), 0xA4A5A6A7 ); + SH7722_SETREG32( data, JCHTBA0(32), 0xA8A9AAB2 ); + SH7722_SETREG32( data, JCHTBA0(33), 0xB3B4B5B6 ); + SH7722_SETREG32( data, JCHTBA0(34), 0xB7B8B9BA ); + SH7722_SETREG32( data, JCHTBA0(35), 0xC2C3C4C5 ); + SH7722_SETREG32( data, JCHTBA0(36), 0xC6C7C8C9 ); + SH7722_SETREG32( data, JCHTBA0(37), 0xCAD2D3D4 ); + SH7722_SETREG32( data, JCHTBA0(38), 0xD5D6D7D8 ); + SH7722_SETREG32( data, JCHTBA0(39), 0xD9DAE1E2 ); + SH7722_SETREG32( data, JCHTBA0(40), 0xE3E4E5E6 ); + SH7722_SETREG32( data, JCHTBA0(41), 0xE7E8E9EA ); + SH7722_SETREG32( data, JCHTBA0(42), 0xF1F2F3F4 ); + SH7722_SETREG32( data, JCHTBA0(43), 0xF5F6F7F8 ); + SH7722_SETREG32( data, JCHTBA0(44), 0xF9FA0000 ); + + SH7722_SETREG32( data, JCHTBA1( 0), 0x00020102 ); + SH7722_SETREG32( data, JCHTBA1( 1), 0x04040304 ); + SH7722_SETREG32( data, JCHTBA1( 2), 0x07050404 ); + SH7722_SETREG32( data, JCHTBA1( 3), 0x00010277 ); + SH7722_SETREG32( data, JCHTBA1( 4), 0x00010203 ); + SH7722_SETREG32( data, JCHTBA1( 5), 0x11040521 ); + SH7722_SETREG32( data, JCHTBA1( 6), 0x31061241 ); + SH7722_SETREG32( data, JCHTBA1( 7), 0x51076171 ); + SH7722_SETREG32( data, JCHTBA1( 8), 0x13223281 ); + SH7722_SETREG32( data, JCHTBA1( 9), 0x08144291 ); + SH7722_SETREG32( data, JCHTBA1(10), 0xA1B1C109 ); + SH7722_SETREG32( data, JCHTBA1(11), 0x233352F0 ); + SH7722_SETREG32( data, JCHTBA1(12), 0x156272D1 ); + SH7722_SETREG32( data, JCHTBA1(13), 0x0A162434 ); + SH7722_SETREG32( data, JCHTBA1(14), 0xE125F117 ); + SH7722_SETREG32( data, JCHTBA1(15), 0x18191A26 ); + SH7722_SETREG32( data, JCHTBA1(16), 0x2728292A ); + SH7722_SETREG32( data, JCHTBA1(17), 0x35363738 ); + SH7722_SETREG32( data, JCHTBA1(18), 0x393A4344 ); + SH7722_SETREG32( data, JCHTBA1(19), 0x45464748 ); + SH7722_SETREG32( data, JCHTBA1(20), 0x494A5354 ); + SH7722_SETREG32( data, JCHTBA1(21), 0x55565758 ); + SH7722_SETREG32( data, JCHTBA1(22), 0x595A6364 ); + SH7722_SETREG32( data, JCHTBA1(23), 0x65666768 ); + SH7722_SETREG32( data, JCHTBA1(24), 0x696A7374 ); + SH7722_SETREG32( data, JCHTBA1(25), 0x75767778 ); + SH7722_SETREG32( data, JCHTBA1(26), 0x797A8283 ); + SH7722_SETREG32( data, JCHTBA1(27), 0x84858687 ); + SH7722_SETREG32( data, JCHTBA1(28), 0x88898A92 ); + SH7722_SETREG32( data, JCHTBA1(29), 0x93949596 ); + SH7722_SETREG32( data, JCHTBA1(30), 0x9798999A ); + SH7722_SETREG32( data, JCHTBA1(31), 0xA2A3A4A5 ); + SH7722_SETREG32( data, JCHTBA1(32), 0xA6A7A8A9 ); + SH7722_SETREG32( data, JCHTBA1(33), 0xAAB2B3B4 ); + SH7722_SETREG32( data, JCHTBA1(34), 0xB5B6B7B8 ); + SH7722_SETREG32( data, JCHTBA1(35), 0xB9BAC2C3 ); + SH7722_SETREG32( data, JCHTBA1(36), 0xC4C5C6C7 ); + SH7722_SETREG32( data, JCHTBA1(37), 0xC8C9CAD2 ); + SH7722_SETREG32( data, JCHTBA1(38), 0xD3D4D5D6 ); + SH7722_SETREG32( data, JCHTBA1(39), 0xD7D8D9DA ); + SH7722_SETREG32( data, JCHTBA1(40), 0xE2E3E4E5 ); + SH7722_SETREG32( data, JCHTBA1(41), 0xE6E7E8E9 ); + SH7722_SETREG32( data, JCHTBA1(42), 0xEAF2F3F4 ); + SH7722_SETREG32( data, JCHTBA1(43), 0xF5F6F7F8 ); + SH7722_SETREG32( data, JCHTBA1(44), 0xF9FA0000 ); + + /* Clear interrupts in shared flags. */ + shared->jpeg_ints = 0; + + D_DEBUG_AT( SH7722_JPEG, " -> starting...\n" ); + + /* State machine. */ + while (true) { + /* Run the state machine. */ + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_RUN_JPEG, &jpeg ) < 0) { + ret = errno2result( errno ); + + D_PERROR( "SH7722/JPEG: SH7722GFX_IOCTL_RUN_JPEG failed!\n" ); + break; + } + + D_ASSERT( jpeg.state != SH7722_JPEG_START ); + + /* Check for loaded buffers. */ + for (i=1; i<=2; i++) { + if (jpeg.buffers & i) { + int amount = coded_data_amount( data ) - written; + + if (amount > SH7722GFX_JPEG_RELOAD_SIZE) + amount = SH7722GFX_JPEG_RELOAD_SIZE; + + D_INFO( "SH7722/JPEG: Coded data amount: + %5d (buffer %d)\n", amount, i ); + + written += write( fd, (void*) data->jpeg_virt + SH7722GFX_JPEG_RELOAD_SIZE * (i-1), amount ); + } + } + + /* Handle end (or error). */ + if (jpeg.state == SH7722_JPEG_END) { + if (jpeg.error) { + D_ERROR( "SH7722/JPEG: ERROR 0x%x!\n", jpeg.error ); + ret = DR_IO; + } + + break; + } + } + + D_INFO( "SH7722/JPEG: Coded data amount: = %5d (written: %d, buffers: %d)\n", + coded_data_amount( data ), written, jpeg.buffers ); + + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + + close( fd ); + + return DR_OK; +} + +#if 0 +static DirectResult +DecodeHeader( SH7722_JPEG_data *data, + DirectStream *stream, + SH7722_JPEG_context *info ) +{ + DirectResult ret; + unsigned int len; + SH772xGfxSharedArea *shared; + + D_DEBUG_AT( SH7722_JPEG, "%s( %p )\n", __FUNCTION__, data ); + + D_ASSERT( data != NULL ); + + shared = data->gfx_shared; + + /* + * Do minimal stuff to decode the image header, serving as a good probe mechanism as well. + */ + + D_DEBUG_AT( SH7722_JPEG, " -> locking JPU...\n" ); + + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_LOCK_JPEG )) { + ret = errno2result( errno ); + D_PERROR( "SH7722/JPEG: Could not lock JPEG engine!\n" ); + return ret; + } + + D_DEBUG_AT( SH7722_JPEG, " -> loading 32k...\n" ); + + /* Prefill reload buffer with 32k. */ + ret = direct_stream_peek( stream, 32*1024, 0, (void*) data->jpeg_virt, &len ); + if (ret) { + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + D_DEBUG_AT( SH7722_JPEG, " -> ERROR from PeekData(): %s\n", DirectResultString(ret) ); + return DR_IO; + } + + D_DEBUG_AT( SH7722_JPEG, " -> %u bytes loaded, setting...\n", len ); + + /* Program JPU from RESET. */ + SH7722_SETREG32( data, JCCMD, JCCMD_RESET ); + SH7722_SETREG32( data, JCMOD, JCMOD_INPUT_CTRL | JCMOD_DSP_DECODE ); + SH7722_SETREG32( data, JINTE, JINTS_INS3_HEADER | JINTS_INS5_ERROR ); + SH7722_SETREG32( data, JIFCNT, JIFCNT_VJSEL_JPU ); + SH7722_SETREG32( data, JIFECNT, JIFECNT_SWAP_4321 ); + SH7722_SETREG32( data, JIFDCNT, JIFDCNT_SWAP_4321 ); + SH7722_SETREG32( data, JIFDSA1, data->jpeg_phys ); + SH7722_SETREG32( data, JIFDDRSZ, len ); + + D_DEBUG_AT( SH7722_JPEG, " -> starting...\n" ); + + /* Clear interrupts in shared flags. */ + shared->jpeg_ints = 0; + + /* Start decoder and begin reading from buffer. */ + SH7722_SETREG32( data, JCCMD, JCCMD_START ); + + /* Stall machine. */ + while (true) { + /* Check for new interrupts in shared flags... */ + u32 ints = shared->jpeg_ints; + if (ints) { + /* ...and clear them (FIXME: race condition in case of multiple IRQs per command!). */ + shared->jpeg_ints &= ~ints; + + D_DEBUG_AT( SH7722_JPEG, " -> JCSTS 0x%08x, JINTS 0x%08x\n", SH7722_GETREG32( data, JCSTS ), ints ); + + /* Check for errors! */ + if (ints & JINTS_INS5_ERROR) { + D_ERROR( "SH7722/JPEG: ERROR 0x%x!\n", SH7722_GETREG32( data, JCDERR ) ); + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + return DR_IO; + } + + /* Check for header interception... */ + if (ints & JINTS_INS3_HEADER) { + /* ...remember image information... */ + info->width = SH7722_GETREG32( data, JIFDDHSZ ); + info->height = SH7722_GETREG32( data, JIFDDVSZ ); + info->mode420 = (SH7722_GETREG32( data, JCMOD ) & 2) ? true : false; + + D_DEBUG_AT( SH7722_JPEG, " -> %dx%d (4:2:%c)\n", + info->width, info->height, info->mode420 ? '0' : '2' ); + + break; + } + } + else { + D_DEBUG_AT( SH7722_JPEG, " -> waiting...\n" ); + + /* ...otherwise wait for the arrival of new interrupt(s). */ + if (ioctl( data->gfx_fd, SH7722GFX_IOCTL_WAIT_JPEG ) < 0) { + D_PERROR( "SH7722/JPEG: Waiting for IRQ failed! (ints: 0x%x - JINTS 0x%x, JCSTS 0x%x)\n", + ints, SH7722_GETREG32( data, JINTS ), SH7722_GETREG32( data, JCSTS ) ); + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + return DR_FAILURE; + } + } + } + + ioctl( data->gfx_fd, SH7722GFX_IOCTL_UNLOCK_JPEG ); + + if (info->width < 16 || info->width > 2560) + return DR_UNSUPPORTED; + + if (info->height < 16 || info->height > 1920) + return DR_UNSUPPORTED; + + return DR_OK; +} +#endif + +/**********************************************************************************************************************/ + +static void write_rgb_span( u8 *src, void *dst, int len, DFBSurfacePixelFormat format ) +{ + int i; + + switch (format) { + case DSPF_RGB332: + for (i = 0; i < len; i++) + ((u8*)dst)[i] = PIXEL_RGB332( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_ARGB1555: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_ARGB1555( 0xff, src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_ARGB2554: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_ARGB2554( 0xff, src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_ARGB4444: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_ARGB4444( 0xff, src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_RGB16: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_RGB16( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_RGB24: + direct_memcpy( dst, src, len*3 ); + break; + + case DSPF_RGB32: + for (i = 0; i < len; i++) + ((u32*)dst)[i] = PIXEL_RGB32( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_ARGB: + for (i = 0; i < len; i++) + ((u32*)dst)[i] = PIXEL_ARGB( 0xff, src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_AiRGB: + for (i = 0; i < len; i++) + ((u32*)dst)[i] = PIXEL_AiRGB( 0xff, src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_RGB555: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_RGB555( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_BGR555: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_BGR555( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + case DSPF_RGB444: + for (i = 0; i < len; i++) + ((u16*)dst)[i] = PIXEL_RGB444( src[i*3+0], src[i*3+1], src[i*3+2] ); + break; + + default: + D_ONCE( "unimplemented destination format (0x%08x)", format ); + break; + } +} + +static inline void +copy_line_nv16( u16 *yy, u16 *cbcr, const u8 *src_ycbcr, int width ) +{ + int x; + + D_ASSUME( !(width & 1) ); + + for (x=0; x> 1); + + src_ycbcr += 6; + } +} + +static inline void +copy_line_y( u16 *yy, const u8 *src_ycbcr, int width ) +{ + int x; + + D_ASSUME( !(width & 1) ); + + for (x=0; xx2 - clip->x1 + 1; + ch = clip->y2 - clip->y1 + 1; + + if (cw < 1 || ch < 1) + return DR_INVAREA; + + D_DEBUG_AT( SH7722_JPEG, "%s( %p, %p|%d [%dx%d] %s )\n", __FUNCTION__, + info, addr, pitch, info->width, info->height, + dfb_pixelformat_name(format) ); + + D_DEBUG_AT( SH7722_JPEG, " -> %d,%d - %4dx%4d [clip %d,%d - %4dx%4d]\n", + DFB_RECTANGLE_VALS( rect ), DFB_RECTANGLE_VALS_FROM_REGION( clip ) ); + + /* No cropping or clipping yet :( */ + if (clip->x1 != 0 || clip->y1 != 0 || + clip->x2 != rect->w - 1 || clip->y2 != rect->h - 1 || rect->w != width || rect->h != height) + { + D_UNIMPLEMENTED(); + return DR_UNIMPLEMENTED; + } + + info->cinfo.output_components = 3; + + /* Calculate destination base address. */ + addr += DFB_BYTES_PER_LINE( format, rect->x ) + rect->y * pitch; + + /* Not all formats yet :( */ + switch (format) { + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_ARGB2554: + case DSPF_ARGB4444: + case DSPF_RGB16: + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_RGB555: + case DSPF_BGR555: + case DSPF_RGB444: + info->cinfo.out_color_space = JCS_RGB; + break; + + case DSPF_NV12: + if (rect->x & 1) + return DFB_INVARG; + + if (rect->y & 1) + return DFB_INVARG; + + addr_uv += rect->x + rect->y / 2 * pitch; + + info->cinfo.out_color_space = JCS_YCbCr; + break; + + case DSPF_NV16: + if (rect->x & 1) + return DFB_INVARG; + + addr_uv += rect->x + rect->y * pitch; + + info->cinfo.out_color_space = JCS_YCbCr; + break; + + default: + D_UNIMPLEMENTED(); + return DR_UNIMPLEMENTED; + } + + D_DEBUG_AT( SH7722_JPEG, " -> decoding...\n" ); + + jpeg_start_decompress( &info->cinfo ); + + row_stride = ((info->cinfo.output_width + 1) & ~1) * 3; + + buffer = (*info->cinfo.mem->alloc_sarray)((j_common_ptr) &info->cinfo, JPOOL_IMAGE, row_stride, 1); + + while (info->cinfo.output_scanline < info->cinfo.output_height) { + jpeg_read_scanlines( &info->cinfo, buffer, 1 ); + + switch (format) { + case DSPF_NV12: + if (info->cinfo.output_scanline & 1) { + copy_line_nv16( addr, addr_uv, *buffer, (rect->w + 1) & ~1 ); + addr_uv += pitch; + } + else + copy_line_y( addr, *buffer, (rect->w + 1) & ~1 ); + break; + + case DSPF_NV16: + copy_line_nv16( addr, addr_uv, *buffer, (rect->w + 1) & ~1 ); + addr_uv += pitch; + break; + + default: + write_rgb_span( *buffer, addr, rect->w, format ); + break; + } + + addr += pitch; + } + + jpeg_finish_decompress( &info->cinfo ); + + return DFB_OK; +} + +/**********************************************************************************************************************/ + +static DirectResult +Initialize_GFX( SH7722_JPEG_data *data ) +{ + D_DEBUG_AT( SH7722_JPEG, "%s( %p )\n", __FUNCTION__, data ); + + /* Open the drawing engine device. */ + data->gfx_fd = direct_try_open( "/dev/sh772x_gfx", "/dev/misc/sh772x_gfx", O_RDWR, true ); + if (data->gfx_fd < 0) + return DR_INIT; + + /* Map its shared data. */ + data->gfx_shared = mmap( NULL, direct_page_align( sizeof(SH772xGfxSharedArea) ), + PROT_READ | PROT_WRITE, + MAP_SHARED, data->gfx_fd, 0 ); + if (data->gfx_shared == MAP_FAILED) { + D_PERROR( "SH7722/GFX: Could not map shared area!\n" ); + close( data->gfx_fd ); + return DR_INIT; + } + + D_DEBUG_AT( SH7722_JPEG, " -> magic 0x%08x\n", data->gfx_shared->magic ); + D_DEBUG_AT( SH7722_JPEG, " -> buffer 0x%08lx\n", data->gfx_shared->buffer_phys ); + D_DEBUG_AT( SH7722_JPEG, " -> jpeg 0x%08lx\n", data->gfx_shared->jpeg_phys ); + + /* Check the magic value. */ + if (data->gfx_shared->magic != SH7722GFX_SHARED_MAGIC) { + D_ERROR( "SH7722/GFX: Magic value 0x%08x doesn't match 0x%08x!\n", + data->gfx_shared->magic, SH7722GFX_SHARED_MAGIC ); + munmap( (void*) data->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + close( data->gfx_fd ); + return DR_INIT; + } + + return DR_OK; +} + +static DirectResult +Shutdown_GFX( SH7722_JPEG_data *data ) +{ + munmap( (void*) data->gfx_shared, direct_page_align( sizeof(SH772xGfxSharedArea) ) ); + + close( data->gfx_fd ); + + return DR_OK; +} + +/**********************************************************************************************************************/ + +static DirectResult +Initialize_Mem( SH7722_JPEG_data *data, + unsigned long phys ) +{ + int fd; + + D_DEBUG_AT( SH7722_JPEG, "%s( %p, 0x%08lx )\n", __FUNCTION__, data, phys ); + + fd = open( "/dev/mem", O_RDWR | O_SYNC ); + if (fd < 0) { + D_PERROR( "SH7722/JPEG: Could not open /dev/mem!\n" ); + return DR_INIT; + } + + data->jpeg_virt = mmap( NULL, direct_page_align( SH7722GFX_JPEG_SIZE ), + PROT_READ | PROT_WRITE, MAP_SHARED, fd, phys ); + if (data->jpeg_virt == MAP_FAILED) { + D_PERROR( "SH7722/JPEG: Could not map /dev/mem at 0x%08lx (length %lu)!\n", + phys, direct_page_align( SH7722GFX_JPEG_SIZE ) ); + close( fd ); + return DR_INIT; + } + + data->jpeg_phys = phys; + data->jpeg_lb1 = data->jpeg_phys + SH7722GFX_JPEG_RELOAD_SIZE * 2; + data->jpeg_lb2 = data->jpeg_lb1 + SH7722GFX_JPEG_LINEBUFFER_SIZE; + + close( fd ); + + return DR_OK; +} + +static DirectResult +Shutdown_Mem( SH7722_JPEG_data *data ) +{ + munmap( (void*) data->jpeg_virt, direct_page_align( SH7722GFX_JPEG_SIZE ) ); + + return DR_OK; +} + +/**********************************************************************************************************************/ + +#define JPEG_PROG_BUF_SIZE 0x10000 + +typedef struct { + struct jpeg_source_mgr pub; /* public fields */ + + JOCTET *data; /* start of buffer */ + + DirectStream *stream; + + int peekonly; + int peekoffset; +} stream_source_mgr; + +typedef stream_source_mgr * stream_src_ptr; + +static void +stream_init_source (j_decompress_ptr cinfo) +{ + stream_src_ptr src = (stream_src_ptr) cinfo->src; + + direct_stream_seek( src->stream, 0 ); /* ignore return value */ +} + +static boolean +stream_fill_input_buffer (j_decompress_ptr cinfo) +{ + DFBResult ret; + unsigned int nbytes = 0; + stream_src_ptr src = (stream_src_ptr) cinfo->src; + + struct timeval tv; + + tv.tv_sec = 0; + tv.tv_usec = 50000; + + direct_stream_wait( src->stream, JPEG_PROG_BUF_SIZE, &tv ); + + if (src->peekonly) { + ret = direct_stream_peek( src->stream, JPEG_PROG_BUF_SIZE, src->peekoffset, src->data, &nbytes ); + if (ret && ret != DFB_EOF) + D_DERROR( ret, "SH7722/JPEG: direct_stream_peek() failed!\n" ); + + src->peekoffset += MAX( nbytes, 0 ); + } + else { + ret = direct_stream_read( src->stream, JPEG_PROG_BUF_SIZE, src->data, &nbytes ); + if (ret && ret != DFB_EOF) + D_DERROR( ret, "SH7722/JPEG: direct_stream_read() failed!\n" ); + } + + if (ret || nbytes <= 0) { + /* Insert a fake EOI marker */ + src->data[0] = (JOCTET) 0xFF; + src->data[1] = (JOCTET) JPEG_EOI; + nbytes = 2; + } + + src->pub.next_input_byte = src->data; + src->pub.bytes_in_buffer = nbytes; + + return TRUE; +} + +static void +stream_skip_input_data (j_decompress_ptr cinfo, long num_bytes) +{ + stream_src_ptr src = (stream_src_ptr) cinfo->src; + + if (num_bytes > 0) { + while (num_bytes > (long) src->pub.bytes_in_buffer) { + num_bytes -= (long) src->pub.bytes_in_buffer; + (void)stream_fill_input_buffer(cinfo); + } + src->pub.next_input_byte += (size_t) num_bytes; + src->pub.bytes_in_buffer -= (size_t) num_bytes; + } +} + +static void +stream_term_source (j_decompress_ptr cinfo) +{ +} + +static void +jpeg_stream_src (j_decompress_ptr cinfo, DirectStream *stream, int peekonly) +{ + stream_src_ptr src; + + cinfo->src = (struct jpeg_source_mgr *) + cinfo->mem->alloc_small ((j_common_ptr) cinfo, JPOOL_PERMANENT, + sizeof (stream_source_mgr)); + + src = (stream_src_ptr) cinfo->src; + + src->data = (JOCTET *) + cinfo->mem->alloc_small ((j_common_ptr) cinfo, JPOOL_PERMANENT, + JPEG_PROG_BUF_SIZE * sizeof (JOCTET)); + + src->stream = stream; + src->peekonly = peekonly; + src->peekoffset = 0; + + src->pub.init_source = stream_init_source; + src->pub.fill_input_buffer = stream_fill_input_buffer; + src->pub.skip_input_data = stream_skip_input_data; + src->pub.resync_to_restart = jpeg_resync_to_restart; /* use default method */ + src->pub.term_source = stream_term_source; + src->pub.bytes_in_buffer = 0; /* forces fill_input_buffer on first read */ + src->pub.next_input_byte = NULL; /* until buffer loaded */ +} + +struct my_error_mgr { + struct jpeg_error_mgr pub; /* "public" fields */ + jmp_buf setjmp_buffer; /* for return to caller */ +}; + +static void +jpeglib_panic(j_common_ptr cinfo) +{ + struct my_error_mgr *myerr = (struct my_error_mgr*) cinfo->err; + longjmp(myerr->setjmp_buffer, 1); +} + +/**********************************************************************************************************************/ + +static SH7722_JPEG_data data; + +DirectResult +SH7722_JPEG_Initialize( void ) +{ + DirectResult ret; + + if (data.ref_count) { + data.ref_count++; + return DR_OK; + } + + ret = Initialize_GFX( &data ); + if (ret) + return ret; + + ret = Initialize_Mem( &data, data.gfx_shared->jpeg_phys ); + if (ret) { + Shutdown_GFX( &data ); + return ret; + } + + data.ref_count = 1; + + return DR_OK; +} + +DirectResult +SH7722_JPEG_Shutdown( void ) +{ + if (!data.ref_count) + return DR_DEAD; + + if (--data.ref_count) + return DR_OK; + + Shutdown_Mem( &data ); + + Shutdown_GFX( &data ); + + return DR_OK; +} + +DirectResult +SH7722_JPEG_Open( DirectStream *stream, + SH7722_JPEG_context *context ) +{ + struct my_error_mgr jerr; + + if (!data.ref_count) + return DR_DEAD; + + context->cinfo.err = jpeg_std_error( &jerr.pub ); + jerr.pub.error_exit = jpeglib_panic; + + if (setjmp( jerr.setjmp_buffer )) { + D_ERROR( "SH7722/JPEG: Error while reading headers!\n" ); + + jpeg_destroy_decompress( &context->cinfo ); + return DFB_FAILURE; + } + + jpeg_create_decompress( &context->cinfo ); + jpeg_stream_src( &context->cinfo, stream, 1 ); + jpeg_read_header( &context->cinfo, TRUE ); + jpeg_calc_output_dimensions( &context->cinfo ); + + context->stream = stream; + context->width = context->cinfo.output_width; + context->height = context->cinfo.output_height; + + context->mode420 = context->cinfo.comp_info[1].h_samp_factor == context->cinfo.comp_info[0].h_samp_factor / 2 && + context->cinfo.comp_info[1].v_samp_factor == context->cinfo.comp_info[0].v_samp_factor / 2 && + context->cinfo.comp_info[2].h_samp_factor == context->cinfo.comp_info[0].h_samp_factor / 2 && + context->cinfo.comp_info[2].v_samp_factor == context->cinfo.comp_info[0].v_samp_factor / 2; + + context->mode444 = context->cinfo.comp_info[1].h_samp_factor == context->cinfo.comp_info[0].h_samp_factor && + context->cinfo.comp_info[1].v_samp_factor == context->cinfo.comp_info[0].v_samp_factor && + context->cinfo.comp_info[2].h_samp_factor == context->cinfo.comp_info[0].h_samp_factor && + context->cinfo.comp_info[2].v_samp_factor == context->cinfo.comp_info[0].v_samp_factor; + + return DFB_OK; +} + +DirectResult +SH7722_JPEG_Decode( SH7722_JPEG_context *context, + const DFBRectangle *rect, + const DFBRegion *clip, + DFBSurfacePixelFormat format, + unsigned long phys, + void *addr, + int pitch, + unsigned int width, + unsigned int height ) +{ + DFBResult ret = DFB_UNSUPPORTED; + DFBRectangle _rect; + DFBRegion _clip; + struct my_error_mgr jerr; + bool sw_only = false; + + if (!data.ref_count) + return DR_DEAD; + + context->cinfo.err = jpeg_std_error( &jerr.pub ); + jerr.pub.error_exit = jpeglib_panic; + + if (setjmp( jerr.setjmp_buffer )) { + D_ERROR( "SH7722/JPEG: Error while decoding image!\n" ); + return DFB_FAILURE; + } + + switch (format) { + case DSPF_NV12: + case DSPF_NV16: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_RGB24: + break; + + case DSPF_RGB332: + case DSPF_ARGB1555: + case DSPF_ARGB2554: + case DSPF_ARGB4444: + case DSPF_ARGB: + case DSPF_AiRGB: + case DSPF_RGB555: + case DSPF_BGR555: + case DSPF_RGB444: + sw_only = true; + break; + + default: + return DR_UNSUPPORTED; + } + + if (!rect) { + _rect.x = 0; + _rect.y = 0; + _rect.w = width; + _rect.h = height; + + rect = &_rect; + } + + if (!clip) { + _clip.x1 = _rect.x; + _clip.y1 = _rect.y; + _clip.x2 = _rect.x + _rect.w - 1; + _clip.y2 = _rect.y + _rect.h - 1; + + clip = &_clip; + } + + if (!context->mode444 && !sw_only) + ret = DecodeHW( &data, context, rect, clip, format, phys, pitch, width, height ); + + if (ret) { + if (addr) { + ret = DecodeSW( context, rect, clip, format, addr, pitch, width, height ); + } + else { + int fd, len = direct_page_align( DFB_PLANE_MULTIPLY( format, height ) * pitch ); + + fd = open( "/dev/mem", O_RDWR | O_SYNC ); + if (fd < 0) { + D_PERROR( "SH7722/JPEG: Could not open /dev/mem!\n" ); + return DR_INIT; + } + + addr = mmap( NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, phys ); + if (addr == MAP_FAILED) { + D_PERROR( "SH7722/JPEG: Could not map /dev/mem at 0x%08lx (length %d)!\n", phys, len ); + close( fd ); + return DR_INIT; + } + + ret = DecodeSW( context, rect, clip, format, addr, pitch, width, height ); + + munmap( addr, len ); + } + } + + return ret; +} + + +DirectResult +SH7722_JPEG_Close( SH7722_JPEG_context *context ) +{ + jpeg_destroy_decompress( &context->cinfo ); + + return DFB_OK; +} + +DirectResult +SH7722_JPEG_Encode( const char *filename, + const DFBRectangle *srcrect, + DFBSurfacePixelFormat srcformat, + unsigned long srcphys, + int srcpitch, + unsigned int width, + unsigned int height, + unsigned int tmpphys ) +{ + DFBRectangle _rect; + + if (!data.ref_count) + return DR_DEAD; + + switch (srcformat) { + case DSPF_NV12: + case DSPF_NV16: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_RGB24: + break; + + default: + return DR_UNSUPPORTED; + } + + if (!srcrect) { + _rect.x = 0; + _rect.y = 0; + _rect.w = width; + _rect.h = height; + + srcrect = &_rect; + } + + return EncodeHW( &data, filename, srcrect, srcformat, srcphys, srcpitch, width, height, tmpphys ); +} + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.h new file mode 100755 index 0000000..506a422 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpeglib.h @@ -0,0 +1,47 @@ +#ifndef __SH7722__SH7722_JPEGLIB_H__ +#define __SH7722__SH7722_JPEGLIB_H__ + +#include + +typedef struct { + DirectStream *stream; + + int width; + int height; + bool mode420; + bool mode444; + + struct jpeg_decompress_struct cinfo; +} SH7722_JPEG_context; + + +DirectResult SH7722_JPEG_Initialize( void ); + +DirectResult SH7722_JPEG_Shutdown( void ); + +DirectResult SH7722_JPEG_Open ( DirectStream *stream, + SH7722_JPEG_context *context ); + +DirectResult SH7722_JPEG_Decode( SH7722_JPEG_context *context, + const DFBRectangle *rect, + const DFBRegion *clip, + DFBSurfacePixelFormat format, + unsigned long phys, + void *addr, + int pitch, + unsigned int width, + unsigned int height ); + +DirectResult SH7722_JPEG_Close ( SH7722_JPEG_context *context ); + +DirectResult SH7722_JPEG_Encode( const char *filename, + const DFBRectangle *srcrect, + DFBSurfacePixelFormat srcformat, + unsigned long srcphys, + int srcpitch, + unsigned int width, + unsigned int height, + unsigned int tmpphys ); + + +#endif diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpegtool.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpegtool.c new file mode 100755 index 0000000..5fd0fad --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_jpegtool.c @@ -0,0 +1,142 @@ +#ifdef SH7722_DEBUG_JPEG +#define DIRECT_ENABLE_DEBUG +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef STANDALONE +#include "sh7722_jpeglib_standalone.h" +#else +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#endif + +#include "sh7722_jpeglib.h" + + +void +write_ppm( const char *filename, + unsigned long phys, + int pitch, + unsigned int width, + unsigned int height ) +{ + int i; + int fd; + int size; + void *mem; + FILE *file; + + size = direct_page_align( pitch * height ); + + fd = open( "/dev/mem", O_RDWR ); + if (fd < 0) { + D_PERROR( "SH7722/JPEG: Could not open /dev/mem!\n" ); + return; + } + + mem = mmap( NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, phys ); + if (mem == MAP_FAILED) { + D_PERROR( "SH7722/JPEG: Could not map /dev/mem at 0x%08lx (length %d)!\n", phys, size ); + close( fd ); + return; + } + + close( fd ); + + file = fopen( filename, "wb" ); + if (!file) { + D_PERROR( "SH7722/JPEG: Could not open '%s' for writing!\n", filename ); + munmap( mem, size ); + return; + } + + fprintf( file, "P6\n%d %d\n255\n", width, height ); + + for (i=0; i\n", argv[0] ); + return -1; + } + +#ifndef STANDALONE + direct_initialize(); + + direct_config->debug = true; +#endif + + ret = SH7722_JPEG_Initialize(); + if (ret) + return ret; + + ret = direct_stream_create( argv[1], &stream ); + if (ret) + goto out; + + ret = SH7722_JPEG_Open( stream, &info ); + if (ret) + goto out; + + D_INFO( "SH7722/JPEGTool: Opened %dx%d image (4:%s)\n", info.width, info.height, + info.mode420 ? "2:0" : info.mode444 ? "4:4" : "2:2?" ); + + format = DSPF_RGB24;// info.mode444 ? DSPF_NV16 : DSPF_NV12; + pitch = (DFB_BYTES_PER_LINE( format, info.width ) + 31) & ~31; + + ret = SH7722_JPEG_Decode( &info, NULL, NULL, format, 0x0f800000, NULL, pitch, info.width, info.height ); + if (ret) + goto out; + + +// Use RGB24 format for this +// write_ppm( "test.ppm", 0x0f800000, pitch, info.width, info.height ); + + ret = SH7722_JPEG_Encode( "test.jpg", NULL, format, 0x0f800000, pitch, info.width, info.height, 0 ); + if (ret) + goto out; + + +out: + if (stream) + direct_stream_destroy( stream ); + + SH7722_JPEG_Shutdown(); + + return ret; +} diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.c new file mode 100755 index 0000000..8628ee8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.c @@ -0,0 +1,529 @@ +#ifdef SH7722_DEBUG_LAYER +#define DIRECT_ENABLE_DEBUG +#endif + + +#include + +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include "sh7722.h" +#include "sh7722_types.h" +#include "sh7722_layer.h" +#include "sh7722_lcd.h" + + +D_DEBUG_DOMAIN( SH7722_Layer, "SH7722/Layer", "Renesas SH7722 Layers" ); + +/**********************************************************************************************************************/ + +static int +sh7722LayerDataSize( void ) +{ + return sizeof(SH7722LayerData); +} + +static int +sh7722RegionDataSize( void ) +{ + return sizeof(SH7722RegionData); +} + +static DFBResult +sh7722InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722LayerData *data = layer_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + /* initialize layer data */ + data->layer = SH7722_LAYER_INPUT1 + sdrv->num_inputs++; + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_ALPHACHANNEL | DLCAPS_OPACITY | + DLCAPS_SCREEN_POSITION | DLCAPS_SRC_COLORKEY; + + description->type = DLTF_STILL_PICTURE | DLTF_GRAPHICS | DLTF_VIDEO; + + /* set name */ + snprintf( description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Input %d", sdrv->num_inputs ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = sdev->lcd_width;; + config->height = sdev->lcd_height; + config->pixelformat = DSPF_RGB16; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_ALPHACHANNEL; + + return DFB_OK; +} + +static DFBResult +sh7722TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722LayerData *slay = layer_data; + CoreLayerRegionConfigFlags fail = 0; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + if (config->options & ~SH7722_LAYER_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + switch (config->format) { + case DSPF_LUT8: + /* Indexed only for third input */ + if (slay->layer != SH7722_LAYER_INPUT3) + fail |= CLRCF_FORMAT; + break; + + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB24: + case DSPF_RGB16: + break; + + case DSPF_NV12: + case DSPF_NV16: + /* YUV only for first input */ + if (slay->layer != SH7722_LAYER_INPUT1) + fail |= CLRCF_FORMAT; + break; + + default: + fail |= CLRCF_FORMAT; + } + + if (config->width < 32 || config->width > sdev->lcd_width) + fail |= CLRCF_WIDTH; + + if (config->height < 32 || config->height > sdev->lcd_height) + fail |= CLRCF_HEIGHT; + + if (config->dest.x >= sdev->lcd_width || config->dest.y >= sdev->lcd_height) + fail |= CLRCF_DEST; + + if (config->dest.x < 0) { + config->dest.x = 0; +// FIXME +// fail |= CLRCF_DEST; + } + + if (config->dest.y < 0) { + config->dest.y = 0; +// FIXME +// fail |= CLRCF_DEST; + } + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +sh7722AddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + SH7722RegionData *sreg = region_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + sreg->config = *config; + + D_MAGIC_SET( sreg, SH7722RegionData ); + + return DFB_OK; +} + +static DFBResult +sh7722SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + int i, n; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722RegionData *sreg = region_data; + SH7722LayerData *slay = layer_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( sreg, SH7722RegionData ); + + n = slay->layer - SH7722_LAYER_INPUT1; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 2 ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Wait for idle BEU. */ + BEU_Wait( sdrv, sdev ); + + /* Update position? */ + if (updated & CLRCF_DEST) { + /* Set horizontal and vertical offset. */ + SH7722_SETREG32( sdrv, BLOCR(n), (config->dest.y << 16) | config->dest.x ); + } + + /* Update size? */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT)) { + int cw = config->width; + int ch = config->height; + + if (config->dest.x + cw > sdev->lcd_width) + cw = sdev->lcd_width - config->dest.x; + + if (config->dest.y + ch > sdev->lcd_height) + ch = sdev->lcd_height - config->dest.y; + + /* Set width and height. */ + SH7722_SETREG32( sdrv, BSSZR(n), (ch << 16) | cw ); + SH7722_SETREG32( sdrv, BTPSR, (ch << 16) | cw ); + } + + /* Update surface? */ + if (updated & CLRCF_SURFACE) { + CoreSurfaceBuffer *buffer = lock->buffer; + + /* Set buffer pitch. */ + SH7722_SETREG32( sdrv, BSMWR(n), lock->pitch ); + + /* Set buffer offset (Y plane or RGB packed). */ + SH7722_SETREG32( sdrv, BSAYR(n), lock->phys ); + + /* Set buffer offset (UV plane). */ + if (DFB_PLANAR_PIXELFORMAT(buffer->format)) { + D_ASSUME( buffer->format == DSPF_NV12 || buffer->format == DSPF_NV16 ); + + SH7722_SETREG32( sdrv, BSACR(n), lock->phys + lock->pitch * surface->config.size.h ); + } + + sreg->surface = surface; + } + + /* Update format? */ + if (updated & CLRCF_FORMAT) { + unsigned long tBSIFR = 0; + unsigned long tBSWPR = BSWPR_MODSEL_EACH | (SH7722_GETREG32( sdrv, BSWPR ) & ~(7 << (n*8))); + + /* Set pixel format. */ + switch (config->format) { + case DSPF_NV12: + tBSIFR |= CHRR_YCBCR_420 | BSIFR1_IN1TE_RGBYUV; + break; + + case DSPF_NV16: + tBSIFR |= CHRR_YCBCR_422 | BSIFR1_IN1TE_RGBYUV; + break; + + case DSPF_ARGB: + tBSIFR |= RPKF_ARGB; + break; + + case DSPF_RGB32: + tBSIFR |= RPKF_RGB32; + break; + + case DSPF_RGB24: + tBSIFR |= RPKF_RGB24; + break; + + case DSPF_RGB16: + tBSIFR |= RPKF_RGB16; + break; + + case DSPF_LUT8: + tBSIFR |= BSIFR3_MOD0_OSD | BSIFR3_MOD1_LUT; + break; + + default: + break; + } + +#if 0 + /* Set swapping. */ + switch (config->format) { + case DSPF_LUT8: + case DSPF_NV12: + case DSPF_NV16: + tBSWPR |= (BSWPR_INPUT_BYTESWAP | + BSWPR_INPUT_WORDSWAP | + BSWPR_INPUT_LONGSWAP) << (n*8); + break; + + case DSPF_RGB16: + tBSWPR |= (BSWPR_INPUT_WORDSWAP | + BSWPR_INPUT_LONGSWAP) << (n*8); + break; + + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB24: + tBSWPR |= (BSWPR_INPUT_LONGSWAP) << (n*8); + break; + + default: + break; + } +#endif + + SH7722_SETREG32( sdrv, BSIFR(n), tBSIFR ); + SH7722_SETREG32( sdrv, BSWPR, tBSWPR ); + } + + /* Update options or opacity? */ + if (updated & (CLRCF_OPTIONS | CLRCF_OPACITY | CLRCF_FORMAT)) { + unsigned long tBBLCR0 = BBLCR0_LAY_123; + + /* Set opacity value. */ + tBBLCR0 &= ~(0xff << (n*8)); + tBBLCR0 |= ((config->options & CLRCF_OPACITY) ? config->opacity : 0xff) << (n*8); + + /* Enable/disable alpha channel. */ + if ((config->options & DLOP_ALPHACHANNEL) && DFB_PIXELFORMAT_HAS_ALPHA(config->format)) + tBBLCR0 |= BBLCR0_AMUX_BLENDPIXEL(n); + else + tBBLCR0 &= ~BBLCR0_AMUX_BLENDPIXEL(n); + + SH7722_SETREG32( sdrv, BBLCR0, tBBLCR0 ); + } + + /* Update CLUT? */ + if (updated & CLRCF_PALETTE && palette) { + const DFBColor *entries = palette->entries; + + for (i=0; i<256; i++) { + SH7722_SETREG32( sdrv, BCLUT(i), PIXEL_ARGB( entries[i].a, + entries[i].r, + entries[i].g, + entries[i].b ) ); + } + } + + + /* Enable or disable input. */ + if ((config->options & DLOP_OPACITY) && !config->opacity) + sdev->input_mask &= ~(1 << n); + else + sdev->input_mask |= (1 << n); + + /* Choose parent input. */ + if (sdev->input_mask) { + unsigned long tBBLCR1 = SH7722_GETREG32( sdrv, BBLCR1 ) & ~BBLCR1_PWD_INPUT_MASK; + + if (sdev->input_mask & 4) + tBBLCR1 |= BBLCR1_PWD_INPUT3; + else if (sdev->input_mask & 2) + tBBLCR1 |= BBLCR1_PWD_INPUT2; + else + tBBLCR1 |= BBLCR1_PWD_INPUT1; + + SH7722_SETREG32( sdrv, BBLCR1, tBBLCR1 ); + } + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + sreg->config = *config; + + return DFB_OK; +} + +static DFBResult +sh7722RemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + int n; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722LayerData *slay = layer_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_ASSERT( sdev != NULL ); + D_ASSERT( slay != NULL ); + + n = slay->layer - SH7722_LAYER_INPUT1; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 2 ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Wait for idle BEU. */ + BEU_Wait( sdrv, sdev ); + + sdev->input_mask &= ~(1 << n); + + /* Choose parent input. */ + if (sdev->input_mask) { + unsigned long tBBLCR1 = SH7722_GETREG32( sdrv, BBLCR1 ) & ~BBLCR1_PWD_INPUT_MASK; + + if (sdev->input_mask & 4) + tBBLCR1 |= BBLCR1_PWD_INPUT3; + else if (sdev->input_mask & 2) + tBBLCR1 |= BBLCR1_PWD_INPUT2; + else + tBBLCR1 |= BBLCR1_PWD_INPUT1; + + SH7722_SETREG32( sdrv, BBLCR1, tBBLCR1 ); + } + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + return DFB_OK; +} + +static DFBResult +sh7722FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + int n; + CoreSurfaceBuffer *buffer; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722LayerData *slay = layer_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( sdrv != NULL ); + D_ASSERT( sdev != NULL ); + D_ASSERT( slay != NULL ); + + n = slay->layer - SH7722_LAYER_INPUT1; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 2 ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Set buffer offset (Y plane or RGB packed). */ + SH7722_SETREG32( sdrv, BSAYR(n), lock->phys ); + + /* Set buffer offset (UV plane). */ + if (DFB_PLANAR_PIXELFORMAT(buffer->format)) { + D_ASSUME( buffer->format == DSPF_NV12 || buffer->format == DSPF_NV16 ); + + SH7722_SETREG32( sdrv, BSACR(n), lock->phys + lock->pitch * surface->config.size.h ); + } + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + /* Wait for idle BEU? */ + if (flags & DSFLIP_WAIT) + BEU_Wait( sdrv, sdev ); + + dfb_surface_flip( surface, false ); + + return DFB_OK; +} + +static DFBResult +sh7722UpdateRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + const DFBRegion *update, + CoreSurfaceBufferLock *lock ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( sdrv != NULL ); + D_ASSERT( sdev != NULL ); + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + if (!(surface->config.caps & DSCAPS_FLIPPING)) + BEU_Wait( sdrv, sdev ); + + return DFB_OK; +} + +DisplayLayerFuncs sh7722LayerFuncs = { + .LayerDataSize = sh7722LayerDataSize, + .RegionDataSize = sh7722RegionDataSize, + .InitLayer = sh7722InitLayer, + + .TestRegion = sh7722TestRegion, + .AddRegion = sh7722AddRegion, + .SetRegion = sh7722SetRegion, + .RemoveRegion = sh7722RemoveRegion, + .FlipRegion = sh7722FlipRegion, + .UpdateRegion = sh7722UpdateRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.h new file mode 100755 index 0000000..b704214 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_layer.h @@ -0,0 +1,11 @@ +#ifndef __SH7722__LAYER_H__ +#define __SH7722__LAYER_H__ + +#include "sh7722_types.h" + +#define SH7722_LAYER_SUPPORTED_OPTIONS (DLOP_ALPHACHANNEL | DLOP_OPACITY | DLOP_SRC_COLORKEY) + +extern DisplayLayerFuncs sh7722LayerFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.c new file mode 100755 index 0000000..47df333 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.c @@ -0,0 +1,172 @@ +#ifdef SH7722_DEBUG_LCD +#define DIRECT_ENABLE_DEBUG +#endif + + +#include + +#include + +#include + +#include + +#include "sh7722.h" + + +D_DEBUG_DOMAIN( SH7722_LCD, "SH7722/LCD", "Renesas SH7722 LCD" ); + +/**********************************************************************************************************************/ + +void +sh7722_lcd_setup( void *drv, + int width, + int height, + ulong phys, + int pitch, + DFBSurfacePixelFormat format, + bool swap ) +{ + u32 MLDDFR = 0; + u32 LDDDSR = 0; + u32 reg; + + D_DEBUG_AT( SH7722_LCD, "%s( %dx%d @%lu:%d )\n", __FUNCTION__, width, height, phys, pitch ); + + D_ASSERT( width > 7 ); + D_ASSERT( height > 0 ); + + D_ASSERT( (phys & 7) == 0 ); + + D_ASSERT( pitch > 0 ); + D_ASSERT( pitch < 0x10000 ); + D_ASSERT( (pitch & 3) == 0 ); + + /* Choose input format. */ + switch (format) { + case DSPF_RGB32: + case DSPF_ARGB: + MLDDFR = 0; + break; + + case DSPF_RGB16: + MLDDFR = 3; + break; + + case DSPF_RGB444: + case DSPF_ARGB4444: + MLDDFR = 8; + break; + + case DSPF_RGB24: + MLDDFR = 11; + break; + + case DSPF_NV12: + MLDDFR = 0x10000; + break; + + case DSPF_NV16: + MLDDFR = 0x10100; + break; + + default: + D_BUG( "invalid format" ); + return; + } + + /* Setup swapping. */ + switch (format) { + case DSPF_NV12: /* 1 byte */ + case DSPF_NV16: + case DSPF_RGB24: + LDDDSR = 7; + break; + + case DSPF_RGB16: /* 2 byte */ + case DSPF_RGB444: + case DSPF_ARGB4444: + LDDDSR = 6; + break; + + case DSPF_RGB32: /* 4 byte */ + case DSPF_ARGB: + LDDDSR = 4; + break; + + default: + D_BUG( "invalid format" ); + return; + } + + /* software reset of the LCD device */ + reg = SH7722_GETREG32( drv, LCDC_LDCNT2R ); + SH7722_SETREG32( drv, LCDC_LDCNT2R, reg | 0x100 ); + while( SH7722_GETREG32( drv, LCDC_LDCNT2R ) & 0x100 ); + + /* stop the LCD while configuring */ + SH7722_SETREG32( drv, LCDC_LDCNT2R, 0 ); + SH7722_SETREG32( drv, LCDC_LDDCKSTPR, 1 ); + + SH7722_SETREG32( drv, LCDC_MLDDCKPAT1R, 0x05555555 ); + SH7722_SETREG32( drv, LCDC_MLDDCKPAT2R, 0x55555555 ); + SH7722_SETREG32( drv, LCDC_LDDCKR, 0x0000003c ); + SH7722_SETREG32( drv, LCDC_MLDMT2R, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_MLDMT3R, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_MLDDFR, MLDDFR ); + SH7722_SETREG32( drv, LCDC_MLDSM1R, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_MLDSM2R, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_MLDSA1R, phys ); + SH7722_SETREG32( drv, LCDC_MLDSA2R, DFB_PLANAR_PIXELFORMAT( format ) ? (phys + pitch * height) : 0 ); + SH7722_SETREG32( drv, LCDC_MLDMLSR, pitch ); + SH7722_SETREG32( drv, LCDC_MLDWBCNTR, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_MLDWBAR, 0x00000000 ); +#if 0 + SH7722_SETREG32( drv, LCDC_MLDMT1R, 0x18000006 ); + SH7722_SETREG32( drv, LCDC_MLDHCNR, ((width / 8) << 16) | (1056 / 8) ); + SH7722_SETREG32( drv, LCDC_MLDHSYNR, ((128 / 8) << 16) | (840 / 8) ); + SH7722_SETREG32( drv, LCDC_MLDVLNR, (height << 16) | 525 ); + SH7722_SETREG32( drv, LCDC_MLDVSYNR, (2 << 16) | 490 ); + SH7722_SETREG32( drv, LCDC_MLDPMR, 0xf6000f00 ); +#elif 0 + SH7722_SETREG32( drv, LCDC_MLDMT1R, 0x1c00000a ); + SH7722_SETREG32( drv, LCDC_MLDHCNR, 0x00500060); + SH7722_SETREG32( drv, LCDC_MLDHSYNR, 0x00010052); + SH7722_SETREG32( drv, LCDC_MLDVLNR, 0x01e00200); + SH7722_SETREG32( drv, LCDC_MLDVSYNR, 0x000301f0); + SH7722_SETREG32( drv, LCDC_MLDPMR, 0x00000000 ); //igel +#elif defined(SH7722_ALGO_PANEL) + SH7722_SETREG32( drv, LCDC_MLDMT1R, 0x1c00000a ); + SH7722_SETREG32( drv, LCDC_MLDHCNR, 0x00500060); + SH7722_SETREG32( drv, LCDC_MLDHSYNR, 0x00010052); + SH7722_SETREG32( drv, LCDC_MLDVLNR, 0x01e0020e); + SH7722_SETREG32( drv, LCDC_MLDVSYNR, 0x000301f0); + SH7722_SETREG32( drv, LCDC_MLDPMR, 0x00000000 ); //igel +#elif defined(ALGO_AP325) + SH7722_SETREG32( drv, LCDC_MLDMT1R, 0x1800000a ); + SH7722_SETREG32( drv, LCDC_MLDHCNR, ((width / 8) << 16) | (1000 / 8) ); + SH7722_SETREG32( drv, LCDC_MLDHSYNR, ((8 / 8) << 16) | (960 / 8) ); + SH7722_SETREG32( drv, LCDC_MLDVLNR, (height << 16) | 624 ); + SH7722_SETREG32( drv, LCDC_MLDVSYNR, (1 << 16) | 560 ); + SH7722_SETREG32( drv, LCDC_MLDPMR, 0x00000000 ); +#endif + SH7722_SETREG32( drv, LCDC_LDINTR, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_LDRCNTR, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_LDDDSR, swap ? LDDDSR : 0 ); + SH7722_SETREG32( drv, LCDC_LDRCR, 0x00000000 ); + SH7722_SETREG32( drv, LCDC_LDPALCR, 0x00000000 ); + + /* enable and start displaying */ + SH7722_SETREG32( drv, LCDC_LDCNT1R, 0x00000001 ); + SH7722_SETREG32( drv, LCDC_LDCNT2R, 0x00000003 ); + SH7722_SETREG32( drv, LCDC_LDDCKSTPR, 0 ); + while( SH7722_GETREG32( drv, LCDC_LDDCKSTPR ) & 0x10000 ); + + /* finally, turn the display on */ + { + SH7722DriverData *sdrv = drv; + if (ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_POWER_DISPLAY ) < 0) + D_PERROR( "SH772xGFX_IOCTL_POWER_DISPLAY\n" ); + } +} + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.h new file mode 100755 index 0000000..4e0a12d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_lcd.h @@ -0,0 +1,17 @@ +#ifndef __SH7722__LCD_H__ +#define __SH7722__LCD_H__ + +#include "sh7722_types.h" + + +void sh7722_lcd_setup( void *drv, + int width, + int height, + ulong phys, + int pitch, + DFBSurfacePixelFormat format, + bool swap ); + + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.c new file mode 100755 index 0000000..d15871d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.c @@ -0,0 +1,412 @@ +#ifdef SH7722_DEBUG_LAYER +#define DIRECT_ENABLE_DEBUG +#endif + + +#include + +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +#include "sh7722.h" +#include "sh7722_types.h" +#include "sh7722_multi.h" + + +D_DEBUG_DOMAIN( SH7722_Layer, "SH7722/Layer", "Renesas SH7722 Layers" ); + +/**********************************************************************************************************************/ + +static int +sh7722LayerDataSize( void ) +{ + return sizeof(SH7722MultiLayerData); +} + +static int +sh7722RegionDataSize( void ) +{ + return sizeof(SH7722MultiRegionData); +} + +static DFBResult +sh7722InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_POSITION | DLCAPS_SRC_COLORKEY | DLCAPS_WINDOWS; + description->type = DLTF_GRAPHICS; + description->regions = 4; + + /* set name */ + snprintf( description->name, DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "Multi Window" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + config->width = sdev->lcd_width; + config->height = sdev->lcd_height; + config->pixelformat = DSPF_NV16; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + return DFB_OK; +} + +static DFBResult +sh7722TestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + CoreLayerRegionConfigFlags fail = 0; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + if (config->options & ~SH7722_MULTI_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + switch (config->format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB24: + case DSPF_RGB16: + break; + +#if FIXME_MAKE_CONFIGURABLE_ + case DSPF_NV12: + case DSPF_NV16: + break; +#endif + + default: + fail |= CLRCF_FORMAT; + } + + if (config->width < 32 || config->width > 1280) + fail |= CLRCF_WIDTH; + + if (config->height < 32 || config->height > 1024) + fail |= CLRCF_HEIGHT; + + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +sh7722AddRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config ) +{ + int n; + SH7722MultiRegionData *sreg = region_data; + SH7722MultiLayerData *slay = layer_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + if (slay->added == 0xF) + return DFB_LIMITEXCEEDED; + + for (n=0; n<4; n++) + if (! (slay->added & (1 << n))) + break; + + D_ASSERT( n < 4 ); + + sreg->config = *config; + + + slay->added |= 1 << n; + + D_MAGIC_SET( sreg, SH7722MultiRegionData ); + + return DFB_OK; +} + +static DFBResult +sh7722SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + int n; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722MultiRegionData *sreg = region_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( sreg, SH7722MultiRegionData ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Wait for idle BEU. */ + BEU_Wait( sdrv, sdev ); + + n = sreg->index; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 3 ); + + /* Update position? */ + if (updated & CLRCF_DEST) { + /* Set horizontal and vertical offset. */ + SH7722_SETREG32( sdrv, BMLOCR(n), (config->dest.y << 16) | config->dest.x ); + } + + /* Update size? */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT)) { + /* Set width and height. */ + SH7722_SETREG32( sdrv, BMSSZR(n), (config->height << 16) | config->width ); + } + + /* Update surface? */ + if (updated & CLRCF_SURFACE) { + CoreSurfaceBuffer *buffer; + + D_ASSERT( surface != NULL ); + + buffer = lock->buffer; + + D_ASSERT( buffer != NULL ); + + /* Set buffer pitch. */ + SH7722_SETREG32( sdrv, BMSMWR(n), lock->pitch ); + + /* Set buffer offset (Y plane or RGB packed). */ + SH7722_SETREG32( sdrv, BMSAYR(n), lock->phys ); + + /* Set buffer offset (UV plane). */ + if (DFB_PLANAR_PIXELFORMAT(buffer->format)) { + D_ASSUME( buffer->format == DSPF_NV12 || buffer->format == DSPF_NV16 ); + + SH7722_SETREG32( sdrv, BMSACR(n), lock->phys + lock->pitch * surface->config.size.h ); + } + } + + /* Update format? */ + if (updated & CLRCF_FORMAT) { + unsigned long tBMSIFR = 0; + + /* Set pixel format. */ + switch (config->format) { + case DSPF_NV12: + tBMSIFR |= CHRR_YCBCR_420; + break; + + case DSPF_NV16: + tBMSIFR |= CHRR_YCBCR_422; + break; + + case DSPF_ARGB: + tBMSIFR |= RPKF_ARGB; + break; + + case DSPF_RGB32: + tBMSIFR |= RPKF_RGB32; + break; + + case DSPF_RGB24: + tBMSIFR |= RPKF_RGB24; + break; + + case DSPF_RGB16: + tBMSIFR |= RPKF_RGB16; + break; + + default: + break; + } + + /* FIXME: all regions need to have the same format! */ + SH7722_SETREG32( sdrv, BMSIFR, tBMSIFR ); + } + + SH7722_SETREG32( sdrv, BMWCR0, SH7722_GETREG32( sdrv, BMWCR0 ) | (1 << n) ); + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + return DFB_OK; +} + +static DFBResult +sh7722RemoveRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + int n; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722MultiRegionData *sreg = region_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_MAGIC_ASSERT( sreg, SH7722MultiRegionData ); + + n = sreg->index; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 3 ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Wait for idle BEU. */ + BEU_Wait( sdrv, sdev ); + + /* Disable multi window. */ + SH7722_SETREG32( sdrv, BMWCR0, SH7722_GETREG32( sdrv, BMWCR0 ) & ~(1 << n) ); + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + return DFB_OK; +} + +static DFBResult +sh7722FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + int n; + CoreSurfaceBuffer *buffer; + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + SH7722MultiRegionData *sreg = region_data; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( sdrv != NULL ); + D_ASSERT( sdev != NULL ); + D_MAGIC_ASSERT( sreg, SH7722MultiRegionData ); + + n = sreg->index; + + D_ASSERT( n >= 0 ); + D_ASSERT( n <= 3 ); + + buffer = lock->buffer; + D_ASSERT( buffer != NULL ); + + fusion_skirmish_prevail( &sdev->beu_lock ); + + /* Wait for idle BEU. */ + BEU_Wait( sdrv, sdev ); + + /* Set buffer pitch. */ + SH7722_SETREG32( sdrv, BMSMWR(n), lock->pitch ); + + /* Set buffer offset (Y plane or RGB packed). */ + SH7722_SETREG32( sdrv, BMSAYR(n), lock->phys ); + + /* Set buffer offset (UV plane). */ + if (DFB_PLANAR_PIXELFORMAT(buffer->format)) { + D_ASSUME( buffer->format == DSPF_NV12 || buffer->format == DSPF_NV16 ); + + SH7722_SETREG32( sdrv, BMSACR(n), lock->phys + lock->pitch * surface->config.size.h ); + } + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + fusion_skirmish_dismiss( &sdev->beu_lock ); + + /* Wait for idle BEU? */ + if (flags & DSFLIP_WAIT) + BEU_Wait( sdrv, sdev ); + + dfb_surface_flip( surface, false ); + + return DFB_OK; +} + +static DFBResult +sh7722UpdateRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + const DFBRegion *update, + CoreSurfaceBufferLock *lock ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + + D_DEBUG_AT( SH7722_Layer, "%s()\n", __FUNCTION__ ); + + D_ASSERT( surface != NULL ); + D_ASSERT( sdrv != NULL ); + D_ASSERT( sdev != NULL ); + + /* Start operation! */ + BEU_Start( sdrv, sdev ); + + return DFB_OK; +} + +DisplayLayerFuncs sh7722MultiLayerFuncs = { + .LayerDataSize = sh7722LayerDataSize, + .RegionDataSize = sh7722RegionDataSize, + .InitLayer = sh7722InitLayer, + + .TestRegion = sh7722TestRegion, + .AddRegion = sh7722AddRegion, + .SetRegion = sh7722SetRegion, + .RemoveRegion = sh7722RemoveRegion, + .FlipRegion = sh7722FlipRegion, + .UpdateRegion = sh7722UpdateRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.h new file mode 100755 index 0000000..1a8008e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_multi.h @@ -0,0 +1,11 @@ +#ifndef __SH7722__MULTI_H__ +#define __SH7722__MULTI_H__ + +#include "sh7722_types.h" + +#define SH7722_MULTI_SUPPORTED_OPTIONS (DLOP_SRC_COLORKEY) + +extern DisplayLayerFuncs sh7722MultiLayerFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_regs.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_regs.h new file mode 100755 index 0000000..c0ef019 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_regs.h @@ -0,0 +1,624 @@ +#ifndef __SH7722__SH7722_REGS_H__ +#define __SH7722__SH7722_REGS_H__ + + +/****************************************************************************** + * Register access + */ + +#define VEU_REG_BASE 0xFE920000 +#define SH7722_BEU_BASE 0xFE930000 +#define LCDC_REG_BASE 0xFE940000 +#define JPEG_REG_BASE 0xFEA00000 + + +/****************************************************************************** + * BEU + */ + +/* BEU start register */ +#define BESTR (SH7722_BEU_BASE + 0x0000) + +/* BEU source memory width register 1 */ +#define BSMWR1 (SH7722_BEU_BASE + 0x0010) + +/* BEU source size register 1 */ +#define BSSZR1 (SH7722_BEU_BASE + 0x0014) + +/* BEU source address Y register 1 */ +#define BSAYR1 (SH7722_BEU_BASE + 0x0018) + +/* BEU source address C register 1 */ +#define BSACR1 (SH7722_BEU_BASE + 0x001C) + +/* BEU source address A register 1 */ +#define BSAAR1 (SH7722_BEU_BASE + 0x0020) + +/* BEU source image format register 1 */ +#define BSIFR1 (SH7722_BEU_BASE + 0x0024) + +/* BEU source memory width register 2 */ +#define BSMWR2 (SH7722_BEU_BASE + 0x0028) + +/* BEU source size register 2 */ +#define BSSZR2 (SH7722_BEU_BASE + 0x002C) + +/* BEU source address Y register 2 */ +#define BSAYR2 (SH7722_BEU_BASE + 0x0030) + +/* BEU source address C register 2 */ +#define BSACR2 (SH7722_BEU_BASE + 0x0034) + +/* BEU source address A register 2 */ +#define BSAAR2 (SH7722_BEU_BASE + 0x0038) + +/* BEU source image format register 2 */ +#define BSIFR2 (SH7722_BEU_BASE + 0x003C) + +/* BEU source memory width register 3 */ +#define BSMWR3 (SH7722_BEU_BASE + 0x0040) + +/* BEU source size register 3 */ +#define BSSZR3 (SH7722_BEU_BASE + 0x0044) + +/* BEU source address Y register 3 */ +#define BSAYR3 (SH7722_BEU_BASE + 0x0048) + +/* BEU source address C register 3 */ +#define BSACR3 (SH7722_BEU_BASE + 0x004C) + +/* BEU source address A register 3 */ +#define BSAAR3 (SH7722_BEU_BASE + 0x0050) + +/* BEU source image format register 3 */ +#define BSIFR3 (SH7722_BEU_BASE + 0x0054) + +/* BEU tile pattern size register */ +#define BTPSR (SH7722_BEU_BASE + 0x0058) + +/* BEU multidisplay source memory width register 1 */ +#define BMSMWR1 (SH7722_BEU_BASE + 0x0070) + +/* BEU multidisplay source size register 1 */ +#define BMSSZR1 (SH7722_BEU_BASE + 0x0074) + +/* BEU multidisplay source address Y register 1 */ +#define BMSAYR1 (SH7722_BEU_BASE + 0x0078) + +/* BEU multidisplay source address C register 1 */ +#define BMSACR1 (SH7722_BEU_BASE + 0x007C) + +/* BEU multidisplay source memory width register 2 */ +#define BMSMWR2 (SH7722_BEU_BASE + 0x0080) + +/* BEU multidisplay source size register 2 */ +#define BMSSZR2 (SH7722_BEU_BASE + 0x0084) + +/* BEU multidisplay source address Y register 2 */ +#define BMSAYR2 (SH7722_BEU_BASE + 0x0088) + +/* BEU multidisplay source address C register 2 */ +#define BMSACR2 (SH7722_BEU_BASE + 0x008C) + +/* BEU multidisplay source memory width register 3 */ +#define BMSMWR3 (SH7722_BEU_BASE + 0x0090) + +/* BEU multidisplay source size register 3 */ +#define BMSSZR3 (SH7722_BEU_BASE + 0x0094) + +/* BEU multidisplay source address Y register 3 */ +#define BMSAYR3 (SH7722_BEU_BASE + 0x0098) + +/* BEU multidisplay source address C register 3 */ +#define BMSACR3 (SH7722_BEU_BASE + 0x009C) + +/* BEU multidisplay source memory width register 4 */ +#define BMSMWR4 (SH7722_BEU_BASE + 0x00A0) + +/* BEU multidisplay source size register 4 */ +#define BMSSZR4 (SH7722_BEU_BASE + 0x00A4) + +/* BEU multidisplay source address Y register 4 */ +#define BMSAYR4 (SH7722_BEU_BASE + 0x00A8) + +/* BEU multidisplay source address C register 4 */ +#define BMSACR4 (SH7722_BEU_BASE + 0x00AC) + +/* BEU multidisplay source image format register */ +#define BMSIFR (SH7722_BEU_BASE + 0x00F0) + +/* BEU blend control register 0 */ +#define BBLCR0 (SH7722_BEU_BASE + 0x0100) + +/* BEU blend control register 1 */ +#define BBLCR1 (SH7722_BEU_BASE + 0x0104) + +/* BEU process control register */ +#define BPROCR (SH7722_BEU_BASE + 0x0108) + +/* BEU multiwindow control register 0 */ +#define BMWCR0 (SH7722_BEU_BASE + 0x010C) + +/* Blend location register 1 */ +#define BLOCR1 (SH7722_BEU_BASE + 0x0114) + +/* Blend location register 2 */ +#define BLOCR2 (SH7722_BEU_BASE + 0x0118) + +/* Blend location register 3 */ +#define BLOCR3 (SH7722_BEU_BASE + 0x011C) + +/* BEU multidisplay location register 1 */ +#define BMLOCR1 (SH7722_BEU_BASE + 0x0120) + +/* BEU multidisplay location register 2 */ +#define BMLOCR2 (SH7722_BEU_BASE + 0x0124) + +/* BEU multidisplay location register 3 */ +#define BMLOCR3 (SH7722_BEU_BASE + 0x0128) + +/* BEU multidisplay location register 4 */ +#define BMLOCR4 (SH7722_BEU_BASE + 0x012C) + +/* BEU multidisplay transparent color control register 1 */ +#define BMPCCR1 (SH7722_BEU_BASE + 0x0130) + +/* BEU multidisplay transparent color control register 2 */ +#define BMPCCR2 (SH7722_BEU_BASE + 0x0134) + +/* Blend pack form register */ +#define BPKFR (SH7722_BEU_BASE + 0x0140) + +/* BEU transparent color control register 0 */ +#define BPCCR0 (SH7722_BEU_BASE + 0x0144) + +/* BEU transparent color control register 11 */ +#define BPCCR11 (SH7722_BEU_BASE + 0x0148) + +/* BEU transparent color control register 12 */ +#define BPCCR12 (SH7722_BEU_BASE + 0x014C) + +/* BEU transparent color control register 21 */ +#define BPCCR21 (SH7722_BEU_BASE + 0x0150) + +/* BEU transparent color control register 22 */ +#define BPCCR22 (SH7722_BEU_BASE + 0x0154) + +/* BEU transparent color control register 31 */ +#define BPCCR31 (SH7722_BEU_BASE + 0x0158) + +/* BEU transparent color control register 32 */ +#define BPCCR32 (SH7722_BEU_BASE + 0x015C) + +/* BEU destination memory width register */ +#define BDMWR (SH7722_BEU_BASE + 0x0160) + +/* BEU destination address Y register */ +#define BDAYR (SH7722_BEU_BASE + 0x0164) + +/* BEU destination address C register */ +#define BDACR (SH7722_BEU_BASE + 0x0168) + +/* BEU address fixed register */ +#define BAFXR (SH7722_BEU_BASE + 0x0180) + +/* BEU swapping register */ +#define BSWPR (SH7722_BEU_BASE + 0x0184) + +/* BEU event interrupt enable register */ +#define BEIER (SH7722_BEU_BASE + 0x0188) + +/* BEU event register */ +#define BEVTR (SH7722_BEU_BASE + 0x018C) + +/* BEU register control register */ +#define BRCNTR (SH7722_BEU_BASE + 0x0194) + +/* BEU status register */ +#define BSTAR (SH7722_BEU_BASE + 0x0198) + +/* BEU module reset register */ +#define BBRSTR (SH7722_BEU_BASE + 0x019C) + +/* BEU register-plane forcible setting register */ +#define BRCHR (SH7722_BEU_BASE + 0x01A0) + + +/* Color Lookup Table - CLUT registers (0-255) */ +#define BCLUT(n) (SH7722_BEU_BASE + 0x3000 + (n) * 0x04) + + + +/* BEU source memory width registers (0-2) */ +#define BSMWR(n) (SH7722_BEU_BASE + 0x0010 + (n) * 0x18) + +/* BEU source size registers (0-2) */ +#define BSSZR(n) (SH7722_BEU_BASE + 0x0014 + (n) * 0x18) + +/* BEU source address Y registers (0-2) */ +#define BSAYR(n) (SH7722_BEU_BASE + 0x0018 + (n) * 0x18) + +/* BEU source address C registers (0-2) */ +#define BSACR(n) (SH7722_BEU_BASE + 0x001C + (n) * 0x18) + +/* BEU source address A registers (0-2) */ +#define BSAAR(n) (SH7722_BEU_BASE + 0x0020 + (n) * 0x18) + +/* BEU source image format registers (0-2) */ +#define BSIFR(n) (SH7722_BEU_BASE + 0x0024 + (n) * 0x18) + + + +/* BEU multidisplay source memory width registers (0-3) */ +#define BMSMWR(n) (SH7722_BEU_BASE + 0x0070 + (n) * 0x10) + +/* BEU multidisplay source size registers (0-3) */ +#define BMSSZR(n) (SH7722_BEU_BASE + 0x0074 + (n) * 0x10) + +/* BEU multidisplay source address Y registers (0-3) */ +#define BMSAYR(n) (SH7722_BEU_BASE + 0x0078 + (n) * 0x10) + +/* BEU multidisplay source address C registers (0-3) */ +#define BMSACR(n) (SH7722_BEU_BASE + 0x007C + (n) * 0x10) + + + +/* Blend location registers (0-2) */ +#define BLOCR(n) (SH7722_BEU_BASE + 0x0114 + (n) * 0x04) + +/* BEU multidisplay location registers (0-3) */ +#define BMLOCR(n) (SH7722_BEU_BASE + 0x0120 + (n) * 0x04) + + +/* BSIFR1-3 */ +#define CHRR_YCBCR_444 0x000 +#define CHRR_YCBCR_422 0x100 +#define CHRR_YCBCR_420 0x200 +#define CHRR_aYCBCR_444 0x300 +#define CHRR_aYCBCR_422 0x400 +#define CHRR_aYCBCR_420 0x500 + +#define RPKF_ARGB 0x000 +#define RPKF_RGB32 0x000 +#define RPKF_RGB24 0x002 +#define RPKF_RGB16 0x003 + +/* BSIFR1 */ +#define BSIFR1_IN1TE_RGBYUV 0x1000 + +/* BSIFR3 */ +#define BSIFR3_MOD0_OSD 0x1000 +#define BSIFR3_MOD1_LUT 0x2000 + +/* BPKFR */ +#define WPCK_RGB12 2 +#define WPCK_RGB16 6 +#define WPCK_RGB18 17 +#define WPCK_RGB32 19 +#define WPCK_RGB24 21 + +#define CHDS_YCBCR444 0x000 +#define CHDS_YCBCR422 0x100 +#define CHDS_YCBCR420 0x200 + +#define BPKFR_RY_YUV 0x000 +#define BPKFR_RY_RGB 0x800 +#define BPKFR_TE_DISABLED 0x000 +#define BPKFR_TE_ENABLED 0x400 + +/* BBLCR0 */ +#define BBLCR0_LAY_123 0x05000000 + +#define BBLCR0_AMUX_BLENDPIXEL(n) (0x10000000 << (n)) + +/* BBLCR1 */ +#define MT_MEMORY 0x10000 +#define MT_VOU 0x20000 +#define MT_MEMORY_VOU 0x30000 +#define MT_LCDC 0x40000 +#define MT_LCDC_MEMORY 0x50000 + +#define BBLCR1_PWD_INPUT1 0x00000000 +#define BBLCR1_PWD_INPUT2 0x01000000 +#define BBLCR1_PWD_INPUT3 0x02000000 +#define BBLCR1_PWD_INPUT_MASK 0x03000000 + +/* BSWPR */ +#define BSWPR_MODSEL_GLOBAL 0x00000000 +#define BSWPR_MODSEL_EACH 0x80000000 + +#define BSWPR_INPUT_BYTESWAP 0x00000001 +#define BSWPR_INPUT_WORDSWAP 0x00000002 +#define BSWPR_INPUT_LONGSWAP 0x00000004 + +#define BSWPR_OUTPUT_BYTESWAP 0x00000010 +#define BSWPR_OUTPUT_WORDSWAP 0x00000020 +#define BSWPR_OUTPUT_LONGSWAP 0x00000040 + +#define BSWPR_INPUT2_BYTESWAP 0x00000100 +#define BSWPR_INPUT2_WORDSWAP 0x00000200 +#define BSWPR_INPUT2_LONGSWAP 0x00000400 + +#define BSWPR_INPUT3_BYTESWAP 0x00010000 +#define BSWPR_INPUT3_WORDSWAP 0x00020000 +#define BSWPR_INPUT3_LONGSWAP 0x00040000 + +#define BSWPR_MULWIN_BYTESWAP 0x01000000 +#define BSWPR_MULWIN_WORDSWAP 0x02000000 +#define BSWPR_MULWIN_LONGSWAP 0x04000000 + + +/****************************************************************************** + * VEU + */ + +#define VEU_VESTR (VEU_REG_BASE + 0x0000) +#define VEU_VESWR (VEU_REG_BASE + 0x0010) +#define VEU_VESSR (VEU_REG_BASE + 0x0014) +#define VEU_VSAYR (VEU_REG_BASE + 0x0018) +#define VEU_VSACR (VEU_REG_BASE + 0x001c) +#define VEU_VBSSR (VEU_REG_BASE + 0x0020) +#define VEU_VEDWR (VEU_REG_BASE + 0x0030) +#define VEU_VDAYR (VEU_REG_BASE + 0x0034) +#define VEU_VDACR (VEU_REG_BASE + 0x0038) +#define VEU_VTRCR (VEU_REG_BASE + 0x0050) +#define VEU_VRFCR (VEU_REG_BASE + 0x0054) +#define VEU_VRFSR (VEU_REG_BASE + 0x0058) +#define VEU_VENHR (VEU_REG_BASE + 0x005c) +#define VEU_VFMCR (VEU_REG_BASE + 0x0070) +#define VEU_VVTCR (VEU_REG_BASE + 0x0074) +#define VEU_VHTCR (VEU_REG_BASE + 0x0078) +#define VEU_VAPCR (VEU_REG_BASE + 0x0080) +#define VEU_VECCR (VEU_REG_BASE + 0x0084) +#define VEU_VAFXR (VEU_REG_BASE + 0x0090) +#define VEU_VSWPR (VEU_REG_BASE + 0x0094) +#define VEU_VEIER (VEU_REG_BASE + 0x00a0) +#define VEU_VEVTR (VEU_REG_BASE + 0x00a4) +#define VEU_VSTAR (VEU_REG_BASE + 0x00b0) +#define VEU_VBSRR (VEU_REG_BASE + 0x00b4) + + +/****************************************************************************** + * LCD + */ + +#define LCDC_LUT(n) (LCDC_REG_BASE + (n) * 4) +#define LCDC_MLDDCKPAT1R (LCDC_REG_BASE + 0x0400) +#define LCDC_MLDDCKPAT2R (LCDC_REG_BASE + 0x0404) +#define LCDC_SLDDCKPAT1R (LCDC_REG_BASE + 0x0408) +#define LCDC_SLDDCKPAT2R (LCDC_REG_BASE + 0x040c) +#define LCDC_LDDCKR (LCDC_REG_BASE + 0x0410) +#define LCDC_LDDCKSTPR (LCDC_REG_BASE + 0x0414) +#define LCDC_MLDMT1R (LCDC_REG_BASE + 0x0418) +#define LCDC_MLDMT2R (LCDC_REG_BASE + 0x041c) +#define LCDC_MLDMT3R (LCDC_REG_BASE + 0x0420) +#define LCDC_MLDDFR (LCDC_REG_BASE + 0x0424) +#define LCDC_MLDSM1R (LCDC_REG_BASE + 0x0428) +#define LCDC_MLDSM2R (LCDC_REG_BASE + 0x042c) +#define LCDC_MLDSA1R (LCDC_REG_BASE + 0x0430) +#define LCDC_MLDSA2R (LCDC_REG_BASE + 0x0434) +#define LCDC_MLDMLSR (LCDC_REG_BASE + 0x0438) +#define LCDC_MLDWBFR (LCDC_REG_BASE + 0x043c) +#define LCDC_MLDWBCNTR (LCDC_REG_BASE + 0x0440) +#define LCDC_MLDWBAR (LCDC_REG_BASE + 0x0444) +#define LCDC_MLDHCNR (LCDC_REG_BASE + 0x0448) +#define LCDC_MLDHSYNR (LCDC_REG_BASE + 0x044c) +#define LCDC_MLDVLNR (LCDC_REG_BASE + 0x0450) +#define LCDC_MLDVSYNR (LCDC_REG_BASE + 0x0454) +#define LCDC_MLDHPDR (LCDC_REG_BASE + 0x0458) +#define LCDC_MLDVPDR (LCDC_REG_BASE + 0x045c) +#define LCDC_MLDPMR (LCDC_REG_BASE + 0x0460) +#define LCDC_LDPALCR (LCDC_REG_BASE + 0x0464) +#define LCDC_LDINTR (LCDC_REG_BASE + 0x0468) +#define LCDC_LDSR (LCDC_REG_BASE + 0x046c) +#define LCDC_LDCNT1R (LCDC_REG_BASE + 0x0470) +#define LCDC_LDCNT2R (LCDC_REG_BASE + 0x0474) +#define LCDC_LDRCNTR (LCDC_REG_BASE + 0x0478) +#define LCDC_LDDDSR (LCDC_REG_BASE + 0x047c) +#define LCDC_LDRCR (LCDC_REG_BASE + 0x0484) + + +/****************************************************************************** + * JPEG + */ + +/* JPEG code mode register */ +#define JCMOD (JPEG_REG_BASE + 0x0000) + +/* JPEG code command register */ +#define JCCMD (JPEG_REG_BASE + 0x0004) + +/* JPEG code status register */ +#define JCSTS (JPEG_REG_BASE + 0x0008) + +/* JPEG code quantization table number register */ +#define JCQTN (JPEG_REG_BASE + 0x000C) + +/* JPEG code Huffman table number register */ +#define JCHTN (JPEG_REG_BASE + 0x0010) + +/* JPEG code DRI upper register */ +#define JCDRIU (JPEG_REG_BASE + 0x0014) + +/* JPEG code DRI lower register */ +#define JCDRID (JPEG_REG_BASE + 0x0018) + +/* JPEG code vertical size upper register */ +#define JCVSZU (JPEG_REG_BASE + 0x001C) + +/* JPEG code vertical size lower register */ +#define JCVSZD (JPEG_REG_BASE + 0x0020) + +/* JPEG code horizontal size upper register */ +#define JCHSZU (JPEG_REG_BASE + 0x0024) + +/* JPEG code horizontal size lower register */ +#define JCHSZD (JPEG_REG_BASE + 0x0028) + +/* JPEG code data count upper register */ +#define JCDTCU (JPEG_REG_BASE + 0x002C) + +/* JPEG code data count middle register */ +#define JCDTCM (JPEG_REG_BASE + 0x0030) + +/* JPEG code data count lower register */ +#define JCDTCD (JPEG_REG_BASE + 0x0034) + +/* JPEG interrupt enable register */ +#define JINTE (JPEG_REG_BASE + 0x0038) + +/* JPEG interrupt status register */ +#define JINTS (JPEG_REG_BASE + 0x003C) + +/* JPEG code decode error register */ +#define JCDERR (JPEG_REG_BASE + 0x0040) + +/* JPEG code reset register */ +#define JCRST (JPEG_REG_BASE + 0x0044) + +/* JPEG interface control register */ +#define JIFCNT (JPEG_REG_BASE + 0x0060) + +/* JPEG interface encoding control register */ +#define JIFECNT (JPEG_REG_BASE + 0x0070) + +/* JPEG interface encode source Y address register 1 */ +#define JIFESYA1 (JPEG_REG_BASE + 0x0074) + +/* JPEG interface encode source C address register 1 */ +#define JIFESCA1 (JPEG_REG_BASE + 0x0078) + +/* JPEG interface encode source Y address register 2 */ +#define JIFESYA2 (JPEG_REG_BASE + 0x007C) + +/* JPEG interface encode source C address register 2 */ +#define JIFESCA2 (JPEG_REG_BASE + 0x0080) + +/* JPEG interface encode source memory width register */ +#define JIFESMW (JPEG_REG_BASE + 0x0084) + +/* JPEG interface encode source vertical size register */ +#define JIFESVSZ (JPEG_REG_BASE + 0x0088) + +/* JPEG interface encode source horizontal size register */ +#define JIFESHSZ (JPEG_REG_BASE + 0x008C) + +/* JPEG interface encode destination address register 1 */ +#define JIFEDA1 (JPEG_REG_BASE + 0x0090) + +/* JPEG interface encode destination address register 2 */ +#define JIFEDA2 (JPEG_REG_BASE + 0x0094) + +/* JPEG interface encode data reload size register */ +#define JIFEDRSZ (JPEG_REG_BASE + 0x0098) + +/* JPEG interface decoding control register */ +#define JIFDCNT (JPEG_REG_BASE + 0x00A0) + +/* JPEG interface decode source address register 1 */ +#define JIFDSA1 (JPEG_REG_BASE + 0x00A4) + +/* JPEG interface decode source address register 2 */ +#define JIFDSA2 (JPEG_REG_BASE + 0x00A8) + +/* JPEG interface decode data reload size register */ +#define JIFDDRSZ (JPEG_REG_BASE + 0x00AC) + +/* JPEG interface decode destination memory width register */ +#define JIFDDMW (JPEG_REG_BASE + 0x00B0) + +/* JPEG interface decode destination vertical size register */ +#define JIFDDVSZ (JPEG_REG_BASE + 0x00B4) + +/* JPEG interface decode destination horizontal size register */ +#define JIFDDHSZ (JPEG_REG_BASE + 0x00B8) + +/* JPEG interface decode destination Y address register 1 */ +#define JIFDDYA1 (JPEG_REG_BASE + 0x00BC) + +/* JPEG interface decode destination C address register 1 */ +#define JIFDDCA1 (JPEG_REG_BASE + 0x00C0) + +/* JPEG interface decode destination Y address register 2 */ +#define JIFDDYA2 (JPEG_REG_BASE + 0x00C4) + +/* JPEG interface decode destination C address register 2 */ +#define JIFDDCA2 (JPEG_REG_BASE + 0x00C8) + + +/* JPEG code quantization table 0 register */ +#define JCQTBL0(n) (JPEG_REG_BASE + 0x10000 + (((n)*4) & 0x3C)) // to 0x1003C + +/* JPEG code quantization table 1 register */ +#define JCQTBL1(n) (JPEG_REG_BASE + 0x10040 + (((n)*4) & 0x3C)) // to 0x1007C + +/* JPEG code quantization table 2 register */ +#define JCQTBL2(n) (JPEG_REG_BASE + 0x10080 + (((n)*4) & 0x3C)) // to 0x100BC + +/* JPEG code quantization table 3 register */ +#define JCQTBL3(n) (JPEG_REG_BASE + 0x100C0 + (((n)*4) & 0x3C)) // to 0x100FC + +/* JPEG code Huffman table DC0 register */ +#define JCHTBD0(n) (JPEG_REG_BASE + 0x10100 + (((n)*4) & 0x1C)) // to 0x1010C + +/* JPEG code Huffman table DC0 register */ +//#define JCHTBD1(n) (JPEG_REG_BASE + 0x10110 + (((n)*4) & 0x0C)) // to 0x10118 + +/* JPEG code Huffman table AC0 register */ +#define JCHTBA0(n) (JPEG_REG_BASE + 0x10120 + (((n)*4) & 0xFC)) // to 0x1012C + +/* JPEG code Huffman table AC0 register */ +//#define JCHTBA1(n) (JPEG_REG_BASE + 0x10130 + (((n)*4) & 0x0C)) // to 0x101D0 + +/* JPEG code Huffman table DC1 register */ +#define JCHTBD1(n) (JPEG_REG_BASE + 0x10200 + (((n)*4) & 0x1C)) // to 0x1020C + +/* JPEG code Huffman table DC1 register */ +//#define JCHTBD3(n) (JPEG_REG_BASE + 0x10210 + (((n)*4) & 0x0C)) // to 0x10218 + +/* JPEG code Huffman table AC1 register */ +#define JCHTBA1(n) (JPEG_REG_BASE + 0x10220 + (((n)*4) & 0xFC)) // to 0x1022C + +/* JPEG code Huffman table AC1 register */ +//#define JCHTBA3(n) (JPEG_REG_BASE + 0x10230 + (((n)*4) & 0xFC)) // to 0x102D0 + + +#define JCCMD_START 0x00000001 +#define JCCMD_RESTART 0x00000002 +#define JCCMD_END 0x00000004 +#define JCCMD_LCMD2 0x00000100 +#define JCCMD_LCMD1 0x00000200 +#define JCCMD_RESET 0x00000080 +#define JCCMD_READ_RESTART 0x00000400 +#define JCCMD_WRITE_RESTART 0x00000800 +#define JCMOD_DSP_ENCODE 0x00000000 +#define JCMOD_DSP_DECODE 0x00000008 +#define JCMOD_INPUT_CTRL 0x00000080 // must always be set +#define JIFCNT_VJSEL_JPU 0x00000000 +#define JIFCNT_VJSEL_VPU 0x00000002 + +#define JIFECNT_LINEBUF_MODE 0x00000002 +#define JIFECNT_SWAP_1234 0x00000000 +#define JIFECNT_SWAP_2143 0x00000010 +#define JIFECNT_SWAP_3412 0x00000020 +#define JIFECNT_SWAP_4321 0x00000030 +#define JIFECNT_RELOAD_ENABLE 0x00000040 + +#define JIFDCNT_LINEBUF_MODE 0x00000001 +#define JIFDCNT_SWAP_1234 0x00000000 +#define JIFDCNT_SWAP_2143 0x00000002 +#define JIFDCNT_SWAP_3412 0x00000004 +#define JIFDCNT_SWAP_4321 0x00000006 +#define JIFDCNT_RELOAD_ENABLE 0x00000008 + +#define JINTS_MASK 0x00007C68 +#define JINTS_INS3_HEADER 0x00000008 +#define JINTS_INS5_ERROR 0x00000020 +#define JINTS_INS6_DONE 0x00000040 +#define JINTS_INS10_XFER_DONE 0x00000400 +#define JINTS_INS11_LINEBUF0 0x00000800 +#define JINTS_INS12_LINEBUF1 0x00001000 +#define JINTS_INS13_LOADED 0x00002000 +#define JINTS_INS14_RELOAD 0x00004000 + +#endif diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.c b/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.c new file mode 100755 index 0000000..2fe4d46 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.c @@ -0,0 +1,85 @@ +#ifdef SH7722_DEBUG_SCREEN +#define DIRECT_ENABLE_DEBUG +#endif + + +#include + +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + + +#include "sh7722.h" +#include "sh7722_screen.h" + + +D_DEBUG_DOMAIN( SH7722_Screen, "SH7722/Screen", "Renesas SH7722 Screen" ); + +/**********************************************************************************************************************/ + +static DFBResult +sh7722InitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + D_DEBUG_AT( SH7722_Screen, "%s()\n", __FUNCTION__ ); + + /* Set the screen capabilities. */ + description->caps = DSCCAPS_NONE; + + /* Set the screen name. */ + snprintf( description->name, DFB_SCREEN_DESC_NAME_LENGTH, "SH7722 Screen" ); + + return DFB_OK; +} + +static DFBResult +sh7722GetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + SH7722DriverData *sdrv = driver_data; + SH7722DeviceData *sdev = sdrv->dev; + D_DEBUG_AT( SH7722_Screen, "%s()\n", __FUNCTION__ ); + + D_ASSERT( ret_width != NULL ); + D_ASSERT( ret_height != NULL ); + + *ret_width = sdev->lcd_width; + *ret_height = sdev->lcd_height; + + return DFB_OK; +} + +ScreenFuncs sh7722ScreenFuncs = { + .InitScreen = sh7722InitScreen, + .GetScreenSize = sh7722GetScreenSize, +}; + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.h new file mode 100755 index 0000000..d545ed8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_screen.h @@ -0,0 +1,9 @@ +#ifndef __SH7722__SCREEN_H__ +#define __SH7722__SCREEN_H__ + +#include + +extern ScreenFuncs sh7722ScreenFuncs; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7722_types.h b/Source/DirectFB/gfxdrivers/sh772x/sh7722_types.h new file mode 100755 index 0000000..ea367da --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7722_types.h @@ -0,0 +1,136 @@ +#ifndef __SH7722__TYPES_H__ +#define __SH7722__TYPES_H__ + +#include + +#include + + +#define SH7722GFX_MAX_PREPARE 8192 + + +typedef enum { + SH7722_LAYER_INPUT1, + SH7722_LAYER_INPUT2, + SH7722_LAYER_INPUT3, + SH7722_LAYER_MULTIWIN +} SH7722LayerID; + + +typedef struct { + SH7722LayerID layer; +} SH7722LayerData; + +typedef struct { + int magic; + + CoreLayerRegionConfig config; + + CoreSurface *surface; + CorePalette *palette; +} SH7722RegionData; + + +typedef struct { + unsigned int added; + unsigned int visible; +} SH7722MultiLayerData; + +typedef struct { + int magic; + + int index; + CoreLayerRegionConfig config; + + CoreSurface *surface; + CorePalette *palette; +} SH7722MultiRegionData; + + +typedef struct { + int sh772x; + + int lcd_width; + int lcd_height; + int lcd_offset; + int lcd_pitch; + int lcd_size; + unsigned long lcd_phys; + DFBSurfacePixelFormat lcd_format; + + /* state validation */ + int v_flags; + + /* prepared register values */ + u32 ble_srcf; + u32 ble_dstf; + + /* cached values */ + unsigned long dst_phys; + int dst_pitch; + int dst_bpp; + int dst_index; + + unsigned long src_phys; + int src_pitch; + int src_bpp; + int src_index; + + unsigned long mask_phys; + int mask_pitch; + DFBSurfacePixelFormat mask_format; + int mask_index; + DFBPoint mask_offset; + DFBSurfaceMaskFlags mask_flags; + + DFBSurfaceDrawingFlags dflags; + DFBSurfaceBlittingFlags bflags; + DFBSurfaceRenderOptions render_options; + + bool ckey_b_enabled; + bool color_change_enabled; + bool mask_enabled; + + unsigned int input_mask; + + s32 matrix[6]; + DFBColor color; + + /* locking */ + FusionSkirmish beu_lock; + + + /* sh7723 */ + u32 rclr; + u32 color16; +} SH7722DeviceData; + + +typedef struct { + SH7722DeviceData *dev; + + CoreDFB *core; + CoreGraphicsDevice *device; + + CoreScreen *screen; + + CoreLayer *multi; + CoreLayer *input1; + CoreLayer *input2; + CoreLayer *input3; + + int gfx_fd; + SH772xGfxSharedArea *gfx_shared; + + int prep_num; + __u32 prep_buf[SH7722GFX_MAX_PREPARE]; + + volatile void *mmio_base; + + int num_inputs; + + volatile void *lcd_virt; +} SH7722DriverData; + +#endif + diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.c b/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.c new file mode 100755 index 0000000..f784e81 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.c @@ -0,0 +1,890 @@ +#ifdef SH7723_DEBUG_BLT + #define DIRECT_ENABLE_DEBUG +#endif + + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "sh7722.h" + +#include "sh7723_blt.h" + + +D_DEBUG_DOMAIN( SH7723_BLT, "SH7723/BLT", "Renesas SH7723 Drawing Engine" ); + +/* + * State validation flags. + * + * There's no prefix because of the macros below. + */ +enum { + DEST = 0x00000001, + CLIP = 0x00000002, + DEST_CLIP = 0x00000003, + + COLOR16 = 0x00000100, + + ALPHA = 0x00001000, + + SOURCE = 0x00010000, + STRANS = 0x00020000, + + ALL = 0x00031103, +}; + +/* + * State handling macros. + */ + +#define SH7723_VALIDATE(flags) do { sdev->v_flags |= (flags); } while (0) +#define SH7723_INVALIDATE(flags) do { sdev->v_flags &= ~(flags); } while (0) + +#define SH7723_CHECK_VALIDATE(flag) do { \ + if ((sdev->v_flags & flag) != flag) \ + sh7723_validate_##flag( sdrv, sdev, state ); \ + } while (0) + +#define DUMP_INFO() D_DEBUG_AT( SH7723_BLT, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + +/**********************************************************************************************************************/ + +static inline bool +start_hardware( SH7722DriverData *sdrv ) +{ + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + if (shared->hw_running || !shared->next_valid || shared->next_end == shared->next_start) + return false; + + shared->hw_running = true; + shared->hw_start = shared->next_start; + shared->hw_end = shared->next_end; + + shared->next_start = shared->next_end = (shared->hw_end + 1 + 3) & ~3; + shared->next_valid = false; + + shared->num_words += shared->hw_end - shared->hw_start; + + shared->num_starts++; + + DUMP_INFO(); + + D_ASSERT( shared->buffer[shared->hw_end] == M2DG_OPCODE_TRAP ); + + SH7722_TDG_SETREG32( sdrv, M2DG_DLSAR, shared->buffer_phys + shared->hw_start*4 ); + SH7722_TDG_SETREG32( sdrv, M2DG_SCLR, 1 ); + return true; +} + +__attribute__((noinline)) +static void +flush_prepared( SH7722DriverData *sdrv ) +{ + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + unsigned int timeout = 2; + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + D_ASSERT( sdrv->prep_num < SH772xGFX_BUFFER_WORDS ); + D_ASSERT( sdrv->prep_num <= D_ARRAY_SIZE(sdrv->prep_buf) ); + + /* Something prepared? */ + while (sdrv->prep_num) { + int next_end; + + /* Mark shared information as invalid. From this point on the interrupt handler + * will not continue with the next block, and we'll start the hardware ourself. */ + shared->next_valid = false; + + /* Check if there's enough space at the end. + * Wait until hardware has started next block before it gets too big. */ + if (shared->next_end + sdrv->prep_num >= SH772xGFX_BUFFER_WORDS || + shared->next_end - shared->next_start >= SH772xGFX_BUFFER_WORDS/4) { + /* If there's no next block waiting, start at the beginning. */ + if (shared->next_start == shared->next_end) + shared->next_start = shared->next_end = 0; + else { + D_ASSERT( shared->buffer[shared->hw_end] == M2DG_OPCODE_TRAP ); + + /* Mark area as valid again. */ + shared->next_valid = true; + + /* Start in case it got idle while doing the checks. */ + if (!start_hardware( sdrv )) { + /* + * Hardware has not been started (still running). + * Check for timeout. */ + if (!timeout--) { + D_ERROR( "SH7723/Blt: Timeout waiting for processing!\n" ); + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + D_ASSERT( shared->buffer[shared->hw_end] == M2DG_OPCODE_TRAP ); + sh7723EngineReset( sdrv, sdrv->dev ); + } + + /* Wait til next block is started. */ + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_NEXT ); + } + + /* Start over with the checks. */ + continue; + } + } + + /* We are appending in case there was already a next block. */ + next_end = shared->next_end + sdrv->prep_num; + + /* Reset the timeout counter. */ + timeout = 2; + + /* While the hardware is running... */ + while (shared->hw_running) { + D_ASSERT( shared->buffer[shared->hw_end] == M2DG_OPCODE_TRAP ); + + /* ...make sure we don't over lap with its current buffer, otherwise wait. */ + if (shared->hw_start > next_end || shared->hw_end < shared->next_start) + break; + + /* Check for timeout. */ + if (!timeout--) { + D_ERROR( "SH7723/Blt: Timeout waiting for space!\n" ); + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + D_ASSERT( shared->buffer[shared->hw_end] == M2DG_OPCODE_TRAP ); + sh7723EngineReset( sdrv, sdrv->dev ); + } + + /* Wait til next block is started. */ + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_NEXT ); + } + + /* Copy from local to shared buffer. */ + direct_memcpy( (void*) &shared->buffer[shared->next_end], &sdrv->prep_buf[0], sdrv->prep_num * sizeof(__u32) ); + + /* Terminate the block. */ + shared->buffer[next_end] = M2DG_OPCODE_TRAP; + + /* Update next block information and mark valid. */ + shared->next_end = next_end; + shared->next_valid = true; + + /* Reset local counter. */ + sdrv->prep_num = 0; + } + + /* Start in case it is idle. */ + start_hardware( sdrv ); +} + +static inline __u32 * +start_buffer( SH7722DriverData *sdrv, + int space ) +{ + /* Check for space in local buffer. */ + if (sdrv->prep_num + space > SH7722GFX_MAX_PREPARE) { + /* Flush local buffer. */ + flush_prepared( sdrv ); + + D_ASSERT( sdrv->prep_num == 0 ); + } + + /* Return next write position. */ + return &sdrv->prep_buf[sdrv->prep_num]; +} + +static inline void +submit_buffer( SH7722DriverData *sdrv, + int entries ) +{ + D_ASSERT( sdrv->prep_num + entries <= SH7722GFX_MAX_PREPARE ); + + /* Increment next write position. */ + sdrv->prep_num += entries; +} + +/**********************************************************************************************************************/ + +static inline void +sh7723_validate_DEST_CLIP( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 18 ); + + D_DEBUG_AT( SH7723_BLT, "%s( 0x%08lx [%d] - %4d,%4d-%4dx%4d )\n", __FUNCTION__, + state->dst.phys, state->dst.pitch, DFB_RECTANGLE_VALS_FROM_REGION( &state->clip ) ); + + prep[0] = M2DG_OPCODE_WPR; + prep[1] = 0x0d4; + prep[2] = SH7723_XY( state->clip.x1, state->clip.y1 ) ; + + prep[3] = M2DG_OPCODE_WPR; + prep[4] = 0x0d8; + prep[5] = SH7723_XY( state->clip.x2, state->clip.y2) ; + + if (sdev->v_flags & DEST) { + submit_buffer( sdrv, 6 ); + } + else { + CoreSurface *surface = state->destination; + CoreSurfaceBuffer *buffer = state->dst.buffer; + + sdev->dst_phys = state->dst.phys; + sdev->dst_pitch = state->dst.pitch; + sdev->dst_bpp = DFB_BYTES_PER_PIXEL( buffer->format ); + sdev->dst_index = DFB_PIXELFORMAT_INDEX( buffer->format ) % DFB_NUM_PIXELFORMATS; + + sdev->rclr &= ~0x00140000; + + switch (buffer->format) { + case DSPF_RGB16: + sdev->rclr |= 0x00040000; + break; + + case DSPF_ARGB1555: + sdev->rclr |= 0x00140000; + break; + + default: + D_BUG("Unexpected pixelformat\n"); + return; + } + + /* Set destination start address. */ + prep[ 6] = M2DG_OPCODE_WPR; + prep[ 7] = 0x50; + prep[ 8] = sdev->dst_phys; + + /* Set destination stride. */ + prep[ 9] = M2DG_OPCODE_WPR; + prep[10] = 0x5c; + prep[11] = sdev->dst_pitch / sdev->dst_bpp; + + /* Set destination pixelformat in rendering control. */ + prep[12] = M2DG_OPCODE_WPR; + prep[13] = 0xc0; + prep[14] = sdev->rclr; + + /* Set system clipping rectangle. */ + prep[15] = M2DG_OPCODE_WPR; + prep[16] = 0xd0; + prep[17] = SH7723_XY( surface->config.size.w - 1, surface->config.size.h - 1 ); + + submit_buffer( sdrv, 18 ); + } + + /* Set the flags. */ + SH7723_VALIDATE( DEST_CLIP ); +} + +static inline void +sh7723_validate_COLOR16( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + sdev->color16 = dfb_pixel_from_color( state->destination->config.format, &state->color ); + + /* Set the flags. */ + SH7723_VALIDATE( COLOR16 ); +} + +static inline void +sh7723_validate_ALPHA( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 3 ); + + prep[0] = M2DG_OPCODE_WPR; + prep[1] = 0x088; + prep[2] = state->color.a; + + submit_buffer( sdrv, 3 ); + + /* Set the flags. */ + SH7723_VALIDATE( ALPHA ); +} + +static inline void +sh7723_validate_SOURCE( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 6 ); + + CoreSurfaceBuffer *buffer = state->src.buffer; + + sdev->src_phys = state->src.phys; + sdev->src_pitch = state->src.pitch; + sdev->src_bpp = DFB_BYTES_PER_PIXEL( buffer->format ); + sdev->src_index = DFB_PIXELFORMAT_INDEX( buffer->format ) % DFB_NUM_PIXELFORMATS; + + /* Set source start address. */ + prep[0] = M2DG_OPCODE_WPR; + prep[1] = 0x4c; + prep[2] = sdev->src_phys; + + /* Set source stride. */ + prep[3] = M2DG_OPCODE_WPR; + prep[4] = 0x58; + prep[5] = sdev->src_pitch / sdev->src_bpp; + + submit_buffer( sdrv, 6 ); + + /* Set the flags. */ + SH7723_VALIDATE( SOURCE ); +} + +static inline void +sh7723_validate_STRANS( SH7722DriverData *sdrv, + SH7722DeviceData *sdev, + CardState *state ) +{ + __u32 *prep = start_buffer( sdrv, 3 ); + + prep[0] = M2DG_OPCODE_WPR; + prep[1] = 0x080; + prep[2] = state->src_colorkey; + + submit_buffer( sdrv, 3 ); + + /* Set the flags. */ + SH7723_VALIDATE( STRANS ); +} + +/**********************************************************************************************************************/ + +DFBResult +sh7723EngineSync( void *drv, void *dev ) +{ + DFBResult ret = DFB_OK; + SH7722DriverData *sdrv = drv; + SH772xGfxSharedArea *shared = sdrv->gfx_shared; + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + while (shared->hw_running && ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_WAIT_IDLE ) < 0) { + if (errno == EINTR) + continue; + + ret = errno2result( errno ); + D_PERROR( "SH7723/BLT: SH7723GFX_IOCTL_WAIT_IDLE failed!\n" ); + + direct_log_printf( NULL, " -> %srunning, hw %d-%d, next %d-%d - %svalid\n", \ + sdrv->gfx_shared->hw_running ? "" : "not ", \ + sdrv->gfx_shared->hw_start, \ + sdrv->gfx_shared->hw_end, \ + sdrv->gfx_shared->next_start, \ + sdrv->gfx_shared->next_end, \ + sdrv->gfx_shared->next_valid ? "" : "not " ); + + break; + } + + if (ret == DFB_OK) { + D_ASSERT( !shared->hw_running ); + D_ASSERT( !shared->next_valid ); + } + + return ret; +} + +void +sh7723EngineReset( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + __u32 *prep; + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + ioctl( sdrv->gfx_fd, SH772xGFX_IOCTL_RESET ); + + prep = start_buffer( sdrv, 4 ); + + /* Reset current pointer. */ + prep[0] = M2DG_OPCODE_MOVE; + prep[1] = 0; + + /* Reset local offset. */ + prep[2] = M2DG_OPCODE_LCOFS; + prep[3] = 0; + + submit_buffer( sdrv, 4 ); +} + +void +sh7723EmitCommands( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + flush_prepared( sdrv ); +} + +void +sh7723FlushTextureCache( void *drv, void *dev ) +{ + SH7722DriverData *sdrv = drv; + __u32 *prep = start_buffer( sdrv, 1 ); + + D_DEBUG_AT( SH7723_BLT, "%s()\n", __FUNCTION__ ); + + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_SYNC | M2DG_SYNC_TCLR; + + submit_buffer( sdrv, 1 ); +} + +/**********************************************************************************************************************/ + +void +sh7723CheckState( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ) +{ + D_DEBUG_AT( SH7723_BLT, "%s( %p, 0x%08x )\n", __FUNCTION__, state, accel ); + + /* Return if the desired function is not supported at all. */ + if (accel & ~(SH7723_SUPPORTED_DRAWINGFUNCTIONS | SH7723_SUPPORTED_BLITTINGFUNCTIONS)) + return; + + /* Return if the destination format is not supported. */ + switch (state->destination->config.format) { + case DSPF_RGB16: +// case DSPF_ARGB1555: + break; + + default: + return; + } + + /* Check if drawing or blitting is requested. */ + if (DFB_DRAWING_FUNCTION( accel )) { + /* Return if unsupported drawing flags are set. */ + if (state->drawingflags & ~SH7723_SUPPORTED_DRAWINGFLAGS) + return; + + /* Return if blending with unsupported blend functions is requested. */ + if (state->drawingflags & DSDRAW_BLEND) { + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + break; + default: + return; + } + + /* Return if blending with unsupported blend functions is requested. */ + if (state->src_blend != DSBF_SRCALPHA || state->dst_blend != DSBF_INVSRCALPHA) + return; + + /* XOR only without blending. */ + if (state->drawingflags & DSDRAW_XOR) + return; + } + + /* Enable acceleration of drawing functions. */ + state->accel |= accel; + } else { + DFBSurfaceBlittingFlags flags = state->blittingflags; + + /* Return if unsupported blitting flags are set. */ + if (flags & ~SH7723_SUPPORTED_BLITTINGFLAGS) + return; + + /* Return if the source format is not supported. */ + if (state->source->config.format != state->destination->config.format) + return; + + /* Return if blending with unsupported blend functions is requested. */ + if (flags & (DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) { + if (state->src_blend != DSBF_SRCALPHA || state->dst_blend != DSBF_INVSRCALPHA) + return; + } + + /* XOR only without blending etc. */ + if (flags & DSBLIT_XOR && + flags & ~(DSBLIT_SRC_COLORKEY | DSBLIT_ROTATE180 | DSBLIT_XOR)) + return; + + /* Return if colorizing for non-font surfaces is requested. */ + if ((flags & DSBLIT_COLORIZE) && !(state->source->type & CSTF_FONT)) + return; + + /* Return if blending with both alpha channel and value is requested. */ + if (D_FLAGS_ARE_SET( flags, DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_BLEND_COLORALPHA)) + return; + + /* Enable acceleration of blitting functions. */ + state->accel |= accel; + } +} + +/* + * Make sure that the hardware is programmed for execution of 'accel' according to the 'state'. + */ +void +sh7723SetState( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + StateModificationFlags modified = state->mod_hw; + + D_DEBUG_AT( SH7723_BLT, "%s( %p, 0x%08x ) <- modified 0x%08x\n", + __FUNCTION__, state, accel, modified ); + + DUMP_INFO(); + + /* + * 1) Invalidate hardware states + * + * Each modification to the hw independent state invalidates one or more hardware states. + */ + + /* Simply invalidate all? */ + if (modified == SMF_ALL) { + SH7723_INVALIDATE( ALL ); + } else if (modified) { + /* Invalidate destination registers. */ + if (modified & SMF_DESTINATION) + SH7723_INVALIDATE( DEST | COLOR16 ); + + /* Invalidate clipping registers. */ + if (modified & SMF_CLIP) + SH7723_INVALIDATE( CLIP ); + + /* Invalidate color registers. */ + if (modified & SMF_COLOR) + SH7723_INVALIDATE( ALPHA | COLOR16 ); + + /* Invalidate source registers. */ + if (modified & SMF_SOURCE) + SH7723_INVALIDATE( SOURCE ); + + /* Invalidate source colorkey. */ + if (modified & SMF_SRC_COLORKEY) + SH7723_INVALIDATE( STRANS ); + } + + /* + * 2) Validate hardware states + * + * Each function has its own set of states that need to be validated. + */ + + /* Always requiring valid destination and clip. */ + SH7723_CHECK_VALIDATE( DEST_CLIP ); + + /* Depending on the function... */ + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWLINE: + /* ...require valid color. */ + SH7723_CHECK_VALIDATE( COLOR16 ); + + /* If blending is used, validate the alpha value. */ + if (state->drawingflags & DSDRAW_BLEND) + SH7723_CHECK_VALIDATE( ALPHA ); + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = SH7723_SUPPORTED_DRAWINGFUNCTIONS; + + break; + + case DFXL_BLIT: + /* ...require valid source. */ + SH7723_CHECK_VALIDATE( SOURCE ); + + /* If blending is used, validate the alpha value. */ + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + SH7723_CHECK_VALIDATE( ALPHA ); + + /* If colorkeying is used, validate the colorkey. */ + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + SH7723_CHECK_VALIDATE( STRANS ); + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = SH7723_SUPPORTED_BLITTINGFUNCTIONS; + + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + + } + + sdev->dflags = state->drawingflags; + sdev->bflags = state->blittingflags; + sdev->render_options = state->render_options; + sdev->color = state->color; + + /* + * 4) Clear modification flags + * + * All flags have been evaluated in 1) and remembered for further validation. + * If the hw independent state is not modified, this function won't get called + * for subsequent rendering functions, unless they aren't defined by 3). + */ + state->mod_hw = 0; +} + +/**********************************************************************************************************************/ + +/* + * Render a filled rectangle using the current hardware state. + */ +bool +sh7723FillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 6 ); + + D_DEBUG_AT( SH7723_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_BITBLTC | M2DG_DRAWMODE_CLIP; + + if (sdev->dflags & DSDRAW_BLEND) + prep[0] |= M2DG_DRAWMODE_ALPHA; + + prep[1] = 0xcc; + prep[2] = sdev->color16; + prep[3] = rect->w - 1; + prep[4] = rect->h - 1; + prep[5] = SH7723_XY( rect->x, rect->y ); + + submit_buffer( sdrv, 6 ); + + return true; +} + +/**********************************************************************************************************************/ + +/* + * Render rectangle outlines using the current hardware state. + */ +bool +sh7723DrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer(sdrv, 8 ); + + int x1, x2, y1, y2; + + x1 = rect->x; + y1 = rect->y; + x2 = rect->x + rect->w - 1; + y2 = rect->y + rect->h - 1; + + D_DEBUG_AT( SH7723_BLT, "%s( %d, %d - %dx%d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( rect ) ); + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_LINE_C | M2DG_DRAWMODE_CLIP; + + if (sdev->dflags & DSDRAW_BLEND) + prep[0] |= M2DG_DRAWMODE_ALPHA; + + prep[1] = (sdev->color16 << 16 ) | 5; + prep[2] = 0; + + prep[3] = SH7723_XY( x1, y1 ); + prep[4] = SH7723_XY( x2, y1 ); + prep[5] = SH7723_XY( x2, y2 ); + prep[6] = SH7723_XY( x1, y2 ); + prep[7] = SH7723_XY( x1, y1 ); + + submit_buffer( sdrv, 8 ); + + return true; +} + +/**********************************************************************************************************************/ + +/* + * Render a triangle using the current hardware state. + */ +bool +sh7723FillTriangle( void *drv, void *dev, DFBTriangle *triangle ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 6 ); + + D_DEBUG_AT( SH7723_BLT, "%s( %d, %d - %dx, %d - %d, %d )\n", __FUNCTION__, + DFB_TRIANGLE_VALS( triangle ) ); + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_POLYGON_4C | M2DG_DRAWMODE_CLIP; + + if (sdev->dflags & DSDRAW_BLEND) + prep[0] |= M2DG_DRAWMODE_ALPHA; + + prep[1] = sdev->color16; + + prep[2] = SH7723_XY( triangle->x1, triangle->y1 ); + prep[3] = SH7723_XY( triangle->x2, triangle->y2 ); + prep[4] = SH7723_XY( triangle->x3, triangle->y3 ); + prep[5] = SH7723_XY( triangle->x3, triangle->y3 ); + + submit_buffer( sdrv, 6 ); + + /* + * TODO: use rlined to draw the aa'ed outline of a polygon + * if also aval, set blke to 1 + */ + + + + return true; +} + +/**********************************************************************************************************************/ + +/* + * Render a line with the specified width using the current hardware state. + */ +bool +sh7723DrawLine( void *drv, void *dev, DFBRegion *line ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 5 ); + + D_DEBUG_AT( SH7723_BLT, "%s( %d, %d - %d, %d )\n", __FUNCTION__, + line->x1, line->y1, line->x2, line->y2 ); + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_LINE_C | M2DG_DRAWMODE_CLIP; + + if (sdev->render_options & DSRO_ANTIALIAS) + prep[0] |= M2DG_DRAWMODE_ANTIALIAS; + + prep[1] = (sdev->color16 << 16) | 2; + prep[2] = 0; + + prep[3] = SH7723_XY( line->x1, line->y1 ); + prep[4] = SH7723_XY( line->x2, line->y2 ); + + submit_buffer( sdrv, 5); + + return true; +} + +/* + * Blit a rectangle using the current hardware state. + */ +bool +sh7723Blit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + SH7722DriverData *sdrv = drv; + SH7722DeviceData *sdev = dev; + __u32 *prep = start_buffer( sdrv, 6 ); + + D_DEBUG_AT( SH7723_BLT, "%s( %d, %d - %dx%d <- %d, %d )\n", __FUNCTION__, + dx, dy, rect->w, rect->h, rect->x, rect->y ); + DUMP_INFO(); + + prep[0] = M2DG_OPCODE_BITBLTA | M2DG_DRAWMODE_CLIP; + + if (sdev->bflags & DSBLIT_BLEND_COLORALPHA) + prep[0] |= M2DG_DRAWMODE_ALPHA; + + if (sdev->bflags & DSBLIT_SRC_COLORKEY) + prep[0] |= M2DG_DRAWMODE_STRANS; + + if (sdev->src_phys == sdev->dst_phys) { + if (dy > rect->y) + prep[0] |= M2DG_DRAWMODE_DSTDIR_Y | M2DG_DRAWMODE_SRCDIR_Y; + else if (dy == rect->y) { + if (dx > rect->x) + prep[0] |= M2DG_DRAWMODE_DSTDIR_X | M2DG_DRAWMODE_SRCDIR_X; + } + } + + prep[1] = 0xcc; + prep[2] = SH7723_XY( rect->x, rect->y ); + prep[3] = rect->w - 1; + prep[4] = rect->h - 1; + prep[5] = SH7723_XY( dx, dy ); + + submit_buffer( sdrv, 6 ); + + return true; +} diff --git a/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.h b/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.h new file mode 100755 index 0000000..182c4b8 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sh772x/sh7723_blt.h @@ -0,0 +1,239 @@ +#ifndef __SH7723_BLT_H__ +#define __SH7723_BLT_H__ + +#include + +#include "sh7722_types.h" + + + +#define SH7723_SUPPORTED_DRAWINGFLAGS (DSDRAW_NOFX | DSDRAW_BLEND) + +#define SH7723_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE | \ + DFXL_FILLTRIANGLE | \ + DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE) + +#define SH7723_SUPPORTED_BLITTINGFLAGS (DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_SRC_COLORKEY) + +#define SH7723_SUPPORTED_BLITTINGFUNCTIONS (DFXL_BLIT) + + +DFBResult sh7723EngineSync ( void *drv, void *dev ); + +void sh7723EngineReset ( void *drv, void *dev ); +void sh7723FlushTextureCache( void *drv, void *dev ); + +void sh7723EmitCommands ( void *drv, void *dev ); + +void sh7723CheckState ( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ); + +void sh7723SetState ( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ); + +bool sh7723FillRectangle ( void *drv, void *dev, DFBRectangle *rect ); +bool sh7723FillTriangle ( void *drv, void *dev, DFBTriangle *triangle ); +bool sh7723DrawRectangle ( void *drv, void *dev, DFBRectangle *rect ); +bool sh7723DrawLine ( void *drv, void *dev, DFBRegion *line ); +bool sh7723Blit ( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +#define SH7723_S16S16(h,l) ((u32)((((u16)(h)) << 16) | ((u16)(l)))) + +#define SH7723_XY(x,y) SH7723_S16S16(x,y) + +#define SH7723_TDG_BASE 0xA4680000 + +//#define BEM_HC_DMA_START (SH7723_TDG_BASE + 0x00044) +#define M2DG_SCLR (SH7723_TDG_BASE + 0x000) +//#define BEM_HC_DMA_ADR (SH7723_TDG_BASE + 0x00040) +#define M2DG_DLSAR (SH7723_TDG_BASE + 0x048) + + + + +#define M2DG_OPCODE_TRAP 0x00000000 +#define M2DG_OPCODE_WPR 0x18000000 +#define M2DG_OPCODE_SYNC 0x12000000 +#define M2DG_OPCODE_LCOFS 0x40000000 +#define M2DG_OPCODE_MOVE 0x48000000 +#define M2DG_OPCODE_NOP 0x08000000 +#define M2DG_OPCODE_INTERRUPT 0x08008000 +#define M2DG_SYNC_TCLR 0x00000010 + +#define M2DG_OPCODE_POLYGON_4C 0x80000000 +#define M2DG_OPCODE_LINE_C 0xB0000000 +#define M2DG_OPCODE_BITBLTA 0xA2000100 +#define M2DG_OPCODE_BITBLTC 0xA0000000 + +#define M2DG_DRAWMODE_STRANS 0x00000800 +#define M2DG_DRAWMODE_CLIP 0x00002000 +#define M2DG_DRAWMODE_ANTIALIAS 0x00000002 +#define M2DG_DRAWMODE_ALPHA 0x00000002 + +#define M2DG_DRAWMODE_SRCDIR_X 0x00000040 +#define M2DG_DRAWMODE_SRCDIR_Y 0x00000020 +#define M2DG_DRAWMODE_DSTDIR_X 0x00000010 +#define M2DG_DRAWMODE_DSTDIR_Y 0x00000008 + + + +//ignore and replace +#define BEM_WR_CTRL (0x00400) +#define BEM_WR_V1 (0x00410) +#define BEM_WR_V2 (0x00414) +#define BEM_WR_FGC (0x00420) + +#define BEM_BE_CTRL (0x00800) +#define BEM_BE_V1 (0x00810) +#define BEM_BE_V2 (0x00814) +#define BEM_BE_V3 (0x00818) +#define BEM_BE_V4 (0x0081C) +#define BEM_BE_COLOR1 (0x00820) +#define BEM_BE_SRC_LOC (0x00830) +#define BEM_BE_SRC_SIZE (0x00834) +#define BEM_BE_MATRIX_A (0x00850) +#define BEM_BE_MATRIX_B (0x00854) +#define BEM_BE_MATRIX_C (0x00858) +#define BEM_BE_MATRIX_D (0x0085C) +#define BEM_BE_MATRIX_E (0x00860) +#define BEM_BE_MATRIX_F (0x00864) +#define BEM_BE_ORIGIN (0x00870) +#define BEM_BE_SC_MIN (0x00880) +#define BEM_BE_SC_MAX (0x00884) + +#define BEM_TE_SRC (0x00C00) +#define BEM_TE_SRC_BASE (0x00C04) +#define BEM_TE_SRC_SIZE (0x00C08) +#define BEM_TE_SRC_CNV (0x00C0C) +#define BEM_TE_MASK (0x00C10) +#define BEM_TE_MASK_BASE (0x00C14) +#define BEM_TE_MASK_SIZE (0x00C18) +#define BEM_TE_MASK_CNV (0x00C1C) +#define BEM_TE_ALPHA (0x00C28) +#define BEM_TE_FILTER (0x00C30) +#define BEM_TE_INVALID (0x00C40) + +#define BEM_PE_DST (0x01000) +#define BEM_PE_DST_BASE (0x01004) +#define BEM_PE_DST_SIZE (0x01008) +#define BEM_PE_SC (0x0100C) +#define BEM_PE_SC0_MIN (0x01010) +#define BEM_PE_SC0_MAX (0x01014) +#define BEM_PE_CKEY (0x01040) +#define BEM_PE_CKEY_B (0x01044) +#define BEM_PE_CKEY_A (0x01048) +#define BEM_PE_COLORCHANGE (0x01050) +#define BEM_PE_ALPHA (0x01058) +#define BEM_PE_COLORCHANGE_0 (0x01060) +#define BEM_PE_COLORCHANGE_1 (0x01064) +#define BEM_PE_OPERATION (0x01080) +#define BEM_PE_FIXEDALPHA (0x01084) +#define BEM_PE_OFFSET (0x01088) +#define BEM_PE_MASK (0x01094) +#define BEM_PE_CACHE (0x010B0) + +/* + * BEM_BE_CTRL + */ +#define BE_FLIP_NONE 0x00000000 +#define BE_FLIP_HORIZONTAL 0x01000000 +#define BE_FLIP_VERTICAL 0x02000000 +#define BE_FLIP_BOTH 0x03000000 + +#define BE_CTRL_FIXMODE_20_12 0x00000000 +#define BE_CTRL_FIXMODE_16_16 0x00100000 +#define BE_CTRL_CLIP 0x00080000 +#define BE_CTRL_ORIGIN 0x00040000 +#define BE_CTRL_ZOOM 0x00020000 +#define BE_CTRL_MATRIX 0x00010000 + +#define BE_CTRL_SCANMODE_LINE 0x00000000 +#define BE_CTRL_SCANMODE_4x4 0x00001000 +#define BE_CTRL_SCANMODE_8x4 0x00002000 + +#define BE_CTRL_BLTDIR_FORWARD 0x00000000 +#define BE_CTRL_BLTDIR_BACKWARD 0x00000100 +#define BE_CTRL_BLTDIR_AUTOMATIC 0x00000200 + +#define BE_CTRL_TEXTURE 0x00000020 +#define BE_CTRL_QUADRANGLE 0x00000002 +#define BE_CTRL_RECTANGLE 0x00000001 + +/* + * BEM_PE_OPERATION + */ +#define BLE_FUNC_NONE 0x00000000 +#define BLE_FUNC_AxB_plus_CxD 0x10000000 +#define BLE_FUNC_CxD_minus_AxB 0x20000000 +#define BLE_FUNC_AxB_minus_CxD 0x30000000 + +#define BLE_ROP_XOR 0x01660000 + +#define BLE_SRCA_FIXED 0x00000000 +#define BLE_SRCA_SOURCE_ALPHA 0x00001000 +#define BLE_SRCA_ALPHA_CHANNEL 0x00002000 + +#define BLE_DSTA_FIXED 0x00000000 +#define BLE_DSTA_DEST_ALPHA 0x00000100 + +#define BLE_SRCF_ZERO 0x00000000 +#define BLE_SRCF_ONE 0x00000010 +#define BLE_SRCF_DST 0x00000020 +#define BLE_SRCF_1_DST 0x00000030 +#define BLE_SRCF_SRC_A 0x00000040 +#define BLE_SRCF_1_SRC_A 0x00000050 +#define BLE_SRCF_DST_A 0x00000060 +#define BLE_SRCF_1_DST_A 0x00000070 + +#define BLE_DSTO_DST 0x00000000 +#define BLE_DSTO_OFFSET 0x00000008 + +#define BLE_DSTF_ZERO 0x00000000 +#define BLE_DSTF_ONE 0x00000001 +#define BLE_DSTF_SRC 0x00000002 +#define BLE_DSTF_1_SRC 0x00000003 +#define BLE_DSTF_SRC_A 0x00000004 +#define BLE_DSTF_1_SRC_A 0x00000005 +#define BLE_DSTF_DST_A 0x00000006 +#define BLE_DSTF_1_DST_A 0x00000007 + +/* + * BEM_PE_CKEY + */ +#define CKEY_EXCLUDE_UNUSED 0x00100000 +#define CKEY_EXCLUDE_ALPHA 0x00010000 +#define CKEY_A_ENABLE 0x00000100 +#define CKEY_B_ENABLE 0x00000001 + +/* + * BEM_PE_COLORCHANGE + */ +#define COLORCHANGE_DISABLE 0x00000000 +#define COLORCHANGE_COMPARE_FIRST 0x0000000b +#define COLORCHANGE_EXCLUDE_UNUSED 0x00010000 + +/* + * BEM_PE_MASK + */ +#define PE_MASK_DISABLE 0x00000000 +#define PE_MASK_COLOR 0x00000001 +#define PE_MASK_ALPHA 0x00000080 + +/* + * BEM_TE_MASK + */ +#define TE_MASK_DISABLE 0x00000000 +#define TE_MASK_ENABLE 0x00010000 + +/* + * BEM_WR_CTRL + */ +#define WR_CTRL_LINE 0x00000002 +#define WR_CTRL_POLYLINE 0x00000003 +#define WR_CTRL_ANTIALIAS 0x00020100 +#define WR_CTRL_ENDPOINT 0x00001000 + +#endif diff --git a/Source/DirectFB/gfxdrivers/sis315/Makefile.am b/Source/DirectFB/gfxdrivers/sis315/Makefile.am new file mode 100755 index 0000000..de0b424 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/Makefile.am @@ -0,0 +1,42 @@ +## Makefile.am for DirectFB/src/core/gfxcards/sis315 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +sis315_LTLIBRARIES = libdirectfb_sis315.la + +if BUILD_STATIC +sis315_DATA = $(sis315_LTLIBRARIES:.la=.o) +endif + +sis315dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_sis315_la_SOURCES = \ + sis315.c \ + sis315.h \ + sis315_accel.c \ + sis315_accel.h \ + sis315_compat.h \ + sis315_mmio.c \ + sis315_mmio.h \ + sis315_regs.h \ + sis315_state.c \ + sis315_state.h + +libdirectfb_sis315_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_sis315_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/sis315/Makefile.in b/Source/DirectFB/gfxdrivers/sis315/Makefile.in new file mode 100755 index 0000000..e41ae8e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/Makefile.in @@ -0,0 +1,607 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL 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'/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ + sort -u` ;; \ + esac; \ + for file in $$dist_files; do \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + if test -d $$d/$$file; then \ + dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-am +all-am: Makefile $(LTLIBRARIES) $(DATA) +installdirs: + for dir in "$(DESTDIR)$(sis315dir)" "$(DESTDIR)$(sis315dir)"; do \ + test -z "$$dir" || $(MKDIR_P) "$$dir"; \ + done +install: install-am +install-exec: install-exec-am +install-data: install-data-am +uninstall: uninstall-am + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-am +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-am + +clean-am: clean-generic clean-libtool clean-sis315LTLIBRARIES \ + mostlyclean-am + +distclean: distclean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-tags + +dvi: dvi-am + +dvi-am: + +html: html-am + +info: info-am + +info-am: + +install-data-am: install-sis315DATA install-sis315LTLIBRARIES + +install-dvi: install-dvi-am + +install-exec-am: + +install-html: install-html-am + +install-info: install-info-am + +install-man: + +install-pdf: install-pdf-am + +install-ps: install-ps-am + +installcheck-am: + +maintainer-clean: maintainer-clean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-sis315DATA uninstall-sis315LTLIBRARIES + +.MAKE: install-am install-strip + +.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ + clean-libtool clean-sis315LTLIBRARIES ctags distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-tags distdir dvi dvi-am html html-am info info-am \ + install install-am install-data install-data-am install-dvi \ + install-dvi-am install-exec install-exec-am install-html \ + install-html-am install-info install-info-am install-man \ + install-pdf install-pdf-am install-ps install-ps-am \ + install-sis315DATA install-sis315LTLIBRARIES install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-sis315DATA \ + uninstall-sis315LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315.c b/Source/DirectFB/gfxdrivers/sis315/sis315.c new file mode 100755 index 0000000..4717fe7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315.c @@ -0,0 +1,355 @@ +/* + * $Id: sis315.c,v 1.20 2007-01-29 01:00:45 dok Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#include + +#include +#include + +#include /* FIXME: Needs to be included before dfb_types.h to work around a type clash with asm/types.h */ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "sis315.h" +#include "sis315_accel.h" +#include "sis315_compat.h" +#include "sis315_state.h" + +DFB_GRAPHICS_DRIVER(sis315); + +#define SIS_SUPPORTED_DRAWING_FUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | DFXL_DRAWLINE) +#define SIS_SUPPORTED_DRAWING_FLAGS \ + (DSDRAW_NOFX) +#define SIS_SUPPORTED_BLITTING_FUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) +#define SIS_SUPPORTED_BLITTING_FLAGS \ + (DSBLIT_SRC_COLORKEY) + +static DFBResult sis_engine_sync(void *driver_data, void *device_data) +{ + (void)driver_data; + (void)device_data; + + /* + * this driver syncs after every command, + * so this function can be left empty + */ + + return DFB_OK; +} + +static void sis_check_state(void *driver_data, void *device_data, + CardState *state, DFBAccelerationMask accel) +{ + (void)driver_data; + (void)device_data; + + switch (state->destination->config.format) { + case DSPF_LUT8: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (DFB_DRAWING_FUNCTION(accel)) { + if (state->drawingflags & ~SIS_SUPPORTED_DRAWING_FLAGS) + return; + if (accel & DFXL_FILLTRIANGLE) { + /* this is faster. don't know why. */ + state->accel = 0; + return; + } + state->accel |= SIS_SUPPORTED_DRAWING_FUNCTIONS; + } + else { + if (state->blittingflags & ~SIS_SUPPORTED_BLITTING_FLAGS) + return; + + switch (state->source->config.format) { + case DSPF_LUT8: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + return; + } + + if (state->source->config.format != state->destination->config.format) + return; + + state->accel |= SIS_SUPPORTED_BLITTING_FUNCTIONS; + } +} + +static void sis_set_state(void *driver_data, void *device_data, + GraphicsDeviceFuncs *funcs, CardState *state, + DFBAccelerationMask accel) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + (void)funcs; + + if (state->mod_hw) { + if (state->mod_hw & SMF_SOURCE) + dev->v_source = 0; + + if (state->mod_hw & SMF_DESTINATION) + dev->v_color = dev->v_destination = 0; + else if (state->mod_hw & SMF_COLOR) + dev->v_color = 0; + + if (state->mod_hw & SMF_SRC_COLORKEY) + dev->v_src_colorkey = 0; + +// if (state->mod_hw & SMF_BLITTING_FLAGS) +// dev->v_blittingflags = 0; + } + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + sis_validate_dst(drv, dev, state); + sis_validate_color(drv, dev, state); + state->set = SIS_SUPPORTED_DRAWING_FUNCTIONS; + break; + case DFXL_BLIT: + sis_validate_src(drv, dev, state); + sis_validate_dst(drv, dev, state); + if (state->blittingflags & DSBLIT_DST_COLORKEY) + sis_set_dst_colorkey(drv, dev, state); + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + sis_set_src_colorkey(drv, dev, state); + state->set = SIS_SUPPORTED_BLITTING_FUNCTIONS; + break; + case DFXL_STRETCHBLIT: + sis_validate_src(drv, dev, state); + sis_validate_dst(drv, dev, state); + if (state->blittingflags & DSBLIT_DST_COLORKEY) + sis_set_dst_colorkey(drv, dev, state); + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + sis_set_src_colorkey(drv, dev, state); + state->set = DFXL_STRETCHBLIT; + break; + default: + D_BUG("unexpected drawing or blitting function"); + break; + } + + if ((state->mod_hw & SMF_CLIP) && (accel!=DFXL_STRETCHBLIT)) + sis_set_clip(drv, &state->clip); + + state->mod_hw = 0; +} + +static void check_sisfb_version(SiSDriverData *drv, const struct sisfb_info *i) +{ + u32 sisfb_version = SISFB_VERSION(i->sisfb_version, + i->sisfb_revision, + i->sisfb_patchlevel); + + if (sisfb_version < SISFB_VERSION(1, 6, 23)) { + fprintf(stderr, "*** Warning: sisfb version < 1.6.23 detected, " + "please update your driver! ***\n"); + drv->has_auto_maximize = false; + } + else { + drv->has_auto_maximize = true; + } +} + +/* + * exported symbols... + */ + +static int driver_probe(CoreGraphicsDevice *device) +{ + switch (dfb_gfxcard_get_accelerator(device)) { + case FB_ACCEL_SIS_GLAMOUR_2: + case FB_ACCEL_SIS_XABRE: + case FB_ACCEL_XGI_VOLARI_Z: + return 1; + default: + return 0; + } +} + +static void driver_get_info(CoreGraphicsDevice *device, + GraphicsDriverInfo *info) +{ + (void)device; + + snprintf(info->name, DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "SiS 315 Driver"); + snprintf(info->vendor, DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Andreas Oberritter "); + + info->version.major = 0; + info->version.minor = 1; + + info->driver_data_size = sizeof(SiSDriverData); + info->device_data_size = sizeof(SiSDeviceData); +} + +static DFBResult driver_init_driver(CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + FBDev *dfb_fbdev; + struct sisfb_info *fbinfo; + u32 fbinfo_size; + u32 zero = 0; + + (void)device_data; + + dfb_fbdev = dfb_system_data(); + if (!dfb_fbdev) + return DFB_IO; + + if (ioctl(dfb_fbdev->fd, SISFB_GET_INFO_SIZE, &fbinfo_size) == 0) { + fbinfo = D_MALLOC(fbinfo_size); + drv->get_info = SISFB_GET_INFO | (fbinfo_size << 16); + drv->get_automaximize = SISFB_GET_AUTOMAXIMIZE; + drv->set_automaximize = SISFB_SET_AUTOMAXIMIZE; + } + else { + fbinfo = D_MALLOC(sizeof(struct sisfb_info)); + drv->get_info = SISFB_GET_INFO_OLD; + drv->get_automaximize = SISFB_GET_AUTOMAXIMIZE_OLD; + drv->set_automaximize = SISFB_SET_AUTOMAXIMIZE_OLD; + } + + if (fbinfo == NULL) + return DFB_NOSYSTEMMEMORY; + + if (ioctl(dfb_fbdev->fd, drv->get_info, fbinfo) == -1) { + D_FREE(fbinfo); + return DFB_IO; + } + + check_sisfb_version(drv, fbinfo); + + D_FREE(fbinfo); + + if (drv->has_auto_maximize) { + if (ioctl(dfb_fbdev->fd, drv->get_automaximize, &drv->auto_maximize)) + return DFB_IO; + if (drv->auto_maximize) + if (ioctl(dfb_fbdev->fd, drv->set_automaximize, &zero)) + return DFB_IO; + } + + drv->mmio_base = dfb_gfxcard_map_mmio(device, 0, -1); + if (!drv->mmio_base) + return DFB_IO; + + /* base functions */ + funcs->EngineSync = sis_engine_sync; + funcs->CheckState = sis_check_state; + funcs->SetState = sis_set_state; + + /* drawing functions */ + funcs->FillRectangle = sis_fill_rectangle; + funcs->DrawRectangle = sis_draw_rectangle; + funcs->DrawLine = sis_draw_line; + + /* blitting functions */ + funcs->Blit = sis_blit; + funcs->StretchBlit = sis_stretchblit; + + /* allocate buffer for stretchBlit with colorkey */ + drv->buffer_offset = dfb_gfxcard_reserve_memory( device, 1024*768*4 ); + + return DFB_OK; +} + +static DFBResult driver_init_device(CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data) +{ + (void)device; + (void)driver_data; + (void)device_data; + + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "315"); + snprintf(device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "SiS"); + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = SIS_SUPPORTED_DRAWING_FUNCTIONS | + SIS_SUPPORTED_BLITTING_FUNCTIONS; + device_info->caps.drawing = SIS_SUPPORTED_DRAWING_FLAGS; + device_info->caps.blitting = SIS_SUPPORTED_BLITTING_FLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + return DFB_OK; +} + +static void driver_close_device(CoreGraphicsDevice *device, + void *driver_data, + void *device_data) +{ + (void)device; + (void)driver_data; + (void)device_data; +} + +static void driver_close_driver(CoreGraphicsDevice *device, + void *driver_data) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + + dfb_gfxcard_unmap_mmio(device, drv->mmio_base, -1); + + if ((drv->has_auto_maximize) && (drv->auto_maximize)) { + FBDev *dfb_fbdev = dfb_system_data(); + if (!dfb_fbdev) + return; + ioctl(dfb_fbdev->fd, drv->set_automaximize, &drv->auto_maximize); + } +} + diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315.h b/Source/DirectFB/gfxdrivers/sis315/sis315.h new file mode 100755 index 0000000..e8b3632 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315.h @@ -0,0 +1,59 @@ +/* + * $Id: sis315.h,v 1.6 2006-11-28 10:53:42 klan Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#ifndef _SIS315_H +#define _SIS315_H + +#include + +typedef struct { + volatile u8 *mmio_base; + bool has_auto_maximize; + u32 auto_maximize; + /* ioctls */ + int get_info; + int get_automaximize; + int set_automaximize; + unsigned long buffer_offset; +} SiSDriverData; + +typedef struct { + /* state validation */ + int v_blittingflags; + int v_color; + int v_destination; + int v_source; + int v_dst_colorkey; + int v_src_colorkey; + + /* stored values */ + int blit_cmd; + int blit_rop; + int cmd_bpp; + int color; + int src_offset; + int src_pitch; + int dst_offset; + int dst_pitch; +} SiSDeviceData; + +#endif /* _SIS315_H */ diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_accel.c b/Source/DirectFB/gfxdrivers/sis315/sis315_accel.c new file mode 100755 index 0000000..99e5489 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_accel.c @@ -0,0 +1,250 @@ +/* + * $Id: sis315_accel.c,v 1.4 2006-10-29 23:24:50 dok Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#include + +#include +#include + +#include "sis315.h" +#include "sis315_mmio.h" +#include "sis315_regs.h" + +static void dump_cmd(SiSDriverData *drv) +{ + int i; + fprintf(stderr,"MMIO8200--MMIO8240 \n"); + for( i = 0x8200 ; i < 0x8240 ; i+=0x10 ) + { + fprintf(stderr,"[%04X]: %08lX %08lX %08lX %08lX\n",i, + sis_rl(drv->mmio_base, i), + sis_rl(drv->mmio_base, i+4), + sis_rl(drv->mmio_base, i+8), + sis_rl(drv->mmio_base, i+12)); + } +} + + +static void sis_idle(SiSDriverData *drv) +{ + while (!(sis_rl(drv->mmio_base, SIS315_2D_CMD_QUEUE_STATUS) & 0x80000000)); +} + +static void sis_cmd(SiSDriverData *drv, SiSDeviceData *dev, u8 pat, u8 src, u32 type, u8 rop) +{ + sis_wl(drv->mmio_base, SIS315_2D_CMD, SIS315_2D_CMD_RECT_CLIP_EN | + dev->cmd_bpp | (rop << 8) | + pat | src | type); + + sis_wl(drv->mmio_base, SIS315_2D_FIRE_TRIGGER, 0); + /* dump_cmd(drv); */ + sis_idle(drv); +} + +bool sis_fill_rectangle(void *driver_data, void *device_data, DFBRectangle *rect) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + sis_wl(drv->mmio_base, SIS315_2D_DST_Y, (rect->x << 16) | rect->y); + sis_wl(drv->mmio_base, SIS315_2D_RECT_WIDTH, (rect->h << 16) | rect->w); + + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_BITBLT, + SIS315_ROP_COPY_PAT); + + return true; +} + +bool sis_draw_rectangle(void *driver_data, void *device_data, DFBRectangle *rect) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + /* from top left ... */ + sis_wl(drv->mmio_base, SIS315_2D_LINE_X0, (rect->y << 16) | rect->x); + /* ... to top right ... */ + sis_wl(drv->mmio_base, SIS315_2D_LINE_X1, (rect->y << 16) | (rect->x + rect->w - 1)); + /* ... to bottom right ... */ + sis_wl(drv->mmio_base, SIS315_2D_LINE_X(2), ((rect->y + rect->h - 1) << 16) | (rect->x + rect->w - 1)); + /* ... to bottom left ... */ + sis_wl(drv->mmio_base, SIS315_2D_LINE_X(3), ((rect->y + rect->h - 1) << 16) | rect->x); + /* ... and back to top left */ + sis_wl(drv->mmio_base, SIS315_2D_LINE_X(4), ((rect->y + 1) << 16) | rect->x); + + sis_wl(drv->mmio_base, SIS315_2D_LINE_COUNT, 4); + + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_LINE_DRAW, + SIS315_ROP_COPY_PAT); + + return true; +} + +bool sis_draw_line(void *driver_data, void *device_data, DFBRegion *line) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + sis_wl(drv->mmio_base, SIS315_2D_LINE_X0, (line->y1 << 16) | line->x1); + sis_wl(drv->mmio_base, SIS315_2D_LINE_X1, (line->y2 << 16) | line->x2); + sis_wl(drv->mmio_base, SIS315_2D_LINE_COUNT, 1); + + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_LINE_DRAW, + SIS315_ROP_COPY_PAT); + + return true; +} + +bool sis_blit(void *driver_data, void *device_data, DFBRectangle *rect, int dx, int dy) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + sis_wl(drv->mmio_base, SIS315_2D_SRC_Y, (rect->x << 16) | rect->y); + sis_wl(drv->mmio_base, SIS315_2D_DST_Y, (dx << 16) | (dy & 0xffff) ); + sis_wl(drv->mmio_base, SIS315_2D_RECT_WIDTH, (rect->h << 16) | rect->w); + + if (dev->v_src_colorkey) { + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_TRANSPARENT_BITBLT, + SIS315_ROP_AND_INVERTED_PAT); + } + else { + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_BITBLT, + SIS315_ROP_COPY); + } + + return true; +} + +bool sis_stretchblit(void *driver_data, void *device_data, DFBRectangle *sr, DFBRectangle *dr ) +{ + SiSDriverData *drv = (SiSDriverData *)driver_data; + SiSDeviceData *dev = (SiSDeviceData *)device_data; + + long lDstWidth, lDstHeight, lSrcWidth, lSrcHeight; + long lSmallWidth, lLargeWidth, lSmallHeight, lLargeHeight; + long lXInitErr, lYInitErr; + unsigned long dst_offset, src_offset, src_pitch, dst_pitch, src_colorkey; + + if((dr->w > 0xfff)|(dr->h > 0xfff)) + return false; + + lSrcWidth = sr->w; + lDstWidth = dr->w; + lSrcHeight = sr->h; + lDstHeight = dr->h; + + if(lDstWidth > lSrcWidth) + { + lLargeWidth = lDstWidth; + lSmallWidth = lSrcWidth; + lXInitErr = 3 * lSrcWidth - 2 * lDstWidth; + } + else + { + lLargeWidth = lSrcWidth; + lSmallWidth = lDstWidth; + lXInitErr = lDstWidth; //HW design + } + + if(lDstHeight > lSrcHeight) + { + lLargeHeight = lDstHeight; + lSmallHeight = lSrcHeight; + lYInitErr = 3 * lSrcHeight - 2 * lDstHeight; + } + else + { + lLargeHeight = lSrcHeight; + lSmallHeight = lDstHeight; + lYInitErr = lDstHeight; //HW design + } + + src_colorkey = sis_rl(drv->mmio_base, SIS315_2D_TRANS_SRC_KEY_HIGH); + + sis_wl(drv->mmio_base, 0x8208, (sr->x << 16) | sr->y & 0xFFFF); + sis_wl(drv->mmio_base, 0x820C, ( dr->x << 16) | dr->y & 0xFFFF); + + sis_wl(drv->mmio_base, 0x8218, (dr->h << 16) | dr->w & 0x0FFF); + sis_wl(drv->mmio_base, 0x821c, (sr->h << 16) | sr->w & 0x0FFF); + + sis_wl(drv->mmio_base, 0x8220, ((((lSmallWidth - lLargeWidth) * 2) << 16 ) | ((lSmallWidth * 2) & 0xFFFF))); + sis_wl(drv->mmio_base, 0x8224, ((((lSmallHeight - lLargeHeight) * 2) << 16 ) | ((lSmallHeight * 2) & 0xFFFF))); + sis_wl(drv->mmio_base, 0x8228, ((lYInitErr << 16) | (lXInitErr & 0xFFFF))); + + dev->blit_cmd = SIS_2D_CMD_DST_Y_INC | SIS_2D_CMD_SRC_X_INC \ + | SIS_2D_CMD_SRC_Y_INC | SIS_2D_CMD_DST_X_INC | SIS315_2D_CMD_STRETCH_BITBLT; + + if(dev->v_src_colorkey) /* DSBLIT_SRC_COLORKEY */ + { + dst_offset = sis_rl(drv->mmio_base, SIS315_2D_DST_ADDR); + src_offset = sis_rl(drv->mmio_base, SIS315_2D_SRC_ADDR); + src_pitch = sis_rl(drv->mmio_base, 0x8204); + dst_pitch = sis_rl(drv->mmio_base, 0x8214); + + /* drv->buffer_offset reserve 1024x768x4 at driver_init_driver() in sis315.c */ + sis_wl(drv->mmio_base, SIS315_2D_DST_ADDR, drv->buffer_offset); + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + dev->blit_cmd, + SIS315_ROP_COPY); + + sis_wl(drv->mmio_base, SIS315_2D_SRC_ADDR, drv->buffer_offset); + sis_wl(drv->mmio_base, SIS315_2D_DST_ADDR, dst_offset); + sis_wl(drv->mmio_base, 0x8204, dst_pitch); + sis_wl(drv->mmio_base, SIS315_2D_SRC_Y, (dr->x << 16) | dr->y); + sis_wl(drv->mmio_base, SIS315_2D_DST_Y, (dr->x << 16) | (dr->y & 0xffff)); + sis_wl(drv->mmio_base, SIS315_2D_RECT_WIDTH, (dr->h << 16) | dr->w); + + sis_wl(drv->mmio_base, SIS315_2D_TRANS_SRC_KEY_HIGH, src_colorkey); + sis_wl(drv->mmio_base, SIS315_2D_TRANS_SRC_KEY_LOW, src_colorkey); + + + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + SIS315_2D_CMD_TRANSPARENT_BITBLT, + SIS315_ROP_AND_INVERTED_PAT); + + sis_wl(drv->mmio_base, SIS315_2D_SRC_ADDR, src_offset); /*restore*/ + sis_wl(drv->mmio_base, 0x8204, src_pitch); + } + else /*simple stretch bitblt */ + { + + //fprintf(stderr,"dev->blit_cmd = %x \n",dev->blit_cmd); + sis_cmd(drv, dev, SIS315_2D_CMD_PAT_FG_REG, + SIS315_2D_CMD_SRC_VIDEO, + dev->blit_cmd, + SIS315_ROP_COPY); + } + + return true; +} diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_accel.h b/Source/DirectFB/gfxdrivers/sis315/sis315_accel.h new file mode 100755 index 0000000..11ead88 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_accel.h @@ -0,0 +1,32 @@ +/* + * $Id: sis315_accel.h,v 1.2 2006-10-29 23:24:50 dok Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#ifndef _SIS315_ACCEL_H +#define _SIS315_ACCEL_H + +bool sis_fill_rectangle(void *driver_data, void *device_data, DFBRectangle *rect); +bool sis_draw_rectangle(void *driver_data, void *device_data, DFBRectangle *rect); +bool sis_draw_line(void *driver_data, void *device_data, DFBRegion *line); +bool sis_blit(void *driver_data, void *device_data, DFBRectangle *rect, int dx, int dy); +bool sis_stretchblit(void *driver_data, void *device_data, DFBRectangle *sr, DFBRectangle *dr ); + +#endif /* _SIS315_ACCEL_H */ diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_compat.h b/Source/DirectFB/gfxdrivers/sis315/sis315_compat.h new file mode 100755 index 0000000..c6f33da --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_compat.h @@ -0,0 +1,89 @@ +#ifndef _SIS315_COMPAT_H +#define _SIS315_COMPAT_H + +#include + +#include + +#ifndef FB_ACCEL_SIS_GLAMOUR_2 +#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ +#endif +#ifndef FB_ACCEL_SIS_XABRE +#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */ +#endif +#ifndef FB_ACCEL_XGI_VOLARI_Z +#define FB_ACCEL_XGI_VOLARI_Z 48 /* Z7 Z9 */ +#endif + +struct sisfb_info { + u32 sisfb_id; /* for identifying sisfb */ +#ifndef SISFB_ID +#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */ +#endif + u32 chip_id; /* PCI-ID of detected chip */ + u32 memory; /* total video memory in KB */ + u32 heapstart; /* heap start offset in KB */ + u8 fbvidmode; /* current sisfb mode */ + + u8 sisfb_version; + u8 sisfb_revision; + u8 sisfb_patchlevel; + + u8 sisfb_caps; /* sisfb capabilities */ + + u32 sisfb_tqlen; /* turbo queue length (in KB) */ + + u32 sisfb_pcibus; /* The card's PCI ID */ + u32 sisfb_pcislot; + u32 sisfb_pcifunc; + + u8 sisfb_lcdpdc; /* PanelDelayCompensation */ + + u8 sisfb_lcda; /* Detected status of LCDA for low res/text modes */ + + u32 sisfb_vbflags; + u32 sisfb_currentvbflags; + + u32 sisfb_scalelcd; + u32 sisfb_specialtiming; + + u8 sisfb_haveemi; + u8 sisfb_emi30,sisfb_emi31,sisfb_emi32,sisfb_emi33; + u8 sisfb_haveemilcd; + + u8 sisfb_lcdpdca; /* PanelDelayCompensation for LCD-via-CRT1 */ + + u16 sisfb_tvxpos, sisfb_tvypos; /* Warning: Values + 32 ! */ + + u32 sisfb_heapsize; /* heap size (in KB) */ + u32 sisfb_videooffset; /* Offset of viewport in video memory (in bytes) */ + + u32 sisfb_curfstn; /* currently running FSTN/DSTN mode */ + u32 sisfb_curdstn; + + u16 sisfb_pci_vendor; /* PCI vendor (SiS or XGI) */ + + u32 sisfb_vbflags2; /* ivideo->vbflags2 */ + + u8 sisfb_can_post; /* sisfb can POST this card */ + u8 sisfb_card_posted; /* card is POSTED */ + u8 sisfb_was_boot_device; /* This card was the boot video device (ie is primary) */ + + u8 reserved[183]; /* for future use */ +}; + +#define SISFB_GET_INFO_SIZE _IOR(0xF3,0x00,u32) + +#define SISFB_GET_INFO _IOR(0xF3,0x01,struct sisfb_info) +#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3,0x03,u32) +#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3,0x03,u32) + +#define SISFB_GET_INFO_OLD _IOR('n',0xF8,u32) +#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n',0xFA,u32) +#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n',0xFA,u32) + + +#define SISFB_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) + + +#endif /* _SIS315_COMPAT_H */ diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.c b/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.c new file mode 100755 index 0000000..415ea0b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.c @@ -0,0 +1,51 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include "config.h" +#include "sis315_mmio.h" +#include "direct/util.h" + +u32 sis_rl(volatile u8 *mmio, unsigned int offset) +{ +#ifdef WORDS_BIGENDIAN + u32 r = *(volatile u32 *)(mmio + offset); + return BSWAP32(r); +#else + return *(volatile u32 *)(mmio + offset); +#endif +} + +void sis_wl(volatile u8 *mmio, unsigned int offset, u32 value) +{ +#ifdef WORDS_BIGENDIAN + *(volatile u32 *)(mmio + offset) = BSWAP32(value); +#else + *(volatile u32 *)(mmio + offset) = value; +#endif +} + diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.h b/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.h new file mode 100755 index 0000000..42de5f0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_mmio.h @@ -0,0 +1,37 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef _SIS315_MMIO_H +#define _SIS315_MMIO_H + +#include + +extern __inline__ u32 sis_rl(volatile u8 *mmio, unsigned int offset); +extern __inline__ void sis_wl(volatile u8 *mmio, unsigned int offset, u32 value); + +#endif diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_regs.h b/Source/DirectFB/gfxdrivers/sis315/sis315_regs.h new file mode 100755 index 0000000..25ff40d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_regs.h @@ -0,0 +1,161 @@ +#ifndef _SIS315_REGS_H +#define _SIS315_REGS_H + +#define PAT_REG_SIZE 384 + +enum sisfb_raster_op_bitblt { + SIS315_ROP_CLEAR = 0x00, /* dst = 0, 0 */ + SIS315_ROP_AND = 0x88, /* dst = dst & src, DSa */ + SIS315_RON_AND_REVERSE = 0x44, /* dst = ~dst & src, SDna */ + SIS315_ROP_COPY = 0xCC, /* dst = src, S */ + SIS315_ROP_AND_INVERTED = 0x22, /* dst = dst & ~src, DSna */ + SIS315_ROP_NOOP = 0xAA, /* dst = dst, D */ + SIS315_ROP_XOR = 0x66, /* dst = dst ^ src, DSx */ + SIS315_ROP_OR = 0xEE, /* dst = dst | src, DSo */ + SIS315_ROP_NOR = 0x11, /* dst = ~(dst | src), DSon */ + SIS315_ROP_EQUIV = 0x99, /* dst = dst ^ ~src, DSxn */ + SIS315_ROP_INVERT = 0x55, /* dst = ~dst, Dn */ + SIS315_ROP_OR_INVERSE = 0xDD, /* dst = ~dst | src, SDno */ + SIS315_ROP_COPY_INVERTED = 0x33, /* dst = ~src, Sn */ + SIS315_ROP_OR_INVERTED = 0xBB, /* dst = ~src | dst, DSno */ + SIS315_ROP_NAND = 0x77, /* dst = ~(dst & src), DSan */ + SIS315_ROP_SET = 0xFF, /* dst = 1, 1 */ + + /* same as above, but with pattern as source */ + SIS315_ROP_CLEAR_PAT = 0x00, /* dst = 0, 0 */ + SIS315_ROP_AND_PAT = 0xA0, /* dst = dst & src, DSa */ + SIS315_RON_AND_REVERSE_PAT = 0x50, /* dst = ~dst & src, SDna */ + SIS315_ROP_COPY_PAT = 0xF0, /* dst = src, S */ + SIS315_ROP_AND_INVERTED_PAT = 0x0A, /* dst = dst & ~src, DSna */ + SIS315_ROP_NOOP_PAT = 0xAA, /* dst = dst, D */ + SIS315_ROP_XOR_PAT = 0x5A, /* dst = dst ^ src, DSx */ + SIS315_ROP_OR_PAT = 0xFA, /* dst = dst | src, DSo */ + SIS315_ROP_NOR_PAT = 0x05, /* dst = ~(dst | src), DSon */ + SIS315_ROP_EQUIV_PAT = 0xA5, /* dst = dst ^ ~src, DSxn */ + SIS315_ROP_INVERT_PAT = 0x55, /* dst = ~dst, Dn */ + SIS315_ROP_OR_REVERSE_PAT = 0xDD, /* dst = ~dst | src, SDno */ + SIS315_ROP_COPY_INVERTED_PAT = 0x0F, /* dst = ~src, Sn */ + SIS315_ROP_OR_INVERTED_PAT = 0xAF, /* dst = ~src | dst, DSno */ + SIS315_ROP_NAND_PAT = 0x5F, /* dst = ~(dst & src), DSan */ + SIS315_ROP_SET_PAT = 0xFF, /* dst = 1, 1 */ +}; + +enum sisfb_raster_op_transparent_bitblt { + SIS315_ROP_BLACK, + SIS315_ROP_NOT_MERGE_PEN, +}; + +enum sis315_2d_registers { + SIS315_2D_SRC_ADDR = 0x8200, + SIS315_2D_SRC_PITCH = 0x8204, SIS315_2D_AGP_BASE = 0x8206, + SIS315_2D_SRC_Y = 0x8208, SIS315_2D_SRC_X = 0x820A, + SIS315_2D_DST_Y = 0x820C, SIS315_2D_DST_X = 0x820E, + SIS315_2D_DST_ADDR = 0x8210, + SIS315_2D_DST_PITCH = 0x8214, SIS315_2D_DST_HEIGHT = 0x8216, + SIS315_2D_RECT_WIDTH = 0x8218, SIS315_2D_RECT_HEIGHT = 0x821A, + SIS315_2D_PAT_FG_COLOR = 0x821C, + SIS315_2D_PAT_BG_COLOR = 0x8220, + SIS315_2D_SRC_FG_COLOR = 0x8224, + SIS315_2D_SRC_BG_COLOR = 0x8228, + SIS315_2D_MONO_MASK = 0x822C, + SIS315_2D_LEFT_CLIP = 0x8234, SIS315_2D_TOP_CLIP = 0x8236, + SIS315_2D_RIGHT_CLIP = 0x8238, SIS315_2D_BOT_CLIP = 0x823A, + SIS315_2D_CMD = 0x823C, + SIS315_2D_FIRE_TRIGGER = 0x8240, + SIS315_2D_PATTERN_REG = 0x8300 +}; + +enum SIS315_2d_registers_StretchBlt { + SIS315_2D_X_ERROR_TERM = 0x8220, + SIS315_2D_Y_ERROR_TERM = 0x8224, + SIS315_2D_X_INITIAL_ERROR = 0x8228 +}; + +enum sis315_2d_registers_drawline { + SIS315_2D_LINE_X0 = 0x8208, SIS315_2D_LINE_Y0 = 0x820A, + SIS315_2D_LINE_X1 = 0x820C, SIS315_2D_LINE_Y1 = 0x820E, + SIS315_2D_LINE_COUNT = 0x8218, SIS315_2D_LINE_STYLE_PERIOD = 0x821A, + SIS315_2D_LINE_STYLE_0 = 0x822C, + SIS315_2D_LINE_STYLE_1 = 0x8230, + SIS315_2D_LINE_Xn = 0x8300, SIS315_2D_LINE_Yn = 0x8302, +}; + +#define SIS315_2D_LINE_X(n) (0x8300 + ((n - 2) << 2)) +#define SIS315_2D_LINE_Y(n) (0x8302 + ((n - 2) << 2)) + +enum sis315_2d_register_transparent_bitblt { + SIS315_2D_TRANS_DEST_KEY_HIGH = 0x821C, + SIS315_2D_TRANS_DEST_KEY_LOW = 0x8220, + SIS315_2D_TRANS_SRC_KEY_HIGH = 0x8224, + SIS315_2D_TRANS_SRC_KEY_LOW = 0x8228, +}; + +enum sis315_2d_cmd_type { + SIS315_2D_CMD_BITBLT = 0x00, SIS315_2D_CMD_COLOREXP = 0x01, + SIS315_2D_CMD_ENCOLOREXP = 0x02, SIS315_2D_CMD_MULTIPLE_SCANLINE = 0x03, + SIS315_2D_CMD_LINE_DRAW = 0x04, SIS315_2D_CMD_TRAPEZOID_FILL = 0x05, + SIS315_2D_CMD_TRANSPARENT_BITBLT = 0x06, SIS315_2D_CMD_ALPHA_BLENDING = 0x07, + SIS315_2D_CMD_3D_FUNCTION = 0x08, SIS315_2D_CMD_CLEAR_Z_BUFFER = 0x09, + SIS315_2D_CMD_GRADIENT_FILL = 0x0A, SIS315_2D_CMD_STRETCH_BITBLT = 0x0B +}; + +enum sis315_2d_cmd_control { + /* source selection */ + SIS315_2D_CMD_SRC_VIDEO = 0x00000000, + SIS315_2D_CMD_SRC_SYSTEM = 0x00000010, + SIS315_2D_CMD_SRC_AGP = 0x00000020, + /* pattern source selection */ + SIS315_2D_CMD_PAT_FG_REG = 0x00000000, + SIS315_2D_CMD_PAT_PAT_REG = 0x00000040, + SIS315_2D_CMD_PAT_MONO_MASK = 0x00000080, + /* color format flags */ + SIS315_2D_CMD_CFB_8 = 0x00000000, + SIS315_2D_CMD_CFB_16 = 0x00010000, + SIS315_2D_CMD_CFB_32 = 0x00020000, + /* clipping flags */ + SIS315_2D_CMD_NOCLIP = 0x00000000, + SIS315_2D_CMD_RECT_CLIP_EN = 0x00040000, + SIS315_2D_CMD_MERGE_CLIP_DIS = 0x04000000, + /* subfunctions for transparent bitblt */ + SIS315_2D_CMD_OPAQUE = 0x00000000, + SIS315_2D_CMD_TRANSPARENT = 0x00100000, + /* subfunctions for alpha blended blit */ + SIS315_2D_CMD_CONSTANT_ALPHA = 0x00000000, + SIS315_2D_CMD_PER_PIXEL_ALPHA = 0x00080000, + SIS315_2D_CMD_NO_DEST_ALPHA = 0x00100000, + SIS315_2D_CMD_3D_FULL_SCENE = 0x00180000, + /* subfunctions for color expansion */ + SIS315_2D_CMD_COLOR_TO_MONO = 0x00100000, + SIS315_2D_CMD_AA_TEXT = 0x00200000, + /* line flags */ + SIS315_2D_CMD_NO_LAST_PIXEL = 0x00200000, + SIS315_2D_CMD_NO_RESET_COUNTER = 0x00400000, + SIS315_2D_CMD_LINE_STLYE_ENABLE = 0x00800000, + /* destination */ + SIS315_DST_VIDEO = 0x00000000, + SIS315_DST_AGP = 0x02000000, + /*for stretchblit */ + SIS_2D_CMD_SRC_Y_DEC = 0x00000000, + SIS_2D_CMD_SRC_Y_INC = 0x00400000, + SIS_2D_CMD_SRC_X_DEC = 0x00000000, + SIS_2D_CMD_SRC_X_INC = 0x00200000, + SIS_2D_CMD_DST_Y_DEC = 0x00000000, + SIS_2D_CMD_DST_Y_INC = 0x00100000, + SIS_2D_CMD_DST_X_DEC = 0x00000000, + SIS_2D_CMD_DST_X_INC = 0x00080000, +#if 0 + SIS315_2D_CMD_DIR_X_INC = 0x00010000, + SIS315_2D_CMD_DIR_X_DEC = 0x00000000, + SIS315_2D_CMD_DIR_Y_INC = 0x00020000, + SIS315_2D_CMD_DIR_Y_DEC = 0x00000000, +#endif +}; + +enum sis315_command_queue_registers { + SIS315_2D_CMD_QUEUE_BASE_ADDRESS = 0x85C0, + SIS315_2D_CMD_QUEUE_WRITE_POINTER = 0x85C4, + SIS315_2D_CMD_QUEUE_READ_POINTER = 0x85C8, + SIS315_2D_CMD_QUEUE_STATUS = 0x85CC +}; + +#endif /* _SIS315_REGS_H */ diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_state.c b/Source/DirectFB/gfxdrivers/sis315/sis315_state.c new file mode 100755 index 0000000..d78a71e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_state.c @@ -0,0 +1,164 @@ +/* + * $Id: sis315_state.c,v 1.6 2006-10-29 23:24:50 dok Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#include + +#include + +#include + +#include +#include + +#include + +#include "sis315.h" +#include "sis315_mmio.h" +#include "sis315_regs.h" +#include "sis315_state.h" + +static u16 dspfToSrcColor(DFBSurfacePixelFormat pf) +{ + switch (DFB_BITS_PER_PIXEL(pf)) { + case 16: + return 0x8000; + case 32: + return 0xc000; + default: + return 0x0000; + } +} + +static u32 dspfToCmdBpp(DFBSurfacePixelFormat pf) +{ + switch (DFB_BITS_PER_PIXEL(pf)) { + case 16: + return SIS315_2D_CMD_CFB_16; + case 32: + return SIS315_2D_CMD_CFB_32; + default: + return SIS315_2D_CMD_CFB_8; + } +} + +void sis_validate_color(SiSDriverData *drv, SiSDeviceData *dev, CardState *state) +{ + u32 color; + + if (dev->v_color) + return; + + switch (state->destination->config.format) { + case DSPF_LUT8: + color = state->color_index; + break; + case DSPF_ARGB1555: + color = PIXEL_ARGB1555(state->color.a, + state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB16: + color = PIXEL_RGB16(state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_RGB32: + color = PIXEL_RGB32(state->color.r, + state->color.g, + state->color.b); + break; + case DSPF_ARGB: + color = PIXEL_ARGB(state->color.a, + state->color.r, + state->color.g, + state->color.b); + break; + default: + D_BUG("unexpected pixelformat"); + return; + } + + sis_wl(drv->mmio_base, SIS315_2D_PAT_FG_COLOR, color); + + dev->v_color = 1; +} + +void sis_validate_dst(SiSDriverData *drv, SiSDeviceData *dev, CardState *state) +{ + CoreSurface *dst = state->destination; + + if (dev->v_destination) + return; + + dev->cmd_bpp = dspfToCmdBpp(dst->config.format); + + sis_wl(drv->mmio_base, SIS315_2D_DST_ADDR, state->dst.offset); + sis_wl(drv->mmio_base, SIS315_2D_DST_PITCH, (0xffff << 16) | state->dst.pitch); + + dev->v_destination = 1; +} + +void sis_validate_src(SiSDriverData *drv, SiSDeviceData *dev, CardState *state) +{ + CoreSurface *src = state->source; + + if (dev->v_source) + return; + + sis_wl(drv->mmio_base, SIS315_2D_SRC_ADDR, state->src.offset); + sis_wl(drv->mmio_base, SIS315_2D_SRC_PITCH, (dspfToSrcColor(src->config.format) << 16) | state->src.pitch); + + dev->v_source = 1; +} + +void sis_set_dst_colorkey(SiSDriverData *drv, SiSDeviceData *dev, CardState *state) +{ + if (dev->v_dst_colorkey) + return; + + sis_wl(drv->mmio_base, SIS315_2D_TRANS_DEST_KEY_HIGH, state->dst_colorkey); + sis_wl(drv->mmio_base, SIS315_2D_TRANS_DEST_KEY_LOW, state->dst_colorkey); + + dev->v_dst_colorkey = 1; +} + +void sis_set_src_colorkey(SiSDriverData *drv, SiSDeviceData *dev, CardState *state) +{ + if (dev->v_src_colorkey) + return; + + sis_wl(drv->mmio_base, SIS315_2D_TRANS_SRC_KEY_HIGH, state->src_colorkey); + sis_wl(drv->mmio_base, SIS315_2D_TRANS_SRC_KEY_LOW, state->src_colorkey); + + dev->v_src_colorkey = 1; +} + + +void sis_set_clip(SiSDriverData *drv, DFBRegion *clip) +{ + sis_wl(drv->mmio_base, SIS315_2D_LEFT_CLIP, (clip->y1 << 16) | clip->x1); + sis_wl(drv->mmio_base, SIS315_2D_RIGHT_CLIP, (clip->y2 << 16) | clip->x2); +} + + + diff --git a/Source/DirectFB/gfxdrivers/sis315/sis315_state.h b/Source/DirectFB/gfxdrivers/sis315/sis315_state.h new file mode 100755 index 0000000..e0c86d7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/sis315/sis315_state.h @@ -0,0 +1,34 @@ +/* + * $Id: sis315_state.h,v 1.2 2006-10-29 23:24:50 dok Exp $ + * + * Copyright (C) 2003 by Andreas Oberritter + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + * + */ + +#ifndef _SIS315_STATE_H +#define _SIS315_STATE_H + +void sis_validate_color(SiSDriverData *drv, SiSDeviceData *dev, CardState *state); +void sis_validate_dst(SiSDriverData *drv, SiSDeviceData *dev, CardState *state); +void sis_validate_src(SiSDriverData *drv, SiSDeviceData *dev, CardState *state); +void sis_set_dst_colorkey(SiSDriverData *drv, SiSDeviceData *dev, CardState *state); +void sis_set_src_colorkey(SiSDriverData *drv, SiSDeviceData *dev, CardState *state); +void sis_set_clip(SiSDriverData *drv, DFBRegion *clip); + + +#endif /* _SIS315_STATE_H */ diff --git a/Source/DirectFB/gfxdrivers/tdfx/Makefile.am b/Source/DirectFB/gfxdrivers/tdfx/Makefile.am new file mode 100755 index 0000000..98264f7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/tdfx/Makefile.am @@ -0,0 +1,34 @@ +## Makefile.am for DirectFB/src/core/gfxcards/tdfx + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_srcdir)/lib \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +tdfx_LTLIBRARIES = libdirectfb_tdfx.la + +if BUILD_STATIC +tdfx_DATA = $(tdfx_LTLIBRARIES:.la=.o) +endif + +tdfxdir = $(MODULEDIR)/gfxdrivers + +libdirectfb_tdfx_la_SOURCES = \ + tdfx.c \ + tdfx.h + +libdirectfb_tdfx_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_tdfx_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/tdfx/Makefile.in b/Source/DirectFB/gfxdrivers/tdfx/Makefile.in new file mode 100755 index 0000000..68e9338 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/tdfx/Makefile.in @@ -0,0 +1,595 @@ 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$<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/tdfx/tdfx.c b/Source/DirectFB/gfxdrivers/tdfx/tdfx.c new file mode 100755 index 0000000..fdc03fc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/tdfx/tdfx.c @@ -0,0 +1,884 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include + + +DFB_GRAPHICS_DRIVER( tdfx ) + +#include "tdfx.h" + +static bool tdfxFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ); +static bool tdfxFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); +static bool tdfxFillTriangle2D ( void *drv, void *dev, DFBTriangle *tri ); +static bool tdfxFillTriangle3D ( void *drv, void *dev, DFBTriangle *tri ); +static bool tdfxDrawLine2D ( void *drv, void *dev, DFBRegion *line ); +//static void tdfxDrawLine3D ( void *drv, void *dev, DFBRegion *line ); + +typedef struct { + /* for fifo/performance monitoring */ + unsigned int fifo_space; + + unsigned int waitfifo_sum; + unsigned int waitfifo_calls; + unsigned int fifo_waitcycles; + unsigned int idle_waitcycles; + unsigned int fifo_cache_hits; + + /* state validation */ + int v_destination2D; + int v_destination3D; + int v_color1; + int v_colorFore; + int v_alphaMode; + int v_source2D; + int v_srcColorkey; + int v_commandExtra; +} TDFXDeviceData; + +typedef struct { + volatile u8 *mmio_base; + Voodoo2D *voodoo2D; + Voodoo3D *voodoo3D; +} TDFXDriverData; + + + +static inline void tdfx_waitfifo( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + unsigned int space ) +{ + int timeout = 1000000; + + tdev->waitfifo_calls++; + tdev->waitfifo_sum += space; + + if (tdev->fifo_space < space) { + while (timeout--) { + tdev->fifo_waitcycles++; + + tdev->fifo_space = (tdrv->voodoo2D->status & 0x3f); + if (tdev->fifo_space >= space) + break; + + } + } else { + tdev->fifo_cache_hits++; + } + + tdev->fifo_space -= space; + + if (!timeout) + D_WARN( "timeout during waitfifo!" ); +} + +static inline void tdfx_waitidle( TDFXDriverData *tdrv, + TDFXDeviceData *tdev ) +{ + int i = 0; + int timeout = 1000000; + +// tdfx_waitfifo( tdrv, tdev, 1 ); + +// voodoo3D->nopCMD = 0; + + while (timeout--) { + tdev->idle_waitcycles++; + + i = (tdrv->voodoo2D->status & (0xF << 7)) ? 0 : i + 1; + if (i == 3) + return; + + } + + D_BUG( "timeout during waitidle!\n"); +} + + +static int blitFormat[] = { + 2, /* DSPF_ARGB1555 */ + 3, /* DSPF_RGB16 */ + 4, /* DSPF_RGB24 */ + 5, /* DSPF_RGB32 */ + 5, /* DSPF_ARGB */ + 0 /* DSPF_A8 */ +}; + +static inline void tdfx_validate_source2D( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + CoreSurface *source = state->source; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + if (tdev->v_source2D) + return; + + tdfx_waitfifo( tdrv, tdev, 2 ); + + voodoo2D->srcBaseAddr = state->src.offset & 0xFFFFFF; + voodoo2D->srcFormat = (state->src.pitch & 0x3FFF) | + (blitFormat[DFB_PIXELFORMAT_INDEX(source->config.format)] << 16); + + tdev->v_source2D = 1; +} + +static inline void tdfx_validate_destination2D( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + CoreSurface *destination = state->destination; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + if (tdev->v_destination2D) + return; + + tdfx_waitfifo( tdrv, tdev, 2 ); + + voodoo2D->dstBaseAddr = state->dst.offset; + voodoo2D->dstFormat = (state->dst.pitch & 0x3FFF) | + (blitFormat[DFB_PIXELFORMAT_INDEX(destination->config.format)] << 16); + + tdev->v_destination2D = 1; +} + +static inline void tdfx_validate_destination3D( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + CoreSurface *destination = state->destination; + Voodoo3D *voodoo3D = tdrv->voodoo3D; + + u32 lfbmode = TDFX_LFBMODE_PIXEL_PIPELINE_ENABLE; + u32 fbzMode = (1 << 9) | 1; + + if (tdev->v_destination3D) + return; + + switch (destination->config.format) { + case DSPF_ARGB1555: + lfbmode |= TDFX_LFBMODE_RGB555; + break; + case DSPF_RGB16: + lfbmode |= TDFX_LFBMODE_RGB565; + break; + case DSPF_RGB32: + lfbmode |= TDFX_LFBMODE_RGB0888; + break; + case DSPF_ARGB: + fbzMode |= (1 << 10); + lfbmode |= TDFX_LFBMODE_ARGB8888; + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + tdfx_waitfifo( tdrv, tdev, 4 ); + + voodoo3D->lfbMode = lfbmode; + voodoo3D->fbzMode = fbzMode; + voodoo3D->colBufferAddr = state->dst.offset; + voodoo3D->colBufferStride = state->dst.pitch; + + tdev->v_destination3D = 1; +} + +static inline void tdfx_validate_color1( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + if (tdev->v_color1) + return; + + tdfx_waitfifo( tdrv, tdev, 1 ); + + tdrv->voodoo3D->color1 = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + + tdev->v_color1 = 1; +} + +static inline void tdfx_validate_colorFore( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + if (tdev->v_colorFore) + return; + + tdfx_waitfifo( tdrv, tdev, 1 ); + + switch (state->destination->config.format) { + case DSPF_A8: + tdrv->voodoo2D->colorFore = state->color.a; + break; + case DSPF_ARGB1555: + tdrv->voodoo2D->colorFore = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB16: + tdrv->voodoo2D->colorFore = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_RGB24: + case DSPF_RGB32: + tdrv->voodoo2D->colorFore = PIXEL_RGB32( state->color.r, + state->color.g, + state->color.b ); + break; + case DSPF_ARGB: + tdrv->voodoo2D->colorFore = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + default: + D_BUG( "unexpected pixelformat!" ); + break; + } + + tdev->v_colorFore = 1; +} + +static inline void tdfx_validate_alphaMode( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + static int tdfxBlendFactor[] = { + 0, + 0x0, /* DSBF_ZERO */ + 0x4, /* DSBF_ONE */ + 0x2, /* DSBF_SRCCOLOR */ + 0x6, /* DSBF_INVSRCCOLOR */ + 0x1, /* DSBF_SRCALPHA */ + 0x5, /* DSBF_INVSRCALPHA */ + 0x3, /* DSBF_DESTALPHA */ + 0x7, /* DSBF_INVDESTALPHA */ + 0x2, /* DSBF_DESTCOLOR */ + 0x6, /* DSBF_INVDESTCOLOR */ + 0xF /* DSBF_SRCALPHASAT */ + }; + + if (tdev->v_alphaMode) + return; + + tdfx_waitfifo( tdrv, tdev, 1 ); + + tdrv->voodoo3D->alphaMode = TDFX_ALPHAMODE_BLEND_ENABLE | + (tdfxBlendFactor[state->src_blend] << 8) | + (tdfxBlendFactor[state->src_blend] << 16) | + (tdfxBlendFactor[state->dst_blend] << 12) | + (tdfxBlendFactor[state->dst_blend] << 20); + + tdev->v_alphaMode = 1; +} + +static inline void tdfx_validate_srcColorkey( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + if (tdev->v_srcColorkey) + return; + + tdfx_waitfifo( tdrv, tdev, 2 ); + + voodoo2D->srcColorkeyMin = + voodoo2D->srcColorkeyMax = state->src_colorkey; + + tdev->v_srcColorkey = 1; +} + +static inline void tdfx_validate_commandExtra( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + CardState *state ) +{ + if (tdev->v_commandExtra) + return; + + tdfx_waitfifo( tdrv, tdev, 1 ); + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + tdrv->voodoo2D->commandExtra = 1; + else + tdrv->voodoo2D->commandExtra = 0; + + tdev->v_commandExtra = 1; +} + + + +static inline void tdfx_set_clip( TDFXDriverData *tdrv, + TDFXDeviceData *tdev, + DFBRegion *clip ) +{ + Voodoo2D *voodoo2D = tdrv->voodoo2D; + Voodoo3D *voodoo3D = tdrv->voodoo3D; + + tdfx_waitfifo( tdrv, tdev, 4 ); + + voodoo2D->clip0Min = ((clip->y1 & 0xFFF) << 16) | + (clip->x1 & 0xFFF); + + voodoo2D->clip0Max = (((clip->y2+1) & 0xFFF) << 16) | + ((clip->x2+1) & 0xFFF); + + voodoo3D->clipLeftRight = ((clip->x1 & 0xFFF) << 16) | + ((clip->x2+1) & 0xFFF); + + voodoo3D->clipTopBottom = ((clip->y1 & 0xFFF) << 16) | + ((clip->y2+1) & 0xFFF); +} + + + +/* required implementations */ + +static DFBResult tdfxEngineSync( void *drv, void *dev ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + + tdfx_waitidle( tdrv, tdev ); + + return DFB_OK; +} + +#define TDFX_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define TDFX_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWLINE | DFXL_FILLTRIANGLE) + +#define TDFX_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_SRC_COLORKEY) + +#define TDFX_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) + + +static void tdfxCheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + /* check for the special drawing function that does not support + the usually supported drawingflags */ + if (accel == DFXL_DRAWLINE && state->drawingflags != DSDRAW_NOFX) + return; + + /* if there are no other drawing flags than the supported */ + if (!(state->drawingflags & ~TDFX_SUPPORTED_DRAWINGFLAGS)) + state->accel |= TDFX_SUPPORTED_DRAWINGFUNCTIONS; + + /* if there are no other blitting flags than the supported + and the source and destination formats are the same */ + if (!(state->blittingflags & ~TDFX_SUPPORTED_BLITTINGFLAGS) && + state->source && state->source->config.format != DSPF_RGB24) + state->accel |= TDFX_SUPPORTED_BLITTINGFUNCTIONS; +} + +static void tdfxSetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + + if (state->mod_hw & SMF_DESTINATION) + tdev->v_destination2D = tdev->v_destination3D = tdev->v_colorFore = 0; + + if (state->mod_hw & SMF_SOURCE) + tdev->v_source2D = 0; + + if (state->mod_hw & (SMF_DST_BLEND | SMF_SRC_BLEND)) + tdev->v_alphaMode = 0; + + if (state->mod_hw & SMF_COLOR) + tdev->v_color1 = tdev->v_colorFore = 0; + + if (state->mod_hw & SMF_SRC_COLORKEY) + tdev->v_srcColorkey = 0; + + if (state->mod_hw & SMF_BLITTING_FLAGS) + tdev->v_commandExtra = 0; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_DRAWLINE: + case DFXL_FILLTRIANGLE: + if (state->drawingflags & DSDRAW_BLEND) { + tdfx_validate_color1( tdrv, tdev, state ); + tdfx_validate_alphaMode( tdrv, tdev, state ); + tdfx_validate_destination3D( tdrv, tdev, state ); + + funcs->FillRectangle = tdfxFillRectangle3D; + funcs->FillTriangle = tdfxFillTriangle3D; + } else { + tdfx_validate_colorFore( tdrv, tdev, state ); + tdfx_validate_destination2D( tdrv, tdev, state ); + + funcs->FillRectangle = tdfxFillRectangle2D; + funcs->FillTriangle = tdfxFillTriangle2D; + } + + state->set |= DFXL_FILLRECTANGLE | DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + if (state->blittingflags & DSBLIT_SRC_COLORKEY) + tdfx_validate_srcColorkey( tdrv, tdev, state ); + + tdfx_validate_commandExtra( tdrv, tdev, state ); + tdfx_validate_source2D( tdrv, tdev, state ); + tdfx_validate_destination2D( tdrv, tdev, state ); + + state->set |= DFXL_BLIT | DFXL_STRETCHBLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + if (state->mod_hw & SMF_CLIP) + tdfx_set_clip( tdrv, tdev, &state->clip ); + + state->mod_hw = 0; +} + +static bool tdfxFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + tdfx_waitfifo( tdrv, tdev, 3 ); + + voodoo2D->dstXY = ((rect->y & 0x1FFF) << 16) | (rect->x & 0x1FFF); + voodoo2D->dstSize = ((rect->h & 0x1FFF) << 16) | (rect->w & 0x1FFF); + + voodoo2D->command = 5 | (1 << 8) | (0xCC << 24); + + return true; +} + +static bool tdfxFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo3D *voodoo3D = tdrv->voodoo3D; + + tdfx_waitfifo( tdrv, tdev, 10 ); + + voodoo3D->vertexAx = S12_4(rect->x); + voodoo3D->vertexAy = S12_4(rect->y); + + voodoo3D->vertexBx = S12_4(rect->x); + voodoo3D->vertexBy = S12_4(rect->y + rect->h); + + voodoo3D->vertexCx = S12_4(rect->x + rect->w); + voodoo3D->vertexCy = S12_4(rect->y + rect->h); + + voodoo3D->triangleCMD = (1 << 31); + + + voodoo3D->vertexBx = S12_4(rect->x + rect->w); + voodoo3D->vertexBy = S12_4(rect->y); + + voodoo3D->triangleCMD = 0; + + return true; +} + +static bool tdfxDrawRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + return false; +} + +static bool tdfxDrawLine2D( void *drv, void *dev, DFBRegion *line ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + tdfx_waitfifo( tdrv, tdev, 5 ); + + voodoo2D->srcXY = ((line->y1 & 0x1FFF) << 16) | (line->x1 & 0x1FFF); + voodoo2D->dstXY = ((line->y2 & 0x1FFF) << 16) | (line->x2 & 0x1FFF); + voodoo2D->command = 6 | (1 << 8) | (0xCC << 24); + + return true; +} + +/*static bool tdfxDrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + int xl, xr, yb, yt; + + if (line->x1 < line->x2) { + xl = -8; + xr = 8; + } + else { + xl = 8; + xr = -8; + } + + if (line->y1 < line->y2) { + yt = -8; + yb = 8; + } + else { + yt = 8; + yb = -8; + } + + tdfx_waitfifo( 10 ); + + voodoo3D->vertexAx = S12_4_( line->x1, xl ); + voodoo3D->vertexAy = S12_4_( line->y1, yt ); + + voodoo3D->vertexBx = S12_4_( line->x2, xl ); + voodoo3D->vertexBy = S12_4_( line->y2, yb ); + + voodoo3D->vertexCx = S12_4_( line->x2, xr ); + voodoo3D->vertexCy = S12_4_( line->y2, yb ); + + voodoo3D->triangleCMD = (1 << 31); + + + voodoo3D->vertexBx = S12_4_( line->x1, xr ); + voodoo3D->vertexBy = S12_4_( line->y1, yt ); + + voodoo3D->triangleCMD = 0; + + return true; +}*/ + +static bool tdfxFillTriangle2D( void *drv, void *dev, DFBTriangle *tri ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + tdfx_waitfifo( tdrv, tdev, 7 ); + + dfb_sort_triangle( tri ); + + voodoo2D->srcXY = ((tri->y1 & 0x1FFF) << 16) | (tri->x1 & 0x1FFF); + voodoo2D->command = 8 | (1 << 8) | (0xCC << 24); + + if (tri->x2 < tri->x3) { + voodoo2D->launchArea[0] = ((tri->y2 & 0x1FFF) << 16) | (tri->x2 & 0x1FFF); + voodoo2D->launchArea[1] = ((tri->y3 & 0x1FFF) << 16) | (tri->x3 & 0x1FFF); + voodoo2D->launchArea[2] = ((tri->y2 & 0x1FFF) << 16) | (tri->x2 & 0x1FFF); + + } else { + voodoo2D->launchArea[0] = ((tri->y3 & 0x1FFF) << 16) | (tri->x3 & 0x1FFF); + voodoo2D->launchArea[1] = ((tri->y2 & 0x1FFF) << 16) | (tri->x2 & 0x1FFF); + voodoo2D->launchArea[2] = ((tri->y3 & 0x1FFF) << 16) | (tri->x3 & 0x1FFF); + + } + + return true; +} + +static bool tdfxFillTriangle3D( void *drv, void *dev, DFBTriangle *tri ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo3D *voodoo3D = tdrv->voodoo3D; + + tdfx_waitfifo( tdrv, tdev, 7 ); + + dfb_sort_triangle( tri ); + + voodoo3D->vertexAx = S12_4(tri->x1); + voodoo3D->vertexAy = S12_4(tri->y1); + + voodoo3D->vertexBx = S12_4(tri->x2); + voodoo3D->vertexBy = S12_4(tri->y2); + + voodoo3D->vertexCx = S12_4(tri->x3); + voodoo3D->vertexCy = S12_4(tri->y3); + + voodoo3D->triangleCMD = (1 << 31); + + voodoo3D->triangleCMD = 0; + + return true; +} + +static bool tdfxBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + u32 cmd = 1 | (1 <<8) | (0xCC << 24);//SST_2D_GO | SST_2D_SCRNTOSCRNBLIT | (ROP_COPY << 24); + + if (rect->x <= dx) { + cmd |= (1 << 14);//SST_2D_X_RIGHT_TO_LEFT; + rect->x += rect->w-1; + dx += rect->w-1; + } + if (rect->y <= dy) { + cmd |= (1 << 15);//SST_2D_Y_BOTTOM_TO_TOP; + rect->y += rect->h-1; + dy += rect->h-1; + } + + + tdfx_waitfifo( tdrv, tdev, 4 ); + + voodoo2D->srcXY = ((rect->y & 0x1FFF) << 16) | (rect->x & 0x1FFF); + voodoo2D->dstXY = ((dy & 0x1FFF) << 16) | (dx & 0x1FFF); + voodoo2D->dstSize = ((rect->h & 0x1FFF) << 16) | (rect->w & 0x1FFF); + + voodoo2D->command = cmd; + + return true; +} + +static bool tdfxStretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) drv; + TDFXDeviceData *tdev = (TDFXDeviceData*) dev; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + + tdfx_waitfifo( tdrv, tdev, 5 ); + + voodoo2D->srcXY = ((sr->y & 0x1FFF) << 16) | (sr->x & 0x1FFF); + voodoo2D->srcSize = ((sr->h & 0x1FFF) << 16) | (sr->w & 0x1FFF); + + voodoo2D->dstXY = ((dr->y & 0x1FFF) << 16) | (dr->x & 0x1FFF); + voodoo2D->dstSize = ((dr->h & 0x1FFF) << 16) | (dr->w & 0x1FFF); + + voodoo2D->command = 2 | (1 << 8) | (0xCC << 24); + + return true; +} + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_3DFX_BANSHEE: /* Banshee/Voodoo3 */ + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "3Dfx Voodoo 3/4/5/Banshee Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + info->version.major = 0; + info->version.minor = 1; + + info->driver_data_size = sizeof (TDFXDriverData); + info->device_data_size = sizeof (TDFXDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) driver_data; + + tdrv->mmio_base = (volatile u8*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!tdrv->mmio_base) + return DFB_IO; + + tdrv->voodoo2D = (Voodoo2D*)(tdrv->mmio_base + 0x100000); + tdrv->voodoo3D = (Voodoo3D*)(tdrv->mmio_base + 0x200000); + + funcs->CheckState = tdfxCheckState; + funcs->SetState = tdfxSetState; + funcs->EngineSync = tdfxEngineSync; + + funcs->DrawRectangle = tdfxDrawRectangle; + funcs->DrawLine = tdfxDrawLine2D; + funcs->Blit = tdfxBlit; + funcs->StretchBlit = tdfxStretchBlit; + + return DFB_OK; +} + + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) driver_data; + TDFXDeviceData *tdev = (TDFXDeviceData*) device_data; + Voodoo2D *voodoo2D = tdrv->voodoo2D; + Voodoo3D *voodoo3D = tdrv->voodoo3D; + + /* fill device info */ + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "Voodoo 3/4/5/Banshee" ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "3Dfx" ); + + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = TDFX_SUPPORTED_DRAWINGFUNCTIONS | + TDFX_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = TDFX_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = TDFX_SUPPORTED_BLITTINGFLAGS; + + device_info->limits.surface_byteoffset_alignment = 32 * 4; + device_info->limits.surface_pixelpitch_alignment = 32; + + + /* initialize card */ + voodoo2D->status = 0; + voodoo3D->nopCMD = 3; + + tdfx_waitfifo( tdrv, tdev, 6 ); + + voodoo3D->clipLeftRight1 = 0; + voodoo3D->clipTopBottom1 = 0; + + voodoo3D->fbzColorPath = TDFX_FBZCOLORPATH_RGBSELECT_COLOR1 | + TDFX_FBZCOLORPATH_ASELECT_COLOR1; + + voodoo3D->textureMode = 0; + + voodoo2D->commandExtra = 0; + voodoo2D->rop = 0xAAAAAA; + + tdfx_waitfifo( tdrv, tdev, 1 ); /* VOODOO !!! */ + + *((volatile u32*)((volatile u8*) tdrv->mmio_base + 0x10c)) = + 1 << 4 | 1 << 8 | 5 << 12 | 1 << 18 | 5 << 24; + + dfb_config->pollvsync_after = 1; + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + TDFXDeviceData *tdev = (TDFXDeviceData*) device_data; + TDFXDriverData *tdrv = (TDFXDriverData*) driver_data; + + (void) tdev; + (void) tdrv; + + D_DEBUG( "DirectFB/TDFX: FIFO Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/TDFX: %9d tdfx_waitfifo calls\n", + tdev->waitfifo_calls ); + D_DEBUG( "DirectFB/TDFX: %9d register writes (tdfx_waitfifo sum)\n", + tdev->waitfifo_sum ); + D_DEBUG( "DirectFB/TDFX: %9d FIFO wait cycles (depends on CPU)\n", + tdev->fifo_waitcycles ); + D_DEBUG( "DirectFB/TDFX: %9d IDLE wait cycles (depends on CPU)\n", + tdev->idle_waitcycles ); + D_DEBUG( "DirectFB/TDFX: %9d FIFO space cache hits(depends on CPU)\n", + tdev->fifo_cache_hits ); + D_DEBUG( "DirectFB/TDFX: Conclusion:\n" ); + D_DEBUG( "DirectFB/TDFX: Average register writes/tdfx_waitfifo" + "call:%.2f\n", + tdev->waitfifo_sum/(float)(tdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/TDFX: Average wait cycles/tdfx_waitfifo call:" + " %.2f\n", + tdev->fifo_waitcycles/(float)(tdev->waitfifo_calls) ); + D_DEBUG( "DirectFB/TDFX: Average fifo space cache hits: %02d%%\n", + (int)(100 * tdev->fifo_cache_hits/ + (float)(tdev->waitfifo_calls)) ); + + D_DEBUG( "DirectFB/TDFX: Pixels Out: %d\n", tdrv->voodoo3D->fbiPixelsOut ); + D_DEBUG( "DirectFB/TDFX: Triangles Out: %d\n", tdrv->voodoo3D->fbiTrianglesOut ); +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + TDFXDriverData *tdrv = (TDFXDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, tdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/tdfx/tdfx.h b/Source/DirectFB/gfxdrivers/tdfx/tdfx.h new file mode 100755 index 0000000..04a9449 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/tdfx/tdfx.h @@ -0,0 +1,250 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __TDFX_H__ +#define __TDFX_H__ + +#include + + +#define S12_4(val) (((u32)((s32)((val) << 4))) & 0xffff) +#define S12_4_(a,b) (((u32)((s32)(((a) << 4) + (b)))) & 0xffff) + + +#define TDFX_LFBMODE_RGB565 0 +#define TDFX_LFBMODE_RGB555 1 +#define TDFX_LFBMODE_RGB0888 4 +#define TDFX_LFBMODE_ARGB8888 5 +#define TDFX_LFBMODE_PIXEL_PIPELINE_ENABLE (1 << 8) + +#define TDFX_CLIP_ENABLE (1 << 31) + + +#define TDFX_ALPHAMODE_BLEND_ENABLE (1 << 4) + +#define TDFX_FBZCOLORPATH_RGBSELECT_COLOR1 2 +#define TDFX_FBZCOLORPATH_ASELECT_COLOR1 (2 << 2) + +typedef volatile struct { + u32 status; + u32 intrCtrl; + + u32 vertexAx; + u32 vertexAy; + u32 vertexBx; + u32 vertexBy; + u32 vertexCx; + u32 vertexCy; + + s32 startR; + s32 startG; + s32 startB; + s32 startZ; + s32 startA; + s32 startS; + s32 startT; + s32 startW; + + s32 dRdX; + s32 dGdX; + s32 dBdX; + s32 dZdX; + s32 dAdX; + s32 dSdX; + s32 dTdX; + s32 dWdX; + + s32 dRdY; + s32 dGdY; + s32 dBdY; + s32 dZdY; + s32 dAdY; + s32 dSdY; + s32 dTdY; + s32 dWdY; + + u32 triangleCMD; + u32 reserved0; + + float fvertexAx; + float fvertexAy; + float fvertexBx; + float fvertexBy; + float fvertexCx; + float fvertexCy; + + float fstartR; + float fstartG; + float fstartB; + float fstartZ; + float fstartA; + float fstartS; + float fstartT; + float fstartW; + + float fdRdX; + float fdGdX; + float fdBdX; + float fdZdX; + float fdAdX; + float fdSdX; + float fdTdX; + float fdWdX; + + float fdRdY; + float fdGdY; + float fdBdY; + float fdZdY; + float fdAdY; + float fdSdY; + float fdTdY; + float fdWdY; + + u32 ftriangleCMD; + u32 fbzColorPath; + u32 fogMode; + u32 alphaMode; + u32 fbzMode; + u32 lfbMode; + u32 clipLeftRight; + u32 clipTopBottom; + + u32 nopCMD; + u32 fastfillCMD; + u32 swapbufferCMD; + u32 fogColor; + u32 zaColor; + u32 chromaKey; + u32 chromaRange; + u32 userIntrCMD; + u32 stipple; + u32 color0; + u32 color1; + + u32 fbiPixelsIn; + u32 fbiChromaFail; + u32 fbiZfuncFail; + u32 fbiAfuncFail; + u32 fbiPixelsOut; + + u32 fogTable[32]; + + u32 reserved1[3]; + + u32 colBufferAddr; + u32 colBufferStride; + u32 auxBufferAddr; + u32 auxBufferStride; + + u32 reserved2; + + u32 clipLeftRight1; + u32 clipTopBottom1; + + u32 reserved3[17]; + u32 swapPending; + u32 leftOverlayBuf; + u32 rightOverlayBuf; + u32 fbiSwapHistory; + u32 fbiTrianglesOut; + u32 sSetupMode; + float sVx; + float sVy; + u32 sARGB; + float sRed; + float sGreen; + float sBlue; + float sAlpha; + float sVz; + float sWb; + float sWtmu0; + float sS_W0; + float sT_W0; + float sWtmu1; + float sS_Wtmu1; + float sT_Wtmu1; + u32 sDrawTriCMD; + u32 sBeginTriCMD; + + u32 reserved[22]; + u32 textureMode; + u32 tLOD; + u32 tDetail; + u32 texBaseAddr; + u32 texBaseAddr1; + u32 texBaseAddr2; + u32 texBaseAddr3_8; + u32 texStride; + u32 trexInit1; + + u32 nccTable0[12]; + u32 nccTable1[12]; + + u32 reserved4[31]; +} Voodoo3D; + + +typedef volatile struct { + u32 status; + u32 intCtrl; + u32 clip0Min; + u32 clip0Max; + u32 dstBaseAddr; + u32 dstFormat; + u32 srcColorkeyMin; + u32 srcColorkeyMax; + u32 dstColorkeyMin; + u32 dstColorkeyMax; + u32 bresError0; + u32 bresError1; + u32 rop; + u32 srcBaseAddr; + u32 commandExtra; + u32 lineStipple; + u32 lineStyle; + u32 pattern0Alias; + u32 pattern1Alias; + u32 clip1Min; + u32 clip1Max; + u32 srcFormat; + u32 srcSize; + u32 srcXY; + u32 colorBack; + u32 colorFore; + u32 dstSize; + u32 dstXY; + u32 command; + + u32 reserved[3]; + + u32 launchArea[32]; + + u32 colorPattern[64]; +} Voodoo2D; + +#endif diff --git a/Source/DirectFB/gfxdrivers/unichrome/Makefile.am b/Source/DirectFB/gfxdrivers/unichrome/Makefile.am new file mode 100755 index 0000000..3d4c3f9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/Makefile.am @@ -0,0 +1,50 @@ +## Makefile.am for DirectFB/gfxdrivers/unichrome + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +AM_CFLAGS = $(DFB_CFLAGS) + +unichrome_LTLIBRARIES = libdirectfb_unichrome.la + +if BUILD_STATIC +unichrome_DATA = $(unichrome_LTLIBRARIES:.la=.o) +endif + +unichromedir = $(MODULEDIR)/gfxdrivers + +libdirectfb_unichrome_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_probe.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + uc_spic.c \ + uc_ioctl.h \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_unichrome_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_unichrome_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la \ + -lm + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/unichrome/Makefile.in b/Source/DirectFB/gfxdrivers/unichrome/Makefile.in new file mode 100755 index 0000000..81e7126 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/Makefile.in @@ -0,0 +1,626 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/unichrome +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(unichromedir)" \ + "$(DESTDIR)$(unichromedir)" +unichromeLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(unichrome_LTLIBRARIES) +libdirectfb_unichrome_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_unichrome_la_OBJECTS = unichrome.lo uc_accel.lo \ + uc_hwset.lo uc_hwmap.lo uc_state.lo uc_fifo.lo uc_overlay.lo \ + uc_ovl_hwmap.lo uc_ovl_hwset.lo uc_primary.lo uc_spic.lo +libdirectfb_unichrome_la_OBJECTS = \ + $(am_libdirectfb_unichrome_la_OBJECTS) +libdirectfb_unichrome_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_unichrome_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_unichrome_la_SOURCES) +DIST_SOURCES = $(libdirectfb_unichrome_la_SOURCES) +unichromeDATA_INSTALL = $(INSTALL_DATA) +DATA = $(unichrome_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +AM_CFLAGS = $(DFB_CFLAGS) +unichrome_LTLIBRARIES = libdirectfb_unichrome.la +@BUILD_STATIC_TRUE@unichrome_DATA = $(unichrome_LTLIBRARIES:.la=.o) +unichromedir = $(MODULEDIR)/gfxdrivers +libdirectfb_unichrome_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_probe.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + uc_spic.c \ + uc_ioctl.h \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_unichrome_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_unichrome_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la \ + -lm + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu gfxdrivers/unichrome/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu gfxdrivers/unichrome/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-unichromeLTLIBRARIES: $(unichrome_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(unichromedir)" || $(MKDIR_P) "$(DESTDIR)$(unichromedir)" + @list='$(unichrome_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(unichromeLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(unichromedir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(unichromeLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(unichromedir)/$$f"; \ + else :; fi; \ + done + +uninstall-unichromeLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(unichrome_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(unichromedir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(unichromedir)/$$p"; \ + done + +clean-unichromeLTLIBRARIES: + -test -z "$(unichrome_LTLIBRARIES)" || rm -f $(unichrome_LTLIBRARIES) + @list='$(unichrome_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libdirectfb_unichrome.la: $(libdirectfb_unichrome_la_OBJECTS) $(libdirectfb_unichrome_la_DEPENDENCIES) + $(libdirectfb_unichrome_la_LINK) -rpath $(unichromedir) $(libdirectfb_unichrome_la_OBJECTS) $(libdirectfb_unichrome_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_accel.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_fifo.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_hwmap.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_hwset.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_overlay.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_ovl_hwmap.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_ovl_hwset.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_primary.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_spic.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_state.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unichrome.Plo@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< +@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ 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then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/unichrome/mmio.h b/Source/DirectFB/gfxdrivers/unichrome/mmio.h new file mode 100755 index 0000000..757445a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/mmio.h @@ -0,0 +1,43 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef _VIA_MMIO_H +#define _VIA_MMIO_H + +#define TRACE_ENTER() printf("Entering %s\n", __PRETTY_FUNCTION__) +#define TRACE_LEAVE() printf("Leaving %s\n", __PRETTY_FUNCTION__) + +#ifdef KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + + +#else // !KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) + +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + +#endif // KERNEL + +#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) +#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) + +#define MAXLOOP 0xffffff + +#endif /* _VIA_MMIO_H */ diff --git a/Source/DirectFB/gfxdrivers/unichrome/regs2d.h b/Source/DirectFB/gfxdrivers/unichrome/regs2d.h new file mode 100755 index 0000000..9accbf7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/regs2d.h @@ -0,0 +1,197 @@ +// Note: This is a modified version of via_regs.h from the XFree86 CVS tree. + +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_2D_H__ +#define __VIA_REGS_2D_H__ + +/* Selected 2D engine raster operations. + * See xc/programs/Xserver/hw/xfree86/xaa/xaarop.h + * in the XFree86 project for the full list. + */ +#define VIA_ROP_DPx (0x5A << 24) +#define VIA_ROP_DSx (0x66 << 24) +#define VIA_ROP_S (0xCC << 24) +#define VIA_ROP_P (0xF0 << 24) + +/* My own reverse-engineered bit definitions */ + +// Use the following definitions with VIA_KEY_CONTROL + +/// When set, red channel is not drawn +#define VIA_KEY_MASK_RED 0x40000000 +/// When set, green channel is not drawn +#define VIA_KEY_MASK_GREEN 0x20000000 +/// When set, blue channel is not drawn +#define VIA_KEY_MASK_BLUE 0x10000000 + +/** When set, destination keying is enabled. + * Caveat: VIA's destination key is the opposite of DirectFB's: + * It draws where there is no match in the destination surface. + */ +#define VIA_KEY_ENABLE_DSTKEY 0x8000 +/** When set, source keying is enabled + * It draws the pixels in the source that do not match the color key. + */ +#define VIA_KEY_ENABLE_SRCKEY 0x4000 +/** Inverts the behaviour of the color keys: + * Dst key: draw where the destination matches the key + * Src key: draw where the source matches the key + * Problem: Since this bit affects both keys, you can not do + * combined source and destination keying with DirectFB. + * The inverted source key is all but useless since it will + * only draw the source pixels that match the key! + * It must be a design error... + */ +#define VIA_KEY_INVERT_KEY 0x2000 + +/* 2D engine registers and bit definitions */ + +#define VIA_MMIO_REGSIZE 0x9000 +#define VIA_MMIO_REGBASE 0x0 +#define VIA_MMIO_VGABASE 0x8000 +#define VIA_MMIO_BLTBASE 0x200000 +#define VIA_MMIO_BLTSIZE 0x10000 + +#define VIA_VQ_SIZE (256*1024) + +/* defines for VIA 2D registers */ +#define VIA_REG_GECMD 0x000 +#define VIA_REG_GEMODE 0x004 +#define VIA_REG_GESTATUS 0x004 /* as same as VIA_REG_GEMODE */ +#define VIA_REG_SRCPOS 0x008 +#define VIA_REG_DSTPOS 0x00C +#define VIA_REG_LINE_K1K2 0x008 +#define VIA_REG_LINE_XY 0x00C +#define VIA_REG_DIMENSION 0x010 /* width and height */ +#define VIA_REG_PATADDR 0x014 +#define VIA_REG_FGCOLOR 0x018 +#define VIA_REG_DSTCOLORKEY 0x018 /* as same as VIA_REG_FG */ +#define VIA_REG_BGCOLOR 0x01C +#define VIA_REG_SRCCOLORKEY 0x01C /* as same as VIA_REG_BG */ +#define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ +#define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ +#define VIA_REG_OFFSET 0x028 +#define VIA_REG_LINE_ERROR 0x028 +#define VIA_REG_KEYCONTROL 0x02C /* color key control */ +#define VIA_REG_SRCBASE 0x030 +#define VIA_REG_DSTBASE 0x034 +#define VIA_REG_PITCH 0x038 /* pitch of src and dst */ +#define VIA_REG_MONOPAT0 0x03C +#define VIA_REG_MONOPAT1 0x040 +#define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ + + +/* defines for VIA video registers */ +#define VIA_REG_INTERRUPT 0x200 +#define VIA_REG_CRTCSTART 0x214 + + +/* defines for VIA HW cursor registers */ +#define VIA_REG_CURSOR_MODE 0x2D0 +#define VIA_REG_CURSOR_POS 0x2D4 +#define VIA_REG_CURSOR_ORG 0x2D8 +#define VIA_REG_CURSOR_BG 0x2DC +#define VIA_REG_CURSOR_FG 0x2E0 + + +/* defines for VIA 3D registers */ +#define VIA_REG_STATUS 0x400 +#define VIA_REG_TRANSET 0x43C +#define VIA_REG_TRANSPACE 0x440 + +/* VIA_REG_STATUS(0x400): Engine Status */ +#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ + + +/* VIA_REG_GECMD(0x00): 2D Engine Command */ +#define VIA_GEC_NOOP 0x00000000 +#define VIA_GEC_BLT 0x00000001 +#define VIA_GEC_LINE 0x00000005 + +#define VIA_GEC_SRC_XY 0x00000000 +#define VIA_GEC_SRC_LINEAR 0x00000010 +#define VIA_GEC_DST_XY 0x00000000 +#define VIA_GEC_DST_LINRAT 0x00000020 + +#define VIA_GEC_SRC_FB 0x00000000 +#define VIA_GEC_SRC_SYS 0x00000040 +#define VIA_GEC_DST_FB 0x00000000 +#define VIA_GEC_DST_SYS 0x00000080 + +#define VIA_GEC_SRC_MONO 0x00000100 /* source is mono */ +#define VIA_GEC_PAT_MONO 0x00000200 /* pattern is mono */ + +#define VIA_GEC_MSRC_OPAQUE 0x00000000 /* mono src is opaque */ +#define VIA_GEC_MSRC_TRANS 0x00000400 /* mono src is transparent */ + +#define VIA_GEC_PAT_FB 0x00000000 /* pattern is in frame buffer */ +#define VIA_GEC_PAT_REG 0x00000800 /* pattern is from reg setting */ + +#define VIA_GEC_CLIP_DISABLE 0x00000000 +#define VIA_GEC_CLIP_ENABLE 0x00001000 + +#define VIA_GEC_FIXCOLOR_PAT 0x00002000 + +#define VIA_GEC_INCX 0x00000000 +#define VIA_GEC_DECY 0x00004000 +#define VIA_GEC_INCY 0x00000000 +#define VIA_GEC_DECX 0x00008000 + +#define VIA_GEC_MPAT_OPAQUE 0x00000000 /* mono pattern is opaque */ +#define VIA_GEC_MPAT_TRANS 0x00010000 /* mono pattern is transparent */ + +#define VIA_GEC_MONO_UNPACK 0x00000000 +#define VIA_GEC_MONO_PACK 0x00020000 +#define VIA_GEC_MONO_DWORD 0x00000000 +#define VIA_GEC_MONO_WORD 0x00040000 +#define VIA_GEC_MONO_BYTE 0x00080000 + +#define VIA_GEC_LASTPIXEL_ON 0x00000000 +#define VIA_GEC_LASTPIXEL_OFF 0x00100000 +#define VIA_GEC_X_MAJOR 0x00000000 +#define VIA_GEC_Y_MAJOR 0x00200000 +#define VIA_GEC_QUICK_START 0x00800000 + + +/* VIA_REG_GEMODE(0x04): GE mode */ +#define VIA_GEM_8bpp 0x00000000 +#define VIA_GEM_16bpp 0x00000100 +#define VIA_GEM_32bpp 0x00000300 + +#define VIA_GEM_640 0x00000000 /* 640*480 */ +#define VIA_GEM_800 0x00000400 /* 800*600 */ +#define VIA_GEM_1024 0x00000800 /* 1024*768 */ +#define VIA_GEM_1280 0x00000C00 /* 1280*1024 */ +#define VIA_GEM_1600 0x00001000 /* 1600*1200 */ +#define VIA_GEM_2048 0x00001400 /* 2048*1536 */ + +/* VIA_REG_PITCH(0x38): Pitch Setting */ +#define VIA_PITCH_ENABLE 0x80000000 + +#endif // __VIA_REGS_2D_H__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/regs3d.h b/Source/DirectFB/gfxdrivers/unichrome/regs3d.h new file mode 100755 index 0000000..6243297 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/regs3d.h @@ -0,0 +1,1642 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_3D_H__ +#define __VIA_REGS_3D_H__ + +#define HC_REG_BASE 0x0400 + +#define HC_ParaN_MASK 0xffffffff +#define HC_Para_MASK 0x00ffffff +#define HC_SubA_MASK 0xff000000 +#define HC_SubA_SHIFT 24 +/* Transmission Setting + */ +#define HC_REG_TRANS_SET 0x003c +#define HC_ParaSubType_MASK 0xff000000 +#define HC_ParaType_MASK 0x00ff0000 +#define HC_ParaOS_MASK 0x0000ff00 +#define HC_ParaAdr_MASK 0x000000ff +#define HC_ParaSubType_SHIFT 24 +#define HC_ParaType_SHIFT 16 +#define HC_ParaOS_SHIFT 8 +#define HC_ParaAdr_SHIFT 0 + +#define HC_ParaType_CmdVdata 0x0000 +#define HC_ParaType_NotTex 0x0001 +#define HC_ParaType_Tex 0x0002 +#define HC_ParaType_Palette 0x0003 +#define HC_ParaType_PreCR 0x0010 +#define HC_ParaType_Auto 0x00fe + +/* Transmission Space + */ +#define HC_REG_Hpara0 0x0040 +#define HC_REG_HpataAF 0x02fc + +/* Read + */ +#define HC_REG_HREngSt 0x0000 +#define HC_REG_HRFIFOempty 0x0004 +#define HC_REG_HRFIFOfull 0x0008 +#define HC_REG_HRErr 0x000c +#define HC_REG_FIFOstatus 0x0010 +/* HC_REG_HREngSt 0x0000 + */ +#define HC_HDASZC_MASK 0x00010000 +#define HC_HSGEMI_MASK 0x0000f000 +#define HC_HLGEMISt_MASK 0x00000f00 +#define HC_HCRSt_MASK 0x00000080 +#define HC_HSE0St_MASK 0x00000040 +#define HC_HSE1St_MASK 0x00000020 +#define HC_HPESt_MASK 0x00000010 +#define HC_HXESt_MASK 0x00000008 +#define HC_HBESt_MASK 0x00000004 +#define HC_HE2St_MASK 0x00000002 +#define HC_HE3St_MASK 0x00000001 +/* HC_REG_HRFIFOempty 0x0004 + */ +#define HC_HRZDempty_MASK 0x00000010 +#define HC_HRTXAempty_MASK 0x00000008 +#define HC_HRTXDempty_MASK 0x00000004 +#define HC_HWZDempty_MASK 0x00000002 +#define HC_HWCDempty_MASK 0x00000001 +/* HC_REG_HRFIFOfull 0x0008 + */ +#define HC_HRZDfull_MASK 0x00000010 +#define HC_HRTXAfull_MASK 0x00000008 +#define HC_HRTXDfull_MASK 0x00000004 +#define HC_HWZDfull_MASK 0x00000002 +#define HC_HWCDfull_MASK 0x00000001 +/* HC_REG_HRErr 0x000c + */ +#define HC_HAGPCMErr_MASK 0x80000000 +#define HC_HAGPCMErrC_MASK 0x70000000 +/* HC_REG_FIFOstatus 0x0010 + */ +#define HC_HRFIFOATall_MASK 0x80000000 +#define HC_HRFIFOATbusy_MASK 0x40000000 +#define HC_HRATFGMDo_MASK 0x00000100 +#define HC_HRATFGMDi_MASK 0x00000080 +#define HC_HRATFRZD_MASK 0x00000040 +#define HC_HRATFRTXA_MASK 0x00000020 +#define HC_HRATFRTXD_MASK 0x00000010 +#define HC_HRATFWZD_MASK 0x00000008 +#define HC_HRATFWCD_MASK 0x00000004 +#define HC_HRATTXTAG_MASK 0x00000002 +#define HC_HRATTXCH_MASK 0x00000001 + +/* AGP Command Setting + */ +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +/* HC_SubA_HAGPCMNT 0x0062 + */ +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +/* HC_SubA_HAGPBpL 0x0063 + */ +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +/* HC_SubA_HAGPBpH 0x0064 + */ +#define HC_HAGPBpH_MASK 0x00ffffff + +/* Miscellaneous Settings + */ +#define HC_SubA_HClipTB 0x0070 +#define HC_SubA_HClipLR 0x0071 +#define HC_SubA_HFPClipTL 0x0072 +#define HC_SubA_HFPClipBL 0x0073 +#define HC_SubA_HFPClipLL 0x0074 +#define HC_SubA_HFPClipRL 0x0075 +#define HC_SubA_HFPClipTBH 0x0076 +#define HC_SubA_HFPClipLRH 0x0077 +#define HC_SubA_HLP 0x0078 +#define HC_SubA_HLPRF 0x0079 +#define HC_SubA_HSolidCL 0x007a +#define HC_SubA_HPixGC 0x007b +#define HC_SubA_HSPXYOS 0x007c +#define HC_SubA_HVertexCNT 0x007d + +#define HC_HClipT_MASK 0x00fff000 +#define HC_HClipT_SHIFT 12 +#define HC_HClipB_MASK 0x00000fff +#define HC_HClipB_SHIFT 0 +#define HC_HClipL_MASK 0x00fff000 +#define HC_HClipL_SHIFT 12 +#define HC_HClipR_MASK 0x00000fff +#define HC_HClipR_SHIFT 0 +#define HC_HFPClipBH_MASK 0x0000ff00 +#define HC_HFPClipBH_SHIFT 8 +#define HC_HFPClipTH_MASK 0x000000ff +#define HC_HFPClipTH_SHIFT 0 +#define HC_HFPClipRH_MASK 0x0000ff00 +#define HC_HFPClipRH_SHIFT 8 +#define HC_HFPClipLH_MASK 0x000000ff +#define HC_HFPClipLH_SHIFT 0 +#define HC_HSolidCH_MASK 0x000000ff +#define HC_HPixGC_MASK 0x00800000 +#define HC_HSPXOS_MASK 0x00fff000 +#define HC_HSPXOS_SHIFT 12 +#define HC_HSPYOS_MASK 0x00000fff + +/* Command + * Command A + */ +#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000*/ +#define HC_HE3Fire_MASK 0x00100000 +#define HC_HPMType_MASK 0x000f0000 +#define HC_HEFlag_MASK 0x0000e000 +#define HC_HShading_MASK 0x00001c00 +#define HC_HPMValidN_MASK 0x00000200 +#define HC_HPLEND_MASK 0x00000100 +#define HC_HVCycle_MASK 0x000000ff +#define HC_HVCycle_Style_MASK 0x000000c0 +#define HC_HVCycle_ChgA_MASK 0x00000030 +#define HC_HVCycle_ChgB_MASK 0x0000000c +#define HC_HVCycle_ChgC_MASK 0x00000003 +#define HC_HPMType_Point 0x00000000 +#define HC_HPMType_Line 0x00010000 +#define HC_HPMType_Tri 0x00020000 +#define HC_HPMType_TriWF 0x00040000 +#define HC_HEFlag_NoAA 0x00000000 +#define HC_HEFlag_ab 0x00008000 +#define HC_HEFlag_bc 0x00004000 +#define HC_HEFlag_ca 0x00002000 +#define HC_HShading_Solid 0x00000000 +#define HC_HShading_FlatA 0x00000400 +#define HC_HShading_FlatB 0x00000800 +#define HC_HShading_FlatC 0x00000c00 +#define HC_HShading_Gouraud 0x00001000 +#define HC_HVCycle_Full 0x00000000 +#define HC_HVCycle_AFP 0x00000040 +#define HC_HVCycle_One 0x000000c0 +#define HC_HVCycle_NewA 0x00000000 +#define HC_HVCycle_AA 0x00000010 +#define HC_HVCycle_AB 0x00000020 +#define HC_HVCycle_AC 0x00000030 +#define HC_HVCycle_NewB 0x00000000 +#define HC_HVCycle_BA 0x00000004 +#define HC_HVCycle_BB 0x00000008 +#define HC_HVCycle_BC 0x0000000c +#define HC_HVCycle_NewC 0x00000000 +#define HC_HVCycle_CA 0x00000001 +#define HC_HVCycle_CB 0x00000002 +#define HC_HVCycle_CC 0x00000003 + +/* Command B + */ +#define HC_HLPrst_MASK 0x00010000 +#define HC_HLLastP_MASK 0x00008000 +#define HC_HVPMSK_MASK 0x00007f80 +#define HC_HBFace_MASK 0x00000040 +#define HC_H2nd1VT_MASK 0x0000003f +#define HC_HVPMSK_X 0x00004000 +#define HC_HVPMSK_Y 0x00002000 +#define HC_HVPMSK_Z 0x00001000 +#define HC_HVPMSK_W 0x00000800 +#define HC_HVPMSK_Cd 0x00000400 +#define HC_HVPMSK_Cs 0x00000200 +#define HC_HVPMSK_S 0x00000100 +#define HC_HVPMSK_T 0x00000080 + +/* Enable Setting + */ +#define HC_SubA_HEnable 0x0000 +#define HC_HenTXEnvMap_MASK 0x00200000 /* environment mapping?? */ +#define HC_HenVertexCNT_MASK 0x00100000 /* vertex counter?? */ +#define HC_HenCPUDAZ_MASK 0x00080000 /* ???? */ +#define HC_HenDASZWC_MASK 0x00040000 /* ???? */ +#define HC_HenFBCull_MASK 0x00020000 /* culling? */ +#define HC_HenCW_MASK 0x00010000 /* color write? */ +#define HC_HenAA_MASK 0x00008000 /* anti aliasing??? */ +#define HC_HenST_MASK 0x00004000 /* stencil?? */ +#define HC_HenZT_MASK 0x00002000 /* z test?? */ +#define HC_HenZW_MASK 0x00001000 /* z write?? */ +#define HC_HenAT_MASK 0x00000800 /* alpha test?? */ +#define HC_HenAW_MASK 0x00000400 /* alpha write?? */ +#define HC_HenSP_MASK 0x00000200 /* specular?? */ +#define HC_HenLP_MASK 0x00000100 /* ???? */ +#define HC_HenTXCH_MASK 0x00000080 /* cache? half speed, right fonts */ +#define HC_HenTXMP_MASK 0x00000040 /* texture mapping */ +#define HC_HenTXPP_MASK 0x00000020 /* perspective correction?? */ +#define HC_HenTXTR_MASK 0x00000010 /* ???? */ +#define HC_HenCS_MASK 0x00000008 /* color space?? looks weird */ +#define HC_HenFOG_MASK 0x00000004 /* obviously fogging */ +#define HC_HenABL_MASK 0x00000002 /* alpha blending */ +#define HC_HenDT_MASK 0x00000001 /* dithering */ + +/* Z Setting + */ +#define HC_SubA_HZWBBasL 0x0010 +#define HC_SubA_HZWBBasH 0x0011 +#define HC_SubA_HZWBType 0x0012 +#define HC_SubA_HZBiasL 0x0013 +#define HC_SubA_HZWBend 0x0014 +#define HC_SubA_HZWTMD 0x0015 +#define HC_SubA_HZWCDL 0x0016 +#define HC_SubA_HZWCTAGnum 0x0017 +#define HC_SubA_HZCYNum 0x0018 +#define HC_SubA_HZWCFire 0x0019 +/* HC_SubA_HZWBType + */ +#define HC_HZWBType_MASK 0x00800000 +#define HC_HZBiasedWB_MASK 0x00400000 +#define HC_HZONEasFF_MASK 0x00200000 +#define HC_HZOONEasFF_MASK 0x00100000 +#define HC_HZWBFM_MASK 0x00030000 +#define HC_HZWBLoc_MASK 0x0000c000 +#define HC_HZWBPit_MASK 0x00003fff +#define HC_HZWBFM_16 0x00000000 +#define HC_HZWBFM_32 0x00020000 +#define HC_HZWBFM_24 0x00030000 +#define HC_HZWBLoc_Local 0x00000000 +#define HC_HZWBLoc_SyS 0x00004000 +/* HC_SubA_HZWBend + */ +#define HC_HZWBend_MASK 0x00ffe000 +#define HC_HZBiasH_MASK 0x000000ff +#define HC_HZWBend_SHIFT 10 +/* HC_SubA_HZWTMD + */ +#define HC_HZWTMD_MASK 0x00070000 +#define HC_HEBEBias_MASK 0x00007f00 +#define HC_HZNF_MASK 0x000000ff +#define HC_HZWTMD_NeverPass 0x00000000 +#define HC_HZWTMD_LT 0x00010000 +#define HC_HZWTMD_EQ 0x00020000 +#define HC_HZWTMD_LE 0x00030000 +#define HC_HZWTMD_GT 0x00040000 +#define HC_HZWTMD_NE 0x00050000 +#define HC_HZWTMD_GE 0x00060000 +#define HC_HZWTMD_AllPass 0x00070000 +#define HC_HEBEBias_SHIFT 8 +/* HC_SubA_HZWCDL 0x0016 + */ +#define HC_HZWCDL_MASK 0x00ffffff +/* HC_SubA_HZWCTAGnum 0x0017 + */ +#define HC_HZWCTAGnum_MASK 0x00ff0000 +#define HC_HZWCTAGnum_SHIFT 16 +#define HC_HZWCDH_MASK 0x000000ff +#define HC_HZWCDH_SHIFT 0 +/* HC_SubA_HZCYNum 0x0018 + */ +#define HC_HZCYNum_MASK 0x00030000 +#define HC_HZCYNum_SHIFT 16 +#define HC_HZWCQWnum_MASK 0x00003fff +#define HC_HZWCQWnum_SHIFT 0 +/* HC_SubA_HZWCFire 0x0019 + */ +#define HC_ZWCFire_MASK 0x00010000 +#define HC_HZWCQWnumLast_MASK 0x00003fff +#define HC_HZWCQWnumLast_SHIFT 0 + +/* Stencil Setting + */ +#define HC_SubA_HSTREF 0x0023 +#define HC_SubA_HSTMD 0x0024 +/* HC_SubA_HSBFM + */ +#define HC_HSBFM_MASK 0x00030000 +#define HC_HSBLoc_MASK 0x0000c000 +#define HC_HSBPit_MASK 0x00003fff +/* HC_SubA_HSTREF + */ +#define HC_HSTREF_MASK 0x00ff0000 +#define HC_HSTOPMSK_MASK 0x0000ff00 +#define HC_HSTBMSK_MASK 0x000000ff +#define HC_HSTREF_SHIFT 16 +#define HC_HSTOPMSK_SHIFT 8 +/* HC_SubA_HSTMD + */ +#define HC_HSTMD_MASK 0x00070000 +#define HC_HSTOPSF_MASK 0x000001c0 +#define HC_HSTOPSPZF_MASK 0x00000038 +#define HC_HSTOPSPZP_MASK 0x00000007 +#define HC_HSTMD_NeverPass 0x00000000 +#define HC_HSTMD_LT 0x00010000 +#define HC_HSTMD_EQ 0x00020000 +#define HC_HSTMD_LE 0x00030000 +#define HC_HSTMD_GT 0x00040000 +#define HC_HSTMD_NE 0x00050000 +#define HC_HSTMD_GE 0x00060000 +#define HC_HSTMD_AllPass 0x00070000 +#define HC_HSTOPSF_KEEP 0x00000000 +#define HC_HSTOPSF_ZERO 0x00000040 +#define HC_HSTOPSF_REPLACE 0x00000080 +#define HC_HSTOPSF_INCRSAT 0x000000c0 +#define HC_HSTOPSF_DECRSAT 0x00000100 +#define HC_HSTOPSF_INVERT 0x00000140 +#define HC_HSTOPSF_INCR 0x00000180 +#define HC_HSTOPSF_DECR 0x000001c0 +#define HC_HSTOPSPZF_KEEP 0x00000000 +#define HC_HSTOPSPZF_ZERO 0x00000008 +#define HC_HSTOPSPZF_REPLACE 0x00000010 +#define HC_HSTOPSPZF_INCRSAT 0x00000018 +#define HC_HSTOPSPZF_DECRSAT 0x00000020 +#define HC_HSTOPSPZF_INVERT 0x00000028 +#define HC_HSTOPSPZF_INCR 0x00000030 +#define HC_HSTOPSPZF_DECR 0x00000038 +#define HC_HSTOPSPZP_KEEP 0x00000000 +#define HC_HSTOPSPZP_ZERO 0x00000001 +#define HC_HSTOPSPZP_REPLACE 0x00000002 +#define HC_HSTOPSPZP_INCRSAT 0x00000003 +#define HC_HSTOPSPZP_DECRSAT 0x00000004 +#define HC_HSTOPSPZP_INVERT 0x00000005 +#define HC_HSTOPSPZP_INCR 0x00000006 +#define HC_HSTOPSPZP_DECR 0x00000007 + +/* Alpha Setting + */ +#define HC_SubA_HABBasL 0x0030 +#define HC_SubA_HABBasH 0x0031 +#define HC_SubA_HABFM 0x0032 +#define HC_SubA_HATMD 0x0033 +#define HC_SubA_HABLCsat 0x0034 +#define HC_SubA_HABLCop 0x0035 +#define HC_SubA_HABLAsat 0x0036 +#define HC_SubA_HABLAop 0x0037 +#define HC_SubA_HABLRCa 0x0038 +#define HC_SubA_HABLRFCa 0x0039 +#define HC_SubA_HABLRCbias 0x003a +#define HC_SubA_HABLRCb 0x003b +#define HC_SubA_HABLRFCb 0x003c +#define HC_SubA_HABLRAa 0x003d +#define HC_SubA_HABLRAb 0x003e +/* HC_SubA_HABFM + */ +#define HC_HABFM_MASK 0x00030000 +#define HC_HABLoc_MASK 0x0000c000 +#define HC_HABPit_MASK 0x000007ff +/* HC_SubA_HATMD + */ +#define HC_HATMD_MASK 0x00000700 +#define HC_HATREF_MASK 0x000000ff +#define HC_HATMD_NeverPass 0x00000000 +#define HC_HATMD_LT 0x00000100 +#define HC_HATMD_EQ 0x00000200 +#define HC_HATMD_LE 0x00000300 +#define HC_HATMD_GT 0x00000400 +#define HC_HATMD_NE 0x00000500 +#define HC_HATMD_GE 0x00000600 +#define HC_HATMD_AllPass 0x00000700 +/* HC_SubA_HABLCsat + */ +#define HC_HABLCsat_MASK 0x00010000 +#define HC_HABLCa_MASK 0x0000fc00 +#define HC_HABLCa_C_MASK 0x0000c000 +#define HC_HABLCa_OPC_MASK 0x00003c00 +#define HC_HABLFCa_MASK 0x000003f0 +#define HC_HABLFCa_C_MASK 0x00000300 +#define HC_HABLFCa_OPC_MASK 0x000000f0 +#define HC_HABLCbias_MASK 0x0000000f +#define HC_HABLCbias_C_MASK 0x00000008 +#define HC_HABLCbias_OPC_MASK 0x00000007 +/*-- Define the input color. + */ +#define HC_XC_Csrc 0x00000000 +#define HC_XC_Cdst 0x00000001 +#define HC_XC_Asrc 0x00000002 +#define HC_XC_Adst 0x00000003 +#define HC_XC_Fog 0x00000004 +#define HC_XC_HABLRC 0x00000005 +#define HC_XC_minSrcDst 0x00000006 +#define HC_XC_maxSrcDst 0x00000007 +#define HC_XC_mimAsrcInvAdst 0x00000008 +#define HC_XC_OPC 0x00000000 +#define HC_XC_InvOPC 0x00000010 +#define HC_XC_OPCp5 0x00000020 +/*-- Define the input Alpha + */ +#define HC_XA_OPA 0x00000000 +#define HC_XA_InvOPA 0x00000010 +#define HC_XA_OPAp5 0x00000020 +#define HC_XA_0 0x00000000 +#define HC_XA_Asrc 0x00000001 +#define HC_XA_Adst 0x00000002 +#define HC_XA_Fog 0x00000003 +#define HC_XA_minAsrcFog 0x00000004 +#define HC_XA_minAsrcAdst 0x00000005 +#define HC_XA_maxAsrcFog 0x00000006 +#define HC_XA_maxAsrcAdst 0x00000007 +#define HC_XA_HABLRA 0x00000008 +#define HC_XA_minAsrcInvAdst 0x00000008 +#define HC_XA_HABLFRA 0x00000009 +/*-- + */ +#define HC_HABLCa_OPC (HC_XC_OPC << 10) +#define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10) +#define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10) +#define HC_HABLCa_Csrc (HC_XC_Csrc << 10) +#define HC_HABLCa_Cdst (HC_XC_Cdst << 10) +#define HC_HABLCa_Asrc (HC_XC_Asrc << 10) +#define HC_HABLCa_Adst (HC_XC_Adst << 10) +#define HC_HABLCa_Fog (HC_XC_Fog << 10) +#define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10) +#define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10) +#define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10) +#define HC_HABLFCa_OPC (HC_XC_OPC << 4) +#define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4) +#define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4) +#define HC_HABLFCa_Csrc (HC_XC_Csrc << 4) +#define HC_HABLFCa_Cdst (HC_XC_Cdst << 4) +#define HC_HABLFCa_Asrc (HC_XC_Asrc << 4) +#define HC_HABLFCa_Adst (HC_XC_Adst << 4) +#define HC_HABLFCa_Fog (HC_XC_Fog << 4) +#define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4) +#define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4) +#define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4) +#define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4) +#define HC_HABLCbias_HABLRCbias 0x00000000 +#define HC_HABLCbias_Asrc 0x00000001 +#define HC_HABLCbias_Adst 0x00000002 +#define HC_HABLCbias_Fog 0x00000003 +#define HC_HABLCbias_Cin 0x00000004 +/* HC_SubA_HABLCop 0x0035 + */ +#define HC_HABLdot_MASK 0x00010000 +#define HC_HABLCop_MASK 0x00004000 +#define HC_HABLCb_MASK 0x00003f00 +#define HC_HABLCb_C_MASK 0x00003000 +#define HC_HABLCb_OPC_MASK 0x00000f00 +#define HC_HABLFCb_MASK 0x000000fc +#define HC_HABLFCb_C_MASK 0x000000c0 +#define HC_HABLFCb_OPC_MASK 0x0000003c +#define HC_HABLCshift_MASK 0x00000003 +#define HC_HABLCb_OPC (HC_XC_OPC << 8) +#define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8) +#define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8) +#define HC_HABLCb_Csrc (HC_XC_Csrc << 8) +#define HC_HABLCb_Cdst (HC_XC_Cdst << 8) +#define HC_HABLCb_Asrc (HC_XC_Asrc << 8) +#define HC_HABLCb_Adst (HC_XC_Adst << 8) +#define HC_HABLCb_Fog (HC_XC_Fog << 8) +#define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8) +#define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8) +#define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8) +#define HC_HABLFCb_OPC (HC_XC_OPC << 2) +#define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2) +#define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2) +#define HC_HABLFCb_Csrc (HC_XC_Csrc << 2) +#define HC_HABLFCb_Cdst (HC_XC_Cdst << 2) +#define HC_HABLFCb_Asrc (HC_XC_Asrc << 2) +#define HC_HABLFCb_Adst (HC_XC_Adst << 2) +#define HC_HABLFCb_Fog (HC_XC_Fog << 2) +#define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2) +#define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2) +#define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2) +#define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2) +/* HC_SubA_HABLAsat 0x0036 + */ +#define HC_HABLAsat_MASK 0x00010000 +#define HC_HABLAa_MASK 0x0000fc00 +#define HC_HABLAa_A_MASK 0x0000c000 +#define HC_HABLAa_OPA_MASK 0x00003c00 +#define HC_HABLFAa_MASK 0x000003f0 +#define HC_HABLFAa_A_MASK 0x00000300 +#define HC_HABLFAa_OPA_MASK 0x000000f0 +#define HC_HABLAbias_MASK 0x0000000f +#define HC_HABLAbias_A_MASK 0x00000008 +#define HC_HABLAbias_OPA_MASK 0x00000007 +#define HC_HABLAa_OPA (HC_XA_OPA << 10) +#define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10) +#define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10) +#define HC_HABLAa_0 (HC_XA_0 << 10) +#define HC_HABLAa_Asrc (HC_XA_Asrc << 10) +#define HC_HABLAa_Adst (HC_XA_Adst << 10) +#define HC_HABLAa_Fog (HC_XA_Fog << 10) +#define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10) +#define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10) +#define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10) +#define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10) +#define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10) +#define HC_HABLFAa_OPA (HC_XA_OPA << 4) +#define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4) +#define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4) +#define HC_HABLFAa_0 (HC_XA_0 << 4) +#define HC_HABLFAa_Asrc (HC_XA_Asrc << 4) +#define HC_HABLFAa_Adst (HC_XA_Adst << 4) +#define HC_HABLFAa_Fog (HC_XA_Fog << 4) +#define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4) +#define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4) +#define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4) +#define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4) +#define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4) +#define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4) +#define HC_HABLAbias_HABLRAbias 0x00000000 +#define HC_HABLAbias_Asrc 0x00000001 +#define HC_HABLAbias_Adst 0x00000002 +#define HC_HABLAbias_Fog 0x00000003 +#define HC_HABLAbias_Aaa 0x00000004 +/* HC_SubA_HABLAop 0x0037 + */ +#define HC_HABLAop_MASK 0x00004000 +#define HC_HABLAb_MASK 0x00003f00 +#define HC_HABLAb_OPA_MASK 0x00000f00 +#define HC_HABLFAb_MASK 0x000000fc +#define HC_HABLFAb_OPA_MASK 0x0000003c +#define HC_HABLAshift_MASK 0x00000003 +#define HC_HABLAb_OPA (HC_XA_OPA << 8) +#define HC_HABLAb_InvOPA (HC_XA_InvOPA << 8) +#define HC_HABLAb_OPAp5 (HC_XA_OPAp5 << 8) +#define HC_HABLAb_0 (HC_XA_0 << 8) +#define HC_HABLAb_Asrc (HC_XA_Asrc << 8) +#define HC_HABLAb_Adst (HC_XA_Adst << 8) +#define HC_HABLAb_Fog (HC_XA_Fog << 8) +#define HC_HABLAb_minAsrcFog (HC_XA_minAsrcFog << 8) +#define HC_HABLAb_minAsrcAdst (HC_XA_minAsrcAdst << 8) +#define HC_HABLAb_maxAsrcFog (HC_XA_maxAsrcFog << 8) +#define HC_HABLAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 8) +#define HC_HABLAb_HABLRA (HC_XA_HABLRA << 8) +#define HC_HABLFAb_OPA (HC_XA_OPA << 2) +#define HC_HABLFAb_InvOPA (HC_XA_InvOPA << 2) +#define HC_HABLFAb_OPAp5 (HC_XA_OPAp5 << 2) +#define HC_HABLFAb_0 (HC_XA_0 << 2) +#define HC_HABLFAb_Asrc (HC_XA_Asrc << 2) +#define HC_HABLFAb_Adst (HC_XA_Adst << 2) +#define HC_HABLFAb_Fog (HC_XA_Fog << 2) +#define HC_HABLFAb_minAsrcFog (HC_XA_minAsrcFog << 2) +#define HC_HABLFAb_minAsrcAdst (HC_XA_minAsrcAdst << 2) +#define HC_HABLFAb_maxAsrcFog (HC_XA_maxAsrcFog << 2) +#define HC_HABLFAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 2) +#define HC_HABLFAb_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 2) +#define HC_HABLFAb_HABLFRA (HC_XA_HABLFRA << 2) +/* HC_SubA_HABLRAa 0x003d + */ +#define HC_HABLRAa_MASK 0x00ff0000 +#define HC_HABLRFAa_MASK 0x0000ff00 +#define HC_HABLRAbias_MASK 0x000000ff +#define HC_HABLRAa_SHIFT 16 +#define HC_HABLRFAa_SHIFT 8 +/* HC_SubA_HABLRAb 0x003e + */ +#define HC_HABLRAb_MASK 0x0000ff00 +#define HC_HABLRFAb_MASK 0x000000ff +#define HC_HABLRAb_SHIFT 8 + +/* Destination Setting + */ +#define HC_SubA_HDBBasL 0x0040 +#define HC_SubA_HDBBasH 0x0041 +#define HC_SubA_HDBFM 0x0042 +#define HC_SubA_HFBBMSKL 0x0043 +#define HC_SubA_HROP 0x0044 +/* HC_SubA_HDBFM 0x0042 + */ +#define HC_HDBFM_MASK 0x001f0000 +#define HC_HDBLoc_MASK 0x0000c000 +#define HC_HDBPit_MASK 0x00003fff +#define HC_HDBFM_RGB555 0x00000000 +#define HC_HDBFM_RGB565 0x00010000 +#define HC_HDBFM_ARGB4444 0x00020000 +#define HC_HDBFM_ARGB1555 0x00030000 +#define HC_HDBFM_BGR555 0x00040000 +#define HC_HDBFM_BGR565 0x00050000 +#define HC_HDBFM_ABGR4444 0x00060000 +#define HC_HDBFM_ABGR1555 0x00070000 +#define HC_HDBFM_ARGB0888 0x00080000 +#define HC_HDBFM_ARGB8888 0x00090000 +#define HC_HDBFM_ABGR0888 0x000a0000 +#define HC_HDBFM_ABGR8888 0x000b0000 +#define HC_HDBLoc_Local 0x00000000 +#define HC_HDBLoc_Sys 0x00004000 +/* HC_SubA_HROP 0x0044 + */ +#define HC_HROP_MASK 0x00000f00 +#define HC_HFBBMSKH_MASK 0x000000ff +#define HC_HROP_BLACK 0x00000000 +#define HC_HROP_DPon 0x00000100 +#define HC_HROP_DPna 0x00000200 +#define HC_HROP_Pn 0x00000300 +#define HC_HROP_PDna 0x00000400 +#define HC_HROP_Dn 0x00000500 +#define HC_HROP_DPx 0x00000600 +#define HC_HROP_DPan 0x00000700 +#define HC_HROP_DPa 0x00000800 +#define HC_HROP_DPxn 0x00000900 +#define HC_HROP_D 0x00000a00 +#define HC_HROP_DPno 0x00000b00 +#define HC_HROP_P 0x00000c00 +#define HC_HROP_PDno 0x00000d00 +#define HC_HROP_DPo 0x00000e00 +#define HC_HROP_WHITE 0x00000f00 + +/* Fog Setting + */ +#define HC_SubA_HFogLF 0x0050 +#define HC_SubA_HFogCL 0x0051 +#define HC_SubA_HFogCH 0x0052 +#define HC_SubA_HFogStL 0x0053 +#define HC_SubA_HFogStH 0x0054 +#define HC_SubA_HFogOOdMF 0x0055 +#define HC_SubA_HFogOOdEF 0x0056 +#define HC_SubA_HFogEndL 0x0057 +#define HC_SubA_HFogDenst 0x0058 +/* HC_SubA_FogLF 0x0050 + */ +#define HC_FogLF_MASK 0x00000010 +#define HC_FogEq_MASK 0x00000008 +#define HC_FogMD_MASK 0x00000007 +#define HC_FogMD_LocalFog 0x00000000 +#define HC_FogMD_LinearFog 0x00000002 +#define HC_FogMD_ExponentialFog 0x00000004 +#define HC_FogMD_Exponential2Fog 0x00000005 +/* #define HC_FogMD_FogTable 0x00000003 */ + +/* HC_SubA_HFogDenst 0x0058 + */ +#define HC_FogDenst_MASK 0x001fff00 +#define HC_FogEndL_MASK 0x000000ff + +/* Texture subtype definitions + */ +#define HC_SubType_Tex0 0x00000000 +#define HC_SubType_Tex1 0x00000001 +#define HC_SubType_TexGeneral 0x000000fe + +/* Attribute of texture n + */ +#define HC_SubA_HTXnL0BasL 0x0000 +#define HC_SubA_HTXnL1BasL 0x0001 +#define HC_SubA_HTXnL2BasL 0x0002 +#define HC_SubA_HTXnL3BasL 0x0003 +#define HC_SubA_HTXnL4BasL 0x0004 +#define HC_SubA_HTXnL5BasL 0x0005 +#define HC_SubA_HTXnL6BasL 0x0006 +#define HC_SubA_HTXnL7BasL 0x0007 +#define HC_SubA_HTXnL8BasL 0x0008 +#define HC_SubA_HTXnL9BasL 0x0009 +#define HC_SubA_HTXnLaBasL 0x000a +#define HC_SubA_HTXnLbBasL 0x000b +#define HC_SubA_HTXnLcBasL 0x000c +#define HC_SubA_HTXnLdBasL 0x000d +#define HC_SubA_HTXnLeBasL 0x000e +#define HC_SubA_HTXnLfBasL 0x000f +#define HC_SubA_HTXnL10BasL 0x0010 +#define HC_SubA_HTXnL11BasL 0x0011 +#define HC_SubA_HTXnL012BasH 0x0020 +#define HC_SubA_HTXnL345BasH 0x0021 +#define HC_SubA_HTXnL678BasH 0x0022 +#define HC_SubA_HTXnL9abBasH 0x0023 +#define HC_SubA_HTXnLcdeBasH 0x0024 +#define HC_SubA_HTXnLf1011BasH 0x0025 +#define HC_SubA_HTXnL0Pit 0x002b +#define HC_SubA_HTXnL1Pit 0x002c +#define HC_SubA_HTXnL2Pit 0x002d +#define HC_SubA_HTXnL3Pit 0x002e +#define HC_SubA_HTXnL4Pit 0x002f +#define HC_SubA_HTXnL5Pit 0x0030 +#define HC_SubA_HTXnL6Pit 0x0031 +#define HC_SubA_HTXnL7Pit 0x0032 +#define HC_SubA_HTXnL8Pit 0x0033 +#define HC_SubA_HTXnL9Pit 0x0034 +#define HC_SubA_HTXnLaPit 0x0035 +#define HC_SubA_HTXnLbPit 0x0036 +#define HC_SubA_HTXnLcPit 0x0037 +#define HC_SubA_HTXnLdPit 0x0038 +#define HC_SubA_HTXnLePit 0x0039 +#define HC_SubA_HTXnLfPit 0x003a +#define HC_SubA_HTXnL10Pit 0x003b +#define HC_SubA_HTXnL11Pit 0x003c +#define HC_SubA_HTXnL0_5WE 0x004b +#define HC_SubA_HTXnL6_bWE 0x004c +#define HC_SubA_HTXnLc_11WE 0x004d +#define HC_SubA_HTXnL0_5HE 0x0051 +#define HC_SubA_HTXnL6_bHE 0x0052 +#define HC_SubA_HTXnLc_11HE 0x0053 +#define HC_SubA_HTXnL0OS 0x0077 +#define HC_SubA_HTXnTB 0x0078 +#define HC_SubA_HTXnMPMD 0x0079 +#define HC_SubA_HTXnCLODu 0x007a +#define HC_SubA_HTXnFM 0x007b +#define HC_SubA_HTXnTRCH 0x007c +#define HC_SubA_HTXnTRCL 0x007d +#define HC_SubA_HTXnTBC 0x007e +#define HC_SubA_HTXnTRAH 0x007f +#define HC_SubA_HTXnTBLCsat 0x0080 +#define HC_SubA_HTXnTBLCop 0x0081 +#define HC_SubA_HTXnTBLMPfog 0x0082 +#define HC_SubA_HTXnTBLAsat 0x0083 +#define HC_SubA_HTXnTBLRCa 0x0085 +#define HC_SubA_HTXnTBLRCb 0x0086 +#define HC_SubA_HTXnTBLRCc 0x0087 +#define HC_SubA_HTXnTBLRCbias 0x0088 +#define HC_SubA_HTXnTBLRAa 0x0089 +#define HC_SubA_HTXnTBLRFog 0x008a +#define HC_SubA_HTXnBumpM00 0x0090 +#define HC_SubA_HTXnBumpM01 0x0091 +#define HC_SubA_HTXnBumpM10 0x0092 +#define HC_SubA_HTXnBumpM11 0x0093 +#define HC_SubA_HTXnLScale 0x0094 +#define HC_SubA_HTXSMD 0x0000 +/* HC_SubA_HTXnL012BasH 0x0020 + */ +#define HC_HTXnL0BasH_MASK 0x000000ff +#define HC_HTXnL1BasH_MASK 0x0000ff00 +#define HC_HTXnL2BasH_MASK 0x00ff0000 +#define HC_HTXnL1BasH_SHIFT 8 +#define HC_HTXnL2BasH_SHIFT 16 +/* HC_SubA_HTXnL345BasH 0x0021 + */ +#define HC_HTXnL3BasH_MASK 0x000000ff +#define HC_HTXnL4BasH_MASK 0x0000ff00 +#define HC_HTXnL5BasH_MASK 0x00ff0000 +#define HC_HTXnL4BasH_SHIFT 8 +#define HC_HTXnL5BasH_SHIFT 16 +/* HC_SubA_HTXnL678BasH 0x0022 + */ +#define HC_HTXnL6BasH_MASK 0x000000ff +#define HC_HTXnL7BasH_MASK 0x0000ff00 +#define HC_HTXnL8BasH_MASK 0x00ff0000 +#define HC_HTXnL7BasH_SHIFT 8 +#define HC_HTXnL8BasH_SHIFT 16 +/* HC_SubA_HTXnL9abBasH 0x0023 + */ +#define HC_HTXnL9BasH_MASK 0x000000ff +#define HC_HTXnLaBasH_MASK 0x0000ff00 +#define HC_HTXnLbBasH_MASK 0x00ff0000 +#define HC_HTXnLaBasH_SHIFT 8 +#define HC_HTXnLbBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0024 + */ +#define HC_HTXnLcBasH_MASK 0x000000ff +#define HC_HTXnLdBasH_MASK 0x0000ff00 +#define HC_HTXnLeBasH_MASK 0x00ff0000 +#define HC_HTXnLdBasH_SHIFT 8 +#define HC_HTXnLeBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0025 + */ +#define HC_HTXnLfBasH_MASK 0x000000ff +#define HC_HTXnL10BasH_MASK 0x0000ff00 +#define HC_HTXnL11BasH_MASK 0x00ff0000 +#define HC_HTXnL10BasH_SHIFT 8 +#define HC_HTXnL11BasH_SHIFT 16 +/* HC_SubA_HTXnL0Pit 0x002b + */ +#define HC_HTXnLnPit_MASK 0x00003fff +#define HC_HTXnEnPit_MASK 0x00080000 +#define HC_HTXnLnPitE_MASK 0x00f00000 +#define HC_HTXnLnPitE_SHIFT 20 +/* HC_SubA_HTXnL0_5WE 0x004b + */ +#define HC_HTXnL0WE_MASK 0x0000000f +#define HC_HTXnL1WE_MASK 0x000000f0 +#define HC_HTXnL2WE_MASK 0x00000f00 +#define HC_HTXnL3WE_MASK 0x0000f000 +#define HC_HTXnL4WE_MASK 0x000f0000 +#define HC_HTXnL5WE_MASK 0x00f00000 +#define HC_HTXnL1WE_SHIFT 4 +#define HC_HTXnL2WE_SHIFT 8 +#define HC_HTXnL3WE_SHIFT 12 +#define HC_HTXnL4WE_SHIFT 16 +#define HC_HTXnL5WE_SHIFT 20 +/* HC_SubA_HTXnL6_bWE 0x004c + */ +#define HC_HTXnL6WE_MASK 0x0000000f +#define HC_HTXnL7WE_MASK 0x000000f0 +#define HC_HTXnL8WE_MASK 0x00000f00 +#define HC_HTXnL9WE_MASK 0x0000f000 +#define HC_HTXnLaWE_MASK 0x000f0000 +#define HC_HTXnLbWE_MASK 0x00f00000 +#define HC_HTXnL7WE_SHIFT 4 +#define HC_HTXnL8WE_SHIFT 8 +#define HC_HTXnL9WE_SHIFT 12 +#define HC_HTXnLaWE_SHIFT 16 +#define HC_HTXnLbWE_SHIFT 20 +/* HC_SubA_HTXnLc_11WE 0x004d + */ +#define HC_HTXnLcWE_MASK 0x0000000f +#define HC_HTXnLdWE_MASK 0x000000f0 +#define HC_HTXnLeWE_MASK 0x00000f00 +#define HC_HTXnLfWE_MASK 0x0000f000 +#define HC_HTXnL10WE_MASK 0x000f0000 +#define HC_HTXnL11WE_MASK 0x00f00000 +#define HC_HTXnLdWE_SHIFT 4 +#define HC_HTXnLeWE_SHIFT 8 +#define HC_HTXnLfWE_SHIFT 12 +#define HC_HTXnL10WE_SHIFT 16 +#define HC_HTXnL11WE_SHIFT 20 +/* HC_SubA_HTXnL0_5HE 0x0051 + */ +#define HC_HTXnL0HE_MASK 0x0000000f +#define HC_HTXnL1HE_MASK 0x000000f0 +#define HC_HTXnL2HE_MASK 0x00000f00 +#define HC_HTXnL3HE_MASK 0x0000f000 +#define HC_HTXnL4HE_MASK 0x000f0000 +#define HC_HTXnL5HE_MASK 0x00f00000 +#define HC_HTXnL1HE_SHIFT 4 +#define HC_HTXnL2HE_SHIFT 8 +#define HC_HTXnL3HE_SHIFT 12 +#define HC_HTXnL4HE_SHIFT 16 +#define HC_HTXnL5HE_SHIFT 20 +/* HC_SubA_HTXnL6_bHE 0x0052 + */ +#define HC_HTXnL6HE_MASK 0x0000000f +#define HC_HTXnL7HE_MASK 0x000000f0 +#define HC_HTXnL8HE_MASK 0x00000f00 +#define HC_HTXnL9HE_MASK 0x0000f000 +#define HC_HTXnLaHE_MASK 0x000f0000 +#define HC_HTXnLbHE_MASK 0x00f00000 +#define HC_HTXnL7HE_SHIFT 4 +#define HC_HTXnL8HE_SHIFT 8 +#define HC_HTXnL9HE_SHIFT 12 +#define HC_HTXnLaHE_SHIFT 16 +#define HC_HTXnLbHE_SHIFT 20 +/* HC_SubA_HTXnLc_11HE 0x0053 + */ +#define HC_HTXnLcHE_MASK 0x0000000f +#define HC_HTXnLdHE_MASK 0x000000f0 +#define HC_HTXnLeHE_MASK 0x00000f00 +#define HC_HTXnLfHE_MASK 0x0000f000 +#define HC_HTXnL10HE_MASK 0x000f0000 +#define HC_HTXnL11HE_MASK 0x00f00000 +#define HC_HTXnLdHE_SHIFT 4 +#define HC_HTXnLeHE_SHIFT 8 +#define HC_HTXnLfHE_SHIFT 12 +#define HC_HTXnL10HE_SHIFT 16 +#define HC_HTXnL11HE_SHIFT 20 +/* HC_SubA_HTXnL0OS 0x0077 + */ +#define HC_HTXnL0OS_MASK 0x003ff000 +#define HC_HTXnLVmax_MASK 0x00000fc0 +#define HC_HTXnLVmin_MASK 0x0000003f +#define HC_HTXnL0OS_SHIFT 12 +#define HC_HTXnLVmax_SHIFT 6 +/* HC_SubA_HTXnTB 0x0078 + */ +#define HC_HTXnTB_MASK 0x00f00000 +#define HC_HTXnFLSe_MASK 0x0000e000 +#define HC_HTXnFLSs_MASK 0x00001c00 +#define HC_HTXnFLTe_MASK 0x00000380 +#define HC_HTXnFLTs_MASK 0x00000070 +#define HC_HTXnFLDs_MASK 0x0000000f +#define HC_HTXnTB_NoTB 0x00000000 +#define HC_HTXnTB_TBC_S 0x00100000 +#define HC_HTXnTB_TBC_T 0x00200000 +#define HC_HTXnTB_TB_S 0x00400000 +#define HC_HTXnTB_TB_T 0x00800000 +#define HC_HTXnFLSe_Nearest 0x00000000 +#define HC_HTXnFLSe_Linear 0x00002000 +#define HC_HTXnFLSe_NonLinear 0x00004000 +#define HC_HTXnFLSe_Sharp 0x00008000 +#define HC_HTXnFLSe_Flat_Gaussian_Cubic 0x0000c000 +#define HC_HTXnFLSs_Nearest 0x00000000 +#define HC_HTXnFLSs_Linear 0x00000400 +#define HC_HTXnFLSs_NonLinear 0x00000800 +#define HC_HTXnFLSs_Flat_Gaussian_Cubic 0x00001800 +#define HC_HTXnFLTe_Nearest 0x00000000 +#define HC_HTXnFLTe_Linear 0x00000080 +#define HC_HTXnFLTe_NonLinear 0x00000100 +#define HC_HTXnFLTe_Sharp 0x00000180 +#define HC_HTXnFLTe_Flat_Gaussian_Cubic 0x00000300 +#define HC_HTXnFLTs_Nearest 0x00000000 +#define HC_HTXnFLTs_Linear 0x00000010 +#define HC_HTXnFLTs_NonLinear 0x00000020 +#define HC_HTXnFLTs_Flat_Gaussian_Cubic 0x00000060 +#define HC_HTXnFLDs_Tex0 0x00000000 +#define HC_HTXnFLDs_Nearest 0x00000001 +#define HC_HTXnFLDs_Linear 0x00000002 +#define HC_HTXnFLDs_NonLinear 0x00000003 +#define HC_HTXnFLDs_Dither 0x00000004 +#define HC_HTXnFLDs_ConstLOD 0x00000005 +#define HC_HTXnFLDs_Ani 0x00000006 +#define HC_HTXnFLDs_AniDither 0x00000007 +/* HC_SubA_HTXnMPMD 0x0079 + */ +#define HC_HTXnMPMD_SMASK 0x00070000 +#define HC_HTXnMPMD_TMASK 0x00380000 +#define HC_HTXnLODDTf_MASK 0x00000007 +#define HC_HTXnXY2ST_MASK 0x00000008 +#define HC_HTXnMPMD_Tsingle 0x00000000 +#define HC_HTXnMPMD_Tclamp 0x00080000 +#define HC_HTXnMPMD_Trepeat 0x00100000 +#define HC_HTXnMPMD_Tmirror 0x00180000 +#define HC_HTXnMPMD_Twrap 0x00200000 +#define HC_HTXnMPMD_Ssingle 0x00000000 +#define HC_HTXnMPMD_Sclamp 0x00010000 +#define HC_HTXnMPMD_Srepeat 0x00020000 +#define HC_HTXnMPMD_Smirror 0x00030000 +#define HC_HTXnMPMD_Swrap 0x00040000 +/* HC_SubA_HTXnCLODu 0x007a + */ +#define HC_HTXnCLODu_MASK 0x000ffc00 +#define HC_HTXnCLODd_MASK 0x000003ff +#define HC_HTXnCLODu_SHIFT 10 +/* HC_SubA_HTXnFM 0x007b + */ +#define HC_HTXnFM_MASK 0x00ff0000 +#define HC_HTXnLoc_MASK 0x00000003 +#define HC_HTXnFM_INDEX 0x00000000 +#define HC_HTXnFM_Intensity 0x00080000 +#define HC_HTXnFM_Lum 0x00100000 +#define HC_HTXnFM_Alpha 0x00180000 +#define HC_HTXnFM_DX 0x00280000 +#define HC_HTXnFM_ARGB16 0x00880000 +#define HC_HTXnFM_ARGB32 0x00980000 +#define HC_HTXnFM_ABGR16 0x00a80000 +#define HC_HTXnFM_ABGR32 0x00b80000 +#define HC_HTXnFM_RGBA16 0x00c80000 +#define HC_HTXnFM_RGBA32 0x00d80000 +#define HC_HTXnFM_BGRA16 0x00e80000 +#define HC_HTXnFM_BGRA32 0x00f80000 +#define HC_HTXnFM_BUMPMAP 0x00380000 +#define HC_HTXnFM_Index1 (HC_HTXnFM_INDEX | 0x00000000) +#define HC_HTXnFM_Index2 (HC_HTXnFM_INDEX | 0x00010000) +#define HC_HTXnFM_Index4 (HC_HTXnFM_INDEX | 0x00020000) +#define HC_HTXnFM_Index8 (HC_HTXnFM_INDEX | 0x00030000) +#define HC_HTXnFM_T1 (HC_HTXnFM_Intensity | 0x00000000) +#define HC_HTXnFM_T2 (HC_HTXnFM_Intensity | 0x00010000) +#define HC_HTXnFM_T4 (HC_HTXnFM_Intensity | 0x00020000) +#define HC_HTXnFM_T8 (HC_HTXnFM_Intensity | 0x00030000) +#define HC_HTXnFM_L1 (HC_HTXnFM_Lum | 0x00000000) +#define HC_HTXnFM_L2 (HC_HTXnFM_Lum | 0x00010000) +#define HC_HTXnFM_L4 (HC_HTXnFM_Lum | 0x00020000) +#define HC_HTXnFM_L8 (HC_HTXnFM_Lum | 0x00030000) +#define HC_HTXnFM_AL44 (HC_HTXnFM_Lum | 0x00040000) +#define HC_HTXnFM_AL88 (HC_HTXnFM_Lum | 0x00050000) +#define HC_HTXnFM_A1 (HC_HTXnFM_Alpha | 0x00000000) +#define HC_HTXnFM_A2 (HC_HTXnFM_Alpha | 0x00010000) +#define HC_HTXnFM_A4 (HC_HTXnFM_Alpha | 0x00020000) +#define HC_HTXnFM_A8 (HC_HTXnFM_Alpha | 0x00030000) +#define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000) +#define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000) +#define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000) +#define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000) +#define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000) +#define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000) +#define HC_HTXnFM_ARGB4444 (HC_HTXnFM_ARGB16 | 0x00030000) +#define HC_HTXnFM_ARGB0888 (HC_HTXnFM_ARGB32 | 0x00000000) +#define HC_HTXnFM_ARGB8888 (HC_HTXnFM_ARGB32 | 0x00010000) +#define HC_HTXnFM_BGR555 (HC_HTXnFM_ABGR16 | 0x00000000) +#define HC_HTXnFM_BGR565 (HC_HTXnFM_ABGR16 | 0x00010000) +#define HC_HTXnFM_ABGR1555 (HC_HTXnFM_ABGR16 | 0x00020000) +#define HC_HTXnFM_ABGR4444 (HC_HTXnFM_ABGR16 | 0x00030000) +#define HC_HTXnFM_ABGR0888 (HC_HTXnFM_ABGR32 | 0x00000000) +#define HC_HTXnFM_ABGR8888 (HC_HTXnFM_ABGR32 | 0x00010000) +#define HC_HTXnFM_RGBA5550 (HC_HTXnFM_RGBA16 | 0x00000000) +#define HC_HTXnFM_RGBA5551 (HC_HTXnFM_RGBA16 | 0x00020000) +#define HC_HTXnFM_RGBA4444 (HC_HTXnFM_RGBA16 | 0x00030000) +#define HC_HTXnFM_RGBA8880 (HC_HTXnFM_RGBA32 | 0x00000000) +#define HC_HTXnFM_RGBA8888 (HC_HTXnFM_RGBA32 | 0x00010000) +#define HC_HTXnFM_BGRA5550 (HC_HTXnFM_BGRA16 | 0x00000000) +#define HC_HTXnFM_BGRA5551 (HC_HTXnFM_BGRA16 | 0x00020000) +#define HC_HTXnFM_BGRA4444 (HC_HTXnFM_BGRA16 | 0x00030000) +#define HC_HTXnFM_BGRA8880 (HC_HTXnFM_BGRA32 | 0x00000000) +#define HC_HTXnFM_BGRA8888 (HC_HTXnFM_BGRA32 | 0x00010000) +#define HC_HTXnFM_VU88 (HC_HTXnFM_BUMPMAP | 0x00000000) +#define HC_HTXnFM_LVU655 (HC_HTXnFM_BUMPMAP | 0x00010000) +#define HC_HTXnFM_LVU888 (HC_HTXnFM_BUMPMAP | 0x00020000) +#define HC_HTXnFM_YUY2 0x00300000 +#define HC_HTXnLoc_Local 0x00000000 +#define HC_HTXnLoc_Sys 0x00000002 +#define HC_HTXnLoc_AGP 0x00000003 +/* HC_SubA_HTXnTRAH 0x007f + */ +#define HC_HTXnTRAH_MASK 0x00ff0000 +#define HC_HTXnTRAL_MASK 0x0000ff00 +#define HC_HTXnTBA_MASK 0x000000ff +#define HC_HTXnTRAH_SHIFT 16 +#define HC_HTXnTRAL_SHIFT 8 +/* HC_SubA_HTXnTBLCsat 0x0080 + *-- Define the input texture. + */ +#define HC_XTC_TOPC 0x00000000 +#define HC_XTC_InvTOPC 0x00000010 +#define HC_XTC_TOPCp5 0x00000020 +#define HC_XTC_Cbias 0x00000000 +#define HC_XTC_InvCbias 0x00000010 +#define HC_XTC_0 0x00000000 +#define HC_XTC_Dif 0x00000001 +#define HC_XTC_Spec 0x00000002 +#define HC_XTC_Tex 0x00000003 +#define HC_XTC_Cur 0x00000004 +#define HC_XTC_Adif 0x00000005 +#define HC_XTC_Fog 0x00000006 +#define HC_XTC_Atex 0x00000007 +#define HC_XTC_Acur 0x00000008 +#define HC_XTC_HTXnTBLRC 0x00000009 +#define HC_XTC_Ctexnext 0x0000000a +/*-- + */ +#define HC_HTXnTBLCsat_MASK 0x00800000 +#define HC_HTXnTBLCa_MASK 0x000fc000 +#define HC_HTXnTBLCb_MASK 0x00001f80 +#define HC_HTXnTBLCc_MASK 0x0000003f +#define HC_HTXnTBLCa_TOPC (HC_XTC_TOPC << 14) +#define HC_HTXnTBLCa_InvTOPC (HC_XTC_InvTOPC << 14) +#define HC_HTXnTBLCa_TOPCp5 (HC_XTC_TOPCp5 << 14) +#define HC_HTXnTBLCa_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCa_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCa_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCa_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCa_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCa_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCa_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCa_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCa_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCa_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCa_Ctexnext (HC_XTC_Ctexnext << 14) +#define HC_HTXnTBLCb_TOPC (HC_XTC_TOPC << 7) +#define HC_HTXnTBLCb_InvTOPC (HC_XTC_InvTOPC << 7) +#define HC_HTXnTBLCb_TOPCp5 (HC_XTC_TOPCp5 << 7) +#define HC_HTXnTBLCb_0 (HC_XTC_0 << 7) +#define HC_HTXnTBLCb_Dif (HC_XTC_Dif << 7) +#define HC_HTXnTBLCb_Spec (HC_XTC_Spec << 7) +#define HC_HTXnTBLCb_Tex (HC_XTC_Tex << 7) +#define HC_HTXnTBLCb_Cur (HC_XTC_Cur << 7) +#define HC_HTXnTBLCb_Adif (HC_XTC_Adif << 7) +#define HC_HTXnTBLCb_Fog (HC_XTC_Fog << 7) +#define HC_HTXnTBLCb_Atex (HC_XTC_Atex << 7) +#define HC_HTXnTBLCb_Acur (HC_XTC_Acur << 7) +#define HC_HTXnTBLCb_HTXnTBLRC (HC_XTC_HTXnTBLRC << 7) +#define HC_HTXnTBLCb_Ctexnext (HC_XTC_Ctexnext << 7) +#define HC_HTXnTBLCc_TOPC (HC_XTC_TOPC << 0) +#define HC_HTXnTBLCc_InvTOPC (HC_XTC_InvTOPC << 0) +#define HC_HTXnTBLCc_TOPCp5 (HC_XTC_TOPCp5 << 0) +#define HC_HTXnTBLCc_0 (HC_XTC_0 << 0) +#define HC_HTXnTBLCc_Dif (HC_XTC_Dif << 0) +#define HC_HTXnTBLCc_Spec (HC_XTC_Spec << 0) +#define HC_HTXnTBLCc_Tex (HC_XTC_Tex << 0) +#define HC_HTXnTBLCc_Cur (HC_XTC_Cur << 0) +#define HC_HTXnTBLCc_Adif (HC_XTC_Adif << 0) +#define HC_HTXnTBLCc_Fog (HC_XTC_Fog << 0) +#define HC_HTXnTBLCc_Atex (HC_XTC_Atex << 0) +#define HC_HTXnTBLCc_Acur (HC_XTC_Acur << 0) +#define HC_HTXnTBLCc_HTXnTBLRC (HC_XTC_HTXnTBLRC << 0) +#define HC_HTXnTBLCc_Ctexnext (HC_XTC_Ctexnext << 0) +/* HC_SubA_HTXnTBLCop 0x0081 + */ +#define HC_HTXnTBLdot_MASK 0x00c00000 +#define HC_HTXnTBLCop_MASK 0x00380000 +#define HC_HTXnTBLCbias_MASK 0x0007c000 +#define HC_HTXnTBLCshift_MASK 0x00001800 +#define HC_HTXnTBLAop_MASK 0x00000380 +#define HC_HTXnTBLAbias_MASK 0x00000078 +#define HC_HTXnTBLAshift_MASK 0x00000003 +#define HC_HTXnTBLCop_Add 0x00000000 +#define HC_HTXnTBLCop_Sub 0x00080000 +#define HC_HTXnTBLCop_Min 0x00100000 +#define HC_HTXnTBLCop_Max 0x00180000 +#define HC_HTXnTBLCop_Mask 0x00200000 +#define HC_HTXnTBLCbias_Cbias (HC_XTC_Cbias << 14) +#define HC_HTXnTBLCbias_InvCbias (HC_XTC_InvCbias << 14) +#define HC_HTXnTBLCbias_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCbias_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCbias_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCbias_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCbias_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCbias_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCbias_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCbias_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCbias_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCbias_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCshift_1 0x00000000 +#define HC_HTXnTBLCshift_2 0x00000800 +#define HC_HTXnTBLCshift_No 0x00001000 +#define HC_HTXnTBLCshift_DotP 0x00001800 +#define HC_HTXnTBLAop_Add 0x00000000 +#define HC_HTXnTBLAop_Sub 0x00000080 +#define HC_HTXnTBLAop_Min 0x00000100 +#define HC_HTXnTBLAop_Max 0x00000180 +#define HC_HTXnTBLAop_Mask 0x00000200 +#define HC_HTXnTBLAbias_Inv 0x00000040 +#define HC_HTXnTBLAbias_Adif 0x00000000 +#define HC_HTXnTBLAbias_Fog 0x00000008 +#define HC_HTXnTBLAbias_Acur 0x00000010 +#define HC_HTXnTBLAbias_HTXnTBLRAbias 0x00000018 +#define HC_HTXnTBLAbias_Atex 0x00000020 +#define HC_HTXnTBLAshift_1 0x00000000 +#define HC_HTXnTBLAshift_2 0x00000001 +#define HC_HTXnTBLAshift_No 0x00000002 +/* #define HC_HTXnTBLAshift_DotP 0x00000003 */ +/* HC_SubA_HTXnTBLMPFog 0x0082 + */ +#define HC_HTXnTBLMPfog_MASK 0x00e00000 +#define HC_HTXnTBLMPfog_0 0x00000000 +#define HC_HTXnTBLMPfog_Adif 0x00200000 +#define HC_HTXnTBLMPfog_Fog 0x00400000 +#define HC_HTXnTBLMPfog_Atex 0x00600000 +#define HC_HTXnTBLMPfog_Acur 0x00800000 +#define HC_HTXnTBLMPfog_GHTXnTBLRFog 0x00a00000 +/* HC_SubA_HTXnTBLAsat 0x0083 + *-- Define the texture alpha input. + */ +#define HC_XTA_TOPA 0x00000000 +#define HC_XTA_InvTOPA 0x00000008 +#define HC_XTA_TOPAp5 0x00000010 +#define HC_XTA_Adif 0x00000000 +#define HC_XTA_Fog 0x00000001 +#define HC_XTA_Acur 0x00000002 +#define HC_XTA_HTXnTBLRA 0x00000003 +#define HC_XTA_Atex 0x00000004 +#define HC_XTA_Atexnext 0x00000005 +/*-- + */ +#define HC_HTXnTBLAsat_MASK 0x00800000 +#define HC_HTXnTBLAMB_MASK 0x00700000 +#define HC_HTXnTBLAa_MASK 0x0007c000 +#define HC_HTXnTBLAb_MASK 0x00000f80 +#define HC_HTXnTBLAc_MASK 0x0000001f +#define HC_HTXnTBLAMB_SHIFT 20 +#define HC_HTXnTBLAa_TOPA (HC_XTA_TOPA << 14) +#define HC_HTXnTBLAa_InvTOPA (HC_XTA_InvTOPA << 14) +#define HC_HTXnTBLAa_TOPAp5 (HC_XTA_TOPAp5 << 14) +#define HC_HTXnTBLAa_Adif (HC_XTA_Adif << 14) +#define HC_HTXnTBLAa_Fog (HC_XTA_Fog << 14) +#define HC_HTXnTBLAa_Acur (HC_XTA_Acur << 14) +#define HC_HTXnTBLAa_HTXnTBLRA (HC_XTA_HTXnTBLRA << 14) +#define HC_HTXnTBLAa_Atex (HC_XTA_Atex << 14) +#define HC_HTXnTBLAa_Atexnext (HC_XTA_Atexnext << 14) +#define HC_HTXnTBLAb_TOPA (HC_XTA_TOPA << 7) +#define HC_HTXnTBLAb_InvTOPA (HC_XTA_InvTOPA << 7) +#define HC_HTXnTBLAb_TOPAp5 (HC_XTA_TOPAp5 << 7) +#define HC_HTXnTBLAb_Adif (HC_XTA_Adif << 7) +#define HC_HTXnTBLAb_Fog (HC_XTA_Fog << 7) +#define HC_HTXnTBLAb_Acur (HC_XTA_Acur << 7) +#define HC_HTXnTBLAb_HTXnTBLRA (HC_XTA_HTXnTBLRA << 7) +#define HC_HTXnTBLAb_Atex (HC_XTA_Atex << 7) +#define HC_HTXnTBLAb_Atexnext (HC_XTA_Atexnext << 7) +#define HC_HTXnTBLAc_TOPA (HC_XTA_TOPA << 0) +#define HC_HTXnTBLAc_InvTOPA (HC_XTA_InvTOPA << 0) +#define HC_HTXnTBLAc_TOPAp5 (HC_XTA_TOPAp5 << 0) +#define HC_HTXnTBLAc_Adif (HC_XTA_Adif << 0) +#define HC_HTXnTBLAc_Fog (HC_XTA_Fog << 0) +#define HC_HTXnTBLAc_Acur (HC_XTA_Acur << 0) +#define HC_HTXnTBLAc_HTXnTBLRA (HC_XTA_HTXnTBLRA << 0) +#define HC_HTXnTBLAc_Atex (HC_XTA_Atex << 0) +#define HC_HTXnTBLAc_Atexnext (HC_XTA_Atexnext << 0) +/* HC_SubA_HTXnTBLRAa 0x0089 + */ +#define HC_HTXnTBLRAa_MASK 0x00ff0000 +#define HC_HTXnTBLRAb_MASK 0x0000ff00 +#define HC_HTXnTBLRAc_MASK 0x000000ff +#define HC_HTXnTBLRAa_SHIFT 16 +#define HC_HTXnTBLRAb_SHIFT 8 +#define HC_HTXnTBLRAc_SHIFT 0 +/* HC_SubA_HTXnTBLRFog 0x008a + */ +#define HC_HTXnTBLRFog_MASK 0x0000ff00 +#define HC_HTXnTBLRAbias_MASK 0x000000ff +#define HC_HTXnTBLRFog_SHIFT 8 +#define HC_HTXnTBLRAbias_SHIFT 0 +/* HC_SubA_HTXnLScale 0x0094 + */ +#define HC_HTXnLScale_MASK 0x0007fc00 +#define HC_HTXnLOff_MASK 0x000001ff +#define HC_HTXnLScale_SHIFT 10 +/* HC_SubA_HTXSMD 0x0000 + */ +#define HC_HTXSMD_MASK 0x00000080 +#define HC_HTXTMD_MASK 0x00000040 +#define HC_HTXNum_MASK 0x00000038 +#define HC_HTXTRMD_MASK 0x00000006 +#define HC_HTXCHCLR_MASK 0x00000001 +#define HC_HTXNum_SHIFT 3 + +/* Texture Palette n + */ +#define HC_SubType_TexPalette0 0x00000000 +#define HC_SubType_TexPalette1 0x00000001 +#define HC_SubType_FogTable 0x00000010 +#define HC_SubType_Stipple 0x00000014 +/* HC_SubA_TexPalette0 0x0000 + */ +#define HC_HTPnA_MASK 0xff000000 +#define HC_HTPnR_MASK 0x00ff0000 +#define HC_HTPnG_MASK 0x0000ff00 +#define HC_HTPnB_MASK 0x000000ff +/* HC_SubA_FogTable 0x0010 + */ +#define HC_HFPn3_MASK 0xff000000 +#define HC_HFPn2_MASK 0x00ff0000 +#define HC_HFPn1_MASK 0x0000ff00 +#define HC_HFPn_MASK 0x000000ff +#define HC_HFPn3_SHIFT 24 +#define HC_HFPn2_SHIFT 16 +#define HC_HFPn1_SHIFT 8 + +/* Auto Testing & Security + */ +#define HC_SubA_HenFIFOAT 0x0000 +#define HC_SubA_HFBDrawFirst 0x0004 +#define HC_SubA_HFBBasL 0x0005 +#define HC_SubA_HFBDst 0x0006 +/* HC_SubA_HenFIFOAT 0x0000 + */ +#define HC_HenFIFOAT_MASK 0x00000020 +#define HC_HenGEMILock_MASK 0x00000010 +#define HC_HenFBASwap_MASK 0x00000008 +#define HC_HenOT_MASK 0x00000004 +#define HC_HenCMDQ_MASK 0x00000002 +#define HC_HenTXCTSU_MASK 0x00000001 +/* HC_SubA_HFBDrawFirst 0x0004 + */ +#define HC_HFBDrawFirst_MASK 0x00000800 +#define HC_HFBQueue_MASK 0x00000400 +#define HC_HFBLock_MASK 0x00000200 +#define HC_HEOF_MASK 0x00000100 +#define HC_HFBBasH_MASK 0x000000ff + +/* GEMI Setting + */ +#define HC_SubA_HTArbRCM 0x0008 +#define HC_SubA_HTArbRZ 0x000a +#define HC_SubA_HTArbWZ 0x000b +#define HC_SubA_HTArbRTX 0x000c +#define HC_SubA_HTArbRCW 0x000d +#define HC_SubA_HTArbE2 0x000e +#define HC_SubA_HArbRQCM 0x0010 +#define HC_SubA_HArbWQCM 0x0011 +#define HC_SubA_HGEMITout 0x0020 +#define HC_SubA_HFthRTXD 0x0040 +#define HC_SubA_HFthRTXA 0x0044 +#define HC_SubA_HCMDQstL 0x0050 +#define HC_SubA_HCMDQendL 0x0051 +#define HC_SubA_HCMDQLen 0x0052 +/* HC_SubA_HTArbRCM 0x0008 + */ +#define HC_HTArbRCM_MASK 0x0000ffff +/* HC_SubA_HTArbRZ 0x000a + */ +#define HC_HTArbRZ_MASK 0x0000ffff +/* HC_SubA_HTArbWZ 0x000b + */ +#define HC_HTArbWZ_MASK 0x0000ffff +/* HC_SubA_HTArbRTX 0x000c + */ +#define HC_HTArbRTX_MASK 0x0000ffff +/* HC_SubA_HTArbRCW 0x000d + */ +#define HC_HTArbRCW_MASK 0x0000ffff +/* HC_SubA_HTArbE2 0x000e + */ +#define HC_HTArbE2_MASK 0x0000ffff +/* HC_SubA_HArbRQCM 0x0010 + */ +#define HC_HTArbRQCM_MASK 0x0000ffff +/* HC_SubA_HArbWQCM 0x0011 + */ +#define HC_HArbWQCM_MASK 0x0000ffff +/* HC_SubA_HGEMITout 0x0020 + */ +#define HC_HGEMITout_MASK 0x000f0000 +#define HC_HNPArbZC_MASK 0x0000ffff +#define HC_HGEMITout_SHIFT 16 +/* HC_SubA_HFthRTXD 0x0040 + */ +#define HC_HFthRTXD_MASK 0x00ff0000 +#define HC_HFthRZD_MASK 0x0000ff00 +#define HC_HFthWZD_MASK 0x000000ff +#define HC_HFthRTXD_SHIFT 16 +#define HC_HFthRZD_SHIFT 8 +/* HC_SubA_HFthRTXA 0x0044 + */ +#define HC_HFthRTXA_MASK 0x000000ff + +/****************************************************************************** +** Define the Halcyon Internal register access constants. For simulator only. +******************************************************************************/ +#define HC_SIMA_HAGPBstL 0x0000 +#define HC_SIMA_HAGPBendL 0x0001 +#define HC_SIMA_HAGPCMNT 0x0002 +#define HC_SIMA_HAGPBpL 0x0003 +#define HC_SIMA_HAGPBpH 0x0004 +#define HC_SIMA_HClipTB 0x0005 +#define HC_SIMA_HClipLR 0x0006 +#define HC_SIMA_HFPClipTL 0x0007 +#define HC_SIMA_HFPClipBL 0x0008 +#define HC_SIMA_HFPClipLL 0x0009 +#define HC_SIMA_HFPClipRL 0x000a +#define HC_SIMA_HFPClipTBH 0x000b +#define HC_SIMA_HFPClipLRH 0x000c +#define HC_SIMA_HLP 0x000d +#define HC_SIMA_HLPRF 0x000e +#define HC_SIMA_HSolidCL 0x000f +#define HC_SIMA_HPixGC 0x0010 +#define HC_SIMA_HSPXYOS 0x0011 +#define HC_SIMA_HCmdA 0x0012 +#define HC_SIMA_HCmdB 0x0013 +#define HC_SIMA_HEnable 0x0014 +#define HC_SIMA_HZWBBasL 0x0015 +#define HC_SIMA_HZWBBasH 0x0016 +#define HC_SIMA_HZWBType 0x0017 +#define HC_SIMA_HZBiasL 0x0018 +#define HC_SIMA_HZWBend 0x0019 +#define HC_SIMA_HZWTMD 0x001a +#define HC_SIMA_HZWCDL 0x001b +#define HC_SIMA_HZWCTAGnum 0x001c +#define HC_SIMA_HZCYNum 0x001d +#define HC_SIMA_HZWCFire 0x001e +/* #define HC_SIMA_HSBBasL 0x001d */ +/* #define HC_SIMA_HSBBasH 0x001e */ +/* #define HC_SIMA_HSBFM 0x001f */ +#define HC_SIMA_HSTREF 0x0020 +#define HC_SIMA_HSTMD 0x0021 +#define HC_SIMA_HABBasL 0x0022 +#define HC_SIMA_HABBasH 0x0023 +#define HC_SIMA_HABFM 0x0024 +#define HC_SIMA_HATMD 0x0025 +#define HC_SIMA_HABLCsat 0x0026 +#define HC_SIMA_HABLCop 0x0027 +#define HC_SIMA_HABLAsat 0x0028 +#define HC_SIMA_HABLAop 0x0029 +#define HC_SIMA_HABLRCa 0x002a +#define HC_SIMA_HABLRFCa 0x002b +#define HC_SIMA_HABLRCbias 0x002c +#define HC_SIMA_HABLRCb 0x002d +#define HC_SIMA_HABLRFCb 0x002e +#define HC_SIMA_HABLRAa 0x002f +#define HC_SIMA_HABLRAb 0x0030 +#define HC_SIMA_HDBBasL 0x0031 +#define HC_SIMA_HDBBasH 0x0032 +#define HC_SIMA_HDBFM 0x0033 +#define HC_SIMA_HFBBMSKL 0x0034 +#define HC_SIMA_HROP 0x0035 +#define HC_SIMA_HFogLF 0x0036 +#define HC_SIMA_HFogCL 0x0037 +#define HC_SIMA_HFogCH 0x0038 +#define HC_SIMA_HFogStL 0x0039 +#define HC_SIMA_HFogStH 0x003a +#define HC_SIMA_HFogOOdMF 0x003b +#define HC_SIMA_HFogOOdEF 0x003c +#define HC_SIMA_HFogEndL 0x003d +#define HC_SIMA_HFogDenst 0x003e +/*---- start of texture 0 setting ---- + */ +#define HC_SIMA_HTX0L0BasL 0x0040 +#define HC_SIMA_HTX0L1BasL 0x0041 +#define HC_SIMA_HTX0L2BasL 0x0042 +#define HC_SIMA_HTX0L3BasL 0x0043 +#define HC_SIMA_HTX0L4BasL 0x0044 +#define HC_SIMA_HTX0L5BasL 0x0045 +#define HC_SIMA_HTX0L6BasL 0x0046 +#define HC_SIMA_HTX0L7BasL 0x0047 +#define HC_SIMA_HTX0L8BasL 0x0048 +#define HC_SIMA_HTX0L9BasL 0x0049 +#define HC_SIMA_HTX0LaBasL 0x004a +#define HC_SIMA_HTX0LbBasL 0x004b +#define HC_SIMA_HTX0LcBasL 0x004c +#define HC_SIMA_HTX0LdBasL 0x004d +#define HC_SIMA_HTX0LeBasL 0x004e +#define HC_SIMA_HTX0LfBasL 0x004f +#define HC_SIMA_HTX0L10BasL 0x0050 +#define HC_SIMA_HTX0L11BasL 0x0051 +#define HC_SIMA_HTX0L012BasH 0x0052 +#define HC_SIMA_HTX0L345BasH 0x0053 +#define HC_SIMA_HTX0L678BasH 0x0054 +#define HC_SIMA_HTX0L9abBasH 0x0055 +#define HC_SIMA_HTX0LcdeBasH 0x0056 +#define HC_SIMA_HTX0Lf1011BasH 0x0057 +#define HC_SIMA_HTX0L0Pit 0x0058 +#define HC_SIMA_HTX0L1Pit 0x0059 +#define HC_SIMA_HTX0L2Pit 0x005a +#define HC_SIMA_HTX0L3Pit 0x005b +#define HC_SIMA_HTX0L4Pit 0x005c +#define HC_SIMA_HTX0L5Pit 0x005d +#define HC_SIMA_HTX0L6Pit 0x005e +#define HC_SIMA_HTX0L7Pit 0x005f +#define HC_SIMA_HTX0L8Pit 0x0060 +#define HC_SIMA_HTX0L9Pit 0x0061 +#define HC_SIMA_HTX0LaPit 0x0062 +#define HC_SIMA_HTX0LbPit 0x0063 +#define HC_SIMA_HTX0LcPit 0x0064 +#define HC_SIMA_HTX0LdPit 0x0065 +#define HC_SIMA_HTX0LePit 0x0066 +#define HC_SIMA_HTX0LfPit 0x0067 +#define HC_SIMA_HTX0L10Pit 0x0068 +#define HC_SIMA_HTX0L11Pit 0x0069 +#define HC_SIMA_HTX0L0_5WE 0x006a +#define HC_SIMA_HTX0L6_bWE 0x006b +#define HC_SIMA_HTX0Lc_11WE 0x006c +#define HC_SIMA_HTX0L0_5HE 0x006d +#define HC_SIMA_HTX0L6_bHE 0x006e +#define HC_SIMA_HTX0Lc_11HE 0x006f +#define HC_SIMA_HTX0L0OS 0x0070 +#define HC_SIMA_HTX0TB 0x0071 +#define HC_SIMA_HTX0MPMD 0x0072 +#define HC_SIMA_HTX0CLODu 0x0073 +#define HC_SIMA_HTX0FM 0x0074 +#define HC_SIMA_HTX0TRCH 0x0075 +#define HC_SIMA_HTX0TRCL 0x0076 +#define HC_SIMA_HTX0TBC 0x0077 +#define HC_SIMA_HTX0TRAH 0x0078 +#define HC_SIMA_HTX0TBLCsat 0x0079 +#define HC_SIMA_HTX0TBLCop 0x007a +#define HC_SIMA_HTX0TBLMPfog 0x007b +#define HC_SIMA_HTX0TBLAsat 0x007c +#define HC_SIMA_HTX0TBLRCa 0x007d +#define HC_SIMA_HTX0TBLRCb 0x007e +#define HC_SIMA_HTX0TBLRCc 0x007f +#define HC_SIMA_HTX0TBLRCbias 0x0080 +#define HC_SIMA_HTX0TBLRAa 0x0081 +#define HC_SIMA_HTX0TBLRFog 0x0082 +#define HC_SIMA_HTX0BumpM00 0x0083 +#define HC_SIMA_HTX0BumpM01 0x0084 +#define HC_SIMA_HTX0BumpM10 0x0085 +#define HC_SIMA_HTX0BumpM11 0x0086 +#define HC_SIMA_HTX0LScale 0x0087 +/*---- end of texture 0 setting ---- 0x008f + */ +#define HC_SIMA_TX0TX1_OFF 0x0050 +/*---- start of texture 1 setting ---- + */ +#define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) +/*---- end of texture 1 setting ---- 0xaf + */ +#define HC_SIMA_HTXSMD 0x00b0 +#define HC_SIMA_HenFIFOAT 0x00b1 +#define HC_SIMA_HFBDrawFirst 0x00b2 +#define HC_SIMA_HFBBasL 0x00b3 +#define HC_SIMA_HTArbRCM 0x00b4 +#define HC_SIMA_HTArbRZ 0x00b5 +#define HC_SIMA_HTArbWZ 0x00b6 +#define HC_SIMA_HTArbRTX 0x00b7 +#define HC_SIMA_HTArbRCW 0x00b8 +#define HC_SIMA_HTArbE2 0x00b9 +#define HC_SIMA_HGEMITout 0x00ba +#define HC_SIMA_HFthRTXD 0x00bb +#define HC_SIMA_HFthRTXA 0x00bc +/* Define the texture palette 0 + */ +#define HC_SIMA_HTP0 0x0100 +#define HC_SIMA_HTP1 0x0200 +#define HC_SIMA_FOGTABLE 0x0300 +#define HC_SIMA_STIPPLE 0x0400 +#define HC_SIMA_HE3Fire 0x0440 +#define HC_SIMA_TRANS_SET 0x0441 +#define HC_SIMA_HREngSt 0x0442 +#define HC_SIMA_HRFIFOempty 0x0443 +#define HC_SIMA_HRFIFOfull 0x0444 +#define HC_SIMA_HRErr 0x0445 +#define HC_SIMA_FIFOstatus 0x0446 + +/****************************************************************************** +** Define the AGP command header. +******************************************************************************/ +#define HC_ACMD_MASK 0xfe000000 +#define HC_ACMD_SUB_MASK 0x0c000000 +#define HC_ACMD_HCmdA 0xee000000 +#define HC_ACMD_HCmdB 0xec000000 +#define HC_ACMD_HCmdC 0xea000000 +#define HC_ACMD_H1 0xf0000000 +#define HC_ACMD_H2 0xf2000000 +#define HC_ACMD_H3 0xf4000000 +#define HC_ACMD_H4 0xf6000000 + +#define HC_ACMD_H1IO_MASK 0x000001ff +#define HC_ACMD_H2IO1_MASK 0x001ff000 +#define HC_ACMD_H2IO2_MASK 0x000001ff +#define HC_ACMD_H2IO1_SHIFT 12 +#define HC_ACMD_H2IO2_SHIFT 0 +#define HC_ACMD_H3IO_MASK 0x000001ff +#define HC_ACMD_H3COUNT_MASK 0x01fff000 +#define HC_ACMD_H3COUNT_SHIFT 12 +#define HC_ACMD_H4ID_MASK 0x000001ff +#define HC_ACMD_H4COUNT_MASK 0x01fffe00 +#define HC_ACMD_H4COUNT_SHIFT 9 + +/******************************************************************************** +** Define Header +********************************************************************************/ +#define HC_HEADER2 0xF210F110 + +/******************************************************************************** +** Define Dummy Value +********************************************************************************/ +#define HC_DUMMY 0xCCCCCCCC +/******************************************************************************** +** Define for DMA use +********************************************************************************/ +#define HALCYON_HEADER2 0XF210F110 +#define HALCYON_FIRECMD 0XEE100000 +#define HALCYON_FIREMASK 0XFFF00000 +#define HALCYON_CMDB 0XEC000000 +#define HALCYON_CMDBMASK 0XFFFE0000 +#define HALCYON_SUB_ADDR0 0X00000000 +#define HALCYON_HEADER1MASK 0XFFFFFF00 +#define HALCYON_HEADER1 0XF0000000 +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +#define HC_HAGPBpH_MASK 0x00ffffff + +#endif // __VIA_REGS_3D_H__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_accel.c b/Source/DirectFB/gfxdrivers/unichrome/uc_accel.c new file mode 100755 index 0000000..a75cc6d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_accel.c @@ -0,0 +1,578 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include + +#include "unichrome.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "mmio.h" + +#define UC_ACCEL_BEGIN() \ + UcDriverData *ucdrv = (UcDriverData*) drv; \ + UcDeviceData *ucdev = (UcDeviceData*) dev; \ + struct uc_fifo *fifo = ucdrv->fifo; \ + /*printf("entering %s\n", __PRETTY_FUNCTION__)*/ + +#define UC_ACCEL_END() \ + UC_FIFO_CHECK(fifo); \ + /*printf("leaving %s\n", __PRETTY_FUNCTION__)*/ + +// Private functions --------------------------------------------------------- + +/** Wait until a new command can be set up. */ + +static inline void uc_waitcmd(UcDriverData* ucdrv, UcDeviceData* ucdev) +{ + int loop = 0; + + if (!ucdev->must_wait) + return; + + //printf("waitcmd "); + + while (VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/Unichrome: Timeout waiting for idle command regulator!\n"); + break; + } + } + + //printf("waited for %d (0x%x) cycles.\n", loop, loop); + + ucdev->cmd_waitcycles += loop; + ucdev->must_wait = 0; +} + +/** Send commands to 2D/3D engine. */ + +void uc_emit_commands(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + uc_waitcmd(ucdrv, ucdev); + + UC_FIFO_FLUSH(fifo); + + ucdev->must_wait = 1; +} + +void uc_flush_texture_cache(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + (void) ucdev; + + UC_FIFO_PREPARE(fifo, 16); + + UC_FIFO_ADD_HDR(fifo, (HC_ParaType_Tex << 16) | (HC_SubType_TexGeneral << 24)); + UC_FIFO_ADD (fifo, 0x00000002); + + UC_FIFO_ADD (fifo, 0x0113000d); + UC_FIFO_ADD (fifo, 0x02ed1316); + UC_FIFO_ADD (fifo, 0x03071000); + + UC_FIFO_CHECK(fifo); +} + +/** + * Draw a horizontal or vertical line. + * + * @param fifo command FIFO + * + * @param x start x position + * @param y start y position + * @param len length + * @param hv if zero: draw from left to right + * if nonzero: draw from top to bottom. + * + * @note This is actually a 1-pixel high or wide rectangular color fill. + */ + +static inline void uc_draw_hv_line(struct uc_fifo* fifo, + int x, int y, int len, int hv, int rop) +{ + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(y) << 16) | RS16(x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, len << (hv ? 16 : 0)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | rop | VIA_GEC_CLIP_ENABLE); +} + +// DirectFB interfacing functions -------------------------------------------- + +// Functions using the 2D engine --- + +bool uc_fill_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 8); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(r->y) << 16) | RS16(r->x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, + (((RS16(r->h - 1)) << 16) | RS16((r->w - 1)))); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | ucdev->draw_rop2d | VIA_GEC_CLIP_ENABLE); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + int rop = ucdev->draw_rop2d; + + // Draw lines, in this order: top, bottom, left, right + + UC_FIFO_PREPARE(fifo, 26); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + uc_draw_hv_line(fifo, r->x, r->y, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y + r->h - 1, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y, r->h - 1, 1, rop); + uc_draw_hv_line(fifo, r->x + r->w - 1, r->y, r->h - 1, 1, rop); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + //printf("%s: l = (%d, %d) - (%d, %d), c = 0x%08x\n", __PRETTY_FUNCTION__, + // line->x1, line->y1, line->x2, line->y2, ucdev->color); + + int cmd; + int dx, dy, tmp, error; + + error = 1; + + cmd = VIA_GEC_LINE | VIA_GEC_FIXCOLOR_PAT | ucdev->draw_rop2d + | VIA_GEC_CLIP_ENABLE; + + dx = line->x2 - line->x1; + if (dx < 0) + { + dx = -dx; + cmd |= VIA_GEC_DECX; // line will be drawn from right + error = 0; + } + + dy = line->y2 - line->y1; + if (dy < 0) + { + dy = -dy; + cmd |= VIA_GEC_DECY; // line will be drawn from bottom + } + + if (dy > dx) + { + tmp = dy; + dy = dx; + dx = tmp; // Swap 'dx' and 'dy' + cmd |= VIA_GEC_Y_MAJOR; // Y major line + } + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_K1K2, + ((((dy << 1) & 0x3fff) << 16)| (((dy - dx) << 1) & 0x3fff))); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_XY, + ((RS16(line->y1) << 16) | RS16(line->x1))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, dx); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_ERROR, + (((dy << 1) - dx - error) & 0x3fff)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +static bool uc_blit_one_plane(void* drv, void* dev, DFBRectangle* rect, int dx, int dy) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = (%d, %d, %d, %d) -> (%d, %d)\n", __PRETTY_FUNCTION__, + // rect->x, rect->y, rect->h, rect->w, dx, dy); + + int cmd = VIA_GEC_BLT | VIA_ROP_S | VIA_GEC_CLIP_ENABLE; + + int sx = rect->x; + int sy = rect->y; + int w = rect->w; + int h = rect->h; + + if (!w || !h) return true; + + (void) ucdev; // Kill 'unused variable' compiler warning. + + if (sx < dx) { + cmd |= VIA_GEC_DECX; + sx += w - 1; + dx += w - 1; + } + + if (sy < dy) { + cmd |= VIA_GEC_DECY; + sy += h - 1; + dy += h - 1; + } + + UC_FIFO_PREPARE(fifo, 10); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_SRCPOS, (RS16(sy) << 16) | RS16(sx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, (RS16(dy) << 16) | RS16(dx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, (RS16(h - 1) << 16) | RS16(w - 1)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +static bool uc_blit_planar(void* drv, void* dev, DFBRectangle* rect, int dx, int dy) +{ + UC_ACCEL_BEGIN() + + int uv_dst_offset = ucdev->dst_offset + (ucdev->dst_pitch * ucdev->dst_height); + int uv_src_offset = ucdev->src_offset + (ucdev->src_pitch * ucdev->src_height); + + int uv_dst_pitch = ucdev->dst_pitch / 2; + int uv_src_pitch = ucdev->src_pitch / 2; + int uv_pitch = ((uv_src_pitch >> 3) & 0x7fff) | (((uv_dst_pitch >> 3) & 0x7fff) << 16); + + DFBRectangle rect2 = *rect; + rect2.h /= 2; + rect2.w /= 2; + rect2.x /= 2; + rect2.y /= 2; + + // first blit the Y plane + + uc_blit_one_plane(drv, dev, rect, dx, dy); + + // now modify the offsets and clip region for the first chrominance plane + + UC_FIFO_PREPARE ( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, VIA_PITCH_ENABLE | uv_pitch ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, uv_src_offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, uv_dst_offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPTL, + (RS16(ucdev->clip.y1/2) << 16) | RS16(ucdev->clip.x1/2) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPBR, + (RS16(ucdev->clip.y2/2) << 16) | RS16(ucdev->clip.x2/2) ); + UC_FIFO_CHECK ( fifo ); + + uc_blit_one_plane(drv, dev, &rect2, dx/2, dy/2); + + // now for the second chrominance plane + + uv_src_offset += uv_src_pitch * ucdev->src_height/2; + uv_dst_offset += uv_dst_pitch * ucdev->dst_height/2; + + UC_FIFO_PREPARE ( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, uv_src_offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, uv_dst_offset >> 3 ); + UC_FIFO_CHECK ( fifo ); + + uc_blit_one_plane(drv, dev, &rect2, dx/2, dy/2); + + // restore the card state to how we found it + + UC_FIFO_PREPARE ( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, VIA_PITCH_ENABLE | ucdev->pitch ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, ucdev->src_offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, ucdev->dst_offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPTL, + (RS16(ucdev->clip.y1) << 16) | RS16(ucdev->clip.x1) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPBR, + (RS16(ucdev->clip.y2) << 16) | RS16(ucdev->clip.x2) ); + UC_FIFO_CHECK ( fifo ); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit(void* drv, void* dev, DFBRectangle* rect, int dx, int dy) +{ + DFBSurfacePixelFormat format = ((UcDeviceData *)dev)->dst_format; + if (format == DSPF_YV12 || format == DSPF_I420) + return uc_blit_planar(drv, dev, rect, dx, dy); + else + return uc_blit_one_plane(drv, dev, rect, dx, dy); +} + +// Functions using the 3D engine --- + +bool uc_fill_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color3d); + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_AFP | + HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC | HC_HShading_FlatC; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 18); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y + r->h, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_AFP | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 20); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line_3d(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, line->x1, line->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, line->x2, line->y2, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_fill_triangle(void* drv, void* dev, DFBTriangle* tri) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 14); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, tri->x1, tri->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, tri->x2, tri->y2, 0); + UC_FIFO_ADD_XYC(fifo, tri->x3, tri->y3, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit_3d(void* drv, void* dev, + DFBRectangle* rect, int dx, int dy) +{ + DFBRectangle dest = {dx, dy, rect->w, rect->h}; + return uc_stretch_blit(drv, dev, rect, &dest); +} + +bool uc_stretch_blit(void* drv, void* dev, + DFBRectangle* sr, DFBRectangle* dr) +{ + UC_ACCEL_BEGIN() + + float w = ucdev->hwtex.l2w; + float h = ucdev->hwtex.l2h; + + float dy = dr->y; + + float s1 = (sr->x ) / w; + float t1 = (sr->y ) / h; + float s2 = (sr->x + sr->w) / w; + float t2 = (sr->y + sr->h) / h; + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_FlatC | + HC_HVCycle_AFP | HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (ucdev->bflags & DSBLIT_DEINTERLACE) { + t1 *= 0.5f; + t2 *= 0.5f; + + if (ucdev->field) + dy += 0.5f; + else + dy -= 0.5f; + } + + UC_FIFO_PREPARE(fifo, 30); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy, 1, 0, s2, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy+dr->h, 1, 0, s1, t2); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy, 1, ucdev->color3d, s1, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy+dr->h, 1, ucdev->color3d, s2, t2); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + +#define DFBCOLOR_TO_ARGB(c) PIXEL_ARGB( (c).a, (c).r, (c).g, (c).b ) + +bool uc_texture_triangles( void *drv, void *dev, + DFBVertex *vertices, int num, + DFBTriangleFormation formation ) +{ + UC_ACCEL_BEGIN() + + int i; + + int cmdB = HC_ACMD_HCmdB | + HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Z | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_Gouraud | + HC_HVCycle_Full; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + + switch (formation) { + case DTTF_LIST: + cmdA |= HC_HVCycle_NewA | HC_HVCycle_NewB | HC_HVCycle_NewC; + break; + case DTTF_STRIP: + cmdA |= HC_HVCycle_AB | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + case DTTF_FAN: + cmdA |= HC_HVCycle_AA | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + default: + D_ONCE( "unknown triangle formation" ); + return false; + } + + UC_FIFO_PREPARE(fifo, 6 + num * 7); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + for (i=0; icolor3d, + vertices[i].s, vertices[i].t); + } + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + + // Blit profiling + + //struct timeval tv_start, tv_stop; + //gettimeofday(&tv_start, NULL); + + // Run test here + + //gettimeofday(&tv_stop, NULL); + + //tv_stop.tv_sec -= tv_start.tv_sec; + //tv_stop.tv_usec -= tv_start.tv_usec; + //if (tv_stop.tv_usec < 0) { + // tv_stop.tv_sec--; + // tv_stop.tv_usec += 1000000; + //} + + //printf("elapsed time: %d us\n", tv_stop.tv_usec); diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_accel.h b/Source/DirectFB/gfxdrivers/unichrome/uc_accel.h new file mode 100755 index 0000000..2255ddc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_accel.h @@ -0,0 +1,123 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_ACCEL_H__ +#define __UC_ACCEL_H__ + +#include "unichrome.h" + + +// 2D accelerator capabilites + +#define UC_DRAWING_FLAGS_2D (DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_2D (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY) + +#define UC_DRAWING_FUNCTIONS_2D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE) + +#define UC_BLITTING_FUNCTIONS_2D (DFXL_BLIT) + + +// 3D accelerator capabilites + +#ifdef UC_ENABLE_3D + +#define UC_DRAWING_FLAGS_3D (DSDRAW_BLEND | DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_3D (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE) + +#define UC_BLITTING_FLAGS_3D_INV (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE) + +#define UC_DRAWING_FUNCTIONS_3D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE | \ + DFXL_FILLTRIANGLE) + +#define UC_BLITTING_FUNCTIONS_3D (DFXL_BLIT | \ + DFXL_STRETCHBLIT | \ + DFXL_TEXTRIANGLES) + +#else + +#define UC_DRAWING_FLAGS_3D 0 +#define UC_BLITTING_FLAGS_3D 0 +#define UC_DRAWING_FUNCTIONS_3D 0 +#define UC_BLITTING_FUNCTIONS_3D 0 + +#endif // UC_ENABLE_3D + + +// Functions + +void uc_emit_commands ( void *drv, + void *dev ); + +void uc_flush_texture_cache( void *drv, + void *dev ); + +bool uc_fill_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_blit ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_fill_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line_3d ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_fill_triangle ( void *drv, + void *dev, + DFBTriangle *tri ); + +bool uc_blit_3d ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_stretch_blit ( void *drv, + void *dev, + DFBRectangle *srect, + DFBRectangle *drect ); + +bool uc_texture_triangles ( void *drv, + void *dev, + DFBVertex *vertices, + int num, + DFBTriangleFormation formation ); + +#endif // __UC_ACCEL_H__ + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.c b/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.c new file mode 100755 index 0000000..cc13433 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.c @@ -0,0 +1,198 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include +#include + +#include + +#include "uc_fifo.h" + +//#define UC_FIFO_DUMP_DATA + +// Private functions --------------------------------------------------------- + +/** + * Pad the FIFO buffer to a 32 byte boundary. Used by uc_flush_agp(). + * @note Equivalent DRI code is in via_ioctl::viaFlushPrimsLocked() + */ + +static void uc_fifo_pad(struct uc_fifo* fifo) +{ + switch (fifo->used & 0x7) + { + case 0: + break; + case 2: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 4: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 6: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + default: + break; + } +} + +/** + * Manually write the FIFO buffer to the hardware. + * @note Equivalent DRI code is in via_ioctl::flush_sys() + */ + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs) +{ + u32* p; + u32* q; + + volatile u32* hwregs = regs; + volatile u32* reg_tset = regs + VIA_REG_TRANSET; + volatile u32* reg_tspace = regs + VIA_REG_TRANSPACE; + + int check2Dcmd; + u32 addr; + + p = fifo->buf; + q = fifo->head; + check2Dcmd = 0; + + uc_fifo_pad(fifo); + +#ifdef UC_FIFO_DUMP_DATA + printf("Flushing FIFO ... \n"); +#endif + + while (p != q) { + + if (*p == HALCYON_HEADER2) { + p++; + check2Dcmd = !(*p == HALCYON_SUB_ADDR0); +#ifdef UC_FIFO_DUMP_DATA + printf("tset = 0x%08x\n", *p); +#endif + *reg_tset = *p; + p++; + } + else if (check2Dcmd && ((*p & HALCYON_HEADER1MASK) == HALCYON_HEADER1)) { + addr = (*p) & 0x0000001f; + p++; +#ifdef UC_FIFO_DUMP_DATA + printf("2D (0x%02x) = 0x%x\n", addr << 2, *p); +#endif + *(hwregs + addr) = *p; + p++; + } + else if ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD) { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + + if ((p != q) && ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD)) + p++; + + if ((*p & HALCYON_CMDBMASK) != HC_ACMD_HCmdB) + check2Dcmd = 1; + } + else { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + } + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} + +/** Use an AGP transfer to write the FIFO buffer to the hardware. Not implemented. */ +#if 0 +static void uc_fifo_flush_agp(struct uc_fifo* fifo) +{ + // TODO - however, there is no point in doing this, because + // an AGP transfer can require more register writes than + // needed for drawing a single primitive. DirectFB needs to + // adopt a begin/end architecture first, like OpenGL has. + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} +#endif + +// Public functions ---------------------------------------------------------- + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create(FusionSHMPoolShared *pool, size_t size) +{ + struct uc_fifo* fifo; + + size += 32; // Needed for padding. + + fifo = SHCALLOC(pool, 1, sizeof(struct uc_fifo)); + if (!fifo) return NULL; + + // Note: malloc won't work for DMA buffers... + + fifo->buf = SHMALLOC(pool, sizeof(u32) * size); + if (!(fifo->buf)) { + SHFREE(pool, fifo); + return NULL; + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->size = (unsigned int) size; + fifo->prep = 0; + + //fifo->flush_sys = uc_fifo_flush_sys; + + //fifo->flush = uc_fifo_flush_sys; + + return fifo; +} + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo) +{ + if (fifo) { + if (fifo->buf) { + SHFREE(pool, fifo->buf); + fifo->buf = NULL; + } + SHFREE(pool, fifo); + } +} diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.h b/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.h new file mode 100755 index 0000000..e7a3d8f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_fifo.h @@ -0,0 +1,268 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_FIFO_H__ +#define __UC_FIFO_H__ + +// Note to self: remove when added to makefile as -DUC_DEBUG. +#define UC_DEBUG 1 + +#include + +#include "regs2d.h" +#include "regs3d.h" +#include "mmio.h" + +/** + * uc_fifo - GPU data queue. + * + * buf: buffer start (userspace address) + * head: pointer to first unused entry. + * + * size: maximum number of entries in the fifo. + * prep: number of entries allocated to be used. + * used: number of entries currently in use. + * + * hwregs: GPU register base address + * reg_tset: address to GPU TRANSET register + * reg_tspace: address to GPU TRANSPACE register + * + * flush: function pointer to flush function (DMA or CPU) + * flush_sys: function pointer to flush_sys (non-DMA) function + */ + +struct uc_fifo +{ + u32* buf; + u32* head; + + unsigned int size; + unsigned int prep; + unsigned int used; + + //void (*flush)(struct uc_fifo* fifo, volatile void *hwregs); + //void (*flush_sys)(struct uc_fifo* fifo, volatile void *hwregs); +}; + +// Help macros --------------------------------------------------------------- + +// For the record: Macros suck maintenance- and debugging-wise, +// but provide guaranteed inlining of the code. + +/** + * Send the contents of the FIFO buffer to the hardware, and clear + * the buffer. The transfer may be performed by the CPU or by DMA. + */ + +//#define UC_FIFO_FLUSH(fifo) (fifo)->flush(fifo,ucdrv->hwregs) + +/** + * Same as UC_FIFO_FLUSH(), but always uses the CPU to transfer data. + */ + +//#define UC_FIFO_FLUSH_SYS(fifo) (fifo)->flush_sys(fifo,ucdrv->hwregs) + +#define UC_FIFO_FLUSH(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) +#define UC_FIFO_FLUSH_SYS(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) + +/** + * Make sure there is room for dwsize double words in the FIFO. + * If necessary, the FIFO is flushed first. + * + * @param fifo the fifo + * @param dwsize number of double words to allocate + * + * @note It is ok to request more space than you will actually + * be using. This is useful when you don't know exactly beforehand + * how many entries you need. + * + * @note equivalent DRI code is in via_ioctl.c::viaCheckDma() + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + D_DEBUG("Unichrome: FIFO full - flushing it."); \ + UC_FIFO_FLUSH(fifo); \ + } \ + if (dwsize + (fifo)->prep + 32 > (fifo)->size) { \ + D_BUG("Unichrome: FIFO too small for allocation."); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#else + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + UC_FIFO_FLUSH(fifo); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#endif // UC_FIFO_DEBUG + +/** + * Add a 32-bit data word to the FIFO. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD(fifo, data) \ + do { \ + *((fifo)->head) = (data); \ + (fifo)->head++; \ + (fifo)->used++; \ + } while(0) + +/** + * Add a command header. (HC_HEADER2 + parameter selection) + * Takes two entries in the fifo. + */ + +#define UC_FIFO_ADD_HDR(fifo, param) \ + do { \ + UC_FIFO_ADD(fifo, HC_HEADER2); \ + UC_FIFO_ADD(fifo, param); \ + } while(0); + +/** + * Add a floating point value to the FIFO. + * Non-floats (e.g integers) are converted first. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD_FLOAT(fifo, val) \ + do { \ + union {float f; u32 i;} v; \ + v.f = (float) (val); \ + UC_FIFO_ADD(fifo, v.i); \ + } while(0) + +/** + * Add a vertex on the form (x, y, color) to the FIFO. + * Takes three entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYC(fifo, x, y, color) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + } while(0) + +/** + * Add a vertex on the form (x, y, w, color, s, t) to the FIFO. + * Takes six entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYWCST(fifo, x, y, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYZWCST(fifo, x, y, z, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, z); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYCST(fifo, x, y, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + + +/** + * Add data specifically for the 2D controller, to the fifo. + * Takes two entries in the FIFO. + * + * @param reg 2D register index + * @param data 32-bit data to add + */ + +#define UC_FIFO_ADD_2D(fifo, reg, data) \ + do { \ + UC_FIFO_ADD(fifo, ((reg) >> 2) | HALCYON_HEADER1); \ + UC_FIFO_ADD(fifo, (data)); \ + } while (0) + +/** + * Add data specifically for a 3D controller register, to the fifo. + * Takes one entry in the FIFO. + * + * @param reg 3D register index (8 bit) + * @param data 24-bit data to add (make sure bits 24 - 31 are cleared!) + */ + +#define UC_FIFO_ADD_3D(fifo, reg, data) \ + UC_FIFO_ADD(fifo, ((reg) << 24) | (data)) + +/** + * Pad the FIFO to an even number of entries. + * Takes zero or one entries in the FIFO. + */ +#define UC_FIFO_PAD_EVEN(fifo) \ + if (fifo->used & 1) UC_FIFO_ADD(fifo, HC_DUMMY) + +/** + * Check for buffer overruns. + * Can be redefined to nothing in release builds. + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_CHECK(fifo) \ + do { \ + if ((fifo)->used > ((fifo)->size) - 32) { \ + D_BUG("Unichrome: FIFO overrun."); \ + } \ + if ((fifo)->used > (fifo)->prep) { \ + D_BUG("Unichrome: FIFO allocation error."); \ + } \ + } while(0) + +#else + +#define UC_FIFO_CHECK(fifo) do { } while(0) + +#endif // UC_DEBUG + + +// FIFO functions ------------------------------------------------------------ + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create( FusionSHMPoolShared *pool, size_t size); + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo); + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs); + +#endif // __UC_FIFO_H__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_hw.h b/Source/DirectFB/gfxdrivers/unichrome/uc_hw.h new file mode 100755 index 0000000..953af37 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_hw.h @@ -0,0 +1,105 @@ +// Shared header file for uc_hwmap.c and uc_hwset.c. + +#ifndef __UC_HW_H__ +#define __UC_HW_H__ + +#include + +#include + +#include "unichrome.h" +#include "uc_fifo.h" + +// GPU - mapping functions (uc_hwmap.c) + +/// Map a DirectFB destination surface pixel format to the hw. (3D) +static inline int uc_map_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HDBFM_ARGB1555; + case DSPF_ARGB4444: return HC_HDBFM_ARGB4444; + case DSPF_RGB16: return HC_HDBFM_RGB565; + case DSPF_RGB32: return HC_HDBFM_ARGB0888; + case DSPF_ARGB: return HC_HDBFM_ARGB8888; + case DSPF_AiRGB: return HC_HDBFM_ARGB8888; // limited support + + case DSPF_YUY2: + case DSPF_YV12: + case DSPF_I420: + // not supported for 3D but don't report an error + return 0; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +/// Map a DirectFB source surface pixel format to the hw. (3D) +static inline int uc_map_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HTXnFM_ARGB1555; + case DSPF_ARGB4444: return HC_HTXnFM_ARGB4444; + case DSPF_RGB16: return HC_HTXnFM_RGB565; + case DSPF_RGB32: return HC_HTXnFM_ARGB0888; + case DSPF_ARGB: return HC_HTXnFM_ARGB8888; + case DSPF_AiRGB: return HC_HTXnFM_ARGB8888; // limited support + case DSPF_A8: return HC_HTXnFM_A8; + case DSPF_LUT8: return HC_HTXnFM_Index8; + case DSPF_YUY2: return HC_HTXnFM_YUY2; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +void uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dformat ); + +void uc_map_blitflags ( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat, + DFBSurfacePixelFormat dformat ); + +// GPU - setting functions (uc_hwset.c) + +void uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_texenv ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_clip ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_3d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_color_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +#endif // __UC_HW_H__ + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_hwmap.c b/Source/DirectFB/gfxdrivers/unichrome/uc_hwmap.c new file mode 100755 index 0000000..fe1dc73 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_hwmap.c @@ -0,0 +1,362 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware mapping functions ------------------------------------------------ + +#include + +#include "uc_hw.h" +#include + +/// Map DirectFB blending functions to hardware +void +uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dst_format ) +{ + bool dst_alpha = DFB_PIXELFORMAT_HAS_ALPHA(dst_format); + + // The HW's blending equation is: + // (Ca * FCa + Cbias + Cb * FCb) << Cshift + + // Set source blending function + + // Ca -- always from source color. + hwalpha->regHABLCsat = HC_HABLCsat_MASK | HC_HABLCa_OPC | HC_HABLCa_Csrc; + // Aa -- always from source alpha. + hwalpha->regHABLAsat = HC_HABLAsat_MASK | HC_HABLAa_OPA | HC_HABLAa_Asrc; + + // FCa and FAa depend on the following condition. + switch (sblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + break; + + case DSBF_SRCALPHASAT: + // GL_SRC_ALPHA_SATURATE + if (!dst_alpha) { + // (f, f, f, 1), f = min(As, 1 - Ad) = min(As, 1 - 1) = 0 + // So (f, f, f, 1) = (0, 0, 0, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { + // (f, f, f, 1), f = min(As, 1 - Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_mimAsrcInvAdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + break; + + default: + break; + } + + // Set destination blending function + + // Op is add. + // bias is 0. + + hwalpha->regHABLCsat |= HC_HABLCbias_HABLRCbias; + hwalpha->regHABLAsat |= HC_HABLAbias_HABLRAbias; + + // Cb -- always from destination color. + hwalpha->regHABLCop = HC_HABLCb_OPC | HC_HABLCb_Cdst; + // Ab -- always from destination alpha. + hwalpha->regHABLAop = HC_HABLAb_OPA | HC_HABLAb_Adst; + + // FCb -- depends on the following condition. + switch (dblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_0; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + break; + + case DSBF_SRCALPHASAT: + // Unsupported? + + default: + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + } +} + +/// Map DFBSurfaceBlittingFlags to the hardware +void +uc_map_blitflags( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat, + DFBSurfacePixelFormat dformat ) +{ + bool gotalpha = DFB_PIXELFORMAT_HAS_ALPHA(sformat); + bool invalpha = DFB_PIXELFORMAT_INV_ALPHA(sformat) || + (!DFB_PIXELFORMAT_INV_ALPHA(sformat) && DFB_PIXELFORMAT_INV_ALPHA(dformat)); + + if (bflags & DSBLIT_COLORIZE) { + // Cv0 = Ct*Cf + + // Hw setting: + // Ca = Ct, Cb = Cf, Cop = +, Cc = 0, Cbias = 0, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_Tex | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_Dif | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_0 | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + else { + // Cv0 = Ct + + // Hw setting: + // Ca = 0, Cb = 0, Cop = +, Cc = 0, Cbias = Ct, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_0 | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_0 | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_Tex | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + + if (bflags & DSBLIT_BLEND_COLORALPHA) { + if ((bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) { + // Av0 = At*Af + + // Hw setting: + // Aa = At, Ab = Af, Cop = +, Ac = 0, Abias = 0, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_Atex | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_Adif | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { + // (!(bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) || !gotalpha + // Av0 = Af + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = Af, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Adif | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } + else { // !(bflags & DSBLIT_BLEND_COLORALPHA) + if (gotalpha && ((bflags & DSBLIT_BLEND_ALPHACHANNEL) || invalpha)) { + // Av0 = At + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = At, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Atex | HC_HTXnTBLAshift_No; + if (invalpha) + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAbias_Inv; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { // !gotalpha + // Av0 = 1.0 + + // D_BUG warning: I'm guessing where values should go, + // and how big (0xff = 1.0 ?) it should be. + + // Hw setting: + // Aa = 1.0, Ab = 1.0, Cop = -, Ac = 1.0, Abias = 1.0, Ashift = No. + // => Av = Aa*(Ab-Ac) + Abias = 1*(1-1)+1 = 1 + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Inv | HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } +} + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_hwset.c b/Source/DirectFB/gfxdrivers/unichrome/uc_hwset.c new file mode 100755 index 0000000..93fb017 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_hwset.c @@ -0,0 +1,446 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware setting functions ------------------------------------------------ + +#include + +#include "uc_hw.h" +#include +#include +#include + +/// Integer 2-logarithm, y = log2(x), where x and y are integers. +#define ILOG2(x,y) ILOG2_PORTABLE(x,y) + +#define ILOG2_PORTABLE(x,y) \ + do { \ + unsigned int i = 0; \ + y = x; \ + while (y != 0) { \ + i++; \ + y = y >> 1; \ + } \ + y = i-1; \ + } while (0) + +#define ILOG2_X86(x,y) // TODO - use BSR (bit scan reverse) instruction + +/// Set alpha blending function (3D) +void +uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_alpha *hwalpha = &ucdev->hwalpha; + + if (UC_IS_VALID( uc_blending_fn )) + return; + + uc_map_blending_fn( hwalpha, state->src_blend, state->dst_blend, + state->destination->config.format ); + + UC_FIFO_PREPARE( fifo, 14 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCsat, hwalpha->regHABLCsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCop, hwalpha->regHABLCop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAsat, hwalpha->regHABLAsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAop, hwalpha->regHABLAop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCa, hwalpha->regHABLRCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCa, hwalpha->regHABLRFCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCbias, hwalpha->regHABLRCbias ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCb, hwalpha->regHABLRCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCb, hwalpha->regHABLRFCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAa, hwalpha->regHABLRAa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAb, hwalpha->regHABLRAb ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_blending_fn ); +} + +/// Set texture environment (3D) +void +uc_set_texenv( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + if (UC_IS_VALID( uc_texenv )) + return; + + uc_map_blitflags( hwtex, state->blittingflags, state->source->config.format, + state->destination->config.format ); + + // Texture mapping method + hwtex->regHTXnTB = HC_HTXnFLSs_Linear | HC_HTXnFLTs_Linear | + HC_HTXnFLSe_Linear | HC_HTXnFLTe_Linear; + + hwtex->regHTXnMPMD = HC_HTXnMPMD_Sclamp | HC_HTXnMPMD_Tclamp; + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24) ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTB, hwtex->regHTXnTB ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnMPMD, hwtex->regHTXnMPMD ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCsat, hwtex->regHTXnTBLCsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCop, hwtex->regHTXnTBLCop_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLMPfog, hwtex->regHTXnTBLMPfog_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLAsat, hwtex->regHTXnTBLAsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRCb, hwtex->regHTXnTBLRCb_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRAa, hwtex->regHTXnTBLRAa_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRFog, hwtex->regHTXnTBLRFog_0 ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_texenv ); +} + +/// Set clipping rectangle (2D and 3D) +void +uc_set_clip( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (DFB_REGION_EQUAL( ucdev->clip, state->clip )) + return; + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + +#ifdef UC_ENABLE_3D + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipTB, + (RS12(state->clip.y1) << 12) | RS12(state->clip.y2+1) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipLR, + (RS12(state->clip.x1) << 12) | RS12(state->clip.x2+1) ); + +#endif + + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPTL, + (RS16(state->clip.y1) << 16) | RS16(state->clip.x1) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPBR, + (RS16(state->clip.y2) << 16) | RS16(state->clip.x2) ); + + UC_FIFO_CHECK( fifo ); + + ucdev->clip = state->clip; +} + +/// Set destination (2D and 3D) +void +uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + CoreSurface *destination = state->destination; + + DFBSurfacePixelFormat dst_format = destination->config.format; + int dst_offset = state->dst.offset; + int dst_pitch = state->dst.pitch; + int dst_height = destination->config.size.h; + int dst_bpp = DFB_BYTES_PER_PIXEL( dst_format ); + + + /* Save FIFO space and CPU cycles. */ + if (ucdev->dst_format == dst_format && + ucdev->dst_offset == dst_offset && + ucdev->dst_pitch == dst_pitch && + ucdev->dst_height == dst_height) + return; + + // 2D engine setting + + ucdev->pitch = (ucdev->pitch & 0x7fff) | (((dst_pitch >> 3) & 0x7fff) << 16); + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, (VIA_PITCH_ENABLE | ucdev->pitch) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, (dst_offset >> 3) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_GEMODE, (dst_bpp - 1) << 8 ); + +#ifdef UC_ENABLE_3D + // 3D engine setting + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasL, dst_offset & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasH, dst_offset >> 24 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBFM, (uc_map_dst_format( dst_format ) | + (dst_pitch & HC_HDBPit_MASK) | + HC_HDBLoc_Local) ); + + UC_FIFO_PAD_EVEN(fifo); +#endif + + UC_FIFO_CHECK( fifo ); + + ucdev->dst_format = dst_format; + ucdev->dst_offset = dst_offset; + ucdev->dst_pitch = dst_pitch; + ucdev->dst_height = dst_height; +} + +/// Set new source (2D) +void +uc_set_source_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_source2d )) + return; + + ucdev->pitch &= 0x7fff0000; + ucdev->pitch |= (state->src.pitch >> 3) & 0x7fff; + + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, state->src.offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, VIA_PITCH_ENABLE | ucdev->pitch ); + + UC_FIFO_CHECK( fifo ); + + ucdev->src_offset = state->src.offset; + ucdev->src_pitch = state->src.pitch; + ucdev->src_height = state->source->config.size.h; + + UC_VALIDATE( uc_source2d ); +} + +/// Set new source (3D) +void +uc_set_source_3d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + CoreSurface *source = state->source; + + int src_height, src_offset, src_pitch; + + if (UC_IS_VALID( uc_source3d )) + return; + + src_height = source->config.size.h; + src_offset = state->src.offset; + src_pitch = state->src.pitch; + + /* + * TODO: Check if we can set the odd/even field as L1/L2 texture and select + * between L0/L1/L2 upon blit. Otherwise we depend on SMF_BLITTINGFLAGS ;( + */ + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + if (source->field) + src_offset += src_pitch; + + src_height >>= 1; + src_pitch <<= 1; + } + + ucdev->field = source->field; + + // Round texture size up to nearest + // value evenly divisible by 2^n + + ILOG2(source->config.size.w, hwtex->we); + hwtex->l2w = 1 << hwtex->we; + if (hwtex->l2w < source->config.size.w) { + hwtex->we++; + hwtex->l2w <<= 1; + } + + ILOG2(src_height, hwtex->he); + hwtex->l2h = 1 << hwtex->he; + if (hwtex->l2h < src_height) { + hwtex->he++; + hwtex->l2h <<= 1; + } + + hwtex->format = uc_map_src_format_3d( source->config.format ); + + UC_FIFO_PREPARE( fifo, 10); + + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24)); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnFM, HC_HTXnLoc_Local | hwtex->format ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0OS, (0 << HC_HTXnLVmax_SHIFT) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5WE, hwtex->we ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5HE, hwtex->he ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL012BasH, (src_offset >> 24) & 0xff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0BasL, (src_offset ) & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0Pit, (HC_HTXnEnPit_MASK | src_pitch) ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + // Upload the palette of a 256 color texture. + + if (hwtex->format == HC_HTXnFM_Index8) { + int i, num; + DFBColor *colors; + + UC_FIFO_PREPARE( fifo, 258 ); + + UC_FIFO_ADD_HDR( fifo, ((HC_ParaType_Palette << 16) | + (HC_SubType_TexPalette0 << 24)) ); + + colors = source->palette->entries; + num = source->palette->num_entries; + + if (num > 256) + num = 256; + + /* What about the last entry? -- dok */ + for (i = 0; i < num; i++) + UC_FIFO_ADD( fifo, PIXEL_ARGB(colors[i].a, colors[i].r, + colors[i].g, colors[i].b) ); + + for (; i < 256; i++) + UC_FIFO_ADD( fifo, 0 ); + + UC_FIFO_CHECK( fifo ); + } + + ucdev->src_offset = src_offset; + ucdev->src_pitch = src_pitch; + ucdev->src_height = src_height; + + UC_VALIDATE( uc_source3d ); +} + +/// Set either destination color key, or fill color, as needed. (2D) +void +uc_set_color_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + u32 color = 0; + + if (UC_IS_VALID( uc_color2d )) + return; + + switch (state->destination->config.format) { + case DSPF_ARGB1555: + color = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + color |= color << 16; + break; + + case DSPF_ARGB4444: + color = PIXEL_ARGB4444( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + color |= color << 16; + break; + + case DSPF_RGB16: + color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b); + color |= color << 16; + break; + + case DSPF_RGB32: + case DSPF_ARGB: + color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + + case DSPF_AiRGB: + color = PIXEL_AiRGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + + default: + D_BUG( "unexpected pixel format" ); + } + + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + // Opaque line drawing needs this + UC_FIFO_ADD_2D( fifo, VIA_REG_MONOPAT0, 0xff ); + + UC_FIFO_ADD_2D( fifo, VIA_REG_KEYCONTROL, 0 ); + UC_FIFO_ADD_2D( fifo, VIA_REG_FGCOLOR, color ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_color2d ); + UC_INVALIDATE( uc_colorkey2d ); +} + +void +uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_colorkey2d )) + return; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, VIA_KEY_ENABLE_SRCKEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_BGCOLOR, state->src_colorkey ); + } + else if (state->blittingflags & DSBLIT_DST_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, + VIA_KEY_ENABLE_DSTKEY | VIA_KEY_INVERT_KEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_FGCOLOR, state->dst_colorkey ); + } + else { + UC_FIFO_PREPARE( fifo, 4 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, 0 ); + } + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_colorkey2d ); + UC_INVALIDATE( uc_color2d ); +} + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_ioctl.h b/Source/DirectFB/gfxdrivers/unichrome/uc_ioctl.h new file mode 100755 index 0000000..7836024 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_ioctl.h @@ -0,0 +1,35 @@ +// Definitions of framebuffer ioctls + +#ifndef __UC_IOCTL_H__ +#define __UC_IOCTL_H__ + +#include +#include +#include + +// Parameters for FBIO_FLIPONVSYNC ioctl +struct fb_flip { + u32 device; + u32 field; + u32 count; + u32 offset[6]; +}; + +#define VIAFB_FLIP_GRAPHICS 0 +#define VIAFB_FLIP_V1 1 +#define VIAFB_FLIP_V3 2 +#define VIAFB_FLIP_SPIC 3 +#define VIAFB_FLIP_NOP 255 + +#ifndef FBIO_FLIPONVSYNC +#define FBIO_FLIPONVSYNC _IOWR('F', 0x21, struct fb_flip) +#endif + +// Parameters for FBIO_WAITFORVSYNC ioctl +#define VIAFB_WAIT_ANY 0 +#define VIAFB_WAIT_TOPFIELD 1 +#define VIAFB_WAIT_BOTTOMFIELD 2 +#define VIAFB_WAIT_FLIP 3 + +#endif // __UC_IOCTL_H__ + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.c b/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.c new file mode 100755 index 0000000..4402cb3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.c @@ -0,0 +1,405 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "uc_ioctl.h" +#include "vidregs.h" +#include "mmio.h" + +#include +#include + +#include + +#include + +#include + +// Forward declaration +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data); + + +static int uc_ovl_datasize( void ) +{ + return sizeof(UcOverlayData); +} + + +static DFBResult +uc_ovl_init_layer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + + // Save a pointer to the layer data for access by the primary + // This is needed to properly support levels and the primary alpha channel + + ucdrv->ovl = ucovl; + + // Set layer type, capabilities and name + + description->caps = UC_OVL_CAPS; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA Unichrome Video"); + + adjustment->flags = DCAF_NONE; + + // Fill out the default configuration + + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + + ucovl->v1.win.w = 720; + ucovl->v1.win.h = 576; + ucovl->v1.win.x = 0; + ucovl->v1.win.y = 0; + + config->width = 720; + config->height = 576; + + config->pixelformat = DSPF_YV12; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + // Reset overlay + + ucovl->extfifo_on = false; + ucovl->hwrev = ucdrv->hwrev; + ucovl->scrwidth = ucovl->v1.win.w; + + ucovl->v1.isenabled = false; + ucovl->v1.cfg = *config; + ucovl->v1.ox = 0; + ucovl->v1.oy = 0; + ucovl->v1.dst_key.index = 0; + ucovl->v1.dst_key.r = 0; + ucovl->v1.dst_key.g = 0; + ucovl->v1.dst_key.b = 0; + ucovl->v1.dstkey_enabled = false; + ucovl->v1.opacity = 0xff; + ucovl->v1.level = 1; + +// adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | +// DCAF_HUE | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + ucovl->v1.adj = *adjustment; + + uc_ovl_remove(layer, driver_data, layer_data, NULL); + + return DFB_OK; +} + + +static DFBResult +uc_ovl_set_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + DFBRectangle win; + + /* remember configuration */ + ucovl->config = *config; + + /* get new destination rectangle */ + win = config->dest; + + // Bounds checking + if ((win.x < -8192) || (win.x > 8192) || + (win.y < -8192) || (win.y > 8192) || + (win.w < 32) || (win.w > 4096) || + (win.h < 32) || (win.h > 4096)) + { + D_DEBUG("Layer size or position is out of bounds."); + return DFB_INVAREA; + } + + ucovl->v1.isenabled = true; + ucovl->v1.win = win; + ucovl->v1.dst_key = config->dst_key; + ucovl->v1.dstkey_enabled = config->options & DLOP_DST_COLORKEY; + + if (config->options & DLOP_OPACITY) + ucovl->v1.opacity = config->opacity; + else + ucovl->v1.opacity = 0xff; + + // printf("uc_overlay: color-keying is %s\n", + // ucovl->v1.dstkey_enabled ? "enabled" : "disabled"); + + ucovl->deinterlace = config->options & DLOP_DEINTERLACING; + ucovl->surface = surface; + ucovl->lock = lock; + + if (ucdrv->canfliponvsync) { + FBDev *dfb_fbdev = dfb_system_data(); + int field_option = VIAFB_WAIT_FLIP; // wait for any pending flip + ioctl(dfb_fbdev->fd, FBIO_WAITFORVSYNC, &field_option); + } + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_CHANGE, surface, lock); +} + + +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + volatile u8* vio = ucdrv->hwregs; + + ucovl->v1.isenabled = false; + + uc_ovl_vcmd_wait(vio); + + VIDEO_OUT(vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL(16,12,8)); + // VIDEO_OUT(vio, ALPHA_V3_FIFO_CONTROL, 0x0407181f); + + if (ucovl->hwrev >= 0x10) { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0); + } + else { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); + } + + VIDEO_OUT(vio, HQV_CONTROL, VIDEO_IN(vio, HQV_CONTROL) & ~HQV_ENABLE); + VIDEO_OUT(vio, V1_CONTROL, VIDEO_IN(vio, V1_CONTROL) & ~V1_ENABLE); + // VIDEO_OUT(vio, V3_CONTROL, VIDEO_IN(vio, V3_CONTROL) & ~V3_ENABLE); + + VIDEO_OUT(vio, V_COMPOSE_MODE, + (VIDEO_IN(vio, V_COMPOSE_MODE) & ~ENABLE_COLOR_KEYING) | V1_COMMAND_FIRE); + + ucovl->surface = NULL; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_test_region(CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed) +{ + CoreLayerRegionConfigFlags fail = 0; + + // Check layer options + + if (config->options & ~UC_OVL_OPTIONS) + fail |= CLRCF_OPTIONS; + + // Check pixelformats + + switch (config->format) { + case DSPF_YUY2: + break; + case DSPF_UYVY: + fail |= CLRCF_FORMAT; // Nope... doesn't work. + break; + case DSPF_I420: + case DSPF_YV12: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + fail |= CLRCF_FORMAT; + } + + // Check width and height + + if (config->width > 4096 || config->width < 32) + fail |= CLRCF_WIDTH; + + if (config->height > 4096 || config->height < 32) + fail |= CLRCF_HEIGHT; + + if (failed) *failed = fail; + if (fail) return DFB_UNSUPPORTED; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_flip_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + //printf("Entering %s ... \n", __PRETTY_FUNCTION__); + + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + DFBResult ret; + FBDev *dfb_fbdev = dfb_system_data(); + + dfb_surface_flip(surface, false); + + ucovl->field = 0; + ucovl->lock = lock; + + if (ucdrv->canfliponvsync) + { + if (ucovl->config.options & DLOP_FIELD_PARITY) + { + struct fb_flip flip; + int field_option; + + field_option = VIAFB_WAIT_FLIP; // ensure last pending flip complete + ioctl(dfb_fbdev->fd, FBIO_WAITFORVSYNC, &field_option); + + flip.device = VIAFB_FLIP_V1; + flip.field = ucovl->config.parity; + flip.count = 0; // until we implement this + + uc_ovl_map_buffer(surface->config.format, + lock->offset, + ucovl->v1.ox, ucovl->v1.oy, surface->config.size.w, surface->config.size.h, + lock->pitch, 0, + &flip.offset[0], &flip.offset[1], &flip.offset[2]); + + ioctl(dfb_fbdev->fd, FBIO_FLIPONVSYNC, &flip); + } + else + { + ret = uc_ovl_update(ucdrv, ucovl, UC_OVL_FLIP, surface, lock); + if (ret) + return ret; + } + } + else + { + if (ucovl->config.options & DLOP_FIELD_PARITY) + { + int field_option; + + if (ucovl->config.parity == 0) // top field first? + field_option = VIAFB_WAIT_BOTTOMFIELD; + else + field_option = VIAFB_WAIT_TOPFIELD; + ioctl(dfb_fbdev->fd, FBIO_WAITFORVSYNC, &field_option); + // that actually waits for VBLANK so we need a further delay + // to be sure the field has started and that the flip will + // take effect on the next field + usleep(2500); + } + + ret = uc_ovl_update(ucdrv, ucovl, UC_OVL_FLIP, surface, lock); + if (ret) + return ret; + } + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync(layer); + + return DFB_OK; +} + +static DFBResult +uc_ovl_get_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int *level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + *level = ucovl->v1.level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (level == 0) return DFB_INVARG; + + if (level < 0) { + // Enable underlay mode. + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, + uc_ovl_map_alpha(ucovl->opacity_primary)); + } + else { + // Enable overlay mode (default) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, + uc_ovl_map_alpha(ucovl->v1.opacity)); + } + VIDEO_OUT(ucdrv->hwregs, V_COMPOSE_MODE, V1_COMMAND_FIRE | + (ucovl->v1.dstkey_enabled ? ENABLE_COLOR_KEYING : 0)); + + ucovl->v1.level = level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_input_field( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + ucovl->field = field; + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_FIELD, ucovl->surface, ucovl->lock); +} + +DisplayLayerFuncs ucOverlayFuncs = { + .LayerDataSize = uc_ovl_datasize, + .InitLayer = uc_ovl_init_layer, + .SetRegion = uc_ovl_set_region, + .RemoveRegion = uc_ovl_remove, + .TestRegion = uc_ovl_test_region, + .FlipRegion = uc_ovl_flip_region, + .GetLevel = uc_ovl_get_level, + .SetLevel = uc_ovl_set_level, + .SetInputField = uc_ovl_set_input_field, +// .SetColorAdjustment = uc_ovl_set_adjustment, +}; diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.h b/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.h new file mode 100755 index 0000000..123a5e0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_overlay.h @@ -0,0 +1,98 @@ +#ifndef __UC_OVERLAY_H__ +#define __UC_OVERLAY_H__ + +#define UC_OVL_CAPS (DLCAPS_SURFACE | DLCAPS_OPACITY | DLCAPS_SCREEN_LOCATION \ + | DLCAPS_DEINTERLACING | DLCAPS_DST_COLORKEY | DLCAPS_LEVELS \ + | DLCAPS_FIELD_PARITY ) +/* | DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST \ + | DLCAPS_SATURATION | DLCAPS_HUE) + */ +#define UC_OVL_OPTIONS (DLOP_DEINTERLACING | DLOP_DST_COLORKEY \ + | DLOP_FIELD_PARITY | DLOP_OPACITY ) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) +#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ + (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) + +// Actions for uc_ovl_update() + +#define UC_OVL_FLIP 1 +#define UC_OVL_CHANGE 2 +#define UC_OVL_FIELD 4 + +/** Overlay layer data. */ +struct uc_ovl_vinfo { + bool isenabled; // True when visible + DFBRectangle win; // Layer screen rectangle. + DFBDisplayLayerConfig cfg; // Layer configuration + int ox, oy; // Top-left visible corner (the offset) + // in the source surface + u8 opacity; // Layer opacity + int level; // Position in the DirectFB layer stack + // < 0 = underlay mode, > 0 = overlay mode + DFBColorAdjustment adj; // Color adjustment (brightness etc) + DFBColorKey dst_key; // Destination color key + bool dstkey_enabled; // Destination color key is enabled +}; + +typedef struct _UcOverlayData { + + // TODO: initialize the variables!!! + + u8 hwrev; // Unichrome revision + int scrwidth; // Current screen width + + bool extfifo_on; // True when we're using the extended fifo. + u8 mclk_save[3]; + + struct uc_ovl_vinfo v1; // Video overlay V1 + + CoreLayerRegionConfig config; + + bool deinterlace; + int field; + + CoreSurface *surface; + CoreSurfaceBufferLock *lock; + + int opacity_primary; // overlay opacity if primary is logically + // above or -1 if primary has alpha channel + +} UcOverlayData; + + +// Video engine - mapping functions (uc_ovl_hwmap.c) + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini); +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount); +u32 uc_ovl_map_qwfetch(int falign, DFBSurfacePixelFormat format, int pfetch); +u32 uc_ovl_map_format(DFBSurfacePixelFormat format); +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, + int* ox, int* oy, int *pfetch); +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int x, int y, int w, int h, int pitch, int field, + u32* y_start, u32* u_start, u32* v_start); +u32 uc_ovl_map_alpha(int opacity); +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo); +u32 uc_ovl_map_fifo(u8 depth, u8 pre_thr, u8 thr); +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2); +u32 uc_ovl_map_colorkey(DFBColorKey* c); + +// Video engine - setting functions (uc_ovl_hwset.c) + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth); +void uc_ovl_vcmd_wait(volatile u8* vio); +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock); +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj); + +#endif // __UC_OVERLAY_H__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwmap.c b/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwmap.c new file mode 100755 index 0000000..9306b59 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwmap.c @@ -0,0 +1,609 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" +#include + +/** + * Map hw settings for vertical scaling. + * + * @param sh source height + * @param dh destination height + * @param zoom will hold vertical setting of zoom register. + * @param mini will hold vertical setting of mini register. + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomHeight() + */ + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini) +{ + u32 sh1, tmp, d; + bool zoom_ok = true; + + if (sh == dh) { // No zoom + // Do nothing + } + else if (sh < dh) { // Zoom in + + tmp = (sh * 0x0400) / dh; + zoom_ok = !(tmp > 0x3ff); + + *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + else { // sw > dh - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sh1 = sh; + for (d = 1; d < 5; d++) { + sh1 >>= 1; + if (sh1 <= dh) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + *mini |= ((d<<1)-1) << 16; // <= {1,3,5,7} << 16 + + // Add scaling + + if (sh1 < dh) { + tmp = (sh1 * 0x400) / dh; + *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + } + + return zoom_ok; +} + + +/** + * Map hw settings for horizontal scaling. + * + * @param sw source width + * @param dw destination width + * + * @param zoom will hold horizontal setting of zoom register. + * @param mini will hold horizontal setting of mini register. + * @param falign will hold fetch aligment + * @param dcount will hold display count + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() + */ +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount) +{ + u32 tmp, sw1, d; + int md; // Minify-divider + bool zoom_ok = true; + + md = 1; + *falign = 0; + + if (sw == dw) { // No zoom + // Do nothing + } + else if (sw < dw) { // Zoom in + + tmp = (sw * 0x0800) / dw; + zoom_ok = !(tmp > 0x7ff); + + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + *mini |= V1_X_INTERPOLY; + } + else { // sw > dw - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sw1 = sw; + for (d = 1; d < 5; d++) { + sw1 >>= 1; + if (sw1 <= dw) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + md = 1 << d; // <= {2,4,8,16} + *falign = ((md<<1)-1) & 0xf; // <= {3,7,15,15} + *mini |= V1_X_INTERPOLY; + *mini |= ((d<<1)-1) << 24; // <= {1,3,5,7} << 24 + + // Add scaling + + if (sw1 < dw) { + //CLE bug + //tmp = sw1*0x0800 / dw; + tmp = (sw1 - 2) * 0x0800 / dw; + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + } + } + + *dcount = sw - md; + + return zoom_ok; +} + + +/** + * @param falign fetch alignment + * @param format overlay pixel format + * @param pfetch source pixels per line + * + * @returns qword fetch register setting + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() + * @note Only call after uc_ovl_map_hzoom() + */ +u32 uc_ovl_map_qwfetch(int falign, DFBSurfacePixelFormat format, int pfetch) +{ + int fetch = 0; + + switch (format) { + case DSPF_YV12: + fetch = ALIGN_TO(pfetch, 32) >> 4; + break; + case DSPF_I420: + fetch = (ALIGN_TO(pfetch, 16) >> 4) + 1; + break; + case DSPF_UYVY: + case DSPF_YUY2: + fetch = (ALIGN_TO(pfetch << 1, 16) >> 4) + 1; + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + fetch = (ALIGN_TO(pfetch << 1, 16) >> 4) + 1; + break; + case DSPF_RGB32: + case DSPF_ARGB: + fetch = (ALIGN_TO(pfetch << 2, 16) >> 4) + 1; + break; + default: + D_BUG("Unexpected pixelformat!"); + break; + } + + if (fetch < 4) fetch = 4; + + // Note: Unsure if alignment is needed or is in the way. + fetch = ALIGN_TO(fetch, falign + 1); + return fetch << 20; // V12_QWORD_PER_LINE +} + + +/** + * Map pixel format. + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() + */ +u32 uc_ovl_map_format(DFBSurfacePixelFormat format) +{ + switch (format) { + case DSPF_YV12: + case DSPF_I420: + return V1_COLORSPACE_SIGN | V1_YUV420; + case DSPF_UYVY: + case DSPF_YUY2: + return V1_COLORSPACE_SIGN | V1_YUV422; + case DSPF_ARGB1555: + return V1_RGB15; + case DSPF_RGB16: + return V1_RGB16; + case DSPF_RGB32: + case DSPF_ARGB: + return V1_RGB32; + default : + D_BUG("Unexpected pixelformat!"); + return V1_YUV422; + } +} + + +/** + * Map overlay window. + * + * @param scrw screen width (eg. 800) + * @param scrh screen height (eg. 600) + * @param win destination window + * @param sw source surface width + * @param sh source surface height + * + * @param win_start will hold window start register setting + * @param win_end will hold window end register setting + * + * @parm ox will hold new leftmost coordinate in source surface + * @parm oy will hold new topmost coordinate in source surface + * @parm pfetch will hold number of required source pixels per line + */ +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, + int* ox, int* oy, int *pfetch) +{ + int x1, y1, x2, y2; + int x,y,dw,dh; // These help making the code readable... + + *ox = 0; + *oy = 0; + *win_start = 0; + *win_end = 0; + + x = win->x; + y = win->y; + dw = win->w; + dh = win->h; + + // For testing the clipping + //scrw -= 100; + //scrh -= 100; + + // Handle invisible case. + if ((x > scrw) || (y > scrh) || (x+dw < 0) || (y+dh < 0)) return; + + // Vertical clipping + + if ((y >= 0) && (y+dh < scrh)) { + // No clipping + y1 = y; + y2 = y+dh-1; + } + else if ((y < 0) && (y+dh < scrh)) { + // Top clip + y2 = y+dh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + y1 = ((4-*oy)&3)*dh/sh; + *oy = (*oy + 3) & ~3; + } + else if ((y >= 0) && (y+dh >= scrh)) { + // Bottom clip + y1 = y; + y2 = scrh-1; + } + else { // if (y < 0) && (y+dh >= scrh) + // Top and bottom clip + y2 = scrh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + y1 = ((4-*oy)&3)*dh/sh; + *oy = (*oy + 3) & ~3; + } + + // Horizontal clipping + + if ((x >= 0) && (x+dw < scrw)) { + // No clipping + x1 = x; + x2 = x+dw-1; + *pfetch = sw; + } + else if ((x < 0) && (x+dw < scrw)) { + // Left clip + x2 = x+dw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + x1 = ((32-*ox)&31)*dw/sw; + *ox = (*ox + 31) & ~31; + *pfetch = sw - *ox; + } + else if ((x >= 0) && (x+dw >= scrw)) { + // Right clip + x1 = x; + x2 = scrw-1; + *pfetch = sw - (x+dw-scrw)*sw/dw; + } + else { // if (x < 0) && (x+dw >= scrw) + // Left and right clip + x2 = scrw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + x1 = ((32-*ox)&31)*dw/sw; + *ox = (*ox + 31) & ~31; + *pfetch = sw - *ox - (x+dw-scrw)*sw/dw; + } + + if (*pfetch < 0) + *pfetch = 0; + + *win_start = (x1 << 16) | y1; + *win_end = (x2 << 16) | y2; + + // For testing the clipping + //*win_start = ((x1+50) << 16) | (y1+50); + //*win_end = ((x2+50) << 16) | (y2+50); +} + + +/** + * Map overlay buffer address. + * + * @param format pixel format + * @param buf Framebuffer address of surface (0 = start of framebuffer) + * @param ox leftmost pixel to show (used when clipping, else set to zero) + * @param oy topmost pixel to show (used when clipping, else set to zero) + * @param w total surface width (does *not* depend on the x parameter) + * @param h total surface height (does *not* depend on the y parameter) + * @param pitch source surface pitch (bytes per pixel) + * + * @param y_start will hold start address of Y(UV) or RGB buffer + * @param u_start will hold start address of Cb buffer (planar modes only) + * @param v_start will hold start address of Cr buffer (planar modes only) + * + * @note Derived from VIA's V4L driver. See ddover.c, + * DDOver_GetSrcStartAddress() and DDOVer_GetYCbCrStartAddress() + */ +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int ox, int oy, int sw, int sh, int sp, int field, + u32* y_start, u32* u_start, u32* v_start) +{ + int swap_cb_cr = 0; + + u32 tmp; + u32 y_offset, uv_offset = 0; + + switch (format) { + + case DSPF_YUY2: + case DSPF_UYVY: + y_offset = ((oy * sp) + ((ox << 1) & ~15)); + break; + + case DSPF_YV12: + swap_cb_cr = 1; + case DSPF_I420: + y_offset = ((((oy & ~3) * sp) + ox + 16) & ~31) ; + if (oy > 0) + uv_offset = (((((oy & ~3) >> 1) * sp) + ox + 16) & ~31) >> 1; + else + uv_offset = y_offset >> 1; + break; + + case DSPF_ARGB1555: + case DSPF_RGB16: + y_offset = (oy * sp) + ((ox * 16) >> 3); + break; + + case DSPF_RGB32: + case DSPF_ARGB: + y_offset = (oy * sp) + ((ox * 32) >> 3); + break; + + default: + y_offset = 0; + uv_offset = 0; + D_BUG("Unexpected pixelformat!"); + } + + if (field) { + y_offset += sp; + uv_offset += sp >> 1; + } + + *y_start = buf + y_offset; + + if (u_start && v_start) { + *u_start = buf + sp * sh + uv_offset; + *v_start = buf + sp * sh + sp * (sh >> 2) + uv_offset; + + if (swap_cb_cr) { + tmp = *u_start; + *u_start = *v_start; + *v_start = tmp; + } + } +} + + +/** + * Map alpha mode and opacity. + * + * @param opacity Alpha opacity: 0 = transparent, 255 = opaque. + * -1 = Use alpha from underlying graphics. + * + * @returns alpha control register setting. + * + * @note: Unfortunately, if using alpha from underlying graphics, + * the video is opaque if alpha = 255 and transparent if = 0. + * The inverse would have made more sense ... + * + * @note: The hardware supports a separate alpha plane as well, + * but it is not implemented here. + * + * @note: Derived from ddmpeg.c, VIAAlphaWin() + */ + +u32 uc_ovl_map_alpha(int opacity) +{ + u32 ctrl = 0x00080000; // Not sure what this number is, supposedly + // it is the "expire number divided by 4". + + if (opacity > 255) opacity = 255; + + if (opacity < 0) { + ctrl |= ALPHA_WIN_BLENDING_GRAPHIC; + } + else { + opacity = opacity >> 4; // Throw away bits 0 - 3 + ctrl |= (opacity << 12) | ALPHA_WIN_BLENDING_CONSTANT; + } + + return ctrl; // V_ALPHA_CONTROL +} + +/** + * Calculate V1 control and fifo-control register values + * @param format pixel format + * @param sw source width + * @param hwrev Unichrome hardware revision + * @param extfifo_on set this true if the extended FIFO is enabled + * @param control will hold value for V1_CONTROL + * @param fifo will hold value for V1_FIFO_CONTROL + */ +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo) +{ + *control = V1_BOB_ENABLE | V1_ENABLE | uc_ovl_map_format(format); + + if (hwrev >= 0x10) { + *control |= V1_EXPIRE_NUM_F; + } + else { + if (extfifo_on) { + *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; + } + else { + *control |= V1_EXPIRE_NUM; + } + } + + if ((format == DSPF_YV12) || (format == DSPF_I420)) { + //Minified video will be skewed without this workaround. + if (sw <= 80) { //Fetch count <= 5 + *fifo = UC_MAP_V1_FIFO_CONTROL(16,0,0); + } + else { + if (hwrev == 0x10) + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(16,12,8); + } + } + else { + if (hwrev >= 0x10) { + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); // Default rev 0x10 + } + else { + if (extfifo_on) + *fifo = UC_MAP_V1_FIFO_CONTROL(48,40,40); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(32,29,16); // Default + } + } +} + +/** uc_ovl_map_adjustment() helper - clamp x to [lo, hi] */ +static float clamp(float x, float lo, float hi) +{ + return (x < lo) ? lo : ((x > hi) ? hi : x); /* 2 nested if's. */ +} + +/** + * uc_ovl_map_adjustment() helper - format x for the hardware. + * + * @param x The value to format. + * @param ndec Number of binary decimals. + * @param sbit sign bit position. + * =0: use two's complement representation + * >0: use a sign bit + positive value. + * @param mask Bitmask + * @param shift Position in hardware register. + */ +static int fmt(float x, int ndec, int sbit, u32 mask, int shift) +{ + int y = (x * (1 << ndec)); + if (sbit && (y < 0)) y = -y | (1 << sbit); + return (((u32) y) & mask) << shift; +} + +/** + * Map color adjustment to Unichrome hardware. + * + * @param adj DirectFB color adjustment. All fields are assumed valid. + * @param a1 Will hold value for V1_ColorSpaceReg_1 + * @param a2 Will hold value for V1_ColorSpaceReg_2 + */ +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2) +{ + float con, sat, bri, hue; + float c, s; + float A, B1, C1, D, B2, C2, B3, C3; + + // Map contrast to [0, 2.0] (preferred: [0, 1.66]), default: 1.0. + con = (float) adj->contrast / 32768.0; + // Map saturation to [0, 2.0], default: 1.0. + sat = (float) adj->saturation / 32768.0; + // Map brightness to [-121, 125], (preferred: [-94, 125.1]), default: 3.97. + bri = (float) (adj->brightness - 31696) / 270.48; + // Map hue to [-pi, pi], default is 0.0. + hue = (float) (adj->hue - 32768) / 10430.378; + // Note: The limits are estimates that need testing. + + // Map parameters to hw registers. + + s = sin(hue) * con * sat; + c = cos(hue) * con * sat; + + A = clamp(1.164*con, 0, 1.9375); + B1 = clamp(-1.596*s, -0.75, 0.75); + C1 = clamp(1.596*c, 1, 2.875); + B2 = clamp( (0.813*s - 0.391*c), 0, -0.875); + C2 = clamp(-(0.813*c + 0.391*s), 0, -1.875); + B3 = clamp(2.018*c, 0, 3.75); + C3 = clamp(2.018*s, -1.25, 1.25); + D = clamp(1.164*(bri-16), -128, 127); + + *a1 = + fmt(A, 4, 0, 0x1f, 24) | fmt(B1, 2, 2, 0x07, 18) | + fmt(C1, 3, 0, 0x1f, 9) | fmt(D, 0, 0, 0xff, 0); + + *a2 = + fmt(B2, 3, 4, 0x7, 25) | fmt(C2, 3, 4, 0xf, 17) | + fmt(B3, 2, 0, 0xf, 10) | fmt(C3, 2, 3, 0xf, 2); +} + +u32 uc_ovl_map_colorkey(DFBColorKey* c) +{ + u32 color; + DFBSurfacePixelFormat fmt; + + color = 0; + fmt = dfb_primary_layer_pixelformat(); + + switch (fmt) + { + case DSPF_ARGB1555: + color = PIXEL_ARGB1555(0, c->r, c->g, c->b); + break; + + case DSPF_RGB16: + color = PIXEL_RGB16(c->r, c->g, c->b); + break; + + case DSPF_RGB24: + case DSPF_RGB32: + case DSPF_ARGB: + color = PIXEL_ARGB(0, c->r, c->g, c->b); + break; + + case DSPF_AiRGB: + color = PIXEL_AiRGB(0, c->r, c->g, c->b); + break; + + default: + D_BUG( "unexpected pixel format" ); + } + + return color; +} diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwset.c b/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwset.c new file mode 100755 index 0000000..f601408 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_ovl_hwset.c @@ -0,0 +1,283 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +#include + +#include + +/** + * Set up the extended video FIFO. + * @note It will be turned on if ucovl->scrwidth > 1024. + */ + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth) +{ + u8* mclk_save = ucovl->mclk_save; + + if (!iopl(3)) { + if (scrwidth <= 1024) { // Disable + if (ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + outb(0x16, 0x3c4); outb(mclk_save[0], 0x3c5); + outb(0x17, 0x3c4); outb(mclk_save[1], 0x3c5); + outb(0x18, 0x3c4); outb(mclk_save[2], 0x3c5); + ucovl->extfifo_on = false; + } + } + else { // Enable + if (!ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + // Save current setting + outb(0x16, 0x3c4); mclk_save[0] = inb(0x3c5); + outb(0x17, 0x3c4); mclk_save[1] = inb(0x3c5); + outb(0x18, 0x3c4); mclk_save[2] = inb(0x3c5); + // Enable extended FIFO + outb(0x17, 0x3c4); outb(0x2f, 0x3c5); + outb(0x16, 0x3c4); outb((mclk_save[0] & 0xf0) | 0x14, 0x3c5); + outb(0x18, 0x3c4); outb(0x56, 0x3c5); + ucovl->extfifo_on = true; + } + } + } + else { + D_BUG( "Unichrome: could set io perissons\n" ); + } + ucovl->scrwidth = scrwidth; +} + +void uc_ovl_vcmd_wait(volatile u8* vio) +{ + while ((VIDEO_IN(vio, V_COMPOSE_MODE) + & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); +} + +/** + * Update the video overlay. + * + * @param action = UC_OVL_CHANGE: update everything + * = UC_OVL_FLIP: only flip to the front surface buffer. + * @param surface source surface + * + * @note: Derived from ddmpeg.c, Upd_Video() + */ + +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, + int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock) +{ + int sw, sh, sp, sfmt; // Source width, height, pitch and format + int dx, dy; // Destination position + int dw, dh; // Destination width and height + int pfetch; // Source pixels required for one line + VideoMode *videomode; + DFBRectangle scr; // Screen size + u32 dst_key = 0; // Destination color key (hw format) + + bool write_buffers = false; + bool write_settings = false; + + volatile u8* vio = ucdrv->hwregs; + + u32 win_start, win_end; // Overlay register settings + u32 zoom, mini; + u32 dcount, falign, qwfetch; + u32 y_start, u_start, v_start; + u32 v_ctrl, fifo_ctrl; + u32 alpha = 0; + + int offset = lock->offset; + + if (!ucovl->v1.isenabled) return DFB_OK; + + qwfetch = 0; + + // Get screen size + videomode = dfb_system_current_mode(); + scr.w = videomode ? videomode->xres : 720; + scr.h = videomode ? videomode->yres : 576; + scr.x = 0; + scr.y = 0; + + if (ucovl->scrwidth != scr.w) { + // FIXME: fix uc_ovl_setup_fifo() + // uc_ovl_setup_fifo(ucovl, scr.w); + action |= UC_OVL_CHANGE; + } + + D_ASSERT(surface); + + sw = surface->config.size.w; + sh = surface->config.size.h; + sp = lock->pitch; + sfmt = surface->config.format; + + if (ucovl->deinterlace) { + /*if (ucovl->field) + offset += sp;*/ + + sh /= 2; + //sp *= 2; + } + + if (action & UC_OVL_CHANGE) { + + if ((sw > 4096) || (sh > 4096) || + (sw < 32) || (sh < 1) || (sp > 0x1fff)) { + D_DEBUG("Layer surface size is out of bounds."); + return DFB_INVAREA; + } + + dx = ucovl->v1.win.x; + dy = ucovl->v1.win.y; + dw = ucovl->v1.win.w; + dh = ucovl->v1.win.h; + + // Get image format, FIFO size, etc. + + uc_ovl_map_v1_control(sfmt, sw, ucovl->hwrev, ucovl->extfifo_on, + &v_ctrl, &fifo_ctrl); + + if (ucovl->deinterlace) { + v_ctrl |= /*V1_BOB_ENABLE |*/ V1_FRAME_BASE; + } + + // Get layer window. + // The parts that fall outside the screen are clipped. + + uc_ovl_map_window(scr.w, scr.h, &(ucovl->v1.win), sw, sh, + &win_start, &win_end, + &ucovl->v1.ox, &ucovl->v1.oy, &pfetch); + + // Get scaling and data-fetch parameters + + // Note: the *_map_?zoom() functions return false if the scaling + // is out of bounds. We don't act on it for now, because it only + // makes the display look strange. + + zoom = 0; + mini = 0; + + uc_ovl_map_vzoom(sh, dh, &zoom, &mini); + uc_ovl_map_hzoom(sw, dw, &zoom, &mini, &falign, &dcount); + qwfetch = uc_ovl_map_qwfetch(falign, sfmt, pfetch); + + // Prepare destination color key + dst_key = uc_ovl_map_colorkey(&(ucovl->v1.dst_key)); + + // prepare opacity + if (ucovl->v1.level > 0) // overlay + alpha = uc_ovl_map_alpha(ucovl->v1.opacity); + else + alpha = uc_ovl_map_alpha(ucovl->opacity_primary); + + write_settings = true; + } + + if (action & (UC_OVL_FIELD | UC_OVL_FLIP | UC_OVL_CHANGE)) { + int field = 0; + // Update the buffer pointers + + if (ucovl->deinterlace) { + field = ucovl->field; + } + + uc_ovl_map_buffer(sfmt, offset, + ucovl->v1.ox, ucovl->v1.oy, sw, surface->config.size.h, sp, 0/*field*/, &y_start, + &u_start, &v_start); + + if (field) { + y_start |= 0x08000000; + } + + write_buffers = true; + } + + // Write to the hardware + +/* if (write_settings || write_buffers) + uc_ovl_vcmd_wait(vio);*/ + + if (write_settings) { + + VIDEO_OUT(vio, V1_CONTROL, v_ctrl); + VIDEO_OUT(vio, V_FIFO_CONTROL, fifo_ctrl); + + VIDEO_OUT(vio, V1_WIN_START_Y, win_start); + VIDEO_OUT(vio, V1_WIN_END_Y, win_end); + + VIDEO_OUT(vio, V1_SOURCE_HEIGHT, (sh << 16) | dcount); + VIDEO_OUT(vio, V12_QWORD_PER_LINE, qwfetch); + VIDEO_OUT(vio, V1_STRIDE, sp | ((sp >> 1) << 16)); + + VIDEO_OUT(vio, V1_MINI_CONTROL, mini); + VIDEO_OUT(vio, V1_ZOOM_CONTROL, zoom); + + VIDEO_OUT(vio, V_COLOR_KEY, dst_key); + + VIDEO_OUT(vio, V_ALPHA_CONTROL, alpha); + } + + if (write_buffers) { + + VIDEO_OUT(vio, V1_STARTADDR_0, y_start); + VIDEO_OUT(vio, V1_STARTADDR_CB0, u_start); + VIDEO_OUT(vio, V1_STARTADDR_CR0, v_start); + } + + if (write_settings || write_buffers) { + VIDEO_OUT(vio, V_COMPOSE_MODE, V1_COMMAND_FIRE | + (ucovl->v1.dstkey_enabled ? ENABLE_COLOR_KEYING : 0)); + } + + return DFB_OK; +} + +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + DFBColorAdjustment* ucadj; + u32 a1, a2; + + ucadj = &ucovl->v1.adj; + + if (adj->flags & DCAF_BRIGHTNESS) + ucadj->brightness = adj->brightness; + if (adj->flags & DCAF_CONTRAST) + ucadj->contrast = adj->contrast; + if (adj->flags & DCAF_HUE) + ucadj->hue = adj->hue; + if (adj->flags & DCAF_SATURATION) + ucadj->saturation = adj->saturation; + + uc_ovl_map_adjustment(ucadj, &a1, &a2); + + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_1, a1); + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_2, a2); + + return DFB_OK; +} diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_primary.c b/Source/DirectFB/gfxdrivers/unichrome/uc_primary.c new file mode 100755 index 0000000..2c32184 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_primary.c @@ -0,0 +1,182 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp , + Andreas Hundt , + Sven Neumann , + Ville Syrjälä and + Claudio Ciccani . + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include +#include +#include + +#include + +#include + +#include + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +/* primary layer hooks */ + +#define OSD_OPTIONS (DLOP_ALPHACHANNEL | DLOP_SRC_COLORKEY | DLOP_OPACITY) + +DisplayLayerFuncs ucOldPrimaryFuncs; +void *ucOldPrimaryDriverData; + +static DFBResult +osdInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + DFBResult ret; + + /* call the original initialization function first */ + ret = ucOldPrimaryFuncs.InitLayer( layer, + ucOldPrimaryDriverData, + layer_data, description, + config, adjustment ); + if (ret) + return ret; + + /* set name */ + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA CLE266 Graphics"); + + /* add some capabilities */ + description->caps |= DLCAPS_ALPHACHANNEL | + DLCAPS_OPACITY | DLCAPS_SRC_COLORKEY; + + return DFB_OK; +} + +static DFBResult +osdTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + DFBResult ret; + CoreLayerRegionConfigFlags fail = 0; + DFBDisplayLayerOptions options = config->options; + + /* remove options before calling the original function */ + config->options = DLOP_NONE; + + /* call the original function */ + ret = ucOldPrimaryFuncs.TestRegion( layer, ucOldPrimaryDriverData, + layer_data, config, &fail ); + + /* check options if specified */ + if (options) { + /* any unsupported option wanted? */ + if (options & ~OSD_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* opacity and alpha channel cannot be used at once */ + if ((options & (DLOP_OPACITY | DLOP_ALPHACHANNEL)) == + (DLOP_OPACITY | DLOP_ALPHACHANNEL)) + { + fail |= CLRCF_OPTIONS; + } + + if ((options & DLOP_ALPHACHANNEL) && config->format != DSPF_AiRGB) + fail |= CLRCF_OPTIONS; + } + + /* restore options */ + config->options = options; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return ret; +} + +static DFBResult +osdSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + /* call the original function */ + ret = ucOldPrimaryFuncs.SetRegion( layer, ucOldPrimaryDriverData, + layer_data, region_data, + config, updated, surface, + palette, lock ); + if (ret) + return ret; + + uc_ovl_vcmd_wait(ucdrv->hwregs); + + /* select pixel based or global alpha */ + + if (!ucdrv->ovl) // overlay not present + return DFB_OK; + + if (config->options & DLOP_ALPHACHANNEL) + ucdrv->ovl->opacity_primary = -1; // use primary alpha for overlay + else if (config->options & DLOP_OPACITY) + ucdrv->ovl->opacity_primary = config->opacity ^ 0xff; // use inverse for overlay + else + ucdrv->ovl->opacity_primary = 0x00; // primary opaque == overlay transparent + + if (ucdrv->ovl->v1.level < 0) // primary on top? + { + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, + uc_ovl_map_alpha(ucdrv->ovl->opacity_primary)); + VIDEO_OUT(ucdrv->hwregs, V_COMPOSE_MODE, + VIDEO_IN(ucdrv->hwregs, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + } + + return DFB_OK; +} + +DisplayLayerFuncs ucPrimaryFuncs = { + .InitLayer = osdInitLayer, + + .TestRegion = osdTestRegion, + .SetRegion = osdSetRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_probe.h b/Source/DirectFB/gfxdrivers/unichrome/uc_probe.h new file mode 100755 index 0000000..3925db9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_probe.h @@ -0,0 +1,42 @@ +/* + Copyright (c) 2004 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_PROBE_H__ +#define __UC_PROBE_H__ + +#ifndef PCI_VENDOR_ID_VIA +#define PCI_VENDOR_ID_VIA 0x1106 +#endif + +#ifndef FB_ACCEL_VIA_UNICHROME +#define FB_ACCEL_VIA_UNICHROME 77 +#endif + +struct uc_via_chipinfo +{ +#ifdef KERNEL + u16 id; // PCI id +#else + u16 id; +#endif + char* name; // Human readable name, e.g CLE266/UniChrome +}; + +static struct uc_via_chipinfo uc_via_devices[] = +{ + {0x3122, "CLE266/UniChrome"}, // aka VT3122 + {0x7205, "KM400/UniChrome"}, // aka VT3205, P4M800 + {0x7204, "K8M800/UniChrome Pro"}, // aka VT3204, Unichrome Pro B + {0x3118, "CN400/UniChrome Pro"}, // aka VT3259, PM8?0, Unichrome Pro A + {0x3344, "CN700/Unichrome Pro"}, // aka VT3314, P4M800Pro, VN800, CN900 + {0x3157, "CX700/Unichrome Pro"}, // aka CX700 CX700M CX700M2 + {0, ""} +}; + +#endif /* __UC_PROBE_H__ */ diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_spic.c b/Source/DirectFB/gfxdrivers/unichrome/uc_spic.c new file mode 100755 index 0000000..b7665b3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_spic.c @@ -0,0 +1,193 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include "unichrome.h" +#include "vidregs.h" +#include "mmio.h" + +#include +#include + +#define UC_SPIC_OPTIONS DLOP_OPACITY + +typedef struct _UcSubpictureData { +} UcSubpictureData; + +static int uc_spic_datasize( void ) +{ + return sizeof(UcSubpictureData); +} + +static void +uc_spic_set_palette( volatile u8* hwregs, CorePalette *palette ) +{ + int i; + + if (palette) { + for (i = 0; i < 16; i++) { + /* TODO: Check r-g-b order. */ + VIDEO_OUT(hwregs, RAM_TABLE_CONTROL, + (palette->entries[i].r << 24) | + (palette->entries[i].g << 16) | + (palette->entries[i].b << 8) | + (i << 4) | RAM_TABLE_RGB_ENABLE); + } + } +} + +static void uc_spic_enable( volatile u8 *hwregs, bool enable ) +{ + VIDEO_OUT(hwregs, SUBP_CONTROL_STRIDE, + (VIDEO_IN(hwregs, SUBP_CONTROL_STRIDE) & ~SUBP_HQV_ENABLE) | + (enable ? SUBP_HQV_ENABLE : 0)); +} + +static void +uc_spic_set_buffer( volatile u8 *hwregs, CoreSurfaceBufferLock *lock ) +{ + if (lock) { + VIDEO_OUT(hwregs, SUBP_STARTADDR, + lock->offset); + VIDEO_OUT(hwregs, SUBP_CONTROL_STRIDE, + (VIDEO_IN(hwregs, SUBP_CONTROL_STRIDE) & ~SUBP_STRIDE_MASK) | + (lock->pitch & SUBP_STRIDE_MASK) | + SUBP_AI44 ); + } +} + +static DFBResult +uc_spic_init_layer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + /* Set layer type, capabilities and name */ + + description->caps = DLCAPS_SURFACE | DLCAPS_OPACITY; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA Unichrome DVD Subpicture"); + + adjustment->flags = DCAF_NONE; + + /* Fill out the default configuration */ + + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + + config->width = 720; + config->height = 576; + + config->pixelformat = DSPF_ALUT44; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + return DFB_OK; +} + +static DFBResult +uc_spic_test_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed) +{ + CoreLayerRegionConfigFlags fail = 0; + + /* Check layer options */ + + if (config->options & ~UC_SPIC_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* Check pixelformats */ + + switch (config->format) { + case DSPF_ALUT44: + break; + //case DSPF_LUTA44: + // IA44 does not exist in DirectFB, but hw supports it. + default: + fail |= CLRCF_FORMAT; + } + + /* Check width and height */ + + if (config->width > 8195 || config->width < 1) + fail |= CLRCF_WIDTH; + + if (config->height > 4096 || config->height < 1) + fail |= CLRCF_HEIGHT; + + if (failed) *failed = fail; + if (fail) return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +uc_spic_set_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + uc_spic_set_palette(ucdrv->hwregs, palette); + uc_spic_set_buffer(ucdrv->hwregs, lock); + uc_spic_enable(ucdrv->hwregs, (config->opacity > 0)); + + return DFB_OK; +} + +static DFBResult +uc_spic_remove( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + uc_spic_enable(ucdrv->hwregs, false); + return DFB_OK; +} + +static DFBResult +uc_spic_flip_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + dfb_surface_flip(surface, false); + uc_spic_set_buffer(ucdrv->hwregs, lock); + + return DFB_OK; +} + +DisplayLayerFuncs ucSubpictureFuncs = { + .LayerDataSize = uc_spic_datasize, + .InitLayer = uc_spic_init_layer, + .SetRegion = uc_spic_set_region, + .RemoveRegion = uc_spic_remove, + .TestRegion = uc_spic_test_region, + .FlipRegion = uc_spic_flip_region, +}; diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_state.c b/Source/DirectFB/gfxdrivers/unichrome/uc_state.c new file mode 100755 index 0000000..6e0fbfa --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_state.c @@ -0,0 +1,350 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include + +#include +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_hw.h" + +enum uc_state_type { + UC_TYPE_UNSUPPORTED, + UC_TYPE_2D, + UC_TYPE_3D +}; + +/// GPU selecting functions -------------------------------------------------- + +static inline bool +uc_has_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_ARGB4444: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_additional_draw_2d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_AiRGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_additional_blit_2d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_YV12: + case DSPF_I420: + case DSPF_YUY2: + case DSPF_AiRGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_has_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_ARGB4444: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + case DSPF_LUT8: + case DSPF_YUY2: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_has_inv_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_AiRGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_has_inv_dst_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_AiRGB: + return true; + + default: + break; + } + + return false; +} + +static inline enum uc_state_type +uc_select_drawtype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_2D) && + !(accel & DFXL_FILLTRIANGLE)) + return UC_TYPE_2D; + + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_3D)) + return UC_TYPE_3D; + + return UC_TYPE_UNSUPPORTED; +} + +static inline enum uc_state_type +uc_select_blittype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_2D)) { + if ((state->source->config.format == state->destination->config.format) && + !((state->blittingflags & DSBLIT_SRC_COLORKEY) && + (state->blittingflags & DSBLIT_DST_COLORKEY)) && + !(accel & (DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES))) + return UC_TYPE_2D; + } + + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_3D)) { + if (uc_has_src_format_3d( state->source->config.format )) + return UC_TYPE_3D; + } + + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_3D_INV)) { + if (uc_has_inv_src_format_3d( state->source->config.format )) + return UC_TYPE_3D; + } + + /* Special case for an inverted destination alpha channel. This + * can only be done if no blending is requested at the same time. */ + if (state->blittingflags == DSBLIT_NOFX) { + if (DFB_PIXELFORMAT_INV_ALPHA(state->destination->config.format) && + !DFB_PIXELFORMAT_INV_ALPHA(state->source->config.format)) + return UC_TYPE_3D; + } + + return UC_TYPE_UNSUPPORTED; +} + +// DirectFB interfacing functions -------------------------------------------- + +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel) +{ + if (DFB_DRAWING_FUNCTION(accel)) { + /* Check drawing parameters. */ + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + if (uc_has_dst_format( state->destination->config.format ) || + uc_additional_draw_2d( state->destination->config.format )) + state->accel |= UC_DRAWING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + if (uc_has_dst_format( state->destination->config.format )) + state->accel |= UC_DRAWING_FUNCTIONS_3D; + break; + default: + return; + } + } + else { + /* Check blitting parameters. */ + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + if (uc_has_dst_format( state->destination->config.format ) || + uc_additional_blit_2d( state->destination->config.format )) + state->accel |= UC_BLITTING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + if (uc_has_dst_format( state->destination->config.format ) || + uc_has_inv_dst_format_3d( state->destination->config.format )) + state->accel |= UC_BLITTING_FUNCTIONS_3D; + break; + default: + return; + } + } +} + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel) +{ + UcDriverData *ucdrv = (UcDriverData*) drv; + UcDeviceData *ucdev = (UcDeviceData*) dev; + struct uc_fifo *fifo = ucdrv->fifo; + + u32 rop3d = HC_HROP_P; + u32 regEnable = HC_HenCW_MASK | HC_HenAW_MASK; + + StateModificationFlags modified = state->mod_hw; + + // Check modified states and update hw + + if (modified & SMF_SOURCE) + UC_INVALIDATE( uc_source2d ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SOURCE)) + UC_INVALIDATE( uc_source3d ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SOURCE | SMF_DESTINATION)) + UC_INVALIDATE( uc_texenv ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SRC_COLORKEY | SMF_DST_COLORKEY)) + UC_INVALIDATE( uc_colorkey2d ); + + if (modified & (SMF_COLOR | SMF_DESTINATION | SMF_DRAWING_FLAGS)) + UC_INVALIDATE( uc_color2d ); + + if (modified & (SMF_SRC_BLEND | SMF_DST_BLEND)) + UC_INVALIDATE( uc_blending_fn ); + + + if (modified & SMF_COLOR) + ucdev->color3d = PIXEL_ARGB( state->color.a, state->color.r, + state->color.g, state->color.b ); + + if (modified & SMF_DRAWING_FLAGS) { + if (state->drawingflags & DSDRAW_XOR) { + ucdev->draw_rop3d = HC_HROP_DPx; + ucdev->draw_rop2d = VIA_ROP_DPx; + } + else { + ucdev->draw_rop3d = HC_HROP_P; + ucdev->draw_rop2d = VIA_ROP_P; + } + } + + ucdev->bflags = state->blittingflags; + + if (modified & SMF_DESTINATION) + uc_set_destination(ucdrv, ucdev, state); + + if (modified & SMF_CLIP) + uc_set_clip(ucdrv, ucdev, state); + + + // Select GPU and check remaining states + + if (DFB_DRAWING_FUNCTION(accel)) { + + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + + uc_set_color_2d(ucdrv, ucdev, state); + + state->set = UC_DRAWING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->FillRectangle = uc_fill_rectangle_3d; + funcs->DrawRectangle = uc_draw_rectangle_3d; + funcs->DrawLine = uc_draw_line_3d; + + if (state->drawingflags & DSDRAW_BLEND) { + uc_set_blending_fn(ucdrv, ucdev, state); + regEnable |= HC_HenABL_MASK; + } + + rop3d = ucdev->draw_rop3d; + + state->set = UC_DRAWING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported drawing function!"); + break; + } + } + else { // DFB_BLITTING_FUNCTION(accel) + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + uc_set_source_2d(ucdrv, ucdev, state); + funcs->Blit = uc_blit; + + uc_set_colorkey_2d(ucdrv, ucdev, state); + state->set = UC_BLITTING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->Blit = uc_blit_3d; + uc_set_source_3d(ucdrv, ucdev, state); + uc_set_texenv(ucdrv, ucdev, state); + uc_set_blending_fn(ucdrv, ucdev, state); + + regEnable |= HC_HenTXMP_MASK | HC_HenTXCH_MASK | HC_HenTXPP_MASK | HC_HenDT_MASK; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_BLEND_COLORALPHA)) + regEnable |= HC_HenABL_MASK; + + state->set = UC_BLITTING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported blitting function!"); + break; + } + } + +#ifdef UC_ENABLE_3D + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + /* Don't know what this does. DRI code always clears it. */ + UC_FIFO_ADD_3D ( fifo, HC_SubA_HPixGC, 0 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HEnable, regEnable ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HFBBMSKL, 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HROP, rop3d | 0xff ); +#endif + + UC_FIFO_CHECK(fifo); + + state->mod_hw = 0; +} + diff --git a/Source/DirectFB/gfxdrivers/unichrome/uc_state.h b/Source/DirectFB/gfxdrivers/unichrome/uc_state.h new file mode 100755 index 0000000..a3e7484 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/uc_state.h @@ -0,0 +1,68 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_STATE__ +#define __UC_STATE__ + +#include +#include +#include + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel); +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel); + + + +/* +struct uc_hw_misc +{ + // These control clipping... + + u32 regHClipTB; + u32 regHClipLR; + u32 regHFPClipTL; + u32 regHFPClipBL; + u32 regHFPClipLL; + u32 regHFPClipRL; + u32 regHFPClipTBH; + u32 regHFPClipLRH; + + // Other functions + + u32 regHLP; // Line stipple pattern + u32 regHLPRF; // Line stipple factor + u32 regHSolidCL; // --- Don't know. Unused in DRI. + u32 regHPixGC; // Don't know. Is kept cleared in DRI. + //u32 regHSPXYOS; // Polygon stipple x and y offsets. Unused here. + u32 regHVertexCNT; // --- Don't know. Unused in DRI. + + u8 ps_xos; // Polygon stipple x-offset. => regHSPXYOS + u8 ps_yos; // Polygon stipple y-offset. => regHSPXYOS + u32 ps_pat[32]; // Polygon stipple pattern buffer. + // These are not registers... +}; + + +/// Stencil control. + +struct uc_hw_stencil +{ + //u32 regHSBBasL; // These aren't in regs3d.h, but they should exist... + //u32 regHSBBasH; + //u32 regHSBFM; + + u32 regHSTREF; // Stencil reference value and plane mask + u32 regHSTMD; // Stencil test function and fail operation and + // zpass/zfail operations. +}; +*/ + +#endif // __UC_STATE__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/unichrome.c b/Source/DirectFB/gfxdrivers/unichrome/unichrome.c new file mode 100755 index 0000000..062334e --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/unichrome.c @@ -0,0 +1,596 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// DirectFB headers + +#include + +#include + +#include + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +// System headers + +#include +#include +#include +#include +#include +#include + +#include + +// Driver headers + +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "uc_ioctl.h" +#include "mmio.h" +#include "uc_probe.h" + +extern DisplayLayerFuncs ucOverlayFuncs; +extern DisplayLayerFuncs ucPrimaryFuncs; +extern DisplayLayerFuncs ucSubpictureFuncs; + +extern DisplayLayerFuncs ucOldPrimaryFuncs; +extern void *ucOldPrimaryDriverData; + + +DFB_GRAPHICS_DRIVER(unichrome) + +//---------- + +/* PCI probing code is derived from gfxdrivers/matrox/matrox.c */ + +/** Read PCI configuration register 'reg' for device at {bus,slot,func}. */ +static int pci_config_in8( unsigned int bus, + unsigned int slot, + unsigned int func, + u8 reg ) +{ + char filename[512]; + int fd; + int val; + + val = 0; + + snprintf( filename, 512, "/proc/bus/pci/%02x/%02x.%x", bus, slot, func ); + + fd = open( filename, O_RDONLY ); + if (fd < 0) { + D_PERROR( "DirectFB/Unichrome: Error opening `%s'!\n", filename ); + return -1; + } + + if (lseek( fd, reg, SEEK_SET ) == reg) { + if (read( fd, &val, 1 ) == 1) { + close( fd ); + return val; + } + } + + close( fd ); + return -1; +} + +/* Probe for a Unichrome device. +* @returns DFB_OK if successful, with ucdrv->hwid, ucdrv->hwrev, +* and ucdrv->name filled in. +*/ +static DFBResult uc_probe_pci( UcDriverData *ucdrv ) +{ + unsigned int bus, devfn, vendor, device; + char line[512]; + FILE *file; + int i; + + const char* filename = "/proc/bus/pci/devices"; + + file = fopen( filename, "r" ); + if (!file) { + D_PERROR( "DirectFB/Unichrome: Error opening `%s'!\n", filename ); + return errno2result( errno ); + } + + while (fgets( line, 512, file )) { + if (sscanf( line, "%02x%02x\t%04x%04x", + &bus, &devfn, &vendor, &device ) != 4) + continue; + + if (vendor != PCI_VENDOR_ID_VIA) + continue; + + for (i = 0; uc_via_devices[i].id != 0; i++) { + if (device == uc_via_devices[i].id) { + // Found a Unichrome device. + ucdrv->hwid = device; + ucdrv->name = uc_via_devices[i].name; + // Read its revision number from the host bridge. + ucdrv->hwrev = pci_config_in8(0, 0, 0, 0xf6); + if (ucdrv->hwrev == -1 && dfb_config->unichrome_revision == -1) { + ucdrv->hwrev = 0x11; // a fairly arbitrary default + D_ERROR( "DirectFB/Unichrome: Failed to determine hardware revision, assuming %d.\n", + ucdrv->hwrev ); + } + // Because we can only auto-detect if we're superuser, + // allow an override + if (dfb_config->unichrome_revision != -1) + ucdrv->hwrev = dfb_config->unichrome_revision; + fclose( file ); + return DFB_OK; + } + } + } + + D_ERROR( "DirectFB/Unichrome: Can't find a Unichrome device in `%s'!\n", + filename ); + + fclose( file ); + return DFB_INIT; +} + +/** + * Dump beginning of virtual queue. + * Use it to check that the VQ actually is in use. */ +#if 0 +static void uc_dump_vq(UcDeviceData *ucdev) +{ + int i; + u8* vq; + + if (!ucdev->vq_start) return; + vq = dfb_system_video_memory_virtual(ucdev->vq_start); + + for (i = 0; i < 128; i++) { + printf("%02x ", *(vq+i)); + if ((i+1) % 16 == 0) printf("\n"); + } +} +#endif + +/** Allocate memory for the virtual queue. */ + +static DFBResult uc_alloc_vq(CoreGraphicsDevice *device, UcDeviceData *ucdev) +{ + if (ucdev->vq_start) return DFB_OK; + + ucdev->vq_size = 256*1024; // 256kb + ucdev->vq_start = dfb_gfxcard_reserve_memory( device, ucdev->vq_size ); + + if (!ucdev->vq_start) + return DFB_INIT; + + ucdev->vq_end = ucdev->vq_start + ucdev->vq_size - 1; + + // Debug: clear buffer + memset((void *) dfb_system_video_memory_virtual(ucdev->vq_start), + 0xcc, ucdev->vq_size); + + // uc_dump_vq(ucdev); + + return DFB_OK; +} + +/** + * Initialize the hardware. + * @param enable enable VQ if true (else disable it.) + */ + +static DFBResult uc_init_2d_engine(CoreGraphicsDevice *device, UcDeviceData *ucdev, UcDriverData *ucdrv, bool enable) +{ + DFBResult result = DFB_OK; + volatile u8* hwregs = ucdrv->hwregs; + int i; + + // Init 2D engine registers to reset 2D engine + + for ( i = 0x04; i <= 0x40; i += 4 ) + VIA_OUT(hwregs, i, 0x0); + + // Init AGP and VQ registers + + VIA_OUT(hwregs, 0x43c, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00000000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + VIA_OUT(hwregs, 0x440, 0x7D000000); + + VIA_OUT(hwregs, 0x43c, 0xfe020000); + VIA_OUT(hwregs, 0x440, 0x00000000); + + if (enable) { + result = uc_alloc_vq(device,ucdev); + enable = (result == DFB_OK); + } + + if (enable) { // Enable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x080003fe); + VIA_OUT(hwregs, 0x440, 0x0a00027c); + VIA_OUT(hwregs, 0x440, 0x0b000260); + VIA_OUT(hwregs, 0x440, 0x0c000274); + VIA_OUT(hwregs, 0x440, 0x0d000264); + VIA_OUT(hwregs, 0x440, 0x0e000000); + VIA_OUT(hwregs, 0x440, 0x0f000020); + VIA_OUT(hwregs, 0x440, 0x1000027e); + VIA_OUT(hwregs, 0x440, 0x110002fe); + VIA_OUT(hwregs, 0x440, 0x200f0060); + + VIA_OUT(hwregs, 0x440, 0x00000006); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + + VIA_OUT(hwregs, 0x440, 0x52000000 | + ((ucdev->vq_start & 0xFF000000) >> 24) | + ((ucdev->vq_end & 0xFF000000) >> 16)); + VIA_OUT(hwregs, 0x440, 0x50000000 | (ucdev->vq_start & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x51000000 | (ucdev->vq_end & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x53000000 | (ucdev->vq_size >> 3)); + } + else { // Disable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x00000004); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + } + + return result; +} + +static void uc_init_3d_engine(volatile u8* hwregs, int hwrev, bool init_all) +{ + u32 i; + + if (init_all) { + + // Clear NotTex registers + + VIA_OUT(hwregs, 0x43C, 0x00010000); + for (i = 0; i <= 0x7d; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear texture unit 0 + + VIA_OUT(hwregs, 0x43C, 0x00020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear texture unit 1 + + VIA_OUT(hwregs, 0x43C, 0x01020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear general texture settings + + VIA_OUT(hwregs, 0x43C, 0xfe020000); + for (i = 0; i <= 0x03; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear palette settings + + VIA_OUT(hwregs, 0x43C, 0x00030000); + for (i = 0; i <= 0xff; i++) + VIA_OUT(hwregs, 0x440, 0); + + VIA_OUT(hwregs, 0x43C, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x10000002); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + + VIA_OUT(hwregs, 0x43C, 0x00fe0000); + + if (hwrev >= 3) + VIA_OUT(hwregs, 0x440,0x40008c0f); + else + VIA_OUT(hwregs, 0x440,0x4000800f); + + VIA_OUT(hwregs, 0x440,0x44000000); + VIA_OUT(hwregs, 0x440,0x45080C04); + VIA_OUT(hwregs, 0x440,0x46800408); + VIA_OUT(hwregs, 0x440,0x50000000); + VIA_OUT(hwregs, 0x440,0x51000000); + VIA_OUT(hwregs, 0x440,0x52000000); + VIA_OUT(hwregs, 0x440,0x53000000); + + } + + VIA_OUT(hwregs, 0x43C,0x00fe0000); + VIA_OUT(hwregs, 0x440,0x08000001); + VIA_OUT(hwregs, 0x440,0x0A000183); + VIA_OUT(hwregs, 0x440,0x0B00019F); + VIA_OUT(hwregs, 0x440,0x0C00018B); + VIA_OUT(hwregs, 0x440,0x0D00019B); + VIA_OUT(hwregs, 0x440,0x0E000000); + VIA_OUT(hwregs, 0x440,0x0F000000); + VIA_OUT(hwregs, 0x440,0x10000000); + VIA_OUT(hwregs, 0x440,0x11000000); + VIA_OUT(hwregs, 0x440,0x20000000); +} + +/** */ + +static void uc_after_set_var(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + + VGA_OUT8(ucdrv->hwregs, 0x3c4, 0x1a); + // Clear bit 6 in extended VGA register 0x1a to prevent system lockup. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) & 0xbf); + // Set bit 2, it might make a difference. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) | 0x4); + + VIA_OUT(ucdrv->hwregs, VIA_REG_CURSOR_MODE, VIA_IN(ucdrv->hwregs, VIA_REG_CURSOR_MODE) & 0xFFFFFFFE); +} + +/** Wait until the engine is idle. */ + +static DFBResult uc_engine_sync(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + UcDeviceData* ucdev = (UcDeviceData*) dev; + + int loop = 0; + +/* printf("Entering uc_engine_sync(), status is 0x%08x\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS)); +*/ + + while ((VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & 0xfffeffff) != 0x00020000) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/Unichrome: Timeout waiting for idle engine!\n"); + break; + + /* FIXME: return DFB_TIMEOUT and implement EngineReset! */ + } + } + + /* printf("Leaving uc_engine_sync(), status is 0x%08x, " + "waiting for %d (0x%x) cycles.\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS), loop, loop); + */ + + ucdev->idle_waitcycles += loop; + ucdev->must_wait = 0; + + return DFB_OK; +} + + +// DirectFB interfacing functions -------------------------------------------- + +static int driver_probe(CoreGraphicsDevice *device) +{ + struct stat s; + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_VIA_UNICHROME: + return 1; + } + + return stat(UNICHROME_DEVICE, &s) + 1; +} + +static void driver_get_info(CoreGraphicsDevice* device, + GraphicsDriverInfo* info) +{ + // Fill in driver info structure. + + snprintf(info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "VIA UniChrome Driver"); + + snprintf(info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "-"); + + snprintf(info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org"); + + snprintf(info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL"); + + info->version.major = 0; + info->version.minor = 4; + + info->driver_data_size = sizeof (UcDriverData); + info->device_data_size = sizeof (UcDeviceData); +} + +static void uc_probe_fbdev(UcDriverData *ucdrv) +{ + struct fb_flip flip; + FBDev *dfb_fbdev = dfb_system_data(); + flip.device = VIAFB_FLIP_NOP; + if (ioctl(dfb_fbdev->fd, FBIO_FLIPONVSYNC, &flip) == 0) + ucdrv->canfliponvsync = true; + else + ucdrv->canfliponvsync = false; +} + +static DFBResult driver_init_driver(CoreGraphicsDevice* device, + GraphicsDeviceFuncs* funcs, + void* driver_data, + void* device_data, + CoreDFB *core) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + ucdrv->file = -1; + ucdrv->pool = dfb_core_shmpool( core ); + + ucdrv->hwregs = dfb_gfxcard_map_mmio( device, 0, 0 ); + if (!ucdrv->hwregs) { + int fd; + + fd = open(UNICHROME_DEVICE, O_RDWR | O_SYNC, 0); + if (fd < 0) { + D_ERROR("DirectFB/Unichrome: Could not access %s. " + "Is the ucio module installed?\n", UNICHROME_DEVICE); + return DFB_IO; + } + + ucdrv->file = fd; + + ucdrv->hwregs = mmap(NULL, 0x1000000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (ucdrv->hwregs == MAP_FAILED) + return DFB_IO; + } + + // Get hardware id and revision. + uc_probe_pci(ucdrv); + + // Check framebuffer device capabilities + uc_probe_fbdev(ucdrv); + + /* FIXME: this belongs to device_data! */ + ucdrv->fifo = uc_fifo_create(ucdrv->pool, UC_FIFO_SIZE); + if (!ucdrv->fifo) + return D_OOSHM(); + + uc_after_set_var(driver_data, device_data); + + // Driver specific initialization + + funcs->CheckState = uc_check_state; + funcs->SetState = uc_set_state; + funcs->EngineSync = uc_engine_sync; + funcs->EmitCommands = uc_emit_commands; + funcs->FlushTextureCache = uc_flush_texture_cache; + funcs->AfterSetVar = uc_after_set_var; + + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + funcs->FillTriangle = uc_fill_triangle; + funcs->Blit = uc_blit; + funcs->StretchBlit = uc_stretch_blit; + funcs->TextureTriangles = uc_texture_triangles; + + ucdrv->ovl = NULL; + + /* install primary layer hooks */ + dfb_layers_hook_primary( device, driver_data, &ucPrimaryFuncs, + &ucOldPrimaryFuncs, &ucOldPrimaryDriverData ); + + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &ucOverlayFuncs ); + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &ucSubpictureFuncs ); + + return DFB_OK; +} + +static DFBResult driver_init_device(CoreGraphicsDevice* device, + GraphicsDeviceInfo* device_info, + void* driver_data, + void* device_data) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + UcDeviceData *ucdev = (UcDeviceData*) device_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + if (ucdrv->name != NULL) { + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "%s", ucdrv->name); + } + else { + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "UniChrome"); + } + snprintf(device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "VIA/S3G"); + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = + UC_DRAWING_FUNCTIONS_2D | UC_DRAWING_FUNCTIONS_3D | + UC_BLITTING_FUNCTIONS_2D | UC_BLITTING_FUNCTIONS_3D; + + device_info->caps.drawing = UC_DRAWING_FLAGS_2D | UC_DRAWING_FLAGS_3D; + device_info->caps.blitting = UC_BLITTING_FLAGS_2D | UC_BLITTING_FLAGS_3D; + + device_info->limits.surface_byteoffset_alignment = 32; + device_info->limits.surface_pixelpitch_alignment = 32; + + ucdev->pitch = 0; + ucdev->draw_rop2d = VIA_ROP_P; + ucdev->draw_rop3d = HC_HROP_P; + ucdev->color = 0; + ucdev->bflags = 0; + + ucdev->must_wait = 0; + ucdev->cmd_waitcycles = 0; + ucdev->idle_waitcycles = 0; + + uc_init_2d_engine(device, ucdev, ucdrv, false); // VQ disabled - can't make it work. + uc_init_3d_engine(ucdrv->hwregs, ucdrv->hwrev, 1); + + return DFB_OK; +} + +static void driver_close_device(CoreGraphicsDevice *device, + void *driver_data, void *device_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcDeviceData* ucdev = (UcDeviceData*) device_data; + + // uc_dump_vq(ucdev); + + uc_engine_sync(driver_data, device_data); + uc_init_2d_engine(device, ucdev, ucdrv, false); +} + +static void driver_close_driver(CoreGraphicsDevice* device, void* driver_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (ucdrv->fifo) + uc_fifo_destroy( ucdrv->pool, ucdrv->fifo ); + + if (ucdrv->file != -1) + close( ucdrv->file ); +} diff --git a/Source/DirectFB/gfxdrivers/unichrome/unichrome.h b/Source/DirectFB/gfxdrivers/unichrome/unichrome.h new file mode 100755 index 0000000..7f8e72b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/unichrome.h @@ -0,0 +1,151 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UNICHROME_H__ +#define __UNICHROME_H__ + +#include +#include +#include +#include + +#include + +#define UNICHROME_DEVICE "/dev/ucio" +#define UC_FIFO_SIZE 4096 + +/** If defined - the driver will use the 3D engine. */ +#define UC_ENABLE_3D +//#undef UC_ENABLE_3D + + +/** Register settings for the current source surface. (3D) */ +struct uc_hw_texture { + DFBSurfaceBlittingFlags bltflags; + + u32 l2w; //width, rounded up to nearest 2^m, eg 600 => 1024 + u32 l2h; //height, rounded up, e.g 480 => 512 + u32 we; //width exponent, i.e m in the number 2^m + u32 he; //height exponent + + u32 format; // HW pixel format + + // 3d engine texture environment, texture unit 0 + + // Used for the DSBLIT_BLEND_ALPHACHANNEL, DSBLIT_BLEND_COLORALPHA + // and DSBLIT_COLORIZE blitting flags. + + u32 regHTXnTB; + u32 regHTXnMPMD; + + u32 regHTXnTBLCsat_0; + u32 regHTXnTBLCop_0; + u32 regHTXnTBLMPfog_0; + u32 regHTXnTBLAsat_0; + u32 regHTXnTBLRCb_0; + u32 regHTXnTBLRAa_0; + u32 regHTXnTBLRFog_0; +}; + + +/** Hardware source-destination blending registers. */ +struct uc_hw_alpha { +/* + u32 regHABBasL; // Alpha buffer, low 24 bits. + u32 regHABBasH; // Alpha buffer, high 8 bits. + u32 regHABFM; // Alpha pixel format, memory type and pitch. + u32 regHATMD; // Alpha test function and reference value. + + // Blending function +*/ + u32 regHABLCsat; + u32 regHABLCop; + u32 regHABLAsat; + u32 regHABLAop; + u32 regHABLRCa; + u32 regHABLRFCa; + u32 regHABLRCbias; + u32 regHABLRCb; + u32 regHABLRFCb; + u32 regHABLRAa; + u32 regHABLRAb; +}; + +typedef enum { + uc_source2d = 0x00000001, + uc_source3d = 0x00000002, + uc_texenv = 0x00000004, + uc_blending_fn = 0x00000008, + uc_color2d = 0x00000010, + uc_colorkey2d = 0x00000020 +} UcStateBits; + +#define UC_VALIDATE(b) (ucdev->valid |= (b)) +#define UC_INVALIDATE(b) (ucdev->valid &= ~(b)) +#define UC_IS_VALID(b) (ucdev->valid & (b)) + +typedef struct _UcDeviceData { + + /* State validation */ + UcStateBits valid; + + /* Current state settings */ + u32 pitch; // combined src/dst pitch (2D) + u32 color; // 2D fill color + u32 color3d; // color for 3D operations + u32 draw_rop2d; // logical drawing ROP (2D) + u32 draw_rop3d; // logical drawing ROP (3D) + + DFBSurfaceBlittingFlags bflags; // blitting flags + DFBRegion clip; // clipping region + + DFBSurfacePixelFormat dst_format; // destination pixel format + int dst_offset; // destination buffer byte offset + int dst_pitch; // destination buffer byte pitch + int dst_height; // destination surface height + int src_offset; // source buffer byte offset + int src_pitch; // source buffer byte pitch + int src_height; // source surface height + + int field; // source field + + /* Hardware settings */ + struct uc_hw_alpha hwalpha; // alpha blending setting (3D) + struct uc_hw_texture hwtex; // hardware settings for blitting (3D) + + + /// Set directly after a 2D/3D engine command is sent. + int must_wait; + unsigned int cmd_waitcycles; + unsigned int idle_waitcycles; + + u32 vq_start; // VQ related + u32 vq_size; + u32 vq_end; + +} UcDeviceData; + + +typedef struct _UcDriverData { + int file; // File handle to mmapped IO region. + int hwid; // Graphics device PCI id. + char hwrev; // Hardware revision + char* name; // Graphics device name, eg CLE266/UniChrome + volatile void* hwregs; // Hardware register base + bool canfliponvsync; // Kernel-assisted flip on vsync available + struct uc_fifo* fifo; // Data FIFO. + + FusionSHMPoolShared *pool; + + struct _UcOverlayData *ovl; // Current overlay settings (initially NULL) + +} UcDriverData; + + +#endif // __UNICHROME_H__ diff --git a/Source/DirectFB/gfxdrivers/unichrome/vidregs.h b/Source/DirectFB/gfxdrivers/unichrome/vidregs.h new file mode 100755 index 0000000..79cde4d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/unichrome/vidregs.h @@ -0,0 +1,499 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIDREGS_H__ +#define __VIDREGS_H__ + + +/* Video registers */ +#define V_FLAGS 0x00 +#define V_CAP_STATUS 0x04 +#define V_FLIP_STATUS 0x04 +#define V_ALPHA_WIN_START 0x08 +#define V_ALPHA_WIN_END 0x0C +#define V_ALPHA_CONTROL 0x10 +#define V_CRT_STARTADDR 0x14 +#define V_CRT_STARTADDR_2 0x18 +#define V_ALPHA_STRIDE 0x1C +#define V_COLOR_KEY 0x20 +#define V_ALPHA_STARTADDR 0x24 +#define V_CHROMAKEY_LOW 0x28 +#define V_CHROMAKEY_HIGH 0x2C + +#define V1_CONTROL 0x30 +#define V12_QWORD_PER_LINE 0x34 +#define V1_STARTADDR_1 0x38 +#define V1_STARTADDR_Y1 V1_STARTADDR_1 /* added by Kevin 3/30/2002 */ +#define V1_STRIDE 0x3C +#define V1_WIN_START_Y 0x40 +#define V1_WIN_START_X 0x42 +#define V1_WIN_END_Y 0x44 +#define V1_WIN_END_X 0x46 +#define V1_STARTADDR_2 0x48 +#define V1_STARTADDR_Y2 V1_STARTADDR_2 /* added by Kevin 3/30/2002 */ +#define V1_ZOOM_CONTROL 0x4C +#define V1_MINI_CONTROL 0x50 +#define V1_STARTADDR_0 0x54 +#define V1_STARTADDR_Y0 V1_STARTADDR_0 /* added by Kevin 3/30/2002 */ +#define V_FIFO_CONTROL 0x58 +#define V1_STARTADDR_3 0x5C +#define V1_STARTADDR_Y3 V1_STARTADDR_3 /* added by Kevin 3/30/2002 */ + +#define HI_CONTROL 0x60 +#define SND_COLOR_KEY 0x64 +#define ALPHA_V3_PREFIFO_CONTROL 0x68 +#define V1_SOURCE_HEIGHT 0x6C +#define HI_TRANSPARENT_COLOR 0x70 +#define V_DISPLAY_TEMP 0x74 /* No use */ +#define ALPHA_V3_FIFO_CONTROL 0x78 +#define V3_SOURCE_WIDTH 0x7C +#define V3_COLOR_KEY 0x80 +#define V1_ColorSpaceReg_1 0x84 +#define V1_ColorSpaceReg_2 0x88 +#define V1_STARTADDR_CB0 0x8C +#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ +#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ +#define V_COMPOSE_MODE 0x98 + +#define V3_STARTADDR_2 0x9C +#define V3_CONTROL 0xA0 +#define V3_STARTADDR_0 0xA4 +#define V3_STARTADDR_1 0xA8 +#define V3_STRIDE 0xAC +#define V3_WIN_START_Y 0xB0 +#define V3_WIN_START_X 0xB2 +#define V3_WIN_END_Y 0xB4 +#define V3_WIN_END_X 0xB6 +#define V3_ALPHA_QWORD_PER_LINE 0xB8 +#define V3_ZOOM_CONTROL 0xBC +#define V3_MINI_CONTROL 0xC0 +#define V3_ColorSpaceReg_1 0xC4 +#define V3_ColorSpaceReg_2 0xC8 +#define V3_DISPLAY_TEMP 0xCC /* No use */ + +#define V1_STARTADDR_CB1 0xE4 +#define V1_STARTADDR_CB2 0xE8 +#define V1_STARTADDR_CB3 0xEC +#define V1_STARTADDR_CR0 0xF0 +#define V1_STARTADDR_CR1 0xF4 +#define V1_STARTADDR_CR2 0xF8 +#define V1_STARTADDR_CR3 0xFC + +/* Video Capture Engine Registers - port 1 */ +#define CAP0_MASKS 0x100 +#define CAP1_MASKS 0x104 +#define CAP0_CONTROL 0x110 +#define CAP0_H_RANGE 0x114 +#define CAP0_V_RANGE 0x118 +#define CAP0_SCAL_CONTROL 0x11C +#define CAP0_VBI_H_RANGE 0x120 +#define CAP0_VBI_V_RANGE 0x124 +#define CAP0_VBI_STARTADDR 0x128 +#define CAP0_VBI_STRIDE 0x12C +#define CAP0_ANCIL_COUNT 0x130 +#define CAP0_MAXCOUNT 0x134 +#define CAP0_VBIMAX_COUNT 0x138 +#define CAP0_DATA_COUNT 0x13C +#define CAP0_FB_STARTADDR0 0x140 +#define CAP0_FB_STARTADDR1 0x144 +#define CAP0_FB_STARTADDR2 0x148 +#define CAP0_STRIDE 0x150 + +/* Video Capture Engine Registers - port 2 */ +#define CAP1_CONTROL 0x154 +#define CAP1_SCAL_CONTROL 0x160 +#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ +#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ +#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ +#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ +#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ +#define CAP1_MAXCOUNT 0x178 +#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ +#define CAP1_DATA_COUNT 0x180 +#define CAP1_FB_STARTADDR0 0x184 +#define CAP1_FB_STARTADDR1 0x188 +#define CAP1_STRIDE 0x18C + +/* SUBPICTURE Registers */ +#define SUBP_CONTROL_STRIDE 0x1C0 +#define SUBP_STARTADDR 0x1C4 +#define RAM_TABLE_CONTROL 0x1C8 +#define RAM_TABLE_READ 0x1CC + +/* HQV Registers */ +#define HQV_CONTROL 0x1D0 +#define HQV_SRC_STARTADDR_Y 0x1D4 +#define HQV_SRC_STARTADDR_U 0x1D8 +#define HQV_SRC_STARTADDR_V 0x1DC +#define HQV_SRC_FETCH_LINE 0x1E0 +#define HQV_FILTER_CONTROL 0x1E4 +#define HQV_MINIFY_CONTROL 0x1E8 +#define HQV_DST_STARTADDR0 0x1EC +#define HQV_DST_STARTADDR1 0x1F0 +#define HQV_DST_STARTADDR2 0x1FC +#define HQV_DST_STRIDE 0x1F4 +#define HQV_SRC_STRIDE 0x1F8 + + + +/* Video command definitions */ + +/* #define V_ALPHA_CONTROL - 0x210 */ +#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 +#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 +#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 +#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 +#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 +#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 +#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 +#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 +#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 + +/* V_CHROMAKEY_LOW - 0x228 */ +#define V_CHROMAKEY_V3 0x80000000 + +/* V1_CONTROL - 0x230 */ +#define V1_ENABLE 0x00000001 +#define V1_FULL_SCREEN 0x00000002 +#define V1_YUV422 0x00000000 +#define V1_RGB32 0x00000004 +#define V1_RGB15 0x00000008 +#define V1_RGB16 0x0000000C +#define V1_YUV420 0x00000010 +#define V1_COLORSPACE_SIGN 0x00000080 +#define V1_SRC_IS_FRAME_PIC 0x00000200 +#define V1_SRC_IS_FIELD_PIC 0x00000000 +#define V1_BOB_ENABLE 0x00400000 +#define V1_FIELD_BASE 0x00000000 +#define V1_FRAME_BASE 0x01000000 +#define V1_SWAP_SW 0x00000000 +#define V1_SWAP_HW_HQV 0x02000000 +#define V1_SWAP_HW_CAPTURE 0x04000000 +#define V1_SWAP_HW_MC 0x06000000 +/* #define V1_DOUBLE_BUFFERS 0x00000000 */ +/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ +#define V1_EXPIRE_NUM 0x00050000 +#define V1_EXPIRE_NUM_A 0x000a0000 +#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ +#define V1_FIFO_EXTENDED 0x00200000 +#define V1_ON_CRT 0x00000000 +#define V1_ON_SND_DISPLAY 0x80000000 +#define V1_FIFO_32V1_32V2 0x00000000 +#define V1_FIFO_48V1_32V2 0x00200000 + +/* V12_QWORD_PER_LINE - 0x234 */ +#define V1_FETCH_COUNT 0x3ff00000 +#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f +#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ + +/* V1_STRIDE */ +#define V1_STRIDE_YMASK 0x00001fff +#define V1_STRIDE_UVMASK 0x1ff00000 + +/* V1_ZOOM_CONTROL - 0x24C */ +#define V1_X_ZOOM_ENABLE 0x80000000 +#define V1_Y_ZOOM_ENABLE 0x00008000 + +/* V1_MINI_CONTROL - 0x250 */ +#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V1_X_DIV_2 0x01000000 +#define V1_X_DIV_4 0x03000000 +#define V1_X_DIV_8 0x05000000 +#define V1_X_DIV_16 0x07000000 +#define V1_Y_DIV_2 0x00010000 +#define V1_Y_DIV_4 0x00030000 +#define V1_Y_DIV_8 0x00050000 +#define V1_Y_DIV_16 0x00070000 + +/* V1_STARTADDR0 - 0x254 */ +#define SW_FLIP_ODD 0x08000000 + +/* V_FIFO_CONTROL - 0x258 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V1_FIFO_DEPTH12 0x0000000B +#define V1_FIFO_DEPTH16 0x0000000F +#define V1_FIFO_DEPTH32 0x0000001F +#define V1_FIFO_DEPTH48 0x0000002F +#define V1_FIFO_DEPTH64 0x0000003F +#define V1_FIFO_THRESHOLD6 0x00000600 +#define V1_FIFO_THRESHOLD8 0x00000800 +#define V1_FIFO_THRESHOLD12 0x00000C00 +#define V1_FIFO_THRESHOLD16 0x00001000 +#define V1_FIFO_THRESHOLD24 0x00001800 +#define V1_FIFO_THRESHOLD32 0x00002000 +#define V1_FIFO_THRESHOLD40 0x00002800 +#define V1_FIFO_THRESHOLD48 0x00003000 +#define V1_FIFO_THRESHOLD56 0x00003800 +#define V1_FIFO_THRESHOLD61 0x00003D00 +#define V1_FIFO_PRETHRESHOLD10 0x0A000000 +#define V1_FIFO_PRETHRESHOLD12 0x0C000000 +#define V1_FIFO_PRETHRESHOLD29 0x1d000000 +#define V1_FIFO_PRETHRESHOLD40 0x28000000 +#define V1_FIFO_PRETHRESHOLD44 0x2c000000 +#define V1_FIFO_PRETHRESHOLD56 0x38000000 +#define V1_FIFO_PRETHRESHOLD61 0x3D000000 + +/* ALPHA_V3_FIFO_CONTROL - 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * 8 level FIFO for ALPHA + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V3_FIFO_DEPTH16 0x0000000F +#define V3_FIFO_DEPTH24 0x00000017 +#define V3_FIFO_DEPTH32 0x0000001F +#define V3_FIFO_DEPTH48 0x0000002F +#define V3_FIFO_DEPTH64 0x0000003F +#define V3_FIFO_THRESHOLD8 0x00000800 +#define V3_FIFO_THRESHOLD12 0x00000C00 +#define V3_FIFO_THRESHOLD16 0x00001000 +#define V3_FIFO_THRESHOLD24 0x00001800 +#define V3_FIFO_THRESHOLD32 0x00002000 +#define V3_FIFO_THRESHOLD40 0x00002800 +#define V3_FIFO_THRESHOLD48 0x00003000 +#define V3_FIFO_THRESHOLD61 0x00003D00 +#define V3_FIFO_PRETHRESHOLD10 0x0000000A +#define V3_FIFO_PRETHRESHOLD12 0x0000000C +#define V3_FIFO_PRETHRESHOLD29 0x0000001d +#define V3_FIFO_PRETHRESHOLD40 0x00000028 +#define V3_FIFO_PRETHRESHOLD44 0x0000002c +#define V3_FIFO_PRETHRESHOLD56 0x00000038 +#define V3_FIFO_PRETHRESHOLD61 0x0000003D +#define V3_FIFO_MASK 0x0000007F +#define ALPHA_FIFO_DEPTH8 0x00070000 +#define ALPHA_FIFO_THRESHOLD4 0x04000000 +#define ALPHA_FIFO_MASK 0xffff0000 +#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 + +/* IA2 */ +#define ColorSpaceValue_1 0x140020f2 +#define ColorSpaceValue_2 0x0a0a2c00 + +#define ColorSpaceValue_1_3123C0 0x13000DED +#define ColorSpaceValue_2_3123C0 0x13171000 + +/* For TV setting */ +#define ColorSpaceValue_1TV 0x140020f2 +#define ColorSpaceValue_2TV 0x0a0a2c00 + +/* V_COMPOSE_MODE - 0x298 */ +/* ENABLE_COLOR_KEYING - renamed from SELECT_VIDEO_IF_COLOR_KEY for DirectFB*/ +#define ENABLE_COLOR_KEYING 0x00000001 /* select video if (color key),otherwise select graphics */ +#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ +#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ +#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ +#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ +#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ +#define COMPOSE_V1_TOP 0x00000000 +#define COMPOSE_V3_TOP 0x00100000 +#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ +#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ +#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ +#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ +#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ +#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ +#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 + +/* V3_ZOOM_CONTROL - 0x2bc */ +#define V3_X_ZOOM_ENABLE 0x80000000 +#define V3_Y_ZOOM_ENABLE 0x00008000 + +/* V3_MINI_CONTROL - 0x2c0 */ +#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V3_X_DIV_2 0x01000000 +#define V3_X_DIV_4 0x03000000 +#define V3_X_DIV_8 0x05000000 +#define V3_X_DIV_16 0x07000000 +#define V3_Y_DIV_2 0x00010000 +#define V3_Y_DIV_4 0x00030000 +#define V3_Y_DIV_8 0x00050000 +#define V3_Y_DIV_16 0x00070000 + +/* SUBP_CONTROL_STRIDE - 0x3c0 */ +#define SUBP_HQV_ENABLE 0x00010000 +#define SUBP_IA44 0x00020000 +#define SUBP_AI44 0x00000000 +#define SUBP_STRIDE_MASK 0x00001fff +#define SUBP_CONTROL_MASK 0x00070000 + +/* RAM_TABLE_CONTROL - 0x3c8 */ +#define RAM_TABLE_RGB_ENABLE 0x00000007 + +/* CAPTURE0_CONTROL - 0x310 */ +#define C0_ENABLE 0x00000001 +#define BUFFER_2_MODE 0x00000000 +#define BUFFER_3_MODE 0x00000004 +#define BUFFER_4_MODE 0x00000006 +#define SWAP_YUYV 0x00000000 +#define SWAP_UYVY 0x00000100 +#define SWAP_YVYU 0x00000200 +#define SWAP_VYUY 0x00000300 +#define IN_601_8 0x00000000 +#define IN_656_8 0x00000010 +#define IN_601_16 0x00000020 +#define IN_656_16 0x00000030 +#define DEINTER_ODD 0x00000000 +#define DEINTER_EVEN 0x00001000 +#define DEINTER_ODD_EVEN 0x00002000 +#define DEINTER_FRAME 0x00003000 +#define VIP_1 0x00000000 +#define VIP_2 0x00000400 +#define H_FILTER_2 0x00010000 +#define H_FILTER_4 0x00020000 +#define H_FILTER_8_1331 0x00030000 +#define H_FILTER_8_12221 0x00040000 +#define VIP_ENABLE 0x00000008 +#define EN_FIELD_SIG 0x00000800 +#define VREF_INVERT 0x00100000 +#define FIELD_INPUT_INVERSE 0x00400000 +#define FIELD_INVERSE 0x40000000 + +#define C1_H_MINI_EN 0x00000800 +#define C0_H_MINI_EN 0x00000800 +#define C1_V_MINI_EN 0x04000000 +#define C0_V_MINI_EN 0x04000000 +#define C1_H_MINI_2 0x00000400 + +/* CAPTURE1_CONTROL - 0x354 */ +#define C1_ENABLE 0x00000001 + +/* V3_CONTROL - 0x2A0 */ +#define V3_ENABLE 0x00000001 +#define V3_FULL_SCREEN 0x00000002 +#define V3_YUV422 0x00000000 +#define V3_RGB32 0x00000004 +#define V3_RGB15 0x00000008 +#define V3_RGB16 0x0000000C +#define V3_COLORSPACE_SIGN 0x00000080 +#define V3_EXPIRE_NUM 0x00040000 +#define V3_EXPIRE_NUM_F 0x000f0000 +#define V3_BOB_ENABLE 0x00400000 +#define V3_FIELD_BASE 0x00000000 +#define V3_FRAME_BASE 0x01000000 +#define V3_SWAP_SW 0x00000000 +#define V3_SWAP_HW_HQV 0x02000000 +#define V3_FLIP_HW_CAPTURE0 0x04000000 +#define V3_FLIP_HW_CAPTURE1 0x06000000 + +/* V3_ALPHA_FETCH_COUNT - 0x2B8 */ +#define V3_FETCH_COUNT 0x3ff00000 +#define ALPHA_FETCH_COUNT 0x000003ff + +/* HQV_CONTROL - 0x3D0 */ +#define HQV_RGB32 0x00000000 +#define HQV_RGB16 0x20000000 +#define HQV_RGB15 0x30000000 +#define HQV_YUV422 0x80000000 +#define HQV_YUV420 0xC0000000 +#define HQV_ENABLE 0x08000000 +#define HQV_SRC_SW 0x00000000 +#define HQV_SRC_MC 0x01000000 +#define HQV_SRC_CAPTURE0 0x02000000 +#define HQV_SRC_CAPTURE1 0x03000000 +#define HQV_FLIP_EVEN 0x00000000 +#define HQV_FLIP_ODD 0x00000020 +#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ +#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ +#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ +#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ +#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ +#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ +#define HQV_IDLE 0x00000008 +#define HQV_FLIP_STATUS 0x00000001 +#define HQV_DOUBLE_BUFF 0x00000000 +#define HQV_TRIPLE_BUFF 0x04000000 +#define HQV_SUBPIC_FLIP 0x00008000 +#define HQV_FIFO_STATUS 0x00001000 + +/* HQV_FILTER_CONTROL - 0x3E4 */ +#define HQV_H_LOWPASS_2TAP 0x00000001 +#define HQV_H_LOWPASS_4TAP 0x00000002 +#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ +#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ +#define HQV_H_HIGH_PASS 0x00000008 +#define HQV_H_LOW_PASS 0x00000000 +#define HQV_V_LOWPASS_2TAP 0x00010000 +#define HQV_V_LOWPASS_4TAP 0x00020000 +#define HQV_V_LOWPASS_8TAP1 0x00030000 +#define HQV_V_LOWPASS_8TAP2 0x00040000 +#define HQV_V_HIGH_PASS 0x00080000 +#define HQV_V_LOW_PASS 0x00000000 +#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 +#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 +#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_H_HIPASS_F1_2TAP 0x00000050 +#define HQV_H_HIPASS_F2_2TAP 0x00000100 +#define HQV_V_HIPASS_F1_2TAP 0x00500000 +#define HQV_V_HIPASS_F2_2TAP 0x01000000 +#define HQV_H_HIPASS_F1_4TAP 0x00000060 +#define HQV_H_HIPASS_F2_4TAP 0x00000200 +#define HQV_V_HIPASS_F1_4TAP 0x00600000 +#define HQV_V_HIPASS_F2_4TAP 0x02000000 +#define HQV_H_HIPASS_F1_8TAP 0x00000080 +#define HQV_H_HIPASS_F2_8TAP 0x00000400 +#define HQV_V_HIPASS_F1_8TAP 0x00800000 +#define HQV_V_HIPASS_F2_8TAP 0x04000000 +/* IA2 NEW */ +#define HQV_V_FILTER2 0x00080000 +#define HQV_H_FILTER2 0x00000008 +#define HQV_H_TAP2_11 0x00000041 +#define HQV_H_TAP4_121 0x00000042 +#define HQV_H_TAP4_1111 0x00000401 +#define HQV_H_TAP8_1331 0x00000221 +#define HQV_H_TAP8_12221 0x00000402 +#define HQV_H_TAP16_1991 0x00000159 +#define HQV_H_TAP16_141041 0x0000026A +#define HQV_H_TAP32 0x0000015A +#define HQV_V_TAP2_11 0x00410000 +#define HQV_V_TAP4_121 0x00420000 +#define HQV_V_TAP4_1111 0x04010000 +#define HQV_V_TAP8_1331 0x02210000 +#define HQV_V_TAP8_12221 0x04020000 +#define HQV_V_TAP16_1991 0x01590000 +#define HQV_V_TAP16_141041 0x026A0000 +#define HQV_V_TAP32 0x015A0000 +#define HQV_V_FILTER_DEFAULT 0x00420000 +#define HQV_H_FILTER_DEFAULT 0x00000040 + +/* HQV_MINI_CONTROL - 0x3E8 */ +#define HQV_H_MINIFY_ENABLE 0x00000800 +#define HQV_V_MINIFY_ENABLE 0x08000000 +#define HQV_VDEBLOCK_FILTER 0x80000000 +#define HQV_HDEBLOCK_FILTER 0x00008000 + +#endif // __VIDREGS_H__ diff --git a/Source/DirectFB/gfxdrivers/vmware/Makefile.am b/Source/DirectFB/gfxdrivers/vmware/Makefile.am new file mode 100755 index 0000000..34c1c38 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/Makefile.am @@ -0,0 +1,36 @@ +## Makefile.am for DirectFB/src/core/gfxcards/vmware + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +vmware_LTLIBRARIES = libdirectfb_vmware.la + +if BUILD_STATIC +vmware_DATA = $(vmware_LTLIBRARIES:.la=.o) +endif + +vmwaredir = $(MODULEDIR)/gfxdrivers + +libdirectfb_vmware_la_SOURCES = \ + vmware_2d.c \ + vmware_2d.h \ + vmware_gfxdriver.c \ + vmware_gfxdriver.h + +libdirectfb_vmware_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) -lm + +libdirectfb_vmware_la_LIBADD = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/vmware/Makefile.in b/Source/DirectFB/gfxdrivers/vmware/Makefile.in new file mode 100755 index 0000000..5259e16 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/Makefile.in @@ -0,0 +1,598 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/vmware +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(vmwaredir)" "$(DESTDIR)$(vmwaredir)" +vmwareLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(vmware_LTLIBRARIES) +libdirectfb_vmware_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_vmware_la_OBJECTS = vmware_2d.lo vmware_gfxdriver.lo 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etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ 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$<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/vmware/vmware_2d.c b/Source/DirectFB/gfxdrivers/vmware/vmware_2d.c new file mode 100755 index 0000000..1e50978 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/vmware_2d.c @@ -0,0 +1,402 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +//#define DIRECT_ENABLE_DEBUG + +#include + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "vmware_2d.h" +#include "vmware_gfxdriver.h" + + +D_DEBUG_DOMAIN( VMWare_2D, "VMWare/2D", "VMWare 2D Acceleration" ); + +/* + * State validation flags. + * + * There's no prefix because of the macros below. + */ +enum { + DESTINATION = 0x00000001, + COLOR = 0x00000002, + + SOURCE = 0x00000010, + + ALL = 0x00000013 +}; + +/* + * State handling macros. + */ + +#define VMWARE_VALIDATE(flags) do { vdev->v_flags |= (flags); } while (0) +#define VMWARE_INVALIDATE(flags) do { vdev->v_flags &= ~(flags); } while (0) + +#define VMWARE_CHECK_VALIDATE(flag) do { \ + if (! (vdev->v_flags & flag)) \ + vmware_validate_##flag( vdev, state ); \ + } while (0) + + +/**************************************************************************************************/ + +/* + * Called by vmwareSetState() to ensure that the destination registers are properly set + * for execution of rendering functions. + */ +static inline void +vmware_validate_DESTINATION( VMWareDeviceData *vdev, + CardState *state ) +{ + /* Remember destination parameters for usage in rendering functions. */ + vdev->dst_addr = state->dst.addr; + vdev->dst_pitch = state->dst.pitch; + vdev->dst_format = state->dst.buffer->format; + vdev->dst_bpp = DFB_BYTES_PER_PIXEL( vdev->dst_format ); + + /* Set the flag. */ + VMWARE_VALIDATE( DESTINATION ); +} + +/* + * Called by vmwareSetState() to ensure that the color register is properly set + * for execution of rendering functions. + */ +static inline void +vmware_validate_COLOR( VMWareDeviceData *vdev, + CardState *state ) +{ + switch (vdev->dst_format) { + case DSPF_ARGB: + vdev->color_pixel = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + + case DSPF_RGB32: + vdev->color_pixel = PIXEL_RGB32( state->color.r, + state->color.g, + state->color.b ); + break; + + case DSPF_RGB16: + vdev->color_pixel = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b ); + break; + + default: + D_BUG( "unexpected format %s", dfb_pixelformat_name(vdev->dst_format) ); + } + + /* Set the flag. */ + VMWARE_VALIDATE( COLOR ); +} + +/* + * Called by vmwareSetState() to ensure that the source registers are properly set + * for execution of blitting functions. + */ +static inline void +vmware_validate_SOURCE( VMWareDeviceData *vdev, + CardState *state ) +{ + /* Remember source parameters for usage in rendering functions. */ + vdev->src_addr = state->src.addr; + vdev->src_pitch = state->src.pitch; + vdev->src_format = state->src.buffer->format; + vdev->src_bpp = DFB_BYTES_PER_PIXEL( vdev->src_format ); + + /* Set the flag. */ + VMWARE_VALIDATE( SOURCE ); +} + +/**************************************************************************************************/ + +/* + * Wait for the blitter to be idle. + * + * This function is called before memory that has been written to by the hardware is about to be + * accessed by the CPU (software driver) or another hardware entity like video encoder (by Flip()). + * It can also be called by applications explicitly, e.g. at the end of a benchmark loop to include + * execution time of queued commands in the measurement. + */ +DFBResult +vmwareEngineSync( void *drv, void *dev ) +{ + return DFB_OK; +} + +/* + * Reset the graphics engine. + */ +void +vmwareEngineReset( void *drv, void *dev ) +{ +} + +/* + * Start processing of queued commands if required. + * + * This function is called before returning from the graphics core to the application. + * Usually that's after each rendering function. The only functions causing multiple commands + * to be queued with a single emition at the end are DrawString(), TileBlit(), BatchBlit(), + * DrawLines() and possibly FillTriangle() which is emulated using multiple FillRectangle() calls. + */ +void +vmwareEmitCommands( void *drv, void *dev ) +{ +} + +/* + * Check for acceleration of 'accel' using the given 'state'. + */ +void +vmwareCheckState( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ) +{ + D_DEBUG_AT( VMWare_2D, "vmwareCheckState (state %p, accel 0x%08x) <- dest %p\n", + state, accel, state->destination ); + + /* Return if the desired function is not supported at all. */ + if (accel & ~(VMWARE_SUPPORTED_DRAWINGFUNCTIONS | VMWARE_SUPPORTED_BLITTINGFUNCTIONS)) + return; + + /* Return if the destination format is not supported. */ + switch (state->destination->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB16: + break; + + default: + return; + } + + /* Check if drawing or blitting is requested. */ + if (DFB_DRAWING_FUNCTION( accel )) { + /* Return if unsupported drawing flags are set. */ + if (state->drawingflags & ~VMWARE_SUPPORTED_DRAWINGFLAGS) + return; + } + else { + /* Return if the source format is not supported. */ + switch (state->source->config.format) { + case DSPF_ARGB: + case DSPF_RGB32: + case DSPF_RGB16: + /* FIXME: Currently only copying blits supported. */ + if (state->source->config.format == state->destination->config.format) + break; + + default: + return; + } + + /* Return if unsupported blitting flags are set. */ + if (state->blittingflags & ~VMWARE_SUPPORTED_BLITTINGFLAGS) + return; + } + + /* Enable acceleration of the function. */ + state->accel |= accel; +} + +/* + * Make sure that the hardware is programmed for execution of 'accel' according to the 'state'. + */ +void +vmwareSetState( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ) +{ + VMWareDeviceData *vdev = (VMWareDeviceData*) dev; + StateModificationFlags modified = state->mod_hw; + + D_DEBUG_AT( VMWare_2D, "vmwareSetState (state %p, accel 0x%08x) <- dest %p, modified 0x%08x\n", + state, accel, state->destination, modified ); + + /* + * 1) Invalidate hardware states + * + * Each modification to the hw independent state invalidates one or more hardware states. + */ + + /* Simply invalidate all? */ + if (modified == SMF_ALL) { + VMWARE_INVALIDATE( ALL ); + } + else if (modified) { + /* Invalidate destination registers. */ + if (modified & SMF_DESTINATION) + VMWARE_INVALIDATE( DESTINATION | COLOR ); + else if (modified & SMF_COLOR) + VMWARE_INVALIDATE( COLOR ); + + if (modified & SMF_SOURCE) + VMWARE_INVALIDATE( SOURCE ); + } + + /* + * 2) Validate hardware states + * + * Each function has its own set of states that need to be validated. + */ + + /* Always requiring valid destination... */ + VMWARE_CHECK_VALIDATE( DESTINATION ); + + /* Depending on the function... */ + switch (accel) { + case DFXL_FILLRECTANGLE: + /* ...require valid drawing color. */ + VMWARE_CHECK_VALIDATE( COLOR ); + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = VMWARE_SUPPORTED_DRAWINGFUNCTIONS; + break; + + case DFXL_BLIT: + /* ...require valid source. */ + VMWARE_CHECK_VALIDATE( SOURCE ); + + /* + * 3) Tell which functions can be called without further validation, i.e. SetState() + * + * When the hw independent state is changed, this collection is reset. + */ + state->set = VMWARE_SUPPORTED_BLITTINGFUNCTIONS; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + /* + * 4) Clear modification flags + * + * All flags have been evaluated in 1) and remembered for further validation. + * If the hw independent state is not modified, this function won't get called + * for subsequent rendering functions, unless they aren't defined by 3). + */ + state->mod_hw = 0; +} + +/* + * Render a filled rectangle using the current hardware state. + */ +bool +vmwareFillRectangle( void *drv, void *dev, DFBRectangle *rect ) +{ + VMWareDeviceData *vdev = (VMWareDeviceData*) dev; + void *addr = vdev->dst_addr + rect->y * vdev->dst_pitch + + DFB_BYTES_PER_LINE(vdev->dst_format, rect->x); + + D_DEBUG_AT( VMWare_2D, "%s( %d,%d-%dx%d )\n", __FUNCTION__, DFB_RECTANGLE_VALS( rect ) ); + + switch (vdev->dst_bpp) { + case 4: + while (rect->h--) { + int w = rect->w; + u32 *dst = addr; + + while (w--) + *dst++ = vdev->color_pixel; + + addr += vdev->dst_pitch; + } + break; + + case 2: + while (rect->h--) { + int w = rect->w; + u16 *dst = addr; + + while (w--) + *dst++ = vdev->color_pixel; + + addr += vdev->dst_pitch; + } + break; + + case 1: + while (rect->h--) { + int w = rect->w; + u8 *dst = addr; + + while (w--) + *dst++ = vdev->color_pixel; + + addr += vdev->dst_pitch; + } + break; + } + + return true; +} + +/* + * Render a filled rectangle using the current hardware state. + */ +bool +vmwareBlit( void *drv, void *dev, DFBRectangle *srect, int dx, int dy ) +{ + VMWareDeviceData *vdev = (VMWareDeviceData*) dev; + void *dst = vdev->dst_addr + dy * vdev->dst_pitch + + DFB_BYTES_PER_LINE(vdev->dst_format, dx); + void *src = vdev->src_addr + srect->y * vdev->src_pitch + + DFB_BYTES_PER_LINE(vdev->src_format, srect->x); + + D_DEBUG_AT( VMWare_2D, "%s( %d,%d-%dx%d -> %d, %d )\n", __FUNCTION__, + DFB_RECTANGLE_VALS( srect ), dx, dy ); + + while (srect->h--) { + direct_memcpy( dst, src, srect->w * vdev->dst_bpp ); + + dst += vdev->dst_pitch; + src += vdev->src_pitch; + } + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/vmware/vmware_2d.h b/Source/DirectFB/gfxdrivers/vmware/vmware_2d.h new file mode 100755 index 0000000..95be709 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/vmware_2d.h @@ -0,0 +1,67 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __VMWARE_2D_H__ +#define __VMWARE_2D_H__ + + +#define VMWARE_SUPPORTED_DRAWINGFLAGS (DSDRAW_NOFX) + +#define VMWARE_SUPPORTED_DRAWINGFUNCTIONS (DFXL_FILLRECTANGLE) + +#define VMWARE_SUPPORTED_BLITTINGFLAGS (DSBLIT_NOFX) + +#define VMWARE_SUPPORTED_BLITTINGFUNCTIONS (DFXL_BLIT) + + +DFBResult vmwareEngineSync ( void *drv, + void *dev ); + +void vmwareEngineReset ( void *drv, + void *dev ); + +void vmwareEmitCommands ( void *drv, + void *dev ); + +void vmwareCheckState ( void *drv, + void *dev, + CardState *state, + DFBAccelerationMask accel ); + +void vmwareSetState ( void *drv, + void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, + DFBAccelerationMask accel ); + +bool vmwareFillRectangle( void *drv, + void *dev, + DFBRectangle *rect ); + +bool vmwareBlit ( void *drv, + void *dev, + DFBRectangle *srect, + int dx, + int dy ); + +#endif + diff --git a/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.c b/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.c new file mode 100755 index 0000000..ee39561 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.c @@ -0,0 +1,128 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include + +#include + +#include +#include + +#include + +#include "vmware_2d.h" +#include "vmware_gfxdriver.h" + + +#include + +DFB_GRAPHICS_DRIVER( vmware ) + + +/**********************************************************************************************************************/ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_VMWARE_BLITTER: + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "VMWare Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "Denis Oliver Kropp" ); + + info->version.major = 0; + info->version.minor = 0; + + info->driver_data_size = sizeof(VMWareDriverData); + info->device_data_size = sizeof(VMWareDeviceData); +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + /* initialize function pointers */ + funcs->EngineSync = vmwareEngineSync; + funcs->EngineReset = vmwareEngineReset; + funcs->EmitCommands = vmwareEmitCommands; + funcs->CheckState = vmwareCheckState; + funcs->SetState = vmwareSetState; + funcs->FillRectangle = vmwareFillRectangle; + funcs->Blit = vmwareBlit; + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + /* fill device info */ + snprintf( device_info->vendor, DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "VMWare" ); + snprintf( device_info->name, DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "(fake) Blitter" ); + + /* device limitations */ + device_info->limits.surface_byteoffset_alignment = 8; + device_info->limits.surface_bytepitch_alignment = 8; + + device_info->caps.flags = 0; + device_info->caps.accel = VMWARE_SUPPORTED_DRAWINGFUNCTIONS | + VMWARE_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = VMWARE_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = VMWARE_SUPPORTED_BLITTINGFLAGS; + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ +} + diff --git a/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.h b/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.h new file mode 100755 index 0000000..3e747bf --- /dev/null +++ b/Source/DirectFB/gfxdrivers/vmware/vmware_gfxdriver.h @@ -0,0 +1,58 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __VMWARE_GFXDRIVER_H__ +#define __VMWARE_GFXDRIVER_H__ + +#ifndef FB_ACCEL_VMWARE_BLITTER +#define FB_ACCEL_VMWARE_BLITTER 51 +#endif + + +typedef struct { + /* validation flags */ + int v_flags; + + /* cached/computed values */ + void *dst_addr; + unsigned long dst_pitch; + DFBSurfacePixelFormat dst_format; + unsigned long dst_bpp; + + void *src_addr; + unsigned long src_pitch; + DFBSurfacePixelFormat src_format; + unsigned long src_bpp; + + unsigned long color_pixel; + + /** Add shared data here... **/ +} VMWareDeviceData; + + +typedef struct { + + /** Add local data here... **/ +} VMWareDriverData; + + +#endif -- cgit