diff options
Diffstat (limited to 'Source/DirectFB/gfxdrivers/cle266')
22 files changed, 7435 insertions, 0 deletions
diff --git a/Source/DirectFB/gfxdrivers/cle266/Makefile.am b/Source/DirectFB/gfxdrivers/cle266/Makefile.am new file mode 100755 index 0000000..fff4976 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/Makefile.am @@ -0,0 +1,47 @@ +## Makefile.am for DirectFB/gfxdrivers/cle266 + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +AM_CFLAGS = $(DFB_CFLAGS) + +cle266_LTLIBRARIES = libdirectfb_cle266.la + +if BUILD_STATIC +cle266_DATA = $(cle266_LTLIBRARIES:.la=.o) +endif + +cle266dir = $(MODULEDIR)/gfxdrivers + +libdirectfb_cle266_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_cle266_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_cle266_la_LIBADD = \ + -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make + diff --git a/Source/DirectFB/gfxdrivers/cle266/Makefile.in b/Source/DirectFB/gfxdrivers/cle266/Makefile.in new file mode 100755 index 0000000..0c7ee2b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/Makefile.in @@ -0,0 +1,619 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/cle266 +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(cle266dir)" "$(DESTDIR)$(cle266dir)" +cle266LTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(cle266_LTLIBRARIES) +libdirectfb_cle266_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_cle266_la_OBJECTS = unichrome.lo uc_accel.lo \ + uc_hwset.lo uc_hwmap.lo uc_state.lo uc_fifo.lo uc_overlay.lo \ + uc_ovl_hwmap.lo uc_ovl_hwset.lo uc_primary.lo +libdirectfb_cle266_la_OBJECTS = $(am_libdirectfb_cle266_la_OBJECTS) +libdirectfb_cle266_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_cle266_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_cle266_la_SOURCES) +DIST_SOURCES = $(libdirectfb_cle266_la_SOURCES) +cle266DATA_INSTALL = $(INSTALL_DATA) +DATA = $(cle266_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ +LD = @LD@ +LDFLAGS = @LDFLAGS@ +LIBJPEG = @LIBJPEG@ +LIBOBJS = @LIBOBJS@ +LIBPNG = @LIBPNG@ +LIBPNG_CONFIG = @LIBPNG_CONFIG@ +LIBS = @LIBS@ +LIBTOOL = @LIBTOOL@ +LN_S = @LN_S@ +LTLIBOBJS = @LTLIBOBJS@ +LT_AGE = @LT_AGE@ +LT_BINARY = @LT_BINARY@ +LT_CURRENT = @LT_CURRENT@ +LT_RELEASE = @LT_RELEASE@ +LT_REVISION = @LT_REVISION@ +MAINT = @MAINT@ +MAKEINFO = @MAKEINFO@ +MAN2HTML = @MAN2HTML@ +MKDIR_P = @MKDIR_P@ +MODULEDIR = @MODULEDIR@ +MODULEDIRNAME = @MODULEDIRNAME@ +NMEDIT = @NMEDIT@ +OBJEXT = @OBJEXT@ +OSX_LIBS = @OSX_LIBS@ +PACKAGE = @PACKAGE@ +PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ +PACKAGE_NAME = @PACKAGE_NAME@ +PACKAGE_STRING = @PACKAGE_STRING@ +PACKAGE_TARNAME = @PACKAGE_TARNAME@ +PACKAGE_VERSION = @PACKAGE_VERSION@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +PERL = @PERL@ +PKG_CONFIG = @PKG_CONFIG@ +PNG_PROVIDER = @PNG_PROVIDER@ +RANLIB = @RANLIB@ +RUNTIME_SYSROOT = @RUNTIME_SYSROOT@ +SDL_CFLAGS = @SDL_CFLAGS@ +SDL_LIBS = @SDL_LIBS@ +SED = @SED@ +SET_MAKE = @SET_MAKE@ +SHELL = @SHELL@ +SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/systems \ + -I$(top_srcdir)/src + +AM_CFLAGS = $(DFB_CFLAGS) +cle266_LTLIBRARIES = libdirectfb_cle266.la +@BUILD_STATIC_TRUE@cle266_DATA = $(cle266_LTLIBRARIES:.la=.o) +cle266dir = $(MODULEDIR)/gfxdrivers +libdirectfb_cle266_la_SOURCES = \ + unichrome.c unichrome.h \ + uc_accel.c uc_accel.h \ + uc_hw.h \ + uc_hwset.c uc_hwmap.c \ + uc_state.c uc_state.h \ + uc_fifo.c uc_fifo.h \ + uc_overlay.c uc_overlay.h \ + uc_ovl_hwmap.c uc_ovl_hwset.c \ + uc_primary.c \ + mmio.h vidregs.h \ + regs2d.h regs3d.h + +libdirectfb_cle266_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_cle266_la_LIBADD = \ + -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu gfxdrivers/cle266/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu gfxdrivers/cle266/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-cle266LTLIBRARIES: $(cle266_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(cle266dir)" || $(MKDIR_P) "$(DESTDIR)$(cle266dir)" + @list='$(cle266_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(cle266LTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(cle266dir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(cle266LTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(cle266dir)/$$f"; \ + else :; fi; \ + done + +uninstall-cle266LTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(cle266_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(cle266dir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(cle266dir)/$$p"; \ + done + +clean-cle266LTLIBRARIES: + -test -z "$(cle266_LTLIBRARIES)" || rm -f $(cle266_LTLIBRARIES) + @list='$(cle266_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libdirectfb_cle266.la: $(libdirectfb_cle266_la_OBJECTS) $(libdirectfb_cle266_la_DEPENDENCIES) + $(libdirectfb_cle266_la_LINK) -rpath $(cle266dir) $(libdirectfb_cle266_la_OBJECTS) $(libdirectfb_cle266_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_accel.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_fifo.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_hwmap.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/uc_hwset.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ 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\ + topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ + list='$(DISTFILES)'; \ + dist_files=`for file in $$list; do echo $$file; done | \ + sed -e "s|^$$srcdirstrip/||;t" \ + -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ + case $$dist_files in \ + */*) $(MKDIR_P) `echo "$$dist_files" | \ + sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ + sort -u` ;; \ + esac; \ + for file in $$dist_files; do \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + if test -d $$d/$$file; then \ + dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-am +all-am: Makefile $(LTLIBRARIES) $(DATA) +installdirs: + for dir in "$(DESTDIR)$(cle266dir)" "$(DESTDIR)$(cle266dir)"; do \ + test -z "$$dir" || $(MKDIR_P) "$$dir"; \ + done +install: install-am +install-exec: install-exec-am +install-data: install-data-am +uninstall: uninstall-am + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-am +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + +distclean-generic: + -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." +clean: clean-am + +clean-am: clean-cle266LTLIBRARIES clean-generic clean-libtool \ + mostlyclean-am + +distclean: distclean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +distclean-am: clean-am distclean-compile distclean-generic \ + distclean-tags + +dvi: dvi-am + +dvi-am: + +html: html-am + +info: info-am + +info-am: + +install-data-am: install-cle266DATA install-cle266LTLIBRARIES + +install-dvi: install-dvi-am + +install-exec-am: + +install-html: install-html-am + +install-info: install-info-am + +install-man: + +install-pdf: install-pdf-am + +install-ps: install-ps-am + +installcheck-am: + +maintainer-clean: maintainer-clean-am + -rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-cle266DATA uninstall-cle266LTLIBRARIES + +.MAKE: install-am install-strip + +.PHONY: CTAGS GTAGS all all-am check check-am clean \ + clean-cle266LTLIBRARIES clean-generic clean-libtool ctags \ + distclean distclean-compile distclean-generic \ + distclean-libtool distclean-tags distdir dvi dvi-am html \ + html-am info info-am install install-am install-cle266DATA \ + install-cle266LTLIBRARIES install-data install-data-am \ + install-dvi install-dvi-am install-exec install-exec-am \ + install-html install-html-am install-info install-info-am \ + install-man install-pdf install-pdf-am install-ps \ + install-ps-am install-strip installcheck installcheck-am \ + installdirs maintainer-clean maintainer-clean-generic \ + mostlyclean mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool pdf pdf-am ps ps-am tags uninstall \ + uninstall-am uninstall-cle266DATA uninstall-cle266LTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/cle266/mmio.h b/Source/DirectFB/gfxdrivers/cle266/mmio.h new file mode 100755 index 0000000..757445a --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/mmio.h @@ -0,0 +1,43 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef _VIA_MMIO_H +#define _VIA_MMIO_H + +#define TRACE_ENTER() printf("Entering %s\n", __PRETTY_FUNCTION__) +#define TRACE_LEAVE() printf("Leaving %s\n", __PRETTY_FUNCTION__) + +#ifdef KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + + +#else // !KERNEL + +#define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) + +#define RS16(val) ((u16)((s16)(val))) +#define RS12(val) (((u16)((s16)(val))) & 0xfff) + +#endif // KERNEL + +#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) +#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) + +#define MAXLOOP 0xffffff + +#endif /* _VIA_MMIO_H */ diff --git a/Source/DirectFB/gfxdrivers/cle266/regs2d.h b/Source/DirectFB/gfxdrivers/cle266/regs2d.h new file mode 100755 index 0000000..33c7951 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/regs2d.h @@ -0,0 +1,197 @@ +// Note: This is a modified version of via_regs.h from the XFree86 CVS tree. + +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_2D_H__ +#define __VIA_REGS_2D_H__ + +/* Selected 2D engine raster operations. + * See xc/programs/Xserver/hw/xfree86/xaa/xaarop.h + * in the XFree86 project for the full list. + */ +#define VIA_ROP_DPx (0x5A << 24) +#define VIA_ROP_DSx (0x66 << 24) +#define VIA_ROP_S (0xCC << 24) +#define VIA_ROP_P (0xF0 << 24) + +/* My own reverse-engineered bit definitions */ + +// Use the following definitions with VIA_KEY_CONTROL + +/// When set, red channel is not drawn +#define VIA_KEY_MASK_RED 0x40000000 +/// When set, green channel is not drawn +#define VIA_KEY_MASK_GREEN 0x20000000 +/// When set, blue channel is not drawn +#define VIA_KEY_MASK_BLUE 0x10000000 + +/** When set, destination keying is enabled. + * Caveat: VIA's destination key is the opposite of DirectFB's: + * It draws where there is no match in the destination surface. + */ +#define VIA_KEY_ENABLE_DSTKEY 0x8000 +/** When set, source keying is enabled + * It draws the pixels in the source that do not match the color key. + */ +#define VIA_KEY_ENABLE_SRCKEY 0x4000 +/** Inverts the behaviour of the color keys: + * Dst key: draw where the destination matches the key + * Src key: draw where the source matches the key + * Problem: Since this bit affects both keys, you can not do + * combined source and destination keying with DirectFB. + * The inverted source key is all but useless since it will + * only draw the source pixels that match the key! + * It must be a design error... + */ +#define VIA_KEY_INVERT_KEY 0x2000 + +/* 2D engine registers and bit definitions */ + +#define VIA_MMIO_REGSIZE 0x9000 +#define VIA_MMIO_REGBASE 0x0 +#define VIA_MMIO_VGABASE 0x8000 +#define VIA_MMIO_BLTBASE 0x200000 +#define VIA_MMIO_BLTSIZE 0x10000 + +#define VIA_VQ_SIZE (256*1024) + +/* defines for VIA 2D registers */ +#define VIA_REG_GECMD 0x000 +#define VIA_REG_GEMODE 0x004 +#define VIA_REG_GESTATUS 0x004 /* as same as VIA_REG_GEMODE */ +#define VIA_REG_SRCPOS 0x008 +#define VIA_REG_DSTPOS 0x00C +#define VIA_REG_LINE_K1K2 0x008 +#define VIA_REG_LINE_XY 0x00C +#define VIA_REG_DIMENSION 0x010 /* width and height */ +#define VIA_REG_PATADDR 0x014 +#define VIA_REG_FGCOLOR 0x018 +#define VIA_REG_DSTCOLORKEY 0x018 /* as same as VIA_REG_FG */ +#define VIA_REG_BGCOLOR 0x01C +#define VIA_REG_SRCCOLORKEY 0x01C /* as same as VIA_REG_BG */ +#define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ +#define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ +#define VIA_REG_OFFSET 0x028 +#define VIA_REG_LINE_ERROR 0x028 +#define VIA_REG_KEYCONTROL 0x02C /* color key control */ +#define VIA_REG_SRCBASE 0x030 +#define VIA_REG_DSTBASE 0x034 +#define VIA_REG_PITCH 0x038 /* pitch of src and dst */ +#define VIA_REG_MONOPAT0 0x03C +#define VIA_REG_MONOPAT1 0x040 +#define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ + + +/* defines for VIA video registers */ +#define VIA_REG_INTERRUPT 0x200 +#define VIA_REG_CRTCSTART 0x214 + + +/* defines for VIA HW cursor registers */ +#define VIA_REG_CURSOR_MODE 0x2D0 +#define VIA_REG_CURSOR_POS 0x2D4 +#define VIA_REG_CURSOR_ORG 0x2D8 +#define VIA_REG_CURSOR_BG 0x2DC +#define VIA_REG_CURSOR_FG 0x2E0 + + +/* defines for VIA 3D registers */ +#define VIA_REG_STATUS 0x400 +#define VIA_REG_TRANSET 0x43C +#define VIA_REG_TRANSPACE 0x440 + +/* VIA_REG_STATUS(0x400): Engine Status */ +#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ + + +/* VIA_REG_GECMD(0x00): 2D Engine Command */ +#define VIA_GEC_NOOP 0x00000000 +#define VIA_GEC_BLT 0x00000001 +#define VIA_GEC_LINE 0x00000005 + +#define VIA_GEC_SRC_XY 0x00000000 +#define VIA_GEC_SRC_LINEAR 0x00000010 +#define VIA_GEC_DST_XY 0x00000000 +#define VIA_GEC_DST_LINRAT 0x00000020 + +#define VIA_GEC_SRC_FB 0x00000000 +#define VIA_GEC_SRC_SYS 0x00000040 +#define VIA_GEC_DST_FB 0x00000000 +#define VIA_GEC_DST_SYS 0x00000080 + +#define VIA_GEC_SRC_MONO 0x00000100 /* source is mono */ +#define VIA_GEC_PAT_MONO 0x00000200 /* pattern is mono */ + +#define VIA_GEC_MSRC_OPAQUE 0x00000000 /* mono src is opaque */ +#define VIA_GEC_MSRC_TRANS 0x00000400 /* mono src is transparent */ + +#define VIA_GEC_PAT_FB 0x00000000 /* pattern is in frame buffer */ +#define VIA_GEC_PAT_REG 0x00000800 /* pattern is from reg setting */ + +#define VIA_GEC_CLIP_DISABLE 0x00000000 +#define VIA_GEC_CLIP_ENABLE 0x00001000 + +#define VIA_GEC_FIXCOLOR_PAT 0x00002000 + +#define VIA_GEC_INCX 0x00000000 +#define VIA_GEC_DECY 0x00004000 +#define VIA_GEC_INCY 0x00000000 +#define VIA_GEC_DECX 0x00008000 + +#define VIA_GEC_MPAT_OPAQUE 0x00000000 /* mono pattern is opaque */ +#define VIA_GEC_MPAT_TRANS 0x00010000 /* mono pattern is transparent */ + +#define VIA_GEC_MONO_UNPACK 0x00000000 +#define VIA_GEC_MONO_PACK 0x00020000 +#define VIA_GEC_MONO_DWORD 0x00000000 +#define VIA_GEC_MONO_WORD 0x00040000 +#define VIA_GEC_MONO_BYTE 0x00080000 + +#define VIA_GEC_LASTPIXEL_ON 0x00000000 +#define VIA_GEC_LASTPIXEL_OFF 0x00100000 +#define VIA_GEC_X_MAJOR 0x00000000 +#define VIA_GEC_Y_MAJOR 0x00200000 +#define VIA_GEC_QUICK_START 0x00800000 + + +/* VIA_REG_GEMODE(0x04): GE mode */ +#define VIA_GEM_8bpp 0x00000000 +#define VIA_GEM_16bpp 0x00000100 +#define VIA_GEM_32bpp 0x00000300 + +#define VIA_GEM_640 0x00000000 /* 640*480 */ +#define VIA_GEM_800 0x00000400 /* 800*600 */ +#define VIA_GEM_1024 0x00000800 /* 1024*768 */ +#define VIA_GEM_1280 0x00000C00 /* 1280*1024 */ +#define VIA_GEM_1600 0x00001000 /* 1600*1200 */ +#define VIA_GEM_2048 0x00001400 /* 2048*1536 */ + +/* VIA_REG_PITCH(0x38): Pitch Setting */ +#define VIA_PITCH_ENABLE 0x80000000 + +#endif // __VIA_REGS_2D_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/regs3d.h b/Source/DirectFB/gfxdrivers/cle266/regs3d.h new file mode 100755 index 0000000..ebc6a0d --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/regs3d.h @@ -0,0 +1,1641 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_REGS_3D_H__ +#define __VIA_REGS_3D_H__ + +#define HC_REG_BASE 0x0400 + +#define HC_ParaN_MASK 0xffffffff +#define HC_Para_MASK 0x00ffffff +#define HC_SubA_MASK 0xff000000 +#define HC_SubA_SHIFT 24 +/* Transmission Setting + */ +#define HC_REG_TRANS_SET 0x003c +#define HC_ParaSubType_MASK 0xff000000 +#define HC_ParaType_MASK 0x00ff0000 +#define HC_ParaOS_MASK 0x0000ff00 +#define HC_ParaAdr_MASK 0x000000ff +#define HC_ParaSubType_SHIFT 24 +#define HC_ParaType_SHIFT 16 +#define HC_ParaOS_SHIFT 8 +#define HC_ParaAdr_SHIFT 0 + +#define HC_ParaType_CmdVdata 0x0000 +#define HC_ParaType_NotTex 0x0001 +#define HC_ParaType_Tex 0x0002 +#define HC_ParaType_Palette 0x0003 +#define HC_ParaType_PreCR 0x0010 +#define HC_ParaType_Auto 0x00fe + +/* Transmission Space + */ +#define HC_REG_Hpara0 0x0040 +#define HC_REG_HpataAF 0x02fc + +/* Read + */ +#define HC_REG_HREngSt 0x0000 +#define HC_REG_HRFIFOempty 0x0004 +#define HC_REG_HRFIFOfull 0x0008 +#define HC_REG_HRErr 0x000c +#define HC_REG_FIFOstatus 0x0010 +/* HC_REG_HREngSt 0x0000 + */ +#define HC_HDASZC_MASK 0x00010000 +#define HC_HSGEMI_MASK 0x0000f000 +#define HC_HLGEMISt_MASK 0x00000f00 +#define HC_HCRSt_MASK 0x00000080 +#define HC_HSE0St_MASK 0x00000040 +#define HC_HSE1St_MASK 0x00000020 +#define HC_HPESt_MASK 0x00000010 +#define HC_HXESt_MASK 0x00000008 +#define HC_HBESt_MASK 0x00000004 +#define HC_HE2St_MASK 0x00000002 +#define HC_HE3St_MASK 0x00000001 +/* HC_REG_HRFIFOempty 0x0004 + */ +#define HC_HRZDempty_MASK 0x00000010 +#define HC_HRTXAempty_MASK 0x00000008 +#define HC_HRTXDempty_MASK 0x00000004 +#define HC_HWZDempty_MASK 0x00000002 +#define HC_HWCDempty_MASK 0x00000001 +/* HC_REG_HRFIFOfull 0x0008 + */ +#define HC_HRZDfull_MASK 0x00000010 +#define HC_HRTXAfull_MASK 0x00000008 +#define HC_HRTXDfull_MASK 0x00000004 +#define HC_HWZDfull_MASK 0x00000002 +#define HC_HWCDfull_MASK 0x00000001 +/* HC_REG_HRErr 0x000c + */ +#define HC_HAGPCMErr_MASK 0x80000000 +#define HC_HAGPCMErrC_MASK 0x70000000 +/* HC_REG_FIFOstatus 0x0010 + */ +#define HC_HRFIFOATall_MASK 0x80000000 +#define HC_HRFIFOATbusy_MASK 0x40000000 +#define HC_HRATFGMDo_MASK 0x00000100 +#define HC_HRATFGMDi_MASK 0x00000080 +#define HC_HRATFRZD_MASK 0x00000040 +#define HC_HRATFRTXA_MASK 0x00000020 +#define HC_HRATFRTXD_MASK 0x00000010 +#define HC_HRATFWZD_MASK 0x00000008 +#define HC_HRATFWCD_MASK 0x00000004 +#define HC_HRATTXTAG_MASK 0x00000002 +#define HC_HRATTXCH_MASK 0x00000001 + +/* AGP Command Setting + */ +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +/* HC_SubA_HAGPCMNT 0x0062 + */ +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +/* HC_SubA_HAGPBpL 0x0063 + */ +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +/* HC_SubA_HAGPBpH 0x0064 + */ +#define HC_HAGPBpH_MASK 0x00ffffff + +/* Miscellaneous Settings + */ +#define HC_SubA_HClipTB 0x0070 +#define HC_SubA_HClipLR 0x0071 +#define HC_SubA_HFPClipTL 0x0072 +#define HC_SubA_HFPClipBL 0x0073 +#define HC_SubA_HFPClipLL 0x0074 +#define HC_SubA_HFPClipRL 0x0075 +#define HC_SubA_HFPClipTBH 0x0076 +#define HC_SubA_HFPClipLRH 0x0077 +#define HC_SubA_HLP 0x0078 +#define HC_SubA_HLPRF 0x0079 +#define HC_SubA_HSolidCL 0x007a +#define HC_SubA_HPixGC 0x007b +#define HC_SubA_HSPXYOS 0x007c +#define HC_SubA_HVertexCNT 0x007d + +#define HC_HClipT_MASK 0x00fff000 +#define HC_HClipT_SHIFT 12 +#define HC_HClipB_MASK 0x00000fff +#define HC_HClipB_SHIFT 0 +#define HC_HClipL_MASK 0x00fff000 +#define HC_HClipL_SHIFT 12 +#define HC_HClipR_MASK 0x00000fff +#define HC_HClipR_SHIFT 0 +#define HC_HFPClipBH_MASK 0x0000ff00 +#define HC_HFPClipBH_SHIFT 8 +#define HC_HFPClipTH_MASK 0x000000ff +#define HC_HFPClipTH_SHIFT 0 +#define HC_HFPClipRH_MASK 0x0000ff00 +#define HC_HFPClipRH_SHIFT 8 +#define HC_HFPClipLH_MASK 0x000000ff +#define HC_HFPClipLH_SHIFT 0 +#define HC_HSolidCH_MASK 0x000000ff +#define HC_HPixGC_MASK 0x00800000 +#define HC_HSPXOS_MASK 0x00fff000 +#define HC_HSPXOS_SHIFT 12 +#define HC_HSPYOS_MASK 0x00000fff + +/* Command + * Command A + */ +#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000*/ +#define HC_HE3Fire_MASK 0x00100000 +#define HC_HPMType_MASK 0x000f0000 +#define HC_HEFlag_MASK 0x0000e000 +#define HC_HShading_MASK 0x00001c00 +#define HC_HPMValidN_MASK 0x00000200 +#define HC_HPLEND_MASK 0x00000100 +#define HC_HVCycle_MASK 0x000000ff +#define HC_HVCycle_Style_MASK 0x000000c0 +#define HC_HVCycle_ChgA_MASK 0x00000030 +#define HC_HVCycle_ChgB_MASK 0x0000000c +#define HC_HVCycle_ChgC_MASK 0x00000003 +#define HC_HPMType_Point 0x00000000 +#define HC_HPMType_Line 0x00010000 +#define HC_HPMType_Tri 0x00020000 +#define HC_HPMType_TriWF 0x00040000 +#define HC_HEFlag_NoAA 0x00000000 +#define HC_HEFlag_ab 0x00008000 +#define HC_HEFlag_bc 0x00004000 +#define HC_HEFlag_ca 0x00002000 +#define HC_HShading_Solid 0x00000000 +#define HC_HShading_FlatA 0x00000400 +#define HC_HShading_FlatB 0x00000800 +#define HC_HShading_FlatC 0x00000c00 +#define HC_HShading_Gouraud 0x00001000 +#define HC_HVCycle_Full 0x00000000 +#define HC_HVCycle_AFP 0x00000040 +#define HC_HVCycle_One 0x000000c0 +#define HC_HVCycle_NewA 0x00000000 +#define HC_HVCycle_AA 0x00000010 +#define HC_HVCycle_AB 0x00000020 +#define HC_HVCycle_AC 0x00000030 +#define HC_HVCycle_NewB 0x00000000 +#define HC_HVCycle_BA 0x00000004 +#define HC_HVCycle_BB 0x00000008 +#define HC_HVCycle_BC 0x0000000c +#define HC_HVCycle_NewC 0x00000000 +#define HC_HVCycle_CA 0x00000001 +#define HC_HVCycle_CB 0x00000002 +#define HC_HVCycle_CC 0x00000003 + +/* Command B + */ +#define HC_HLPrst_MASK 0x00010000 +#define HC_HLLastP_MASK 0x00008000 +#define HC_HVPMSK_MASK 0x00007f80 +#define HC_HBFace_MASK 0x00000040 +#define HC_H2nd1VT_MASK 0x0000003f +#define HC_HVPMSK_X 0x00004000 +#define HC_HVPMSK_Y 0x00002000 +#define HC_HVPMSK_Z 0x00001000 +#define HC_HVPMSK_W 0x00000800 +#define HC_HVPMSK_Cd 0x00000400 +#define HC_HVPMSK_Cs 0x00000200 +#define HC_HVPMSK_S 0x00000100 +#define HC_HVPMSK_T 0x00000080 + +/* Enable Setting + */ +#define HC_SubA_HEnable 0x0000 +#define HC_HenTXEnvMap_MASK 0x00200000 /* environment mapping?? */ +#define HC_HenVertexCNT_MASK 0x00100000 /* vertex counter?? */ +#define HC_HenCPUDAZ_MASK 0x00080000 /* ???? */ +#define HC_HenDASZWC_MASK 0x00040000 /* ???? */ +#define HC_HenFBCull_MASK 0x00020000 /* culling? */ +#define HC_HenCW_MASK 0x00010000 /* color write? */ +#define HC_HenAA_MASK 0x00008000 /* anti aliasing??? */ +#define HC_HenST_MASK 0x00004000 /* stencil?? */ +#define HC_HenZT_MASK 0x00002000 /* z test?? */ +#define HC_HenZW_MASK 0x00001000 /* z write?? */ +#define HC_HenAT_MASK 0x00000800 /* alpha test?? */ +#define HC_HenAW_MASK 0x00000400 /* alpha write?? */ +#define HC_HenSP_MASK 0x00000200 /* specular?? */ +#define HC_HenLP_MASK 0x00000100 /* ???? */ +#define HC_HenTXCH_MASK 0x00000080 /* cache? half speed, right fonts */ +#define HC_HenTXMP_MASK 0x00000040 /* texture mapping */ +#define HC_HenTXPP_MASK 0x00000020 /* perspective correction?? */ +#define HC_HenTXTR_MASK 0x00000010 /* ???? */ +#define HC_HenCS_MASK 0x00000008 /* color space?? looks weird */ +#define HC_HenFOG_MASK 0x00000004 /* obviously fogging */ +#define HC_HenABL_MASK 0x00000002 /* alpha blending */ +#define HC_HenDT_MASK 0x00000001 /* dithering */ + +/* Z Setting + */ +#define HC_SubA_HZWBBasL 0x0010 +#define HC_SubA_HZWBBasH 0x0011 +#define HC_SubA_HZWBType 0x0012 +#define HC_SubA_HZBiasL 0x0013 +#define HC_SubA_HZWBend 0x0014 +#define HC_SubA_HZWTMD 0x0015 +#define HC_SubA_HZWCDL 0x0016 +#define HC_SubA_HZWCTAGnum 0x0017 +#define HC_SubA_HZCYNum 0x0018 +#define HC_SubA_HZWCFire 0x0019 +/* HC_SubA_HZWBType + */ +#define HC_HZWBType_MASK 0x00800000 +#define HC_HZBiasedWB_MASK 0x00400000 +#define HC_HZONEasFF_MASK 0x00200000 +#define HC_HZOONEasFF_MASK 0x00100000 +#define HC_HZWBFM_MASK 0x00030000 +#define HC_HZWBLoc_MASK 0x0000c000 +#define HC_HZWBPit_MASK 0x00003fff +#define HC_HZWBFM_16 0x00000000 +#define HC_HZWBFM_32 0x00020000 +#define HC_HZWBFM_24 0x00030000 +#define HC_HZWBLoc_Local 0x00000000 +#define HC_HZWBLoc_SyS 0x00004000 +/* HC_SubA_HZWBend + */ +#define HC_HZWBend_MASK 0x00ffe000 +#define HC_HZBiasH_MASK 0x000000ff +#define HC_HZWBend_SHIFT 10 +/* HC_SubA_HZWTMD + */ +#define HC_HZWTMD_MASK 0x00070000 +#define HC_HEBEBias_MASK 0x00007f00 +#define HC_HZNF_MASK 0x000000ff +#define HC_HZWTMD_NeverPass 0x00000000 +#define HC_HZWTMD_LT 0x00010000 +#define HC_HZWTMD_EQ 0x00020000 +#define HC_HZWTMD_LE 0x00030000 +#define HC_HZWTMD_GT 0x00040000 +#define HC_HZWTMD_NE 0x00050000 +#define HC_HZWTMD_GE 0x00060000 +#define HC_HZWTMD_AllPass 0x00070000 +#define HC_HEBEBias_SHIFT 8 +/* HC_SubA_HZWCDL 0x0016 + */ +#define HC_HZWCDL_MASK 0x00ffffff +/* HC_SubA_HZWCTAGnum 0x0017 + */ +#define HC_HZWCTAGnum_MASK 0x00ff0000 +#define HC_HZWCTAGnum_SHIFT 16 +#define HC_HZWCDH_MASK 0x000000ff +#define HC_HZWCDH_SHIFT 0 +/* HC_SubA_HZCYNum 0x0018 + */ +#define HC_HZCYNum_MASK 0x00030000 +#define HC_HZCYNum_SHIFT 16 +#define HC_HZWCQWnum_MASK 0x00003fff +#define HC_HZWCQWnum_SHIFT 0 +/* HC_SubA_HZWCFire 0x0019 + */ +#define HC_ZWCFire_MASK 0x00010000 +#define HC_HZWCQWnumLast_MASK 0x00003fff +#define HC_HZWCQWnumLast_SHIFT 0 + +/* Stencil Setting + */ +#define HC_SubA_HSTREF 0x0023 +#define HC_SubA_HSTMD 0x0024 +/* HC_SubA_HSBFM + */ +#define HC_HSBFM_MASK 0x00030000 +#define HC_HSBLoc_MASK 0x0000c000 +#define HC_HSBPit_MASK 0x00003fff +/* HC_SubA_HSTREF + */ +#define HC_HSTREF_MASK 0x00ff0000 +#define HC_HSTOPMSK_MASK 0x0000ff00 +#define HC_HSTBMSK_MASK 0x000000ff +#define HC_HSTREF_SHIFT 16 +#define HC_HSTOPMSK_SHIFT 8 +/* HC_SubA_HSTMD + */ +#define HC_HSTMD_MASK 0x00070000 +#define HC_HSTOPSF_MASK 0x000001c0 +#define HC_HSTOPSPZF_MASK 0x00000038 +#define HC_HSTOPSPZP_MASK 0x00000007 +#define HC_HSTMD_NeverPass 0x00000000 +#define HC_HSTMD_LT 0x00010000 +#define HC_HSTMD_EQ 0x00020000 +#define HC_HSTMD_LE 0x00030000 +#define HC_HSTMD_GT 0x00040000 +#define HC_HSTMD_NE 0x00050000 +#define HC_HSTMD_GE 0x00060000 +#define HC_HSTMD_AllPass 0x00070000 +#define HC_HSTOPSF_KEEP 0x00000000 +#define HC_HSTOPSF_ZERO 0x00000040 +#define HC_HSTOPSF_REPLACE 0x00000080 +#define HC_HSTOPSF_INCRSAT 0x000000c0 +#define HC_HSTOPSF_DECRSAT 0x00000100 +#define HC_HSTOPSF_INVERT 0x00000140 +#define HC_HSTOPSF_INCR 0x00000180 +#define HC_HSTOPSF_DECR 0x000001c0 +#define HC_HSTOPSPZF_KEEP 0x00000000 +#define HC_HSTOPSPZF_ZERO 0x00000008 +#define HC_HSTOPSPZF_REPLACE 0x00000010 +#define HC_HSTOPSPZF_INCRSAT 0x00000018 +#define HC_HSTOPSPZF_DECRSAT 0x00000020 +#define HC_HSTOPSPZF_INVERT 0x00000028 +#define HC_HSTOPSPZF_INCR 0x00000030 +#define HC_HSTOPSPZF_DECR 0x00000038 +#define HC_HSTOPSPZP_KEEP 0x00000000 +#define HC_HSTOPSPZP_ZERO 0x00000001 +#define HC_HSTOPSPZP_REPLACE 0x00000002 +#define HC_HSTOPSPZP_INCRSAT 0x00000003 +#define HC_HSTOPSPZP_DECRSAT 0x00000004 +#define HC_HSTOPSPZP_INVERT 0x00000005 +#define HC_HSTOPSPZP_INCR 0x00000006 +#define HC_HSTOPSPZP_DECR 0x00000007 + +/* Alpha Setting + */ +#define HC_SubA_HABBasL 0x0030 +#define HC_SubA_HABBasH 0x0031 +#define HC_SubA_HABFM 0x0032 +#define HC_SubA_HATMD 0x0033 +#define HC_SubA_HABLCsat 0x0034 +#define HC_SubA_HABLCop 0x0035 +#define HC_SubA_HABLAsat 0x0036 +#define HC_SubA_HABLAop 0x0037 +#define HC_SubA_HABLRCa 0x0038 +#define HC_SubA_HABLRFCa 0x0039 +#define HC_SubA_HABLRCbias 0x003a +#define HC_SubA_HABLRCb 0x003b +#define HC_SubA_HABLRFCb 0x003c +#define HC_SubA_HABLRAa 0x003d +#define HC_SubA_HABLRAb 0x003e +/* HC_SubA_HABFM + */ +#define HC_HABFM_MASK 0x00030000 +#define HC_HABLoc_MASK 0x0000c000 +#define HC_HABPit_MASK 0x000007ff +/* HC_SubA_HATMD + */ +#define HC_HATMD_MASK 0x00000700 +#define HC_HATREF_MASK 0x000000ff +#define HC_HATMD_NeverPass 0x00000000 +#define HC_HATMD_LT 0x00000100 +#define HC_HATMD_EQ 0x00000200 +#define HC_HATMD_LE 0x00000300 +#define HC_HATMD_GT 0x00000400 +#define HC_HATMD_NE 0x00000500 +#define HC_HATMD_GE 0x00000600 +#define HC_HATMD_AllPass 0x00000700 +/* HC_SubA_HABLCsat + */ +#define HC_HABLCsat_MASK 0x00010000 +#define HC_HABLCa_MASK 0x0000fc00 +#define HC_HABLCa_C_MASK 0x0000c000 +#define HC_HABLCa_OPC_MASK 0x00003c00 +#define HC_HABLFCa_MASK 0x000003f0 +#define HC_HABLFCa_C_MASK 0x00000300 +#define HC_HABLFCa_OPC_MASK 0x000000f0 +#define HC_HABLCbias_MASK 0x0000000f +#define HC_HABLCbias_C_MASK 0x00000008 +#define HC_HABLCbias_OPC_MASK 0x00000007 +/*-- Define the input color. + */ +#define HC_XC_Csrc 0x00000000 +#define HC_XC_Cdst 0x00000001 +#define HC_XC_Asrc 0x00000002 +#define HC_XC_Adst 0x00000003 +#define HC_XC_Fog 0x00000004 +#define HC_XC_HABLRC 0x00000005 +#define HC_XC_minSrcDst 0x00000006 +#define HC_XC_maxSrcDst 0x00000007 +#define HC_XC_mimAsrcInvAdst 0x00000008 +#define HC_XC_OPC 0x00000000 +#define HC_XC_InvOPC 0x00000010 +#define HC_XC_OPCp5 0x00000020 +/*-- Define the input Alpha + */ +#define HC_XA_OPA 0x00000000 +#define HC_XA_InvOPA 0x00000010 +#define HC_XA_OPAp5 0x00000020 +#define HC_XA_0 0x00000000 +#define HC_XA_Asrc 0x00000001 +#define HC_XA_Adst 0x00000002 +#define HC_XA_Fog 0x00000003 +#define HC_XA_minAsrcFog 0x00000004 +#define HC_XA_minAsrcAdst 0x00000005 +#define HC_XA_maxAsrcFog 0x00000006 +#define HC_XA_maxAsrcAdst 0x00000007 +#define HC_XA_HABLRA 0x00000008 +#define HC_XA_minAsrcInvAdst 0x00000008 +#define HC_XA_HABLFRA 0x00000009 +/*-- + */ +#define HC_HABLCa_OPC (HC_XC_OPC << 10) +#define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10) +#define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10) +#define HC_HABLCa_Csrc (HC_XC_Csrc << 10) +#define HC_HABLCa_Cdst (HC_XC_Cdst << 10) +#define HC_HABLCa_Asrc (HC_XC_Asrc << 10) +#define HC_HABLCa_Adst (HC_XC_Adst << 10) +#define HC_HABLCa_Fog (HC_XC_Fog << 10) +#define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10) +#define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10) +#define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10) +#define HC_HABLFCa_OPC (HC_XC_OPC << 4) +#define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4) +#define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4) +#define HC_HABLFCa_Csrc (HC_XC_Csrc << 4) +#define HC_HABLFCa_Cdst (HC_XC_Cdst << 4) +#define HC_HABLFCa_Asrc (HC_XC_Asrc << 4) +#define HC_HABLFCa_Adst (HC_XC_Adst << 4) +#define HC_HABLFCa_Fog (HC_XC_Fog << 4) +#define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4) +#define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4) +#define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4) +#define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4) +#define HC_HABLCbias_HABLRCbias 0x00000000 +#define HC_HABLCbias_Asrc 0x00000001 +#define HC_HABLCbias_Adst 0x00000002 +#define HC_HABLCbias_Fog 0x00000003 +#define HC_HABLCbias_Cin 0x00000004 +/* HC_SubA_HABLCop 0x0035 + */ +#define HC_HABLdot_MASK 0x00010000 +#define HC_HABLCop_MASK 0x00004000 +#define HC_HABLCb_MASK 0x00003f00 +#define HC_HABLCb_C_MASK 0x00003000 +#define HC_HABLCb_OPC_MASK 0x00000f00 +#define HC_HABLFCb_MASK 0x000000fc +#define HC_HABLFCb_C_MASK 0x000000c0 +#define HC_HABLFCb_OPC_MASK 0x0000003c +#define HC_HABLCshift_MASK 0x00000003 +#define HC_HABLCb_OPC (HC_XC_OPC << 8) +#define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8) +#define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8) +#define HC_HABLCb_Csrc (HC_XC_Csrc << 8) +#define HC_HABLCb_Cdst (HC_XC_Cdst << 8) +#define HC_HABLCb_Asrc (HC_XC_Asrc << 8) +#define HC_HABLCb_Adst (HC_XC_Adst << 8) +#define HC_HABLCb_Fog (HC_XC_Fog << 8) +#define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8) +#define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8) +#define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8) +#define HC_HABLFCb_OPC (HC_XC_OPC << 2) +#define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2) +#define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2) +#define HC_HABLFCb_Csrc (HC_XC_Csrc << 2) +#define HC_HABLFCb_Cdst (HC_XC_Cdst << 2) +#define HC_HABLFCb_Asrc (HC_XC_Asrc << 2) +#define HC_HABLFCb_Adst (HC_XC_Adst << 2) +#define HC_HABLFCb_Fog (HC_XC_Fog << 2) +#define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2) +#define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2) +#define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2) +#define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2) +/* HC_SubA_HABLAsat 0x0036 + */ +#define HC_HABLAsat_MASK 0x00010000 +#define HC_HABLAa_MASK 0x0000fc00 +#define HC_HABLAa_A_MASK 0x0000c000 +#define HC_HABLAa_OPA_MASK 0x00003c00 +#define HC_HABLFAa_MASK 0x000003f0 +#define HC_HABLFAa_A_MASK 0x00000300 +#define HC_HABLFAa_OPA_MASK 0x000000f0 +#define HC_HABLAbias_MASK 0x0000000f +#define HC_HABLAbias_A_MASK 0x00000008 +#define HC_HABLAbias_OPA_MASK 0x00000007 +#define HC_HABLAa_OPA (HC_XA_OPA << 10) +#define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10) +#define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10) +#define HC_HABLAa_0 (HC_XA_0 << 10) +#define HC_HABLAa_Asrc (HC_XA_Asrc << 10) +#define HC_HABLAa_Adst (HC_XA_Adst << 10) +#define HC_HABLAa_Fog (HC_XA_Fog << 10) +#define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10) +#define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10) +#define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10) +#define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10) +#define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10) +#define HC_HABLFAa_OPA (HC_XA_OPA << 4) +#define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4) +#define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4) +#define HC_HABLFAa_0 (HC_XA_0 << 4) +#define HC_HABLFAa_Asrc (HC_XA_Asrc << 4) +#define HC_HABLFAa_Adst (HC_XA_Adst << 4) +#define HC_HABLFAa_Fog (HC_XA_Fog << 4) +#define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4) +#define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4) +#define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4) +#define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4) +#define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4) +#define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4) +#define HC_HABLAbias_HABLRAbias 0x00000000 +#define HC_HABLAbias_Asrc 0x00000001 +#define HC_HABLAbias_Adst 0x00000002 +#define HC_HABLAbias_Fog 0x00000003 +#define HC_HABLAbias_Aaa 0x00000004 +/* HC_SubA_HABLAop 0x0037 + */ +#define HC_HABLAop_MASK 0x00004000 +#define HC_HABLAb_MASK 0x00003f00 +#define HC_HABLAb_OPA_MASK 0x00000f00 +#define HC_HABLFAb_MASK 0x000000fc +#define HC_HABLFAb_OPA_MASK 0x0000003c +#define HC_HABLAshift_MASK 0x00000003 +#define HC_HABLAb_OPA (HC_XA_OPA << 8) +#define HC_HABLAb_InvOPA (HC_XA_InvOPA << 8) +#define HC_HABLAb_OPAp5 (HC_XA_OPAp5 << 8) +#define HC_HABLAb_0 (HC_XA_0 << 8) +#define HC_HABLAb_Asrc (HC_XA_Asrc << 8) +#define HC_HABLAb_Adst (HC_XA_Adst << 8) +#define HC_HABLAb_Fog (HC_XA_Fog << 8) +#define HC_HABLAb_minAsrcFog (HC_XA_minAsrcFog << 8) +#define HC_HABLAb_minAsrcAdst (HC_XA_minAsrcAdst << 8) +#define HC_HABLAb_maxAsrcFog (HC_XA_maxAsrcFog << 8) +#define HC_HABLAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 8) +#define HC_HABLAb_HABLRA (HC_XA_HABLRA << 8) +#define HC_HABLFAb_OPA (HC_XA_OPA << 2) +#define HC_HABLFAb_InvOPA (HC_XA_InvOPA << 2) +#define HC_HABLFAb_OPAp5 (HC_XA_OPAp5 << 2) +#define HC_HABLFAb_0 (HC_XA_0 << 2) +#define HC_HABLFAb_Asrc (HC_XA_Asrc << 2) +#define HC_HABLFAb_Adst (HC_XA_Adst << 2) +#define HC_HABLFAb_Fog (HC_XA_Fog << 2) +#define HC_HABLFAb_minAsrcFog (HC_XA_minAsrcFog << 2) +#define HC_HABLFAb_minAsrcAdst (HC_XA_minAsrcAdst << 2) +#define HC_HABLFAb_maxAsrcFog (HC_XA_maxAsrcFog << 2) +#define HC_HABLFAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 2) +#define HC_HABLFAb_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 2) +#define HC_HABLFAb_HABLFRA (HC_XA_HABLFRA << 2) +/* HC_SubA_HABLRAa 0x003d + */ +#define HC_HABLRAa_MASK 0x00ff0000 +#define HC_HABLRFAa_MASK 0x0000ff00 +#define HC_HABLRAbias_MASK 0x000000ff +#define HC_HABLRAa_SHIFT 16 +#define HC_HABLRFAa_SHIFT 8 +/* HC_SubA_HABLRAb 0x003e + */ +#define HC_HABLRAb_MASK 0x0000ff00 +#define HC_HABLRFAb_MASK 0x000000ff +#define HC_HABLRAb_SHIFT 8 + +/* Destination Setting + */ +#define HC_SubA_HDBBasL 0x0040 +#define HC_SubA_HDBBasH 0x0041 +#define HC_SubA_HDBFM 0x0042 +#define HC_SubA_HFBBMSKL 0x0043 +#define HC_SubA_HROP 0x0044 +/* HC_SubA_HDBFM 0x0042 + */ +#define HC_HDBFM_MASK 0x001f0000 +#define HC_HDBLoc_MASK 0x0000c000 +#define HC_HDBPit_MASK 0x00003fff +#define HC_HDBFM_RGB555 0x00000000 +#define HC_HDBFM_RGB565 0x00010000 +#define HC_HDBFM_ARGB4444 0x00020000 +#define HC_HDBFM_ARGB1555 0x00030000 +#define HC_HDBFM_BGR555 0x00040000 +#define HC_HDBFM_BGR565 0x00050000 +#define HC_HDBFM_ABGR4444 0x00060000 +#define HC_HDBFM_ABGR1555 0x00070000 +#define HC_HDBFM_ARGB0888 0x00080000 +#define HC_HDBFM_ARGB8888 0x00090000 +#define HC_HDBFM_ABGR0888 0x000a0000 +#define HC_HDBFM_ABGR8888 0x000b0000 +#define HC_HDBLoc_Local 0x00000000 +#define HC_HDBLoc_Sys 0x00004000 +/* HC_SubA_HROP 0x0044 + */ +#define HC_HROP_MASK 0x00000f00 +#define HC_HFBBMSKH_MASK 0x000000ff +#define HC_HROP_BLACK 0x00000000 +#define HC_HROP_DPon 0x00000100 +#define HC_HROP_DPna 0x00000200 +#define HC_HROP_Pn 0x00000300 +#define HC_HROP_PDna 0x00000400 +#define HC_HROP_Dn 0x00000500 +#define HC_HROP_DPx 0x00000600 +#define HC_HROP_DPan 0x00000700 +#define HC_HROP_DPa 0x00000800 +#define HC_HROP_DPxn 0x00000900 +#define HC_HROP_D 0x00000a00 +#define HC_HROP_DPno 0x00000b00 +#define HC_HROP_P 0x00000c00 +#define HC_HROP_PDno 0x00000d00 +#define HC_HROP_DPo 0x00000e00 +#define HC_HROP_WHITE 0x00000f00 + +/* Fog Setting + */ +#define HC_SubA_HFogLF 0x0050 +#define HC_SubA_HFogCL 0x0051 +#define HC_SubA_HFogCH 0x0052 +#define HC_SubA_HFogStL 0x0053 +#define HC_SubA_HFogStH 0x0054 +#define HC_SubA_HFogOOdMF 0x0055 +#define HC_SubA_HFogOOdEF 0x0056 +#define HC_SubA_HFogEndL 0x0057 +#define HC_SubA_HFogDenst 0x0058 +/* HC_SubA_FogLF 0x0050 + */ +#define HC_FogLF_MASK 0x00000010 +#define HC_FogEq_MASK 0x00000008 +#define HC_FogMD_MASK 0x00000007 +#define HC_FogMD_LocalFog 0x00000000 +#define HC_FogMD_LinearFog 0x00000002 +#define HC_FogMD_ExponentialFog 0x00000004 +#define HC_FogMD_Exponential2Fog 0x00000005 +/* #define HC_FogMD_FogTable 0x00000003 */ + +/* HC_SubA_HFogDenst 0x0058 + */ +#define HC_FogDenst_MASK 0x001fff00 +#define HC_FogEndL_MASK 0x000000ff + +/* Texture subtype definitions + */ +#define HC_SubType_Tex0 0x00000000 +#define HC_SubType_Tex1 0x00000001 +#define HC_SubType_TexGeneral 0x000000fe + +/* Attribute of texture n + */ +#define HC_SubA_HTXnL0BasL 0x0000 +#define HC_SubA_HTXnL1BasL 0x0001 +#define HC_SubA_HTXnL2BasL 0x0002 +#define HC_SubA_HTXnL3BasL 0x0003 +#define HC_SubA_HTXnL4BasL 0x0004 +#define HC_SubA_HTXnL5BasL 0x0005 +#define HC_SubA_HTXnL6BasL 0x0006 +#define HC_SubA_HTXnL7BasL 0x0007 +#define HC_SubA_HTXnL8BasL 0x0008 +#define HC_SubA_HTXnL9BasL 0x0009 +#define HC_SubA_HTXnLaBasL 0x000a +#define HC_SubA_HTXnLbBasL 0x000b +#define HC_SubA_HTXnLcBasL 0x000c +#define HC_SubA_HTXnLdBasL 0x000d +#define HC_SubA_HTXnLeBasL 0x000e +#define HC_SubA_HTXnLfBasL 0x000f +#define HC_SubA_HTXnL10BasL 0x0010 +#define HC_SubA_HTXnL11BasL 0x0011 +#define HC_SubA_HTXnL012BasH 0x0020 +#define HC_SubA_HTXnL345BasH 0x0021 +#define HC_SubA_HTXnL678BasH 0x0022 +#define HC_SubA_HTXnL9abBasH 0x0023 +#define HC_SubA_HTXnLcdeBasH 0x0024 +#define HC_SubA_HTXnLf1011BasH 0x0025 +#define HC_SubA_HTXnL0Pit 0x002b +#define HC_SubA_HTXnL1Pit 0x002c +#define HC_SubA_HTXnL2Pit 0x002d +#define HC_SubA_HTXnL3Pit 0x002e +#define HC_SubA_HTXnL4Pit 0x002f +#define HC_SubA_HTXnL5Pit 0x0030 +#define HC_SubA_HTXnL6Pit 0x0031 +#define HC_SubA_HTXnL7Pit 0x0032 +#define HC_SubA_HTXnL8Pit 0x0033 +#define HC_SubA_HTXnL9Pit 0x0034 +#define HC_SubA_HTXnLaPit 0x0035 +#define HC_SubA_HTXnLbPit 0x0036 +#define HC_SubA_HTXnLcPit 0x0037 +#define HC_SubA_HTXnLdPit 0x0038 +#define HC_SubA_HTXnLePit 0x0039 +#define HC_SubA_HTXnLfPit 0x003a +#define HC_SubA_HTXnL10Pit 0x003b +#define HC_SubA_HTXnL11Pit 0x003c +#define HC_SubA_HTXnL0_5WE 0x004b +#define HC_SubA_HTXnL6_bWE 0x004c +#define HC_SubA_HTXnLc_11WE 0x004d +#define HC_SubA_HTXnL0_5HE 0x0051 +#define HC_SubA_HTXnL6_bHE 0x0052 +#define HC_SubA_HTXnLc_11HE 0x0053 +#define HC_SubA_HTXnL0OS 0x0077 +#define HC_SubA_HTXnTB 0x0078 +#define HC_SubA_HTXnMPMD 0x0079 +#define HC_SubA_HTXnCLODu 0x007a +#define HC_SubA_HTXnFM 0x007b +#define HC_SubA_HTXnTRCH 0x007c +#define HC_SubA_HTXnTRCL 0x007d +#define HC_SubA_HTXnTBC 0x007e +#define HC_SubA_HTXnTRAH 0x007f +#define HC_SubA_HTXnTBLCsat 0x0080 +#define HC_SubA_HTXnTBLCop 0x0081 +#define HC_SubA_HTXnTBLMPfog 0x0082 +#define HC_SubA_HTXnTBLAsat 0x0083 +#define HC_SubA_HTXnTBLRCa 0x0085 +#define HC_SubA_HTXnTBLRCb 0x0086 +#define HC_SubA_HTXnTBLRCc 0x0087 +#define HC_SubA_HTXnTBLRCbias 0x0088 +#define HC_SubA_HTXnTBLRAa 0x0089 +#define HC_SubA_HTXnTBLRFog 0x008a +#define HC_SubA_HTXnBumpM00 0x0090 +#define HC_SubA_HTXnBumpM01 0x0091 +#define HC_SubA_HTXnBumpM10 0x0092 +#define HC_SubA_HTXnBumpM11 0x0093 +#define HC_SubA_HTXnLScale 0x0094 +#define HC_SubA_HTXSMD 0x0000 +/* HC_SubA_HTXnL012BasH 0x0020 + */ +#define HC_HTXnL0BasH_MASK 0x000000ff +#define HC_HTXnL1BasH_MASK 0x0000ff00 +#define HC_HTXnL2BasH_MASK 0x00ff0000 +#define HC_HTXnL1BasH_SHIFT 8 +#define HC_HTXnL2BasH_SHIFT 16 +/* HC_SubA_HTXnL345BasH 0x0021 + */ +#define HC_HTXnL3BasH_MASK 0x000000ff +#define HC_HTXnL4BasH_MASK 0x0000ff00 +#define HC_HTXnL5BasH_MASK 0x00ff0000 +#define HC_HTXnL4BasH_SHIFT 8 +#define HC_HTXnL5BasH_SHIFT 16 +/* HC_SubA_HTXnL678BasH 0x0022 + */ +#define HC_HTXnL6BasH_MASK 0x000000ff +#define HC_HTXnL7BasH_MASK 0x0000ff00 +#define HC_HTXnL8BasH_MASK 0x00ff0000 +#define HC_HTXnL7BasH_SHIFT 8 +#define HC_HTXnL8BasH_SHIFT 16 +/* HC_SubA_HTXnL9abBasH 0x0023 + */ +#define HC_HTXnL9BasH_MASK 0x000000ff +#define HC_HTXnLaBasH_MASK 0x0000ff00 +#define HC_HTXnLbBasH_MASK 0x00ff0000 +#define HC_HTXnLaBasH_SHIFT 8 +#define HC_HTXnLbBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0024 + */ +#define HC_HTXnLcBasH_MASK 0x000000ff +#define HC_HTXnLdBasH_MASK 0x0000ff00 +#define HC_HTXnLeBasH_MASK 0x00ff0000 +#define HC_HTXnLdBasH_SHIFT 8 +#define HC_HTXnLeBasH_SHIFT 16 +/* HC_SubA_HTXnLcdeBasH 0x0025 + */ +#define HC_HTXnLfBasH_MASK 0x000000ff +#define HC_HTXnL10BasH_MASK 0x0000ff00 +#define HC_HTXnL11BasH_MASK 0x00ff0000 +#define HC_HTXnL10BasH_SHIFT 8 +#define HC_HTXnL11BasH_SHIFT 16 +/* HC_SubA_HTXnL0Pit 0x002b + */ +#define HC_HTXnLnPit_MASK 0x00003fff +#define HC_HTXnEnPit_MASK 0x00080000 +#define HC_HTXnLnPitE_MASK 0x00f00000 +#define HC_HTXnLnPitE_SHIFT 20 +/* HC_SubA_HTXnL0_5WE 0x004b + */ +#define HC_HTXnL0WE_MASK 0x0000000f +#define HC_HTXnL1WE_MASK 0x000000f0 +#define HC_HTXnL2WE_MASK 0x00000f00 +#define HC_HTXnL3WE_MASK 0x0000f000 +#define HC_HTXnL4WE_MASK 0x000f0000 +#define HC_HTXnL5WE_MASK 0x00f00000 +#define HC_HTXnL1WE_SHIFT 4 +#define HC_HTXnL2WE_SHIFT 8 +#define HC_HTXnL3WE_SHIFT 12 +#define HC_HTXnL4WE_SHIFT 16 +#define HC_HTXnL5WE_SHIFT 20 +/* HC_SubA_HTXnL6_bWE 0x004c + */ +#define HC_HTXnL6WE_MASK 0x0000000f +#define HC_HTXnL7WE_MASK 0x000000f0 +#define HC_HTXnL8WE_MASK 0x00000f00 +#define HC_HTXnL9WE_MASK 0x0000f000 +#define HC_HTXnLaWE_MASK 0x000f0000 +#define HC_HTXnLbWE_MASK 0x00f00000 +#define HC_HTXnL7WE_SHIFT 4 +#define HC_HTXnL8WE_SHIFT 8 +#define HC_HTXnL9WE_SHIFT 12 +#define HC_HTXnLaWE_SHIFT 16 +#define HC_HTXnLbWE_SHIFT 20 +/* HC_SubA_HTXnLc_11WE 0x004d + */ +#define HC_HTXnLcWE_MASK 0x0000000f +#define HC_HTXnLdWE_MASK 0x000000f0 +#define HC_HTXnLeWE_MASK 0x00000f00 +#define HC_HTXnLfWE_MASK 0x0000f000 +#define HC_HTXnL10WE_MASK 0x000f0000 +#define HC_HTXnL11WE_MASK 0x00f00000 +#define HC_HTXnLdWE_SHIFT 4 +#define HC_HTXnLeWE_SHIFT 8 +#define HC_HTXnLfWE_SHIFT 12 +#define HC_HTXnL10WE_SHIFT 16 +#define HC_HTXnL11WE_SHIFT 20 +/* HC_SubA_HTXnL0_5HE 0x0051 + */ +#define HC_HTXnL0HE_MASK 0x0000000f +#define HC_HTXnL1HE_MASK 0x000000f0 +#define HC_HTXnL2HE_MASK 0x00000f00 +#define HC_HTXnL3HE_MASK 0x0000f000 +#define HC_HTXnL4HE_MASK 0x000f0000 +#define HC_HTXnL5HE_MASK 0x00f00000 +#define HC_HTXnL1HE_SHIFT 4 +#define HC_HTXnL2HE_SHIFT 8 +#define HC_HTXnL3HE_SHIFT 12 +#define HC_HTXnL4HE_SHIFT 16 +#define HC_HTXnL5HE_SHIFT 20 +/* HC_SubA_HTXnL6_bHE 0x0052 + */ +#define HC_HTXnL6HE_MASK 0x0000000f +#define HC_HTXnL7HE_MASK 0x000000f0 +#define HC_HTXnL8HE_MASK 0x00000f00 +#define HC_HTXnL9HE_MASK 0x0000f000 +#define HC_HTXnLaHE_MASK 0x000f0000 +#define HC_HTXnLbHE_MASK 0x00f00000 +#define HC_HTXnL7HE_SHIFT 4 +#define HC_HTXnL8HE_SHIFT 8 +#define HC_HTXnL9HE_SHIFT 12 +#define HC_HTXnLaHE_SHIFT 16 +#define HC_HTXnLbHE_SHIFT 20 +/* HC_SubA_HTXnLc_11HE 0x0053 + */ +#define HC_HTXnLcHE_MASK 0x0000000f +#define HC_HTXnLdHE_MASK 0x000000f0 +#define HC_HTXnLeHE_MASK 0x00000f00 +#define HC_HTXnLfHE_MASK 0x0000f000 +#define HC_HTXnL10HE_MASK 0x000f0000 +#define HC_HTXnL11HE_MASK 0x00f00000 +#define HC_HTXnLdHE_SHIFT 4 +#define HC_HTXnLeHE_SHIFT 8 +#define HC_HTXnLfHE_SHIFT 12 +#define HC_HTXnL10HE_SHIFT 16 +#define HC_HTXnL11HE_SHIFT 20 +/* HC_SubA_HTXnL0OS 0x0077 + */ +#define HC_HTXnL0OS_MASK 0x003ff000 +#define HC_HTXnLVmax_MASK 0x00000fc0 +#define HC_HTXnLVmin_MASK 0x0000003f +#define HC_HTXnL0OS_SHIFT 12 +#define HC_HTXnLVmax_SHIFT 6 +/* HC_SubA_HTXnTB 0x0078 + */ +#define HC_HTXnTB_MASK 0x00f00000 +#define HC_HTXnFLSe_MASK 0x0000e000 +#define HC_HTXnFLSs_MASK 0x00001c00 +#define HC_HTXnFLTe_MASK 0x00000380 +#define HC_HTXnFLTs_MASK 0x00000070 +#define HC_HTXnFLDs_MASK 0x0000000f +#define HC_HTXnTB_NoTB 0x00000000 +#define HC_HTXnTB_TBC_S 0x00100000 +#define HC_HTXnTB_TBC_T 0x00200000 +#define HC_HTXnTB_TB_S 0x00400000 +#define HC_HTXnTB_TB_T 0x00800000 +#define HC_HTXnFLSe_Nearest 0x00000000 +#define HC_HTXnFLSe_Linear 0x00002000 +#define HC_HTXnFLSe_NonLinear 0x00004000 +#define HC_HTXnFLSe_Sharp 0x00008000 +#define HC_HTXnFLSe_Flat_Gaussian_Cubic 0x0000c000 +#define HC_HTXnFLSs_Nearest 0x00000000 +#define HC_HTXnFLSs_Linear 0x00000400 +#define HC_HTXnFLSs_NonLinear 0x00000800 +#define HC_HTXnFLSs_Flat_Gaussian_Cubic 0x00001800 +#define HC_HTXnFLTe_Nearest 0x00000000 +#define HC_HTXnFLTe_Linear 0x00000080 +#define HC_HTXnFLTe_NonLinear 0x00000100 +#define HC_HTXnFLTe_Sharp 0x00000180 +#define HC_HTXnFLTe_Flat_Gaussian_Cubic 0x00000300 +#define HC_HTXnFLTs_Nearest 0x00000000 +#define HC_HTXnFLTs_Linear 0x00000010 +#define HC_HTXnFLTs_NonLinear 0x00000020 +#define HC_HTXnFLTs_Flat_Gaussian_Cubic 0x00000060 +#define HC_HTXnFLDs_Tex0 0x00000000 +#define HC_HTXnFLDs_Nearest 0x00000001 +#define HC_HTXnFLDs_Linear 0x00000002 +#define HC_HTXnFLDs_NonLinear 0x00000003 +#define HC_HTXnFLDs_Dither 0x00000004 +#define HC_HTXnFLDs_ConstLOD 0x00000005 +#define HC_HTXnFLDs_Ani 0x00000006 +#define HC_HTXnFLDs_AniDither 0x00000007 +/* HC_SubA_HTXnMPMD 0x0079 + */ +#define HC_HTXnMPMD_SMASK 0x00070000 +#define HC_HTXnMPMD_TMASK 0x00380000 +#define HC_HTXnLODDTf_MASK 0x00000007 +#define HC_HTXnXY2ST_MASK 0x00000008 +#define HC_HTXnMPMD_Tsingle 0x00000000 +#define HC_HTXnMPMD_Tclamp 0x00080000 +#define HC_HTXnMPMD_Trepeat 0x00100000 +#define HC_HTXnMPMD_Tmirror 0x00180000 +#define HC_HTXnMPMD_Twrap 0x00200000 +#define HC_HTXnMPMD_Ssingle 0x00000000 +#define HC_HTXnMPMD_Sclamp 0x00010000 +#define HC_HTXnMPMD_Srepeat 0x00020000 +#define HC_HTXnMPMD_Smirror 0x00030000 +#define HC_HTXnMPMD_Swrap 0x00040000 +/* HC_SubA_HTXnCLODu 0x007a + */ +#define HC_HTXnCLODu_MASK 0x000ffc00 +#define HC_HTXnCLODd_MASK 0x000003ff +#define HC_HTXnCLODu_SHIFT 10 +/* HC_SubA_HTXnFM 0x007b + */ +#define HC_HTXnFM_MASK 0x00ff0000 +#define HC_HTXnLoc_MASK 0x00000003 +#define HC_HTXnFM_INDEX 0x00000000 +#define HC_HTXnFM_Intensity 0x00080000 +#define HC_HTXnFM_Lum 0x00100000 +#define HC_HTXnFM_Alpha 0x00180000 +#define HC_HTXnFM_DX 0x00280000 +#define HC_HTXnFM_ARGB16 0x00880000 +#define HC_HTXnFM_ARGB32 0x00980000 +#define HC_HTXnFM_ABGR16 0x00a80000 +#define HC_HTXnFM_ABGR32 0x00b80000 +#define HC_HTXnFM_RGBA16 0x00c80000 +#define HC_HTXnFM_RGBA32 0x00d80000 +#define HC_HTXnFM_BGRA16 0x00e80000 +#define HC_HTXnFM_BGRA32 0x00f80000 +#define HC_HTXnFM_BUMPMAP 0x00380000 +#define HC_HTXnFM_Index1 (HC_HTXnFM_INDEX | 0x00000000) +#define HC_HTXnFM_Index2 (HC_HTXnFM_INDEX | 0x00010000) +#define HC_HTXnFM_Index4 (HC_HTXnFM_INDEX | 0x00020000) +#define HC_HTXnFM_Index8 (HC_HTXnFM_INDEX | 0x00030000) +#define HC_HTXnFM_T1 (HC_HTXnFM_Intensity | 0x00000000) +#define HC_HTXnFM_T2 (HC_HTXnFM_Intensity | 0x00010000) +#define HC_HTXnFM_T4 (HC_HTXnFM_Intensity | 0x00020000) +#define HC_HTXnFM_T8 (HC_HTXnFM_Intensity | 0x00030000) +#define HC_HTXnFM_L1 (HC_HTXnFM_Lum | 0x00000000) +#define HC_HTXnFM_L2 (HC_HTXnFM_Lum | 0x00010000) +#define HC_HTXnFM_L4 (HC_HTXnFM_Lum | 0x00020000) +#define HC_HTXnFM_L8 (HC_HTXnFM_Lum | 0x00030000) +#define HC_HTXnFM_AL44 (HC_HTXnFM_Lum | 0x00040000) +#define HC_HTXnFM_AL88 (HC_HTXnFM_Lum | 0x00050000) +#define HC_HTXnFM_A1 (HC_HTXnFM_Alpha | 0x00000000) +#define HC_HTXnFM_A2 (HC_HTXnFM_Alpha | 0x00010000) +#define HC_HTXnFM_A4 (HC_HTXnFM_Alpha | 0x00020000) +#define HC_HTXnFM_A8 (HC_HTXnFM_Alpha | 0x00030000) +#define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000) +#define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000) +#define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000) +#define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000) +#define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000) +#define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000) +#define HC_HTXnFM_ARGB4444 (HC_HTXnFM_ARGB16 | 0x00030000) +#define HC_HTXnFM_ARGB0888 (HC_HTXnFM_ARGB32 | 0x00000000) +#define HC_HTXnFM_ARGB8888 (HC_HTXnFM_ARGB32 | 0x00010000) +#define HC_HTXnFM_BGR555 (HC_HTXnFM_ABGR16 | 0x00000000) +#define HC_HTXnFM_BGR565 (HC_HTXnFM_ABGR16 | 0x00010000) +#define HC_HTXnFM_ABGR1555 (HC_HTXnFM_ABGR16 | 0x00020000) +#define HC_HTXnFM_ABGR4444 (HC_HTXnFM_ABGR16 | 0x00030000) +#define HC_HTXnFM_ABGR0888 (HC_HTXnFM_ABGR32 | 0x00000000) +#define HC_HTXnFM_ABGR8888 (HC_HTXnFM_ABGR32 | 0x00010000) +#define HC_HTXnFM_RGBA5550 (HC_HTXnFM_RGBA16 | 0x00000000) +#define HC_HTXnFM_RGBA5551 (HC_HTXnFM_RGBA16 | 0x00020000) +#define HC_HTXnFM_RGBA4444 (HC_HTXnFM_RGBA16 | 0x00030000) +#define HC_HTXnFM_RGBA8880 (HC_HTXnFM_RGBA32 | 0x00000000) +#define HC_HTXnFM_RGBA8888 (HC_HTXnFM_RGBA32 | 0x00010000) +#define HC_HTXnFM_BGRA5550 (HC_HTXnFM_BGRA16 | 0x00000000) +#define HC_HTXnFM_BGRA5551 (HC_HTXnFM_BGRA16 | 0x00020000) +#define HC_HTXnFM_BGRA4444 (HC_HTXnFM_BGRA16 | 0x00030000) +#define HC_HTXnFM_BGRA8880 (HC_HTXnFM_BGRA32 | 0x00000000) +#define HC_HTXnFM_BGRA8888 (HC_HTXnFM_BGRA32 | 0x00010000) +#define HC_HTXnFM_VU88 (HC_HTXnFM_BUMPMAP | 0x00000000) +#define HC_HTXnFM_LVU655 (HC_HTXnFM_BUMPMAP | 0x00010000) +#define HC_HTXnFM_LVU888 (HC_HTXnFM_BUMPMAP | 0x00020000) +#define HC_HTXnLoc_Local 0x00000000 +#define HC_HTXnLoc_Sys 0x00000002 +#define HC_HTXnLoc_AGP 0x00000003 +/* HC_SubA_HTXnTRAH 0x007f + */ +#define HC_HTXnTRAH_MASK 0x00ff0000 +#define HC_HTXnTRAL_MASK 0x0000ff00 +#define HC_HTXnTBA_MASK 0x000000ff +#define HC_HTXnTRAH_SHIFT 16 +#define HC_HTXnTRAL_SHIFT 8 +/* HC_SubA_HTXnTBLCsat 0x0080 + *-- Define the input texture. + */ +#define HC_XTC_TOPC 0x00000000 +#define HC_XTC_InvTOPC 0x00000010 +#define HC_XTC_TOPCp5 0x00000020 +#define HC_XTC_Cbias 0x00000000 +#define HC_XTC_InvCbias 0x00000010 +#define HC_XTC_0 0x00000000 +#define HC_XTC_Dif 0x00000001 +#define HC_XTC_Spec 0x00000002 +#define HC_XTC_Tex 0x00000003 +#define HC_XTC_Cur 0x00000004 +#define HC_XTC_Adif 0x00000005 +#define HC_XTC_Fog 0x00000006 +#define HC_XTC_Atex 0x00000007 +#define HC_XTC_Acur 0x00000008 +#define HC_XTC_HTXnTBLRC 0x00000009 +#define HC_XTC_Ctexnext 0x0000000a +/*-- + */ +#define HC_HTXnTBLCsat_MASK 0x00800000 +#define HC_HTXnTBLCa_MASK 0x000fc000 +#define HC_HTXnTBLCb_MASK 0x00001f80 +#define HC_HTXnTBLCc_MASK 0x0000003f +#define HC_HTXnTBLCa_TOPC (HC_XTC_TOPC << 14) +#define HC_HTXnTBLCa_InvTOPC (HC_XTC_InvTOPC << 14) +#define HC_HTXnTBLCa_TOPCp5 (HC_XTC_TOPCp5 << 14) +#define HC_HTXnTBLCa_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCa_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCa_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCa_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCa_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCa_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCa_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCa_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCa_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCa_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCa_Ctexnext (HC_XTC_Ctexnext << 14) +#define HC_HTXnTBLCb_TOPC (HC_XTC_TOPC << 7) +#define HC_HTXnTBLCb_InvTOPC (HC_XTC_InvTOPC << 7) +#define HC_HTXnTBLCb_TOPCp5 (HC_XTC_TOPCp5 << 7) +#define HC_HTXnTBLCb_0 (HC_XTC_0 << 7) +#define HC_HTXnTBLCb_Dif (HC_XTC_Dif << 7) +#define HC_HTXnTBLCb_Spec (HC_XTC_Spec << 7) +#define HC_HTXnTBLCb_Tex (HC_XTC_Tex << 7) +#define HC_HTXnTBLCb_Cur (HC_XTC_Cur << 7) +#define HC_HTXnTBLCb_Adif (HC_XTC_Adif << 7) +#define HC_HTXnTBLCb_Fog (HC_XTC_Fog << 7) +#define HC_HTXnTBLCb_Atex (HC_XTC_Atex << 7) +#define HC_HTXnTBLCb_Acur (HC_XTC_Acur << 7) +#define HC_HTXnTBLCb_HTXnTBLRC (HC_XTC_HTXnTBLRC << 7) +#define HC_HTXnTBLCb_Ctexnext (HC_XTC_Ctexnext << 7) +#define HC_HTXnTBLCc_TOPC (HC_XTC_TOPC << 0) +#define HC_HTXnTBLCc_InvTOPC (HC_XTC_InvTOPC << 0) +#define HC_HTXnTBLCc_TOPCp5 (HC_XTC_TOPCp5 << 0) +#define HC_HTXnTBLCc_0 (HC_XTC_0 << 0) +#define HC_HTXnTBLCc_Dif (HC_XTC_Dif << 0) +#define HC_HTXnTBLCc_Spec (HC_XTC_Spec << 0) +#define HC_HTXnTBLCc_Tex (HC_XTC_Tex << 0) +#define HC_HTXnTBLCc_Cur (HC_XTC_Cur << 0) +#define HC_HTXnTBLCc_Adif (HC_XTC_Adif << 0) +#define HC_HTXnTBLCc_Fog (HC_XTC_Fog << 0) +#define HC_HTXnTBLCc_Atex (HC_XTC_Atex << 0) +#define HC_HTXnTBLCc_Acur (HC_XTC_Acur << 0) +#define HC_HTXnTBLCc_HTXnTBLRC (HC_XTC_HTXnTBLRC << 0) +#define HC_HTXnTBLCc_Ctexnext (HC_XTC_Ctexnext << 0) +/* HC_SubA_HTXnTBLCop 0x0081 + */ +#define HC_HTXnTBLdot_MASK 0x00c00000 +#define HC_HTXnTBLCop_MASK 0x00380000 +#define HC_HTXnTBLCbias_MASK 0x0007c000 +#define HC_HTXnTBLCshift_MASK 0x00001800 +#define HC_HTXnTBLAop_MASK 0x00000380 +#define HC_HTXnTBLAbias_MASK 0x00000078 +#define HC_HTXnTBLAshift_MASK 0x00000003 +#define HC_HTXnTBLCop_Add 0x00000000 +#define HC_HTXnTBLCop_Sub 0x00080000 +#define HC_HTXnTBLCop_Min 0x00100000 +#define HC_HTXnTBLCop_Max 0x00180000 +#define HC_HTXnTBLCop_Mask 0x00200000 +#define HC_HTXnTBLCbias_Cbias (HC_XTC_Cbias << 14) +#define HC_HTXnTBLCbias_InvCbias (HC_XTC_InvCbias << 14) +#define HC_HTXnTBLCbias_0 (HC_XTC_0 << 14) +#define HC_HTXnTBLCbias_Dif (HC_XTC_Dif << 14) +#define HC_HTXnTBLCbias_Spec (HC_XTC_Spec << 14) +#define HC_HTXnTBLCbias_Tex (HC_XTC_Tex << 14) +#define HC_HTXnTBLCbias_Cur (HC_XTC_Cur << 14) +#define HC_HTXnTBLCbias_Adif (HC_XTC_Adif << 14) +#define HC_HTXnTBLCbias_Fog (HC_XTC_Fog << 14) +#define HC_HTXnTBLCbias_Atex (HC_XTC_Atex << 14) +#define HC_HTXnTBLCbias_Acur (HC_XTC_Acur << 14) +#define HC_HTXnTBLCbias_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14) +#define HC_HTXnTBLCshift_1 0x00000000 +#define HC_HTXnTBLCshift_2 0x00000800 +#define HC_HTXnTBLCshift_No 0x00001000 +#define HC_HTXnTBLCshift_DotP 0x00001800 +#define HC_HTXnTBLAop_Add 0x00000000 +#define HC_HTXnTBLAop_Sub 0x00000080 +#define HC_HTXnTBLAop_Min 0x00000100 +#define HC_HTXnTBLAop_Max 0x00000180 +#define HC_HTXnTBLAop_Mask 0x00000200 +#define HC_HTXnTBLAbias_Inv 0x00000040 +#define HC_HTXnTBLAbias_Adif 0x00000000 +#define HC_HTXnTBLAbias_Fog 0x00000008 +#define HC_HTXnTBLAbias_Acur 0x00000010 +#define HC_HTXnTBLAbias_HTXnTBLRAbias 0x00000018 +#define HC_HTXnTBLAbias_Atex 0x00000020 +#define HC_HTXnTBLAshift_1 0x00000000 +#define HC_HTXnTBLAshift_2 0x00000001 +#define HC_HTXnTBLAshift_No 0x00000002 +/* #define HC_HTXnTBLAshift_DotP 0x00000003 */ +/* HC_SubA_HTXnTBLMPFog 0x0082 + */ +#define HC_HTXnTBLMPfog_MASK 0x00e00000 +#define HC_HTXnTBLMPfog_0 0x00000000 +#define HC_HTXnTBLMPfog_Adif 0x00200000 +#define HC_HTXnTBLMPfog_Fog 0x00400000 +#define HC_HTXnTBLMPfog_Atex 0x00600000 +#define HC_HTXnTBLMPfog_Acur 0x00800000 +#define HC_HTXnTBLMPfog_GHTXnTBLRFog 0x00a00000 +/* HC_SubA_HTXnTBLAsat 0x0083 + *-- Define the texture alpha input. + */ +#define HC_XTA_TOPA 0x00000000 +#define HC_XTA_InvTOPA 0x00000008 +#define HC_XTA_TOPAp5 0x00000010 +#define HC_XTA_Adif 0x00000000 +#define HC_XTA_Fog 0x00000001 +#define HC_XTA_Acur 0x00000002 +#define HC_XTA_HTXnTBLRA 0x00000003 +#define HC_XTA_Atex 0x00000004 +#define HC_XTA_Atexnext 0x00000005 +/*-- + */ +#define HC_HTXnTBLAsat_MASK 0x00800000 +#define HC_HTXnTBLAMB_MASK 0x00700000 +#define HC_HTXnTBLAa_MASK 0x0007c000 +#define HC_HTXnTBLAb_MASK 0x00000f80 +#define HC_HTXnTBLAc_MASK 0x0000001f +#define HC_HTXnTBLAMB_SHIFT 20 +#define HC_HTXnTBLAa_TOPA (HC_XTA_TOPA << 14) +#define HC_HTXnTBLAa_InvTOPA (HC_XTA_InvTOPA << 14) +#define HC_HTXnTBLAa_TOPAp5 (HC_XTA_TOPAp5 << 14) +#define HC_HTXnTBLAa_Adif (HC_XTA_Adif << 14) +#define HC_HTXnTBLAa_Fog (HC_XTA_Fog << 14) +#define HC_HTXnTBLAa_Acur (HC_XTA_Acur << 14) +#define HC_HTXnTBLAa_HTXnTBLRA (HC_XTA_HTXnTBLRA << 14) +#define HC_HTXnTBLAa_Atex (HC_XTA_Atex << 14) +#define HC_HTXnTBLAa_Atexnext (HC_XTA_Atexnext << 14) +#define HC_HTXnTBLAb_TOPA (HC_XTA_TOPA << 7) +#define HC_HTXnTBLAb_InvTOPA (HC_XTA_InvTOPA << 7) +#define HC_HTXnTBLAb_TOPAp5 (HC_XTA_TOPAp5 << 7) +#define HC_HTXnTBLAb_Adif (HC_XTA_Adif << 7) +#define HC_HTXnTBLAb_Fog (HC_XTA_Fog << 7) +#define HC_HTXnTBLAb_Acur (HC_XTA_Acur << 7) +#define HC_HTXnTBLAb_HTXnTBLRA (HC_XTA_HTXnTBLRA << 7) +#define HC_HTXnTBLAb_Atex (HC_XTA_Atex << 7) +#define HC_HTXnTBLAb_Atexnext (HC_XTA_Atexnext << 7) +#define HC_HTXnTBLAc_TOPA (HC_XTA_TOPA << 0) +#define HC_HTXnTBLAc_InvTOPA (HC_XTA_InvTOPA << 0) +#define HC_HTXnTBLAc_TOPAp5 (HC_XTA_TOPAp5 << 0) +#define HC_HTXnTBLAc_Adif (HC_XTA_Adif << 0) +#define HC_HTXnTBLAc_Fog (HC_XTA_Fog << 0) +#define HC_HTXnTBLAc_Acur (HC_XTA_Acur << 0) +#define HC_HTXnTBLAc_HTXnTBLRA (HC_XTA_HTXnTBLRA << 0) +#define HC_HTXnTBLAc_Atex (HC_XTA_Atex << 0) +#define HC_HTXnTBLAc_Atexnext (HC_XTA_Atexnext << 0) +/* HC_SubA_HTXnTBLRAa 0x0089 + */ +#define HC_HTXnTBLRAa_MASK 0x00ff0000 +#define HC_HTXnTBLRAb_MASK 0x0000ff00 +#define HC_HTXnTBLRAc_MASK 0x000000ff +#define HC_HTXnTBLRAa_SHIFT 16 +#define HC_HTXnTBLRAb_SHIFT 8 +#define HC_HTXnTBLRAc_SHIFT 0 +/* HC_SubA_HTXnTBLRFog 0x008a + */ +#define HC_HTXnTBLRFog_MASK 0x0000ff00 +#define HC_HTXnTBLRAbias_MASK 0x000000ff +#define HC_HTXnTBLRFog_SHIFT 8 +#define HC_HTXnTBLRAbias_SHIFT 0 +/* HC_SubA_HTXnLScale 0x0094 + */ +#define HC_HTXnLScale_MASK 0x0007fc00 +#define HC_HTXnLOff_MASK 0x000001ff +#define HC_HTXnLScale_SHIFT 10 +/* HC_SubA_HTXSMD 0x0000 + */ +#define HC_HTXSMD_MASK 0x00000080 +#define HC_HTXTMD_MASK 0x00000040 +#define HC_HTXNum_MASK 0x00000038 +#define HC_HTXTRMD_MASK 0x00000006 +#define HC_HTXCHCLR_MASK 0x00000001 +#define HC_HTXNum_SHIFT 3 + +/* Texture Palette n + */ +#define HC_SubType_TexPalette0 0x00000000 +#define HC_SubType_TexPalette1 0x00000001 +#define HC_SubType_FogTable 0x00000010 +#define HC_SubType_Stipple 0x00000014 +/* HC_SubA_TexPalette0 0x0000 + */ +#define HC_HTPnA_MASK 0xff000000 +#define HC_HTPnR_MASK 0x00ff0000 +#define HC_HTPnG_MASK 0x0000ff00 +#define HC_HTPnB_MASK 0x000000ff +/* HC_SubA_FogTable 0x0010 + */ +#define HC_HFPn3_MASK 0xff000000 +#define HC_HFPn2_MASK 0x00ff0000 +#define HC_HFPn1_MASK 0x0000ff00 +#define HC_HFPn_MASK 0x000000ff +#define HC_HFPn3_SHIFT 24 +#define HC_HFPn2_SHIFT 16 +#define HC_HFPn1_SHIFT 8 + +/* Auto Testing & Security + */ +#define HC_SubA_HenFIFOAT 0x0000 +#define HC_SubA_HFBDrawFirst 0x0004 +#define HC_SubA_HFBBasL 0x0005 +#define HC_SubA_HFBDst 0x0006 +/* HC_SubA_HenFIFOAT 0x0000 + */ +#define HC_HenFIFOAT_MASK 0x00000020 +#define HC_HenGEMILock_MASK 0x00000010 +#define HC_HenFBASwap_MASK 0x00000008 +#define HC_HenOT_MASK 0x00000004 +#define HC_HenCMDQ_MASK 0x00000002 +#define HC_HenTXCTSU_MASK 0x00000001 +/* HC_SubA_HFBDrawFirst 0x0004 + */ +#define HC_HFBDrawFirst_MASK 0x00000800 +#define HC_HFBQueue_MASK 0x00000400 +#define HC_HFBLock_MASK 0x00000200 +#define HC_HEOF_MASK 0x00000100 +#define HC_HFBBasH_MASK 0x000000ff + +/* GEMI Setting + */ +#define HC_SubA_HTArbRCM 0x0008 +#define HC_SubA_HTArbRZ 0x000a +#define HC_SubA_HTArbWZ 0x000b +#define HC_SubA_HTArbRTX 0x000c +#define HC_SubA_HTArbRCW 0x000d +#define HC_SubA_HTArbE2 0x000e +#define HC_SubA_HArbRQCM 0x0010 +#define HC_SubA_HArbWQCM 0x0011 +#define HC_SubA_HGEMITout 0x0020 +#define HC_SubA_HFthRTXD 0x0040 +#define HC_SubA_HFthRTXA 0x0044 +#define HC_SubA_HCMDQstL 0x0050 +#define HC_SubA_HCMDQendL 0x0051 +#define HC_SubA_HCMDQLen 0x0052 +/* HC_SubA_HTArbRCM 0x0008 + */ +#define HC_HTArbRCM_MASK 0x0000ffff +/* HC_SubA_HTArbRZ 0x000a + */ +#define HC_HTArbRZ_MASK 0x0000ffff +/* HC_SubA_HTArbWZ 0x000b + */ +#define HC_HTArbWZ_MASK 0x0000ffff +/* HC_SubA_HTArbRTX 0x000c + */ +#define HC_HTArbRTX_MASK 0x0000ffff +/* HC_SubA_HTArbRCW 0x000d + */ +#define HC_HTArbRCW_MASK 0x0000ffff +/* HC_SubA_HTArbE2 0x000e + */ +#define HC_HTArbE2_MASK 0x0000ffff +/* HC_SubA_HArbRQCM 0x0010 + */ +#define HC_HTArbRQCM_MASK 0x0000ffff +/* HC_SubA_HArbWQCM 0x0011 + */ +#define HC_HArbWQCM_MASK 0x0000ffff +/* HC_SubA_HGEMITout 0x0020 + */ +#define HC_HGEMITout_MASK 0x000f0000 +#define HC_HNPArbZC_MASK 0x0000ffff +#define HC_HGEMITout_SHIFT 16 +/* HC_SubA_HFthRTXD 0x0040 + */ +#define HC_HFthRTXD_MASK 0x00ff0000 +#define HC_HFthRZD_MASK 0x0000ff00 +#define HC_HFthWZD_MASK 0x000000ff +#define HC_HFthRTXD_SHIFT 16 +#define HC_HFthRZD_SHIFT 8 +/* HC_SubA_HFthRTXA 0x0044 + */ +#define HC_HFthRTXA_MASK 0x000000ff + +/****************************************************************************** +** Define the Halcyon Internal register access constants. For simulator only. +******************************************************************************/ +#define HC_SIMA_HAGPBstL 0x0000 +#define HC_SIMA_HAGPBendL 0x0001 +#define HC_SIMA_HAGPCMNT 0x0002 +#define HC_SIMA_HAGPBpL 0x0003 +#define HC_SIMA_HAGPBpH 0x0004 +#define HC_SIMA_HClipTB 0x0005 +#define HC_SIMA_HClipLR 0x0006 +#define HC_SIMA_HFPClipTL 0x0007 +#define HC_SIMA_HFPClipBL 0x0008 +#define HC_SIMA_HFPClipLL 0x0009 +#define HC_SIMA_HFPClipRL 0x000a +#define HC_SIMA_HFPClipTBH 0x000b +#define HC_SIMA_HFPClipLRH 0x000c +#define HC_SIMA_HLP 0x000d +#define HC_SIMA_HLPRF 0x000e +#define HC_SIMA_HSolidCL 0x000f +#define HC_SIMA_HPixGC 0x0010 +#define HC_SIMA_HSPXYOS 0x0011 +#define HC_SIMA_HCmdA 0x0012 +#define HC_SIMA_HCmdB 0x0013 +#define HC_SIMA_HEnable 0x0014 +#define HC_SIMA_HZWBBasL 0x0015 +#define HC_SIMA_HZWBBasH 0x0016 +#define HC_SIMA_HZWBType 0x0017 +#define HC_SIMA_HZBiasL 0x0018 +#define HC_SIMA_HZWBend 0x0019 +#define HC_SIMA_HZWTMD 0x001a +#define HC_SIMA_HZWCDL 0x001b +#define HC_SIMA_HZWCTAGnum 0x001c +#define HC_SIMA_HZCYNum 0x001d +#define HC_SIMA_HZWCFire 0x001e +/* #define HC_SIMA_HSBBasL 0x001d */ +/* #define HC_SIMA_HSBBasH 0x001e */ +/* #define HC_SIMA_HSBFM 0x001f */ +#define HC_SIMA_HSTREF 0x0020 +#define HC_SIMA_HSTMD 0x0021 +#define HC_SIMA_HABBasL 0x0022 +#define HC_SIMA_HABBasH 0x0023 +#define HC_SIMA_HABFM 0x0024 +#define HC_SIMA_HATMD 0x0025 +#define HC_SIMA_HABLCsat 0x0026 +#define HC_SIMA_HABLCop 0x0027 +#define HC_SIMA_HABLAsat 0x0028 +#define HC_SIMA_HABLAop 0x0029 +#define HC_SIMA_HABLRCa 0x002a +#define HC_SIMA_HABLRFCa 0x002b +#define HC_SIMA_HABLRCbias 0x002c +#define HC_SIMA_HABLRCb 0x002d +#define HC_SIMA_HABLRFCb 0x002e +#define HC_SIMA_HABLRAa 0x002f +#define HC_SIMA_HABLRAb 0x0030 +#define HC_SIMA_HDBBasL 0x0031 +#define HC_SIMA_HDBBasH 0x0032 +#define HC_SIMA_HDBFM 0x0033 +#define HC_SIMA_HFBBMSKL 0x0034 +#define HC_SIMA_HROP 0x0035 +#define HC_SIMA_HFogLF 0x0036 +#define HC_SIMA_HFogCL 0x0037 +#define HC_SIMA_HFogCH 0x0038 +#define HC_SIMA_HFogStL 0x0039 +#define HC_SIMA_HFogStH 0x003a +#define HC_SIMA_HFogOOdMF 0x003b +#define HC_SIMA_HFogOOdEF 0x003c +#define HC_SIMA_HFogEndL 0x003d +#define HC_SIMA_HFogDenst 0x003e +/*---- start of texture 0 setting ---- + */ +#define HC_SIMA_HTX0L0BasL 0x0040 +#define HC_SIMA_HTX0L1BasL 0x0041 +#define HC_SIMA_HTX0L2BasL 0x0042 +#define HC_SIMA_HTX0L3BasL 0x0043 +#define HC_SIMA_HTX0L4BasL 0x0044 +#define HC_SIMA_HTX0L5BasL 0x0045 +#define HC_SIMA_HTX0L6BasL 0x0046 +#define HC_SIMA_HTX0L7BasL 0x0047 +#define HC_SIMA_HTX0L8BasL 0x0048 +#define HC_SIMA_HTX0L9BasL 0x0049 +#define HC_SIMA_HTX0LaBasL 0x004a +#define HC_SIMA_HTX0LbBasL 0x004b +#define HC_SIMA_HTX0LcBasL 0x004c +#define HC_SIMA_HTX0LdBasL 0x004d +#define HC_SIMA_HTX0LeBasL 0x004e +#define HC_SIMA_HTX0LfBasL 0x004f +#define HC_SIMA_HTX0L10BasL 0x0050 +#define HC_SIMA_HTX0L11BasL 0x0051 +#define HC_SIMA_HTX0L012BasH 0x0052 +#define HC_SIMA_HTX0L345BasH 0x0053 +#define HC_SIMA_HTX0L678BasH 0x0054 +#define HC_SIMA_HTX0L9abBasH 0x0055 +#define HC_SIMA_HTX0LcdeBasH 0x0056 +#define HC_SIMA_HTX0Lf1011BasH 0x0057 +#define HC_SIMA_HTX0L0Pit 0x0058 +#define HC_SIMA_HTX0L1Pit 0x0059 +#define HC_SIMA_HTX0L2Pit 0x005a +#define HC_SIMA_HTX0L3Pit 0x005b +#define HC_SIMA_HTX0L4Pit 0x005c +#define HC_SIMA_HTX0L5Pit 0x005d +#define HC_SIMA_HTX0L6Pit 0x005e +#define HC_SIMA_HTX0L7Pit 0x005f +#define HC_SIMA_HTX0L8Pit 0x0060 +#define HC_SIMA_HTX0L9Pit 0x0061 +#define HC_SIMA_HTX0LaPit 0x0062 +#define HC_SIMA_HTX0LbPit 0x0063 +#define HC_SIMA_HTX0LcPit 0x0064 +#define HC_SIMA_HTX0LdPit 0x0065 +#define HC_SIMA_HTX0LePit 0x0066 +#define HC_SIMA_HTX0LfPit 0x0067 +#define HC_SIMA_HTX0L10Pit 0x0068 +#define HC_SIMA_HTX0L11Pit 0x0069 +#define HC_SIMA_HTX0L0_5WE 0x006a +#define HC_SIMA_HTX0L6_bWE 0x006b +#define HC_SIMA_HTX0Lc_11WE 0x006c +#define HC_SIMA_HTX0L0_5HE 0x006d +#define HC_SIMA_HTX0L6_bHE 0x006e +#define HC_SIMA_HTX0Lc_11HE 0x006f +#define HC_SIMA_HTX0L0OS 0x0070 +#define HC_SIMA_HTX0TB 0x0071 +#define HC_SIMA_HTX0MPMD 0x0072 +#define HC_SIMA_HTX0CLODu 0x0073 +#define HC_SIMA_HTX0FM 0x0074 +#define HC_SIMA_HTX0TRCH 0x0075 +#define HC_SIMA_HTX0TRCL 0x0076 +#define HC_SIMA_HTX0TBC 0x0077 +#define HC_SIMA_HTX0TRAH 0x0078 +#define HC_SIMA_HTX0TBLCsat 0x0079 +#define HC_SIMA_HTX0TBLCop 0x007a +#define HC_SIMA_HTX0TBLMPfog 0x007b +#define HC_SIMA_HTX0TBLAsat 0x007c +#define HC_SIMA_HTX0TBLRCa 0x007d +#define HC_SIMA_HTX0TBLRCb 0x007e +#define HC_SIMA_HTX0TBLRCc 0x007f +#define HC_SIMA_HTX0TBLRCbias 0x0080 +#define HC_SIMA_HTX0TBLRAa 0x0081 +#define HC_SIMA_HTX0TBLRFog 0x0082 +#define HC_SIMA_HTX0BumpM00 0x0083 +#define HC_SIMA_HTX0BumpM01 0x0084 +#define HC_SIMA_HTX0BumpM10 0x0085 +#define HC_SIMA_HTX0BumpM11 0x0086 +#define HC_SIMA_HTX0LScale 0x0087 +/*---- end of texture 0 setting ---- 0x008f + */ +#define HC_SIMA_TX0TX1_OFF 0x0050 +/*---- start of texture 1 setting ---- + */ +#define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) +/*---- end of texture 1 setting ---- 0xaf + */ +#define HC_SIMA_HTXSMD 0x00b0 +#define HC_SIMA_HenFIFOAT 0x00b1 +#define HC_SIMA_HFBDrawFirst 0x00b2 +#define HC_SIMA_HFBBasL 0x00b3 +#define HC_SIMA_HTArbRCM 0x00b4 +#define HC_SIMA_HTArbRZ 0x00b5 +#define HC_SIMA_HTArbWZ 0x00b6 +#define HC_SIMA_HTArbRTX 0x00b7 +#define HC_SIMA_HTArbRCW 0x00b8 +#define HC_SIMA_HTArbE2 0x00b9 +#define HC_SIMA_HGEMITout 0x00ba +#define HC_SIMA_HFthRTXD 0x00bb +#define HC_SIMA_HFthRTXA 0x00bc +/* Define the texture palette 0 + */ +#define HC_SIMA_HTP0 0x0100 +#define HC_SIMA_HTP1 0x0200 +#define HC_SIMA_FOGTABLE 0x0300 +#define HC_SIMA_STIPPLE 0x0400 +#define HC_SIMA_HE3Fire 0x0440 +#define HC_SIMA_TRANS_SET 0x0441 +#define HC_SIMA_HREngSt 0x0442 +#define HC_SIMA_HRFIFOempty 0x0443 +#define HC_SIMA_HRFIFOfull 0x0444 +#define HC_SIMA_HRErr 0x0445 +#define HC_SIMA_FIFOstatus 0x0446 + +/****************************************************************************** +** Define the AGP command header. +******************************************************************************/ +#define HC_ACMD_MASK 0xfe000000 +#define HC_ACMD_SUB_MASK 0x0c000000 +#define HC_ACMD_HCmdA 0xee000000 +#define HC_ACMD_HCmdB 0xec000000 +#define HC_ACMD_HCmdC 0xea000000 +#define HC_ACMD_H1 0xf0000000 +#define HC_ACMD_H2 0xf2000000 +#define HC_ACMD_H3 0xf4000000 +#define HC_ACMD_H4 0xf6000000 + +#define HC_ACMD_H1IO_MASK 0x000001ff +#define HC_ACMD_H2IO1_MASK 0x001ff000 +#define HC_ACMD_H2IO2_MASK 0x000001ff +#define HC_ACMD_H2IO1_SHIFT 12 +#define HC_ACMD_H2IO2_SHIFT 0 +#define HC_ACMD_H3IO_MASK 0x000001ff +#define HC_ACMD_H3COUNT_MASK 0x01fff000 +#define HC_ACMD_H3COUNT_SHIFT 12 +#define HC_ACMD_H4ID_MASK 0x000001ff +#define HC_ACMD_H4COUNT_MASK 0x01fffe00 +#define HC_ACMD_H4COUNT_SHIFT 9 + +/******************************************************************************** +** Define Header +********************************************************************************/ +#define HC_HEADER2 0xF210F110 + +/******************************************************************************** +** Define Dummy Value +********************************************************************************/ +#define HC_DUMMY 0xCCCCCCCC +/******************************************************************************** +** Define for DMA use +********************************************************************************/ +#define HALCYON_HEADER2 0XF210F110 +#define HALCYON_FIRECMD 0XEE100000 +#define HALCYON_FIREMASK 0XFFF00000 +#define HALCYON_CMDB 0XEC000000 +#define HALCYON_CMDBMASK 0XFFFE0000 +#define HALCYON_SUB_ADDR0 0X00000000 +#define HALCYON_HEADER1MASK 0XFFFFFF00 +#define HALCYON_HEADER1 0XF0000000 +#define HC_SubA_HAGPBstL 0x0060 +#define HC_SubA_HAGPBendL 0x0061 +#define HC_SubA_HAGPCMNT 0x0062 +#define HC_SubA_HAGPBpL 0x0063 +#define HC_SubA_HAGPBpH 0x0064 +#define HC_HAGPCMNT_MASK 0x00800000 +#define HC_HCmdErrClr_MASK 0x00400000 +#define HC_HAGPBendH_MASK 0x0000ff00 +#define HC_HAGPBstH_MASK 0x000000ff +#define HC_HAGPBendH_SHIFT 8 +#define HC_HAGPBstH_SHIFT 0 +#define HC_HAGPBpL_MASK 0x00fffffc +#define HC_HAGPBpID_MASK 0x00000003 +#define HC_HAGPBpID_PAUSE 0x00000000 +#define HC_HAGPBpID_JUMP 0x00000001 +#define HC_HAGPBpID_STOP 0x00000002 +#define HC_HAGPBpH_MASK 0x00ffffff + +#endif // __VIA_REGS_3D_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_accel.c b/Source/DirectFB/gfxdrivers/cle266/uc_accel.c new file mode 100755 index 0000000..caad848 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_accel.c @@ -0,0 +1,504 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include <direct/messages.h> + +#include <gfx/convert.h> + +#include "unichrome.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "mmio.h" + +#define UC_ACCEL_BEGIN() \ + UcDriverData *ucdrv = (UcDriverData*) drv; \ + UcDeviceData *ucdev = (UcDeviceData*) dev; \ + struct uc_fifo *fifo = ucdrv->fifo; \ + /*printf("entering %s\n", __PRETTY_FUNCTION__)*/ + +#define UC_ACCEL_END() \ + UC_FIFO_CHECK(fifo); \ + /*printf("leaving %s\n", __PRETTY_FUNCTION__)*/ + +// Private functions --------------------------------------------------------- + +/** Wait until a new command can be set up. */ + +static inline void uc_waitcmd(UcDriverData* ucdrv, UcDeviceData* ucdev) +{ + int loop = 0; + + if (!ucdev->must_wait) + return; + + //printf("waitcmd "); + + while (VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/VIA: Timeout waiting for idle command regulator!\n"); + break; + } + } + + //printf("waited for %d (0x%x) cycles.\n", loop, loop); + + ucdev->cmd_waitcycles += loop; + ucdev->must_wait = 0; +} + +/** Send commands to 2D/3D engine. */ + +void uc_emit_commands(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + uc_waitcmd(ucdrv, ucdev); + + UC_FIFO_FLUSH(fifo); + + ucdev->must_wait = 1; +} + +void uc_flush_texture_cache(void* drv, void* dev) +{ + UC_ACCEL_BEGIN() + + (void) ucdev; + + UC_FIFO_PREPARE(fifo, 4); + + UC_FIFO_ADD_HDR(fifo, (HC_ParaType_Tex << 16) | (HC_SubType_TexGeneral << 24)); + UC_FIFO_ADD_3D(fifo, HC_SubA_HTXSMD, HC_HTXCHCLR_MASK); + UC_FIFO_ADD_3D(fifo, HC_SubA_HTXSMD, 0); + + UC_FIFO_CHECK(fifo); +} + +/** + * Draw a horizontal or vertical line. + * + * @param fifo command FIFO + * + * @param x start x position + * @param y start y position + * @param len length + * @param hv if zero: draw from left to right + * if nonzero: draw from top to bottom. + * + * @note This is actually a 1-pixel high or wide rectangular color fill. + */ + +static inline void uc_draw_hv_line(struct uc_fifo* fifo, + int x, int y, int len, int hv, int rop) +{ + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(y) << 16) | RS16(x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, len << (hv ? 16 : 0)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | rop | VIA_GEC_CLIP_ENABLE); +} + +// DirectFB interfacing functions -------------------------------------------- + +// Functions using the 2D engine --- + +bool uc_fill_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 8); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, ((RS16(r->y) << 16) | RS16(r->x))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, + (((RS16(r->h - 1)) << 16) | RS16((r->w - 1)))); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, VIA_GEC_BLT | VIA_GEC_FIXCOLOR_PAT + | ucdev->draw_rop2d | VIA_GEC_CLIP_ENABLE); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color); + + int rop = ucdev->draw_rop2d; + + // Draw lines, in this order: top, bottom, left, right + + UC_FIFO_PREPARE(fifo, 26); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + uc_draw_hv_line(fifo, r->x, r->y, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y + r->h - 1, r->w - 1, 0, rop); + uc_draw_hv_line(fifo, r->x, r->y, r->h - 1, 1, rop); + uc_draw_hv_line(fifo, r->x + r->w - 1, r->y, r->h - 1, 1, rop); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + //printf("%s: l = (%d, %d) - (%d, %d), c = 0x%08x\n", __PRETTY_FUNCTION__, + // line->x1, line->y1, line->x2, line->y2, ucdev->color); + + int cmd; + int dx, dy, tmp, error; + + error = 1; + + cmd = VIA_GEC_LINE | VIA_GEC_FIXCOLOR_PAT | ucdev->draw_rop2d + | VIA_GEC_CLIP_ENABLE; + + dx = line->x2 - line->x1; + if (dx < 0) + { + dx = -dx; + cmd |= VIA_GEC_DECX; // line will be drawn from right + error = 0; + } + + dy = line->y2 - line->y1; + if (dy < 0) + { + dy = -dy; + cmd |= VIA_GEC_DECY; // line will be drawn from bottom + } + + if (dy > dx) + { + tmp = dy; + dy = dx; + dx = tmp; // Swap 'dx' and 'dy' + cmd |= VIA_GEC_Y_MAJOR; // Y major line + } + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_K1K2, + ((((dy << 1) & 0x3fff) << 16)| (((dy - dx) << 1) & 0x3fff))); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_XY, + ((RS16(line->y1) << 16) | RS16(line->x1))); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, dx); + UC_FIFO_ADD_2D(fifo, VIA_REG_LINE_ERROR, + (((dy << 1) - dx - error) & 0x3fff)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit(void* drv, void* dev, DFBRectangle* rect, int dx, int dy) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = (%d, %d, %d, %d) -> (%d, %d)\n", __PRETTY_FUNCTION__, + // rect->x, rect->y, rect->h, rect->w, dx, dy); + + int cmd = VIA_GEC_BLT | VIA_ROP_S | VIA_GEC_CLIP_ENABLE; + + int sx = rect->x; + int sy = rect->y; + int w = rect->w; + int h = rect->h; + + if (!w || !h) return true; + + (void) ucdev; // Kill 'unused variable' compiler warning. + + if (sx < dx) { + cmd |= VIA_GEC_DECX; + sx += w - 1; + dx += w - 1; + } + + if (sy < dy) { + cmd |= VIA_GEC_DECY; + sy += h - 1; + dy += h - 1; + } + + UC_FIFO_PREPARE(fifo, 10); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_NotTex << 16); + + UC_FIFO_ADD_2D(fifo, VIA_REG_SRCPOS, (RS16(sy) << 16) | RS16(sx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DSTPOS, (RS16(dy) << 16) | RS16(dx)); + UC_FIFO_ADD_2D(fifo, VIA_REG_DIMENSION, (RS16(h - 1) << 16) | RS16(w - 1)); + UC_FIFO_ADD_2D(fifo, VIA_REG_GECMD, cmd); + + UC_ACCEL_END(); + return true; +} + +// Functions using the 3D engine --- + +bool uc_fill_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + //printf("%s: r = {%d, %d, %d, %d}, c = 0x%08x\n", __PRETTY_FUNCTION__, + // r->x, r->y, r->w, r->h, ucdev->color3d); + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_AFP | + HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC | HC_HShading_FlatC; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (r->w == 0 || r->h == 0) return true; + + UC_FIFO_PREPARE(fifo, 18); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y + r->h, 0); + UC_FIFO_ADD_XYC(fifo, r->x + r->w, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_rectangle_3d(void* drv, void* dev, DFBRectangle* r) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_AFP | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 20); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x + r->w - 1, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y + r->h - 1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, r->x, r->y, ucdev->color3d); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_draw_line_3d(void* drv, void* dev, DFBRegion* line) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Line | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 12); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, line->x1, line->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, line->x2, line->y2, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + return true; +} + +bool uc_fill_triangle(void* drv, void* dev, DFBTriangle* tri) +{ + UC_ACCEL_BEGIN() + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Cd; + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HVCycle_Full | HC_HShading_FlatA; + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + UC_FIFO_PREPARE(fifo, 14); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYC(fifo, tri->x1, tri->y1, ucdev->color3d); + UC_FIFO_ADD_XYC(fifo, tri->x2, tri->y2, 0); + UC_FIFO_ADD_XYC(fifo, tri->x3, tri->y3, 0); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_ACCEL_END(); + return true; +} + +bool uc_blit_3d(void* drv, void* dev, + DFBRectangle* rect, int dx, int dy) +{ + // TODO: Write separate blit function to save some overhead. + + // Hmm, I don't think we can save anything beyond a few CPU cycles. -- dok + + DFBRectangle dest = {dx, dy, rect->w, rect->h}; + return uc_stretch_blit(drv, dev, rect, &dest); +} + +bool uc_stretch_blit(void* drv, void* dev, + DFBRectangle* sr, DFBRectangle* dr) +{ + UC_ACCEL_BEGIN() + + float w = ucdev->hwtex.l2w; + float h = ucdev->hwtex.l2h; + + float dy = dr->y; + + float s1 = (sr->x ) / w; + float t1 = (sr->y ) / h; + float s2 = (sr->x + sr->w) / w; + float t2 = (sr->y + sr->h) / h; + + int cmdB = HC_ACMD_HCmdB | HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_FlatC | + HC_HVCycle_AFP | HC_HVCycle_AA | HC_HVCycle_BB | HC_HVCycle_NewC; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + if (ucdev->bflags & DSBLIT_DEINTERLACE) { + t1 *= 0.5f; + t2 *= 0.5f; + + if (ucdev->field) + dy += 0.5f; + else + dy -= 0.5f; + } + + UC_FIFO_PREPARE(fifo, 30); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy, 1, 0, s2, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy+dr->h, 1, 0, s1, t2); + UC_FIFO_ADD_XYWCST(fifo, dr->x, dy, 1, ucdev->color3d, s1, t1); + UC_FIFO_ADD_XYWCST(fifo, dr->x+dr->w, dy+dr->h, 1, ucdev->color3d, s2, t2); + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + +#define DFBCOLOR_TO_ARGB(c) PIXEL_ARGB( (c).a, (c).r, (c).g, (c).b ) + +bool uc_texture_triangles( void *drv, void *dev, + DFBVertex *vertices, int num, + DFBTriangleFormation formation ) +{ + UC_ACCEL_BEGIN() + + int i; + + int cmdB = HC_ACMD_HCmdB | + HC_HVPMSK_X | HC_HVPMSK_Y | HC_HVPMSK_Z | HC_HVPMSK_W | + HC_HVPMSK_Cd | HC_HVPMSK_S | HC_HVPMSK_T; + + int cmdA = HC_ACMD_HCmdA | HC_HPMType_Tri | HC_HShading_Gouraud | + HC_HVCycle_Full; + + int cmdA_End = cmdA | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; + + + switch (formation) { + case DTTF_LIST: + cmdA |= HC_HVCycle_NewA | HC_HVCycle_NewB | HC_HVCycle_NewC; + break; + case DTTF_STRIP: + cmdA |= HC_HVCycle_AB | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + case DTTF_FAN: + cmdA |= HC_HVCycle_AA | HC_HVCycle_BC | HC_HVCycle_NewC; + break; + default: + D_ONCE( "unknown triangle formation" ); + return false; + } + + UC_FIFO_PREPARE(fifo, 6 + num * 7); + + UC_FIFO_ADD_HDR(fifo, HC_ParaType_CmdVdata << 16); + UC_FIFO_ADD(fifo, cmdB); + UC_FIFO_ADD(fifo, cmdA); + + for (i=0; i<num; i++) { + UC_FIFO_ADD_XYZWCST(fifo, + vertices[i].x, vertices[i].y, + vertices[i].z, vertices[i].w, ucdev->color3d, + vertices[i].s, vertices[i].t); + } + + UC_FIFO_ADD(fifo, cmdA_End); + + UC_FIFO_PAD_EVEN(fifo); + + UC_ACCEL_END(); + + return true; +} + + // Blit profiling + + //struct timeval tv_start, tv_stop; + //gettimeofday(&tv_start, NULL); + + // Run test here + + //gettimeofday(&tv_stop, NULL); + + //tv_stop.tv_sec -= tv_start.tv_sec; + //tv_stop.tv_usec -= tv_start.tv_usec; + //if (tv_stop.tv_usec < 0) { + // tv_stop.tv_sec--; + // tv_stop.tv_usec += 1000000; + //} + + //printf("elapsed time: %d us\n", tv_stop.tv_usec); diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_accel.h b/Source/DirectFB/gfxdrivers/cle266/uc_accel.h new file mode 100755 index 0000000..fb6e111 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_accel.h @@ -0,0 +1,119 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_ACCEL_H__ +#define __UC_ACCEL_H__ + +#include "unichrome.h" + + +// 2D accelerator capabilites + +#define UC_DRAWING_FLAGS_2D (DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_2D (DSBLIT_SRC_COLORKEY | DSBLIT_DST_COLORKEY) + +#define UC_DRAWING_FUNCTIONS_2D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE) + +#define UC_BLITTING_FUNCTIONS_2D (DFXL_BLIT) + + +// 3D accelerator capabilites + +#ifdef UC_ENABLE_3D + +#define UC_DRAWING_FLAGS_3D (DSDRAW_BLEND | DSDRAW_XOR) + +#define UC_BLITTING_FLAGS_3D (DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_BLEND_COLORALPHA | \ + DSBLIT_COLORIZE | \ + DSBLIT_DEINTERLACE) + +#define UC_DRAWING_FUNCTIONS_3D (DFXL_DRAWLINE | \ + DFXL_DRAWRECTANGLE | \ + DFXL_FILLRECTANGLE | \ + DFXL_FILLTRIANGLE) + +#define UC_BLITTING_FUNCTIONS_3D (DFXL_BLIT | \ + DFXL_STRETCHBLIT | \ + DFXL_TEXTRIANGLES) + +#else + +#define UC_DRAWING_FLAGS_3D 0 +#define UC_BLITTING_FLAGS_3D 0 +#define UC_DRAWING_FUNCTIONS_3D 0 +#define UC_BLITTING_FUNCTIONS_3D 0 + +#endif // UC_ENABLE_3D + + +// Functions + +void uc_emit_commands ( void *drv, + void *dev ); + +void uc_flush_texture_cache( void *drv, + void *dev ); + +bool uc_fill_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_blit ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_fill_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_rectangle_3d ( void *drv, + void *dev, + DFBRectangle *rect ); + +bool uc_draw_line_3d ( void *drv, + void *dev, + DFBRegion *line ); + +bool uc_fill_triangle ( void *drv, + void *dev, + DFBTriangle *tri ); + +bool uc_blit_3d ( void *drv, + void *dev, + DFBRectangle *rect, + int dx, + int dy ); + +bool uc_stretch_blit ( void *drv, + void *dev, + DFBRectangle *srect, + DFBRectangle *drect ); + +bool uc_texture_triangles ( void *drv, + void *dev, + DFBVertex *vertices, + int num, + DFBTriangleFormation formation ); + +#endif // __UC_ACCEL_H__ + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c new file mode 100755 index 0000000..cc13433 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.c @@ -0,0 +1,198 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> + +#include <fusion/shmalloc.h> + +#include "uc_fifo.h" + +//#define UC_FIFO_DUMP_DATA + +// Private functions --------------------------------------------------------- + +/** + * Pad the FIFO buffer to a 32 byte boundary. Used by uc_flush_agp(). + * @note Equivalent DRI code is in via_ioctl::viaFlushPrimsLocked() + */ + +static void uc_fifo_pad(struct uc_fifo* fifo) +{ + switch (fifo->used & 0x7) + { + case 0: + break; + case 2: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 4: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + case 6: + UC_FIFO_ADD(fifo, HALCYON_HEADER2); + UC_FIFO_ADD(fifo, HC_ParaType_NotTex << 16); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + UC_FIFO_ADD(fifo, HC_DUMMY); + break; + default: + break; + } +} + +/** + * Manually write the FIFO buffer to the hardware. + * @note Equivalent DRI code is in via_ioctl::flush_sys() + */ + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs) +{ + u32* p; + u32* q; + + volatile u32* hwregs = regs; + volatile u32* reg_tset = regs + VIA_REG_TRANSET; + volatile u32* reg_tspace = regs + VIA_REG_TRANSPACE; + + int check2Dcmd; + u32 addr; + + p = fifo->buf; + q = fifo->head; + check2Dcmd = 0; + + uc_fifo_pad(fifo); + +#ifdef UC_FIFO_DUMP_DATA + printf("Flushing FIFO ... \n"); +#endif + + while (p != q) { + + if (*p == HALCYON_HEADER2) { + p++; + check2Dcmd = !(*p == HALCYON_SUB_ADDR0); +#ifdef UC_FIFO_DUMP_DATA + printf("tset = 0x%08x\n", *p); +#endif + *reg_tset = *p; + p++; + } + else if (check2Dcmd && ((*p & HALCYON_HEADER1MASK) == HALCYON_HEADER1)) { + addr = (*p) & 0x0000001f; + p++; +#ifdef UC_FIFO_DUMP_DATA + printf("2D (0x%02x) = 0x%x\n", addr << 2, *p); +#endif + *(hwregs + addr) = *p; + p++; + } + else if ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD) { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + + if ((p != q) && ((*p & HALCYON_FIREMASK) == HALCYON_FIRECMD)) + p++; + + if ((*p & HALCYON_CMDBMASK) != HC_ACMD_HCmdB) + check2Dcmd = 1; + } + else { +#ifdef UC_FIFO_DUMP_DATA + printf("tspace = 0x%08x\n", *p); +#endif + *reg_tspace = *p; + p++; + } + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} + +/** Use an AGP transfer to write the FIFO buffer to the hardware. Not implemented. */ +#if 0 +static void uc_fifo_flush_agp(struct uc_fifo* fifo) +{ + // TODO - however, there is no point in doing this, because + // an AGP transfer can require more register writes than + // needed for drawing a single primitive. DirectFB needs to + // adopt a begin/end architecture first, like OpenGL has. + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->prep = 0; +} +#endif + +// Public functions ---------------------------------------------------------- + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create(FusionSHMPoolShared *pool, size_t size) +{ + struct uc_fifo* fifo; + + size += 32; // Needed for padding. + + fifo = SHCALLOC(pool, 1, sizeof(struct uc_fifo)); + if (!fifo) return NULL; + + // Note: malloc won't work for DMA buffers... + + fifo->buf = SHMALLOC(pool, sizeof(u32) * size); + if (!(fifo->buf)) { + SHFREE(pool, fifo); + return NULL; + } + + fifo->head = fifo->buf; + fifo->used = 0; + fifo->size = (unsigned int) size; + fifo->prep = 0; + + //fifo->flush_sys = uc_fifo_flush_sys; + + //fifo->flush = uc_fifo_flush_sys; + + return fifo; +} + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo) +{ + if (fifo) { + if (fifo->buf) { + SHFREE(pool, fifo->buf); + fifo->buf = NULL; + } + SHFREE(pool, fifo); + } +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h new file mode 100755 index 0000000..c7e2fe3 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_fifo.h @@ -0,0 +1,268 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_FIFO_H__ +#define __UC_FIFO_H__ + +// Note to self: remove when added to makefile as -DUC_DEBUG. +#define UC_DEBUG 1 + +#include <dfb_types.h> + +#include "regs2d.h" +#include "regs3d.h" +#include "mmio.h" + +/** + * uc_fifo - GPU data queue. + * + * buf: buffer start (userspace address) + * head: pointer to first unused entry. + * + * size: maximum number of entries in the fifo. + * prep: number of entries allocated to be used. + * used: number of entries currently in use. + * + * hwregs: GPU register base address + * reg_tset: address to GPU TRANSET register + * reg_tspace: address to GPU TRANSPACE register + * + * flush: function pointer to flush function (DMA or CPU) + * flush_sys: function pointer to flush_sys (non-DMA) function + */ + +struct uc_fifo +{ + u32* buf; + u32* head; + + unsigned int size; + unsigned int prep; + unsigned int used; + + //void (*flush)(struct uc_fifo* fifo, volatile void *hwregs); + //void (*flush_sys)(struct uc_fifo* fifo, volatile void *hwregs); +}; + +// Help macros --------------------------------------------------------------- + +// For the record: Macros suck maintenance- and debugging-wise, +// but provide guaranteed inlining of the code. + +/** + * Send the contents of the FIFO buffer to the hardware, and clear + * the buffer. The transfer may be performed by the CPU or by DMA. + */ + +//#define UC_FIFO_FLUSH(fifo) (fifo)->flush(fifo,ucdrv->hwregs) + +/** + * Same as UC_FIFO_FLUSH(), but always uses the CPU to transfer data. + */ + +//#define UC_FIFO_FLUSH_SYS(fifo) (fifo)->flush_sys(fifo,ucdrv->hwregs) + +#define UC_FIFO_FLUSH(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) +#define UC_FIFO_FLUSH_SYS(fifo) uc_fifo_flush_sys(fifo,ucdrv->hwregs) + +/** + * Make sure there is room for dwsize double words in the FIFO. + * If necessary, the FIFO is flushed first. + * + * @param fifo the fifo + * @param dwsize number of double words to allocate + * + * @note It is ok to request more space than you will actually + * be using. This is useful when you don't know exactly beforehand + * how many entries you need. + * + * @note equivalent DRI code is in via_ioctl.c::viaCheckDma() + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + D_DEBUG("CLE266: FIFO full - flushing it."); \ + UC_FIFO_FLUSH(fifo); \ + } \ + if (dwsize + (fifo)->prep + 32 > (fifo)->size) { \ + D_BUG("CLE266: FIFO too small for allocation."); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#else + +#define UC_FIFO_PREPARE(fifo, dwsize) \ + do { \ + if ((fifo)->used + dwsize + 32 > (fifo)->size) { \ + UC_FIFO_FLUSH(fifo); \ + } \ + (fifo)->prep += dwsize; \ + } while(0) + +#endif // UC_FIFO_DEBUG + +/** + * Add a 32-bit data word to the FIFO. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD(fifo, data) \ + do { \ + *((fifo)->head) = (data); \ + (fifo)->head++; \ + (fifo)->used++; \ + } while(0) + +/** + * Add a command header. (HC_HEADER2 + parameter selection) + * Takes two entries in the fifo. + */ + +#define UC_FIFO_ADD_HDR(fifo, param) \ + do { \ + UC_FIFO_ADD(fifo, HC_HEADER2); \ + UC_FIFO_ADD(fifo, param); \ + } while(0); + +/** + * Add a floating point value to the FIFO. + * Non-floats (e.g integers) are converted first. + * Takes one entry in the FIFO. + */ + +#define UC_FIFO_ADD_FLOAT(fifo, val) \ + do { \ + union {float f; u32 i;} v; \ + v.f = (float) (val); \ + UC_FIFO_ADD(fifo, v.i); \ + } while(0) + +/** + * Add a vertex on the form (x, y, color) to the FIFO. + * Takes three entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYC(fifo, x, y, color) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + } while(0) + +/** + * Add a vertex on the form (x, y, w, color, s, t) to the FIFO. + * Takes six entries in the FIFO. + * The color format is 0xAARRGGBB. + */ + +#define UC_FIFO_ADD_XYWCST(fifo, x, y, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYZWCST(fifo, x, y, z, w, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD_FLOAT(fifo, z); \ + UC_FIFO_ADD_FLOAT(fifo, w); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + +#define UC_FIFO_ADD_XYCST(fifo, x, y, color, s, t) \ + do { \ + UC_FIFO_ADD_FLOAT(fifo, x); \ + UC_FIFO_ADD_FLOAT(fifo, y); \ + UC_FIFO_ADD(fifo, color); \ + UC_FIFO_ADD_FLOAT(fifo, s); \ + UC_FIFO_ADD_FLOAT(fifo, t); \ + } while(0) + + +/** + * Add data specifically for the 2D controller, to the fifo. + * Takes two entries in the FIFO. + * + * @param reg 2D register index + * @param data 32-bit data to add + */ + +#define UC_FIFO_ADD_2D(fifo, reg, data) \ + do { \ + UC_FIFO_ADD(fifo, ((reg) >> 2) | HALCYON_HEADER1); \ + UC_FIFO_ADD(fifo, (data)); \ + } while (0) + +/** + * Add data specifically for a 3D controller register, to the fifo. + * Takes one entry in the FIFO. + * + * @param reg 3D register index (8 bit) + * @param data 24-bit data to add (make sure bits 24 - 31 are cleared!) + */ + +#define UC_FIFO_ADD_3D(fifo, reg, data) \ + UC_FIFO_ADD(fifo, ((reg) << 24) | (data)) + +/** + * Pad the FIFO to an even number of entries. + * Takes zero or one entries in the FIFO. + */ +#define UC_FIFO_PAD_EVEN(fifo) \ + if (fifo->used & 1) UC_FIFO_ADD(fifo, HC_DUMMY) + +/** + * Check for buffer overruns. + * Can be redefined to nothing in release builds. + */ + +#ifdef UC_DEBUG + +#define UC_FIFO_CHECK(fifo) \ + do { \ + if ((fifo)->used > ((fifo)->size) - 32) { \ + D_BUG("CLE266: FIFO overrun."); \ + } \ + if ((fifo)->used > (fifo)->prep) { \ + D_BUG("CLE266: FIFO allocation error."); \ + } \ + } while(0) + +#else + +#define UC_FIFO_CHECK(fifo) do { } while(0) + +#endif // UC_DEBUG + + +// FIFO functions ------------------------------------------------------------ + +/** Create a FIFO. Returns NULL on failure. */ + +struct uc_fifo* uc_fifo_create(FusionSHMPoolShared *pool, size_t size); + +/** Destroy a FIFO */ + +void uc_fifo_destroy(FusionSHMPoolShared *pool, struct uc_fifo* fifo); + +void uc_fifo_flush_sys(struct uc_fifo* fifo, volatile void *regs); + +#endif // __UC_FIFO_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hw.h b/Source/DirectFB/gfxdrivers/cle266/uc_hw.h new file mode 100755 index 0000000..83e3085 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hw.h @@ -0,0 +1,93 @@ +// Shared header file for uc_hwmap.c and uc_hwset.c. + +#ifndef __UC_HW_H__ +#define __UC_HW_H__ + +#include <direct/messages.h> + +#include <core/coredefs.h> + +#include "unichrome.h" +#include "uc_fifo.h" + +// GPU - mapping functions (uc_hwmap.c) + +/// Map a DirectFB destination surface pixel format to the hw. (3D) +static inline int uc_map_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HDBFM_ARGB1555; + case DSPF_RGB16: return HC_HDBFM_RGB565; + case DSPF_RGB32: return HC_HDBFM_ARGB0888; + case DSPF_ARGB: return HC_HDBFM_ARGB8888; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +/// Map a DirectFB source surface pixel format to the hw. (3D) +static inline int uc_map_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: return HC_HTXnFM_ARGB1555; + case DSPF_RGB16: return HC_HTXnFM_RGB565; + case DSPF_RGB32: return HC_HTXnFM_ARGB0888; + case DSPF_ARGB: return HC_HTXnFM_ARGB8888; + case DSPF_A8: return HC_HTXnFM_A8; + case DSPF_LUT8: return HC_HTXnFM_Index8; + + default: + D_BUG( "unexpected pixel format" ); + } + + return 0; +} + +void uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dformat ); + +void uc_map_blitflags ( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat ); + +// GPU - setting functions (uc_hwset.c) + +void uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_texenv ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_clip ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_source_3d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_color_2d ( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +void uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ); + +#endif // __UC_HW_H__ + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c b/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c new file mode 100755 index 0000000..4c2d8a0 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hwmap.c @@ -0,0 +1,357 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware mapping functions ------------------------------------------------ + +#include <config.h> + +#include "uc_hw.h" +#include <gfx/convert.h> + +/// Map DirectFB blending functions to hardware +void +uc_map_blending_fn( struct uc_hw_alpha *hwalpha, + DFBSurfaceBlendFunction sblend, + DFBSurfaceBlendFunction dblend, + DFBSurfacePixelFormat dst_format ) +{ + bool dst_alpha = DFB_PIXELFORMAT_HAS_ALPHA(dst_format); + + // The HW's blending equation is: + // (Ca * FCa + Cbias + Cb * FCb) << Cshift + + // Set source blending function + + // Ca -- always from source color. + hwalpha->regHABLCsat = HC_HABLCsat_MASK | HC_HABLCa_OPC | HC_HABLCa_Csrc; + // Aa -- always from source alpha. + hwalpha->regHABLAsat = HC_HABLAsat_MASK | HC_HABLAa_OPA | HC_HABLAa_Asrc; + + // FCa and FAa depend on the following condition. + switch (sblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Csrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Asrc; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Asrc; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Adst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_OPA | HC_HABLFAa_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_InvOPC | HC_HABLFCa_Cdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_Adst; + break; + + case DSBF_SRCALPHASAT: + // GL_SRC_ALPHA_SATURATE + if (!dst_alpha) { + // (f, f, f, 1), f = min(As, 1 - Ad) = min(As, 1 - 1) = 0 + // So (f, f, f, 1) = (0, 0, 0, 1) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_HABLRCa; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + else { + // (f, f, f, 1), f = min(As, 1 - Ad) + hwalpha->regHABLCsat |= HC_HABLFCa_OPC | HC_HABLFCa_mimAsrcInvAdst; + hwalpha->regHABLAsat |= HC_HABLFAa_InvOPA | HC_HABLFAa_HABLFRA; + hwalpha->regHABLRFCa = 0x0; + hwalpha->regHABLRAa = 0x0; + } + break; + default: + D_BUG("Unsupported blending function!"); + break; + } + + // Set destination blending function + + // Op is add. + // bias is 0. + + hwalpha->regHABLCsat |= HC_HABLCbias_HABLRCbias; + hwalpha->regHABLAsat |= HC_HABLAbias_HABLRAbias; + + // Cb -- always from destination color. + hwalpha->regHABLCop = HC_HABLCb_OPC | HC_HABLCb_Cdst; + // Ab -- always from destination alpha. + hwalpha->regHABLAop = HC_HABLAb_OPA | HC_HABLAb_Adst; + + // FCb -- depends on the following condition. + switch (dblend) { + case DSBF_ZERO: + // GL_ZERO -- (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_ONE: + // GL_ONE -- (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + + case DSBF_SRCCOLOR: + // GL_SRC_COLOR -- (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCCOLOR: + // GL_ONE_MINUS_SRC_COLOR -- (1, 1, 1, 1) - (Rs, Gs, Bs, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Csrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Asrc; + break; + + case DSBF_SRCALPHA: + // GL_SRC_ALPHA -- (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Asrc; + break; + + case DSBF_INVSRCALPHA: + // GL_ONE_MINUS_SRC_ALPHA -- (1, 1, 1, 1) - (As, As, As, As) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Asrc; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_0; + break; + + case DSBF_DESTALPHA: + // GL_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_INVDESTALPHA: + // GL_ONE_MINUS_DST_ALPHA + if (!dst_alpha) { // (1, 1, 1, 1) - (1, 1, 1, 1) = (0, 0, 0, 0) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + } + else { // (1, 1, 1, 1) - (Ad, Ad, Ad, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Adst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + } + break; + + case DSBF_DESTCOLOR: + // GL_DST_COLOR -- (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_Adst; + break; + + case DSBF_INVDESTCOLOR: + // GL_ONE_MINUS_DST_COLOR -- (1, 1, 1, 1) - (Rd, Gd, Bd, Ad) + hwalpha->regHABLCop |= HC_HABLFCb_InvOPC | HC_HABLFCb_Cdst; + hwalpha->regHABLAop |= HC_HABLFAb_InvOPA | HC_HABLFAb_Adst; + break; + + case DSBF_SRCALPHASAT: + // Unsupported? + + default: + hwalpha->regHABLCop |= HC_HABLFCb_OPC | HC_HABLFCb_HABLRCb; + hwalpha->regHABLAop |= HC_HABLFAb_OPA | HC_HABLFAb_HABLFRA; + hwalpha->regHABLRFCb = 0x0; + hwalpha->regHABLRAb = 0x0; + break; + } +} + +/// Map DFBSurfaceBlittingFlags to the hardware +void +uc_map_blitflags( struct uc_hw_texture *tex, + DFBSurfaceBlittingFlags bflags, + DFBSurfacePixelFormat sformat ) +{ + bool gotalpha = DFB_PIXELFORMAT_HAS_ALPHA(sformat); + + if (bflags & DSBLIT_COLORIZE) { + // Cv0 = Ct*Cf + + // Hw setting: + // Ca = Ct, Cb = Cf, Cop = +, Cc = 0, Cbias = 0, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_Tex | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_Dif | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_0 | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + else { + // Cv0 = Ct + + // Hw setting: + // Ca = 0, Cb = 0, Cop = +, Cc = 0, Cbias = Ct, Cshift = No. + + tex->regHTXnTBLCsat_0 = HC_HTXnTBLCsat_MASK | + HC_HTXnTBLCa_TOPC | HC_HTXnTBLCa_0 | + HC_HTXnTBLCb_TOPC | HC_HTXnTBLCb_0 | + HC_HTXnTBLCc_TOPC | HC_HTXnTBLCc_0; + tex->regHTXnTBLCop_0 = HC_HTXnTBLCop_Add | + HC_HTXnTBLCbias_Cbias | HC_HTXnTBLCbias_Tex | + HC_HTXnTBLCshift_No; + tex->regHTXnTBLMPfog_0 = HC_HTXnTBLMPfog_0; + } + + if (bflags & DSBLIT_BLEND_COLORALPHA) { + if ((bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) { + // Av0 = At*Af + + // Hw setting: + // Aa = At, Ab = Af, Cop = +, Ac = 0, Abias = 0, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_Atex | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_Adif | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { + // (!(bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) || !gotalpha + // Av0 = Af + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = Af, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Adif | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } + else { // !(bflags & DSBLIT_BLEND_COLORALPHA) + if ((bflags & DSBLIT_BLEND_ALPHACHANNEL) && gotalpha) { + // Av0 = At + + // Hw setting: + // Aa = 0, Ab = 0, Cop = +, Ac = 0, Abias = At, Ashift = No. + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Atex | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + else { // !gotalpha + // Av0 = 1.0 + + // D_BUG warning: I'm guessing where values should go, + // and how big (0xff = 1.0 ?) it should be. + + // Hw setting: + // Aa = 1.0, Ab = 1.0, Cop = -, Ac = 1.0, Abias = 1.0, Ashift = No. + // => Av = Aa*(Ab-Ac) + Abias = 1*(1-1)+1 = 1 + + tex->regHTXnTBLAsat_0 = HC_HTXnTBLAsat_MASK | + HC_HTXnTBLAa_TOPA | HC_HTXnTBLAa_HTXnTBLRA | + HC_HTXnTBLAb_TOPA | HC_HTXnTBLAb_HTXnTBLRA | + HC_HTXnTBLAc_TOPA | HC_HTXnTBLAc_HTXnTBLRA; + tex->regHTXnTBLCop_0 |= HC_HTXnTBLAop_Add | + HC_HTXnTBLAbias_Inv | HC_HTXnTBLAbias_HTXnTBLRAbias | HC_HTXnTBLAshift_No; + tex->regHTXnTBLRAa_0 = 0x0; + tex->regHTXnTBLRFog_0 = 0x0; + } + } +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c b/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c new file mode 100755 index 0000000..8ba9d09 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_hwset.c @@ -0,0 +1,419 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +// Hardware setting functions ------------------------------------------------ + +#include <config.h> + +#include "uc_hw.h" +#include <core/state.h> +#include <core/palette.h> +#include <gfx/convert.h> + +/// Integer 2-logarithm, y = log2(x), where x and y are integers. +#define ILOG2(x,y) ILOG2_PORTABLE(x,y) + +#define ILOG2_PORTABLE(x,y) \ + do { \ + unsigned int i = 0; \ + y = x; \ + while (y != 0) { \ + i++; \ + y = y >> 1; \ + } \ + y = i-1; \ + } while (0) + +#define ILOG2_X86(x,y) // TODO - use BSR (bit scan reverse) instruction + +/// Set alpha blending function (3D) +void +uc_set_blending_fn( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_alpha *hwalpha = &ucdev->hwalpha; + + if (UC_IS_VALID( uc_blending_fn )) + return; + + uc_map_blending_fn( hwalpha, state->src_blend, state->dst_blend, + state->destination->config.format ); + + UC_FIFO_PREPARE( fifo, 14 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCsat, hwalpha->regHABLCsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLCop, hwalpha->regHABLCop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAsat, hwalpha->regHABLAsat ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLAop, hwalpha->regHABLAop ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCa, hwalpha->regHABLRCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCa, hwalpha->regHABLRFCa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCbias, hwalpha->regHABLRCbias ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRCb, hwalpha->regHABLRCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRFCb, hwalpha->regHABLRFCb ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAa, hwalpha->regHABLRAa ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HABLRAb, hwalpha->regHABLRAb ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_blending_fn ); +} + +/// Set texture environment (3D) +void +uc_set_texenv( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + if (UC_IS_VALID( uc_texenv )) + return; + + uc_map_blitflags( hwtex, state->blittingflags, state->source->config.format ); + + // Texture mapping method + hwtex->regHTXnTB = HC_HTXnFLSs_Linear | HC_HTXnFLTs_Linear | + HC_HTXnFLSe_Linear | HC_HTXnFLTe_Linear; + + hwtex->regHTXnMPMD = HC_HTXnMPMD_Sclamp | HC_HTXnMPMD_Tclamp; + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24) ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTB, hwtex->regHTXnTB ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnMPMD, hwtex->regHTXnMPMD ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCsat, hwtex->regHTXnTBLCsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLCop, hwtex->regHTXnTBLCop_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLMPfog, hwtex->regHTXnTBLMPfog_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLAsat, hwtex->regHTXnTBLAsat_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRCb, hwtex->regHTXnTBLRCb_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRAa, hwtex->regHTXnTBLRAa_0 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnTBLRFog, hwtex->regHTXnTBLRFog_0 ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_texenv ); +} + +/// Set clipping rectangle (2D and 3D) +void +uc_set_clip( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (DFB_REGION_EQUAL( ucdev->clip, state->clip )) + return; + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + +#ifdef UC_ENABLE_3D + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipTB, + (RS12(state->clip.y1) << 12) | RS12(state->clip.y2+1) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HClipLR, + (RS12(state->clip.x1) << 12) | RS12(state->clip.x2+1) ); + +#endif + + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPTL, + (RS16(state->clip.y1) << 16) | RS16(state->clip.x1) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_CLIPBR, + (RS16(state->clip.y2) << 16) | RS16(state->clip.x2) ); + + UC_FIFO_CHECK( fifo ); + + ucdev->clip = state->clip; +} + +/// Set destination (2D and 3D) +void +uc_set_destination( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + CoreSurface *destination = state->destination; + + DFBSurfacePixelFormat dst_format = destination->config.format; + int dst_offset = state->dst.offset; + int dst_pitch = state->dst.pitch; + int dst_bpp = DFB_BYTES_PER_PIXEL( dst_format ); + + + /* Save FIFO space and CPU cycles. */ + if (ucdev->dst_format == dst_format && + ucdev->dst_offset == dst_offset && + ucdev->dst_pitch == dst_pitch) + return; + + // 2D engine setting + + ucdev->pitch = (ucdev->pitch & 0x7fff) | (((dst_pitch >> 3) & 0x7fff) << 16); + + UC_FIFO_PREPARE( fifo, 12 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, (VIA_PITCH_ENABLE | ucdev->pitch) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_DSTBASE, (dst_offset >> 3) ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_GEMODE, (dst_bpp - 1) << 8 ); + +#ifdef UC_ENABLE_3D + // 3D engine setting + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasL, dst_offset & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBBasH, dst_offset >> 24 ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HDBFM, (uc_map_dst_format( dst_format ) | + (dst_pitch & HC_HDBPit_MASK) | + HC_HDBLoc_Local) ); + + UC_FIFO_PAD_EVEN(fifo); +#endif + + UC_FIFO_CHECK( fifo ); + + ucdev->dst_format = dst_format; + ucdev->dst_offset = dst_offset; + ucdev->dst_pitch = dst_pitch; +} + +/// Set new source (2D) +void +uc_set_source_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_source2d )) + return; + + ucdev->pitch &= 0x7fff0000; + ucdev->pitch |= (state->src.pitch >> 3) & 0x7fff; + + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_SRCBASE, state->src.offset >> 3 ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_PITCH, VIA_PITCH_ENABLE | ucdev->pitch ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_source2d ); +} + +/// Set new source (3D) +void +uc_set_source_3d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + struct uc_hw_texture *hwtex = &ucdev->hwtex; + + CoreSurface *source = state->source; + + int src_height, src_offset, src_pitch; + + if (UC_IS_VALID( uc_source3d )) + return; + + src_height = source->config.size.h; + src_offset = state->src.offset; + src_pitch = state->src.pitch; + + /* + * TODO: Check if we can set the odd/even field as L1/L2 texture and select + * between L0/L1/L2 upon blit. Otherwise we depend on SMF_BLITTINGFLAGS ;( + */ + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + if (source->field) + src_offset += src_pitch; + + src_height >>= 1; + src_pitch <<= 1; + } + + ucdev->field = source->field; + + // Round texture size up to nearest + // value evenly divisible by 2^n + + ILOG2(source->config.size.w, hwtex->we); + hwtex->l2w = 1 << hwtex->we; + if (hwtex->l2w < source->config.size.w) { + hwtex->we++; + hwtex->l2w <<= 1; + } + + ILOG2(src_height, hwtex->he); + hwtex->l2h = 1 << hwtex->he; + if (hwtex->l2h < src_height) { + hwtex->he++; + hwtex->l2h <<= 1; + } + + hwtex->format = uc_map_src_format_3d( source->config.format ); + + UC_FIFO_PREPARE( fifo, 10); + + UC_FIFO_ADD_HDR( fifo, (HC_ParaType_Tex << 16) | (HC_SubType_Tex0 << 24)); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnFM, HC_HTXnLoc_Local | hwtex->format ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0OS, (0 << HC_HTXnLVmax_SHIFT) ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5WE, hwtex->we ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0_5HE, hwtex->he ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL012BasH, (src_offset >> 24) & 0xff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0BasL, (src_offset ) & 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HTXnL0Pit, (HC_HTXnEnPit_MASK | src_pitch) ); + + UC_FIFO_PAD_EVEN( fifo ); + + UC_FIFO_CHECK( fifo ); + + // Upload the palette of a 256 color texture. + + if (hwtex->format == HC_HTXnFM_Index8) { + int i, num; + DFBColor *colors; + + UC_FIFO_PREPARE( fifo, 258 ); + + UC_FIFO_ADD_HDR( fifo, ((HC_ParaType_Palette << 16) | + (HC_SubType_TexPalette0 << 24)) ); + + colors = source->palette->entries; + num = source->palette->num_entries; + + if (num > 256) + num = 256; + + /* What about the last entry? -- dok */ + for (i = 0; i < num; i++) + UC_FIFO_ADD( fifo, PIXEL_ARGB(colors[i].a, colors[i].r, + colors[i].g, colors[i].b) ); + + for (; i < 256; i++) + UC_FIFO_ADD( fifo, 0 ); + + UC_FIFO_CHECK( fifo ); + } + + UC_VALIDATE( uc_source3d ); +} + +/// Set either destination color key, or fill color, as needed. (2D) +void +uc_set_color_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + u32 color = 0; + + if (UC_IS_VALID( uc_color2d )) + return; + + switch (state->destination->config.format) { + case DSPF_ARGB1555: + color = PIXEL_ARGB1555( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + color |= color << 16; + break; + + case DSPF_RGB16: + color = PIXEL_RGB16( state->color.r, + state->color.g, + state->color.b); + color |= color << 16; + break; + + case DSPF_RGB32: + case DSPF_ARGB: + color = PIXEL_ARGB( state->color.a, + state->color.r, + state->color.g, + state->color.b ); + break; + + default: + D_BUG( "unexpected pixel format" ); + } + + + UC_FIFO_PREPARE( fifo, 8 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + // Opaque line drawing needs this + UC_FIFO_ADD_2D( fifo, VIA_REG_MONOPAT0, 0xff ); + + UC_FIFO_ADD_2D( fifo, VIA_REG_KEYCONTROL, 0 ); + UC_FIFO_ADD_2D( fifo, VIA_REG_FGCOLOR, color ); + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_color2d ); + UC_INVALIDATE( uc_colorkey2d ); +} + +void +uc_set_colorkey_2d( UcDriverData *ucdrv, + UcDeviceData *ucdev, + CardState *state ) +{ + struct uc_fifo *fifo = ucdrv->fifo; + + if (UC_IS_VALID( uc_colorkey2d )) + return; + + if (state->blittingflags & DSBLIT_SRC_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, VIA_KEY_ENABLE_SRCKEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_BGCOLOR, state->src_colorkey ); + } + else if (state->blittingflags & DSBLIT_DST_COLORKEY) { + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, + VIA_KEY_ENABLE_DSTKEY | VIA_KEY_INVERT_KEY ); + UC_FIFO_ADD_2D ( fifo, VIA_REG_FGCOLOR, state->dst_colorkey ); + } + else { + UC_FIFO_PREPARE( fifo, 4 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + UC_FIFO_ADD_2D ( fifo, VIA_REG_KEYCONTROL, 0 ); + } + + UC_FIFO_CHECK( fifo ); + + UC_VALIDATE( uc_colorkey2d ); + UC_INVALIDATE( uc_color2d ); +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c new file mode 100755 index 0000000..2c50476 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.c @@ -0,0 +1,320 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +#include <direct/messages.h> + +#include <core/system.h> + +#include <misc/conf.h> + +// Forward declaration +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data); + + +static int uc_ovl_datasize( void ) +{ + return sizeof(UcOverlayData); +} + + +static DFBResult +uc_ovl_init_layer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + + // Set layer type, capabilities and name + + description->caps = UC_OVL_CAPS; + description->type = DLTF_GRAPHICS | DLTF_VIDEO | DLTF_STILL_PICTURE; + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA CLE266 Video"); + + adjustment->flags = DCAF_NONE; + + // Fill out the default configuration + + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | DLCONF_OPTIONS; + + ucovl->v1.win.w = 720; + ucovl->v1.win.h = 576; + ucovl->v1.win.x = 0; + ucovl->v1.win.y = 0; + + config->width = 720; + config->height = 576; + + config->pixelformat = DSPF_YV12; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + // Reset overlay + + ucovl->extfifo_on = false; + ucovl->hwrev = ucdrv->hwrev; + ucovl->scrwidth = ucovl->v1.win.w; + + ucovl->v1.isenabled = false; + ucovl->v1.cfg = *config; + ucovl->v1.ox = 0; + ucovl->v1.oy = 0; + +// adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | +// DCAF_HUE | DCAF_SATURATION; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + ucovl->v1.adj = *adjustment; + + uc_ovl_remove(layer, driver_data, layer_data, NULL); + + return DFB_OK; +} + + +static DFBResult +uc_ovl_set_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + + /* get new destination rectangle */ + DFBRectangle win = config->dest;; + + // Bounds checking + if ((win.x < -8192) || (win.x > 8192) || + (win.y < -8192) || (win.y > 8192) || + (win.w < 32) || (win.w > 4096) || + (win.h < 32) || (win.h > 4096)) + { + D_DEBUG("Layer size or position is out of bounds."); + return DFB_INVAREA; + } + + ucovl->v1.isenabled = true; + ucovl->v1.win = win; + + ucovl->deinterlace = config->options & DLOP_DEINTERLACING; + ucovl->surface = surface; + ucovl->lock = lock; + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_CHANGE, surface, lock); +} + + +static DFBResult +uc_ovl_remove(CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + volatile u8* vio = ucdrv->hwregs; + + ucovl->v1.isenabled = false; + + uc_ovl_vcmd_wait(vio); + + VIDEO_OUT(vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL(16,12,8)); + // VIDEO_OUT(vio, ALPHA_V3_FIFO_CONTROL, 0x0407181f); + + if (ucovl->hwrev == 0x10) { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0); + } + else { + VIDEO_OUT(vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); + VIDEO_OUT(vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); + } + + VIDEO_OUT(vio, HQV_CONTROL, VIDEO_IN(vio, HQV_CONTROL) & ~HQV_ENABLE); + VIDEO_OUT(vio, V1_CONTROL, VIDEO_IN(vio, V1_CONTROL) & ~V1_ENABLE); + // VIDEO_OUT(vio, V3_CONTROL, VIDEO_IN(vio, V3_CONTROL) & ~V3_ENABLE); + + VIDEO_OUT(vio, V_COMPOSE_MODE, + VIDEO_IN(vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + ucovl->surface = NULL; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_test_region(CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed) +{ + CoreLayerRegionConfigFlags fail = 0; + + // Check layer options + + if (config->options & ~UC_OVL_OPTIONS) + fail |= CLRCF_OPTIONS; + + // Check pixelformats + + switch (config->format) { + case DSPF_YUY2: + break; + case DSPF_UYVY: + fail |= CLRCF_FORMAT; // Nope... doesn't work. + break; + case DSPF_I420: + case DSPF_YV12: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + default: + fail |= CLRCF_FORMAT; + } + + // Check width and height + + if (config->width > 4096 || config->width < 32) + fail |= CLRCF_WIDTH; + + if (config->height > 4096 || config->height < 32) + fail |= CLRCF_HEIGHT; + + if (failed) *failed = fail; + if (fail) return DFB_UNSUPPORTED; + + return DFB_OK; +} + + +static DFBResult +uc_ovl_flip_region( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock) +{ + //printf("Entering %s ... \n", __PRETTY_FUNCTION__); + + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + DFBResult ret; + + if (((flags & DSFLIP_WAITFORSYNC) == DSFLIP_WAITFORSYNC) && + !dfb_config->pollvsync_after) + dfb_layer_wait_vsync( layer ); + + dfb_surface_flip(surface, false); + + ucovl->field = 0; + ucovl->lock = lock; + + ret = uc_ovl_update(ucdrv, ucovl, UC_OVL_FLIP, surface, lock); + if (ret) + return ret; + + if ((flags & DSFLIP_WAIT) && + (dfb_config->pollvsync_after || !(flags & DSFLIP_ONSYNC))) + dfb_layer_wait_vsync(layer); + + return DFB_OK; +} + +static DFBResult +uc_ovl_get_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int *level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + *level = ucovl->v1.level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_level(CoreLayer *layer, + void *driver_data, + void *layer_data, + int level) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (level == 0) return DFB_INVARG; + if (level > 0) { + // Enable underlay mode. + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(-1)); + } + else { + // Enable overlay mode (default) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, + uc_ovl_map_alpha(ucovl->v1.opacity)); + } + + ucovl->v1.level = level; + return DFB_OK; +} + +static DFBResult +uc_ovl_set_input_field( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + ucovl->field = field; + + return uc_ovl_update(ucdrv, ucovl, UC_OVL_FIELD, ucovl->surface, ucovl->lock); +} + +DisplayLayerFuncs ucOverlayFuncs = { + .LayerDataSize = uc_ovl_datasize, + .InitLayer = uc_ovl_init_layer, + .SetRegion = uc_ovl_set_region, + .RemoveRegion = uc_ovl_remove, + .TestRegion = uc_ovl_test_region, + .FlipRegion = uc_ovl_flip_region, + .GetLevel = uc_ovl_get_level, + .SetLevel = uc_ovl_set_level, + .SetInputField = uc_ovl_set_input_field, + .SetColorAdjustment = uc_ovl_set_adjustment, +}; diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h new file mode 100755 index 0000000..e687980 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_overlay.h @@ -0,0 +1,85 @@ +#ifndef __UC_OVERLAY_H__ +#define __UC_OVERLAY_H__ + +#define UC_OVL_CAPS (DLCAPS_SURFACE | DLCAPS_OPACITY | DLCAPS_SCREEN_LOCATION \ + | DLCAPS_DEINTERLACING | DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST \ + | DLCAPS_SATURATION | DLCAPS_HUE) +#define UC_OVL_OPTIONS (DLOP_DEINTERLACING) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) +#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ + (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) + +// Actions for uc_ovl_update() + +#define UC_OVL_FLIP 1 +#define UC_OVL_CHANGE 2 +#define UC_OVL_FIELD 4 + +/** Overlay layer data. */ +struct uc_ovl_vinfo { + bool isenabled; // True when visible + DFBRectangle win; // Layer screen rectangle. + DFBDisplayLayerConfig cfg; // Layer configuration + int ox, oy; // Top-left visible corner (the offset) + // in the source surface + u8 opacity; // Layer opacity + int level; // Position in the DirectFB layer stack + // < 0 = underlay mode, > 0 = overlay mode + DFBColorAdjustment adj; // Color adjustment (brightness etc) +}; + +typedef struct _UcOverlayData { + + // TODO: initialize the variables!!! + + u8 hwrev; // CLE266 revision + int scrwidth; // Current screen width + + bool extfifo_on; // True when we're using the extended fifo. + u8 mclk_save[3]; + + struct uc_ovl_vinfo v1; // Video overlay V1 + + bool deinterlace; + int field; + + CoreSurface *surface; + + CoreSurfaceBufferLock *lock; +} UcOverlayData; + + +// Video engine - mapping functions (uc_ovl_hwmap.c) + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini); +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount); +u32 uc_ovl_map_qwpitch(int falign, DFBSurfacePixelFormat format, int sw); +u32 uc_ovl_map_format(DFBSurfacePixelFormat format); +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, int* ox, int* oy); +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int x, int y, int w, int h, int pitch, int field, + u32* y_start, u32* u_start, u32* v_start); +u32 uc_ovl_map_alpha(int opacity); +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo); +u32 uc_ovl_map_fifo(u8 depth, u8 pre_thr, u8 thr); +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2); + +// Video engine - setting functions (uc_ovl_hwset.c) + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth); +void uc_ovl_vcmd_wait(volatile u8* vio); +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock); +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj); + +#endif // __UC_OVERLAY_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c new file mode 100755 index 0000000..890b9bc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwmap.c @@ -0,0 +1,560 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include <direct/messages.h> + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" +#include <math.h> + +/** + * Map hw settings for vertical scaling. + * + * @param sh source height + * @param dh destination height + * @param zoom will hold vertical setting of zoom register. + * @param mini will hold vertical setting of mini register. + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomHeight() + */ + +bool uc_ovl_map_vzoom(int sh, int dh, u32* zoom, u32* mini) +{ + u32 sh1, tmp, d; + bool zoom_ok = true; + + if (sh == dh) { // No zoom + // Do nothing + } + else if (sh < dh) { // Zoom in + + tmp = (sh * 0x0400) / dh; + zoom_ok = !(tmp > 0x3ff); + + *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + else { // sw > dh - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sh1 = sh; + for (d = 1; d < 5; d++) { + sh1 >>= 1; + if (sh1 <= dh) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + *mini |= ((d<<1)-1) << 16; // <= {1,3,5,7} << 16 + + // Add scaling + + if (sh1 < dh) { + tmp = (sh1 * 0x400) / dh; + *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + } + + return zoom_ok; +} + + +/** + * Map hw settings for horizontal scaling. + * + * @param sw source width + * @param dw destination width + * + * @param zoom will hold horizontal setting of zoom register. + * @param mini will hold horizontal setting of mini register. + * @param falign will hold fetch aligment + * @param dcount will hold display count + * + * @returns true if successful. + * false if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() + */ +bool uc_ovl_map_hzoom(int sw, int dw, u32* zoom, u32* mini, + u32* falign, u32* dcount) +{ + u32 tmp, sw1, d; + int md; // Minify-divider + bool zoom_ok = true; + + md = 1; + *falign = 0; + + if (sw == dw) { // No zoom + // Do nothing + } + else if (sw < dw) { // Zoom in + + tmp = (sw * 0x0800) / dw; + zoom_ok = !(tmp > 0x7ff); + + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + *mini |= V1_X_INTERPOLY; + } + else { // sw > dw - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sw1 = sw; + for (d = 1; d < 5; d++) { + sw1 >>= 1; + if (sw1 <= dw) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = false; + } + + md = 1 << d; // <= {2,4,8,16} + *falign = ((md<<1)-1) & 0xf; // <= {3,7,15,15} + *mini |= V1_X_INTERPOLY; + *mini |= ((d<<1)-1) << 24; // <= {1,3,5,7} << 24 + + // Add scaling + + if (sw1 < dw) { + //CLE bug + //tmp = sw1*0x0800 / dw; + tmp = (sw1 - 2) * 0x0800 / dw; + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + } + } + + *dcount = sw - md; + + return zoom_ok; +} + + +/** + * @param falign fetch alignment + * @param format overlay pixel format + * @param sw source width + * + * @returns qword pitch register setting + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() + * @note Only call after uc_ovl_map_hzoom() + */ +u32 uc_ovl_map_qwpitch(int falign, DFBSurfacePixelFormat format, int sw) +{ + int fetch = 0; + + switch (format) { + case DSPF_YV12: + fetch = ALIGN_TO(sw, 32) >> 4; + break; + case DSPF_I420: + fetch = (ALIGN_TO(sw, 16) >> 4) + 1; + break; + case DSPF_UYVY: + case DSPF_YUY2: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case DSPF_RGB32: + case DSPF_ARGB: + fetch = (ALIGN_TO(sw << 2, 16) >> 4) + 1; + break; + default: + D_BUG("Unexpected pixelformat!"); + break; + } + + if (fetch < 4) fetch = 4; + + // Note: Unsure if alignment is needed or is in the way. + fetch = ALIGN_TO(fetch, falign + 1); + return fetch << 20; // V12_QWORD_PER_LINE +} + + +/** + * Map pixel format. + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() + */ +u32 uc_ovl_map_format(DFBSurfacePixelFormat format) +{ + switch (format) { + case DSPF_YV12: + case DSPF_I420: + return V1_COLORSPACE_SIGN | V1_YUV420; + case DSPF_UYVY: + case DSPF_YUY2: + return V1_COLORSPACE_SIGN | V1_YUV422; + case DSPF_ARGB1555: + return V1_RGB15; + case DSPF_RGB16: + return V1_RGB16; + case DSPF_RGB32: + case DSPF_ARGB: + return V1_RGB32; + default : + D_BUG("Unexpected pixelformat!"); + return V1_YUV422; + } +} + + +/** + * Map overlay window. + * + * @param scrw screen width (eg. 800) + * @param scrh screen height (eg. 600) + * @param win destination window + * @param sw source surface width + * @param sh source surface height + * + * @param win_start will hold window start register setting + * @param win_end will hold window end register setting + * + * @parm ox will hold new leftmost coordinate in source surface + * @parm oy will hold new topmost coordinate in source surface + */ +void uc_ovl_map_window(int scrw, int scrh, DFBRectangle* win, int sw, int sh, + u32* win_start, u32* win_end, int* ox, int* oy) +{ + int x1, y1, x2, y2; + int x,y,dw,dh; // These help making the code readable... + + *ox = 0; + *oy = 0; + *win_start = 0; + *win_end = 0; + + x = win->x; + y = win->y; + dw = win->w; + dh = win->h; + + // For testing the clipping + //scrw -= 100; + //scrh -= 100; + + // Handle invisible case. + if ((x > scrw) || (y > scrh) || (x+dw < 0) || (y+dh < 0)) return; + + // Vertical clipping + + if ((y >= 0) && (y+dh < scrh)) { + // No clipping + y1 = y; + y2 = y+dh-1; + } + else if ((y < 0) && (y+dh < scrh)) { + // Top clip + y1 = 0; + y2 = y+dh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + } + else if ((y >= 0) && (y+dh >= scrh)) { + // Bottom clip + y1 = y; + y2 = scrh-1; + } + else { // if (y < 0) && (y+dh >= scrh) + // Top and bottom clip + y1 = 0; + y2 = scrh-1; + *oy = (int) (((float) (sh * -y)) / ((float) dh) + 0.5); + } + + // Horizontal clipping + + if ((x >= 0) && (x+dw < scrw)) { + // No clipping + x1 = x; + x2 = x+dw-1; + } + else if ((x < 0) && (x+dw < scrw)) { + // Left clip + x1 = 0; + x2 = x+dw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + } + else if ((x >= 0) && (x+dw >= scrw)) { + // Right clip + x1 = x; + x2 = scrw-1; + } + else { // if (x < 0) && (x+dw >= scrw) + // Left and right clip + x1 = 0; + x2 = scrw-1; + *ox = (int) (((float) (sw * -x)) / ((float) dw) + 0.5); + } + + *win_start = (x1 << 16) | y1; + *win_end = (x2 << 16) | y2; + + // For testing the clipping + //*win_start = ((x1+50) << 16) | (y1+50); + //*win_end = ((x2+50) << 16) | (y2+50); +} + + +/** + * Map overlay buffer address. + * + * @param format pixel format + * @param buf Framebuffer address of surface (0 = start of framebuffer) + * @param ox leftmost pixel to show (used when clipping, else set to zero) + * @param oy topmost pixel to show (used when clipping, else set to zero) + * @param w total surface width (does *not* depend on the x parameter) + * @param h total surface height (does *not* depend on the y parameter) + * @param pitch source surface pitch (bytes per pixel) + * + * @param y_start will hold start address of Y(UV) or RGB buffer + * @param u_start will hold start address of Cb buffer (planar modes only) + * @param v_start will hold start address of Cr buffer (planar modes only) + * + * @note Derived from VIA's V4L driver. See ddover.c, + * DDOver_GetSrcStartAddress() and DDOVer_GetYCbCrStartAddress() + */ +void uc_ovl_map_buffer(DFBSurfacePixelFormat format, u32 buf, + int ox, int oy, int sw, int sh, int sp, int field, + u32* y_start, u32* u_start, u32* v_start) +{ + int swap_cb_cr = 0; + + u32 tmp; + u32 y_offset, uv_offset = 0; + + switch (format) { + + case DSPF_YUY2: + case DSPF_UYVY: + y_offset = ((oy * sp) + ((ox << 1) & ~15)); + break; + + case DSPF_YV12: + swap_cb_cr = 1; + case DSPF_I420: + y_offset = ((((oy & ~3) * sp) + ox) & ~31) ; + if (oy > 0) + uv_offset = (((((oy & ~3) >> 1) * sp) + ox) & ~31) >> 1; + else + uv_offset = y_offset >> 1; + break; + + case DSPF_ARGB1555: + case DSPF_RGB16: + y_offset = (oy * sp) + ((ox * 16) >> 3); + break; + + case DSPF_RGB32: + case DSPF_ARGB: + y_offset = (oy * sp) + ((ox * 32) >> 3); + break; + + default: + y_offset = 0; + uv_offset = 0; + D_BUG("Unexpected pixelformat!"); + } + + if (field) { + y_offset += sp; + uv_offset += sp >> 1; + } + + *y_start = buf + y_offset; + + if (u_start && v_start) { + *u_start = buf + sp * sh + uv_offset; + *v_start = buf + sp * sh + sp * (sh >> 2) + uv_offset; + + if (swap_cb_cr) { + tmp = *u_start; + *u_start = *v_start; + *v_start = tmp; + } + } +} + + +/** + * Map alpha mode and opacity. + * + * @param opacity Alpha opacity: 0 = transparent, 255 = opaque. + * -1 = Use alpha from underlying graphics. + * + * @returns alpha control register setting. + * + * @note: Unfortunately, if using alpha from underlying graphics, + * the video is opaque if alpha = 255 and transparent if = 0. + * The inverse would have made more sense ... + * + * @note: The hardware supports a separate alpha plane as well, + * but it is not implemented here. + * + * @note: Derived from ddmpeg.c, VIAAlphaWin() + */ + +u32 uc_ovl_map_alpha(int opacity) +{ + u32 ctrl = 0x00080000; // Not sure what this number is, supposedly + // it is the "expire number divided by 4". + + if (opacity > 255) opacity = 255; + + if (opacity < 0) { + ctrl |= ALPHA_WIN_BLENDING_GRAPHIC; + } + else { + opacity = opacity >> 4; // Throw away bits 0 - 3 + ctrl |= (opacity << 12) | ALPHA_WIN_BLENDING_CONSTANT; + } + + return ctrl; // V_ALPHA_CONTROL +} + +/** + * Calculate V1 control and fifo-control register values + * @param format pixel format + * @param sw source width + * @param hwrev CLE266 hardware revision + * @param extfifo_on set this true if the extended FIFO is enabled + * @param control will hold value for V1_CONTROL + * @param fifo will hold value for V1_FIFO_CONTROL + */ +void uc_ovl_map_v1_control(DFBSurfacePixelFormat format, int sw, + int hwrev, bool extfifo_on, + u32* control, u32* fifo) +{ + *control = V1_BOB_ENABLE | V1_ENABLE | uc_ovl_map_format(format); + + if (hwrev == 0x10) { + *control |= V1_EXPIRE_NUM_F; + } + else { + if (extfifo_on) { + *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; + } + else { + *control |= V1_EXPIRE_NUM; + } + } + + if ((format == DSPF_YV12) || (format == DSPF_I420)) { + //Minified video will be skewed without this workaround. + if (sw <= 80) { //Fetch count <= 5 + *fifo = UC_MAP_V1_FIFO_CONTROL(16,0,0); + } + else { + if (hwrev == 0x10) + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(16,12,8); + } + } + else { + if (hwrev == 0x10) { + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); // Default rev 0x10 + } + else { + if (extfifo_on) + *fifo = UC_MAP_V1_FIFO_CONTROL(48,40,40); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(32,29,16); // Default + } + } +} + +/** uc_ovl_map_adjustment() helper - clamp x to [lo, hi] */ +static float clamp(float x, float lo, float hi) +{ + return (x < lo) ? lo : ((x > hi) ? hi : x); /* 2 nested if's. */ +} + +/** + * uc_ovl_map_adjustment() helper - format x for the hardware. + * + * @param x The value to format. + * @param ndec Number of binary decimals. + * @param sbit sign bit position. + * =0: use two's complement representation + * >0: use a sign bit + positive value. + * @param mask Bitmask + * @param shift Position in hardware register. + */ +static int fmt(float x, int ndec, int sbit, u32 mask, int shift) +{ + int y = (x * (1 << ndec)); + if (sbit && (y < 0)) y = -y | (1 << sbit); + return (((u32) y) & mask) << shift; +} + +/** + * Map color adjustment to CLE266 hardware. + * + * @param adj DirectFB color adjustment. All fields are assumed valid. + * @param a1 Will hold value for V1_ColorSpaceReg_1 + * @param a2 Will hold value for V1_ColorSpaceReg_2 + */ +void uc_ovl_map_adjustment(DFBColorAdjustment* adj, u32* a1, u32* a2) +{ + float con, sat, bri, hue; + float c, s; + float A, B1, C1, D, B2, C2, B3, C3; + + // Map contrast to [0, 2.0] (preferred: [0, 1.66]), default: 1.0. + con = (float) adj->contrast / 32768.0; + // Map saturation to [0, 2.0], default: 1.0. + sat = (float) adj->saturation / 32768.0; + // Map brightness to [-121, 125], (preferred: [-94, 125.1]), default: 3.97. + bri = (float) (adj->brightness - 31696) / 270.48; + // Map hue to [-pi, pi], default is 0.0. + hue = (float) (adj->hue - 32768) / 10430.378; + // Note: The limits are estimates that need testing. + + // Map parameters to hw registers. + + s = sin(hue) * con * sat; + c = cos(hue) * con * sat; + + A = clamp(1.164*con, 0, 1.9375); + B1 = clamp(-1.596*s, -0.75, 0.75); + C1 = clamp(1.596*c, 1, 2.875); + B2 = clamp( (0.813*s - 0.391*c), 0, -0.875); + C2 = clamp(-(0.813*c + 0.391*s), 0, -1.875); + B3 = clamp(2.018*c, 0, 3.75); + C3 = clamp(2.018*s, -1.25, 1.25); + D = clamp(1.164*(bri-16), -128, 127); + + *a1 = + fmt(A, 4, 0, 0x1f, 24) | fmt(B1, 2, 2, 0x07, 18) | + fmt(C1, 3, 0, 0x1f, 9) | fmt(D, 0, 0, 0xff, 0); + + *a2 = + fmt(B2, 3, 4, 0x7, 25) | fmt(C2, 3, 4, 0xf, 17) | + fmt(B3, 2, 0, 0xf, 10) | fmt(C3, 2, 3, 0xf, 2); +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c new file mode 100755 index 0000000..e8ba755 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_ovl_hwset.c @@ -0,0 +1,266 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include <sys/io.h> + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +#include <direct/messages.h> + +#include <core/system.h> + +/** + * Set up the extended video FIFO. + * @note It will be turned on if ucovl->scrwidth > 1024. + */ + +void uc_ovl_setup_fifo(UcOverlayData* ucovl, int scrwidth) +{ + u8* mclk_save = ucovl->mclk_save; + + if (!iopl(3)) { + if (scrwidth <= 1024) { // Disable + if (ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + outb(0x16, 0x3c4); outb(mclk_save[0], 0x3c5); + outb(0x17, 0x3c4); outb(mclk_save[1], 0x3c5); + outb(0x18, 0x3c4); outb(mclk_save[2], 0x3c5); + ucovl->extfifo_on = false; + } + } + else { // Enable + if (!ucovl->extfifo_on) { + + dfb_layer_wait_vsync(dfb_layer_at(DLID_PRIMARY)); + + // Save current setting + outb(0x16, 0x3c4); mclk_save[0] = inb(0x3c5); + outb(0x17, 0x3c4); mclk_save[1] = inb(0x3c5); + outb(0x18, 0x3c4); mclk_save[2] = inb(0x3c5); + // Enable extended FIFO + outb(0x17, 0x3c4); outb(0x2f, 0x3c5); + outb(0x16, 0x3c4); outb((mclk_save[0] & 0xf0) | 0x14, 0x3c5); + outb(0x18, 0x3c4); outb(0x56, 0x3c5); + ucovl->extfifo_on = true; + } + } + } + else { + printf("cle266: could set io perissons\n"); + } + ucovl->scrwidth = scrwidth; +} + +void uc_ovl_vcmd_wait(volatile u8* vio) +{ + while ((VIDEO_IN(vio, V_COMPOSE_MODE) + & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); +} + +/** + * Update the video overlay. + * + * @param action = UC_OVL_CHANGE: update everything + * = UC_OVL_FLIP: only flip to the front surface buffer. + * @param surface source surface + * + * @note: Derived from ddmpeg.c, Upd_Video() + */ + +DFBResult uc_ovl_update(UcDriverData* ucdrv, + UcOverlayData* ucovl, + int action, + CoreSurface* surface, + CoreSurfaceBufferLock* lock) +{ + int sw, sh, sp, sfmt; // Source width, height, pitch and format + int dx, dy; // Destination position + int dw, dh; // Destination width and height + VideoMode *videomode; + DFBRectangle scr; // Screen size + + bool write_buffers = false; + bool write_settings = false; + + volatile u8* vio = ucdrv->hwregs; + + u32 win_start, win_end; // Overlay register settings + u32 zoom, mini; + u32 dcount, falign, qwpitch; + u32 y_start, u_start, v_start; + u32 v_ctrl, fifo_ctrl; + + int offset = lock->offset; + + + if (!ucovl->v1.isenabled) return DFB_OK; + + qwpitch = 0; + + // Get screen size + videomode = dfb_system_current_mode(); + scr.w = videomode ? videomode->xres : 720; + scr.h = videomode ? videomode->yres : 576; + scr.x = 0; + scr.y = 0; + + if (ucovl->scrwidth != scr.w) { + // FIXME: fix uc_ovl_setup_fifo() + // uc_ovl_setup_fifo(ucovl, scr.w); + action |= UC_OVL_CHANGE; + } + + D_ASSERT(surface); + + sw = surface->config.size.w; + sh = surface->config.size.h; + sp = lock->pitch; + sfmt = surface->config.format; + + if (ucovl->deinterlace) { + /*if (ucovl->field) + offset += sp;*/ + + sh /= 2; + //sp *= 2; + } + + if (action & UC_OVL_CHANGE) { + + if ((sw > 4096) || (sh > 4096) || + (sw < 32) || (sh < 1) || (sp > 0x1fff)) { + D_DEBUG("Layer surface size is out of bounds."); + return DFB_INVAREA; + } + + dx = ucovl->v1.win.x; + dy = ucovl->v1.win.y; + dw = ucovl->v1.win.w; + dh = ucovl->v1.win.h; + + // Get image format, FIFO size, etc. + + uc_ovl_map_v1_control(sfmt, sw, ucovl->hwrev, ucovl->extfifo_on, + &v_ctrl, &fifo_ctrl); + + if (ucovl->deinterlace) { + v_ctrl |= /*V1_BOB_ENABLE |*/ V1_FRAME_BASE; + } + + // Get layer window. + // The parts that fall outside the screen are clipped. + + uc_ovl_map_window(scr.w, scr.h, &(ucovl->v1.win), sw, sh, + &win_start, &win_end, &ucovl->v1.ox, &ucovl->v1.oy); + + // Get scaling and data-fetch parameters + + // Note: the *_map_?zoom() functions return false if the scaling + // is out of bounds. We don't act on it for now, because it only + // makes the display look strange. + + zoom = 0; + mini = 0; + + uc_ovl_map_vzoom(sh, dh, &zoom, &mini); + uc_ovl_map_hzoom(sw, dw, &zoom, &mini, &falign, &dcount); + qwpitch = uc_ovl_map_qwpitch(falign, sfmt, sw); + + write_settings = true; + } + + if (action & (UC_OVL_FIELD | UC_OVL_FLIP | UC_OVL_CHANGE)) { + int field = 0; + // Update the buffer pointers + + if (ucovl->deinterlace) { + field = ucovl->field; + } + + uc_ovl_map_buffer(sfmt, offset, + ucovl->v1.ox, ucovl->v1.oy, sw, surface->config.size.h, sp, 0/*field*/, &y_start, + &u_start, &v_start); + + if (field) { + y_start |= 0x08000000; + } + + write_buffers = true; + } + + // Write to the hardware + +/* if (write_settings || write_buffers) + uc_ovl_vcmd_wait(vio);*/ + + if (write_settings) { + + VIDEO_OUT(vio, V1_CONTROL, v_ctrl); + VIDEO_OUT(vio, V_FIFO_CONTROL, fifo_ctrl); + + VIDEO_OUT(vio, V1_WIN_START_Y, win_start); + VIDEO_OUT(vio, V1_WIN_END_Y, win_end); + + VIDEO_OUT(vio, V1_SOURCE_HEIGHT, (sh << 16) | dcount); + VIDEO_OUT(vio, V12_QWORD_PER_LINE, qwpitch); + VIDEO_OUT(vio, V1_STRIDE, sp | ((sp >> 1) << 16)); + + VIDEO_OUT(vio, V1_MINI_CONTROL, mini); + VIDEO_OUT(vio, V1_ZOOM_CONTROL, zoom); + } + + if (write_buffers) { + + VIDEO_OUT(vio, V1_STARTADDR_0, y_start); + VIDEO_OUT(vio, V1_STARTADDR_CB0, u_start); + VIDEO_OUT(vio, V1_STARTADDR_CR0, v_start); + } + + if (write_settings || write_buffers) { + VIDEO_OUT(vio, V_COMPOSE_MODE, V1_COMMAND_FIRE); + } + + return DFB_OK; +} + +DFBResult uc_ovl_set_adjustment(CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj) +{ + UcOverlayData* ucovl = (UcOverlayData*) layer_data; + UcDriverData* ucdrv = (UcDriverData*) driver_data; + DFBColorAdjustment* ucadj; + u32 a1, a2; + + ucadj = &ucovl->v1.adj; + + if (adj->flags & DCAF_BRIGHTNESS) + ucadj->brightness = adj->brightness; + if (adj->flags & DCAF_CONTRAST) + ucadj->contrast = adj->contrast; + if (adj->flags & DCAF_HUE) + ucadj->hue = adj->hue; + if (adj->flags & DCAF_SATURATION) + ucadj->saturation = adj->saturation; + + uc_ovl_map_adjustment(ucadj, &a1, &a2); + + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_1, a1); + VIDEO_OUT(ucdrv->hwregs, V1_ColorSpaceReg_2, a2); + + return DFB_OK; +} diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_primary.c b/Source/DirectFB/gfxdrivers/cle266/uc_primary.c new file mode 100755 index 0000000..d0d0fe9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_primary.c @@ -0,0 +1,176 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <string.h> +#include <stdio.h> + +#include <directfb.h> + +#include <core/layers.h> + +#include <misc/conf.h> + +#include "unichrome.h" +#include "uc_overlay.h" +#include "vidregs.h" +#include "mmio.h" + +/* primary layer hooks */ + +#define OSD_OPTIONS (DLOP_ALPHACHANNEL | DLOP_SRC_COLORKEY | DLOP_OPACITY) + +DisplayLayerFuncs ucOldPrimaryFuncs; +void *ucOldPrimaryDriverData; + +static DFBResult +osdInitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + DFBResult ret; + + /* call the original initialization function first */ + ret = ucOldPrimaryFuncs.InitLayer( layer, + ucOldPrimaryDriverData, + layer_data, description, + config, adjustment ); + if (ret) + return ret; + + /* set name */ + snprintf(description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "VIA CLE266 Graphics"); + + /* add support for options */ + config->flags |= DLCONF_OPTIONS; + + config->pixelformat = dfb_config->mode.format ? + dfb_config->mode.format : DSPF_ARGB; + config->options = DLOP_ALPHACHANNEL; + + /* add some capabilities */ + description->caps |= DLCAPS_ALPHACHANNEL | + DLCAPS_OPACITY | DLCAPS_SRC_COLORKEY; + + return DFB_OK; +} + +static DFBResult +osdTestRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + DFBResult ret; + CoreLayerRegionConfigFlags fail = 0; + DFBDisplayLayerOptions options = config->options; + + /* remove options before calling the original function */ + config->options = DLOP_NONE; + + /* call the original function */ + ret = ucOldPrimaryFuncs.TestRegion( layer, ucOldPrimaryDriverData, + layer_data, config, &fail ); + + /* check options if specified */ + if (options) { + /* any unsupported option wanted? */ + if (options & ~OSD_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* opacity and alpha channel cannot be used at once */ + if ((options & (DLOP_OPACITY | DLOP_ALPHACHANNEL)) == + (DLOP_OPACITY | DLOP_ALPHACHANNEL)) + { + fail |= CLRCF_OPTIONS; + } + } + + /* restore options */ + config->options = options; + + if (failed) + *failed = fail; + + if (fail) + return DFB_UNSUPPORTED; + + return ret; +} + +static DFBResult +osdSetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + DFBResult ret; + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + /* call the original function */ + ret = ucOldPrimaryFuncs.SetRegion( layer, ucOldPrimaryDriverData, + layer_data, region_data, + config, updated, surface, + palette, lock ); + if (ret) + return ret; + + uc_ovl_vcmd_wait(ucdrv->hwregs); + + /* select pixel based or global alpha */ + + if (config->options & DLOP_ALPHACHANNEL) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(-1)); + else if (config->options & DLOP_OPACITY) + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(config->opacity)); + else + VIDEO_OUT(ucdrv->hwregs, V_ALPHA_CONTROL, uc_ovl_map_alpha(0xff)); + + VIDEO_OUT(ucdrv->hwregs, V_COMPOSE_MODE, V1_COMMAND_FIRE); + + return DFB_OK; +} + +DisplayLayerFuncs ucPrimaryFuncs = { + .InitLayer = osdInitLayer, + + .TestRegion = osdTestRegion, + .SetRegion = osdSetRegion, +}; + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_state.c b/Source/DirectFB/gfxdrivers/cle266/uc_state.c new file mode 100755 index 0000000..7ac74e9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_state.c @@ -0,0 +1,269 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#include <config.h> + +#include <gfx/convert.h> +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_hw.h" + +enum uc_state_type { + UC_TYPE_UNSUPPORTED, + UC_TYPE_2D, + UC_TYPE_3D +}; + +/// GPU selecting functions -------------------------------------------------- + +static inline bool +uc_has_dst_format( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + return true; + + default: + break; + } + + return false; +} + +static inline bool +uc_has_src_format_3d( DFBSurfacePixelFormat format ) +{ + switch (format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_A8: + case DSPF_LUT8: + return true; + + default: + break; + } + + return false; +} + +static inline enum uc_state_type +uc_select_drawtype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_2D) && + !(accel & DFXL_FILLTRIANGLE)) + return UC_TYPE_2D; + + if (!(state->drawingflags & ~UC_DRAWING_FLAGS_3D)) + return UC_TYPE_3D; + + return UC_TYPE_UNSUPPORTED; +} + +static inline enum uc_state_type +uc_select_blittype( CardState* state, + DFBAccelerationMask accel ) +{ + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_2D)) { + if ((state->source->config.format == state->destination->config.format) && + !((state->blittingflags & DSBLIT_SRC_COLORKEY) && + (state->blittingflags & DSBLIT_DST_COLORKEY)) && + !(accel & (DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES))) + return UC_TYPE_2D; + } + + if (!(state->blittingflags & ~UC_BLITTING_FLAGS_3D)) { + if (uc_has_src_format_3d( state->source->config.format )) + return UC_TYPE_3D; + } + + return UC_TYPE_UNSUPPORTED; +} + +// DirectFB interfacing functions -------------------------------------------- + +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel) +{ + /* Check destination format. */ + if (!uc_has_dst_format( state->destination->config.format )) + return; + + if (DFB_DRAWING_FUNCTION(accel)) { + /* Check drawing parameters. */ + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + state->accel |= UC_DRAWING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + state->accel |= UC_DRAWING_FUNCTIONS_3D; + break; + default: + return; + } + } + else { + /* Check blitting parameters. */ + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + state->accel |= UC_BLITTING_FUNCTIONS_2D; + break; + case UC_TYPE_3D: + state->accel |= UC_BLITTING_FUNCTIONS_3D; + break; + default: + return; + } + } +} + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel) +{ + UcDriverData *ucdrv = (UcDriverData*) drv; + UcDeviceData *ucdev = (UcDeviceData*) dev; + struct uc_fifo *fifo = ucdrv->fifo; + + u32 rop3d = HC_HROP_P; + u32 regEnable = HC_HenCW_MASK | HC_HenAW_MASK; + + StateModificationFlags modified = state->mod_hw; + + // Check modified states and update hw + + if (modified & SMF_SOURCE) + UC_INVALIDATE( uc_source2d ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SOURCE)) + UC_INVALIDATE( uc_source3d | uc_texenv ); + + if (modified & (SMF_BLITTING_FLAGS | SMF_SRC_COLORKEY | SMF_DST_COLORKEY)) + UC_INVALIDATE( uc_colorkey2d ); + + if (modified & (SMF_COLOR | SMF_DESTINATION | SMF_DRAWING_FLAGS)) + UC_INVALIDATE( uc_color2d ); + + if (modified & (SMF_SRC_BLEND | SMF_DST_BLEND)) + UC_INVALIDATE( uc_blending_fn ); + + + if (modified & SMF_COLOR) + ucdev->color3d = PIXEL_ARGB( state->color.a, state->color.r, + state->color.g, state->color.b ); + + if (modified & SMF_DRAWING_FLAGS) { + if (state->drawingflags & DSDRAW_XOR) { + ucdev->draw_rop3d = HC_HROP_DPx; + ucdev->draw_rop2d = VIA_ROP_DPx; + } + else { + ucdev->draw_rop3d = HC_HROP_P; + ucdev->draw_rop2d = VIA_ROP_P; + } + } + + ucdev->bflags = state->blittingflags; + + if (modified & SMF_DESTINATION) + uc_set_destination(ucdrv, ucdev, state); + + if (modified & SMF_CLIP) + uc_set_clip(ucdrv, ucdev, state); + + + // Select GPU and check remaining states + + if (DFB_DRAWING_FUNCTION(accel)) { + + switch (uc_select_drawtype(state, accel)) { + case UC_TYPE_2D: + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + + uc_set_color_2d(ucdrv, ucdev, state); + + state->set = UC_DRAWING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->FillRectangle = uc_fill_rectangle_3d; + funcs->DrawRectangle = uc_draw_rectangle_3d; + funcs->DrawLine = uc_draw_line_3d; + + if (state->drawingflags & DSDRAW_BLEND) { + uc_set_blending_fn(ucdrv, ucdev, state); + regEnable |= HC_HenABL_MASK; + } + + rop3d = ucdev->draw_rop3d; + + state->set = UC_DRAWING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported drawing function!"); + break; + } + } + else { // DFB_BLITTING_FUNCTION(accel) + switch (uc_select_blittype(state, accel)) { + case UC_TYPE_2D: + uc_set_source_2d(ucdrv, ucdev, state); + funcs->Blit = uc_blit; + + uc_set_colorkey_2d(ucdrv, ucdev, state); + state->set = UC_BLITTING_FUNCTIONS_2D; + break; + + case UC_TYPE_3D: + funcs->Blit = uc_blit_3d; + uc_set_source_3d(ucdrv, ucdev, state); + uc_set_texenv(ucdrv, ucdev, state); + uc_set_blending_fn(ucdrv, ucdev, state); + + regEnable |= HC_HenTXMP_MASK | HC_HenTXCH_MASK | HC_HenTXPP_MASK | HC_HenDT_MASK; + + if (state->blittingflags & (DSBLIT_BLEND_ALPHACHANNEL | + DSBLIT_BLEND_COLORALPHA)) + regEnable |= HC_HenABL_MASK; + + state->set = UC_BLITTING_FUNCTIONS_3D; + break; + + case UC_TYPE_UNSUPPORTED: + D_BUG("Unsupported drawing function!"); + break; + } + } + +#ifdef UC_ENABLE_3D + UC_FIFO_PREPARE( fifo, 6 ); + UC_FIFO_ADD_HDR( fifo, HC_ParaType_NotTex << 16 ); + + /* Don't know what this does. DRI code always clears it. */ + UC_FIFO_ADD_3D ( fifo, HC_SubA_HPixGC, 0 ); + + UC_FIFO_ADD_3D ( fifo, HC_SubA_HEnable, regEnable ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HFBBMSKL, 0xffffff ); + UC_FIFO_ADD_3D ( fifo, HC_SubA_HROP, rop3d | 0xff ); +#endif + + UC_FIFO_CHECK(fifo); + + state->mod_hw = 0; +} + diff --git a/Source/DirectFB/gfxdrivers/cle266/uc_state.h b/Source/DirectFB/gfxdrivers/cle266/uc_state.h new file mode 100755 index 0000000..a3e7484 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/uc_state.h @@ -0,0 +1,68 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UC_STATE__ +#define __UC_STATE__ + +#include <directfb.h> +#include <core/state.h> +#include <core/gfxcard.h> + +void uc_set_state(void *drv, void *dev, GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel); +void uc_check_state(void *drv, void *dev, + CardState *state, DFBAccelerationMask accel); + + + +/* +struct uc_hw_misc +{ + // These control clipping... + + u32 regHClipTB; + u32 regHClipLR; + u32 regHFPClipTL; + u32 regHFPClipBL; + u32 regHFPClipLL; + u32 regHFPClipRL; + u32 regHFPClipTBH; + u32 regHFPClipLRH; + + // Other functions + + u32 regHLP; // Line stipple pattern + u32 regHLPRF; // Line stipple factor + u32 regHSolidCL; // --- Don't know. Unused in DRI. + u32 regHPixGC; // Don't know. Is kept cleared in DRI. + //u32 regHSPXYOS; // Polygon stipple x and y offsets. Unused here. + u32 regHVertexCNT; // --- Don't know. Unused in DRI. + + u8 ps_xos; // Polygon stipple x-offset. => regHSPXYOS + u8 ps_yos; // Polygon stipple y-offset. => regHSPXYOS + u32 ps_pat[32]; // Polygon stipple pattern buffer. + // These are not registers... +}; + + +/// Stencil control. + +struct uc_hw_stencil +{ + //u32 regHSBBasL; // These aren't in regs3d.h, but they should exist... + //u32 regHSBBasH; + //u32 regHSBFM; + + u32 regHSTREF; // Stencil reference value and plane mask + u32 regHSTMD; // Stencil test function and fail operation and + // zpass/zfail operations. +}; +*/ + +#endif // __UC_STATE__ diff --git a/Source/DirectFB/gfxdrivers/cle266/unichrome.c b/Source/DirectFB/gfxdrivers/cle266/unichrome.c new file mode 100755 index 0000000..7dbb8bc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/unichrome.c @@ -0,0 +1,548 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + + +/* + +EPIA-M benchmarks (df_dok) + + SW v0.0.1 v0.1.0 v0.2.0 v0.3 + +Anti-aliased Text 98.97 - - - 280.80 KChars/sec +Anti-aliased Text (blend) 28.85 - - - 280.61 KChars/sec +Fill Rectangles 25.21 443.46 437.05 432.39 435.60 Mpixel/sec +Fill Rectangles (blend) 5.54 - 130.12 128.42 127.82 MPixel/sec +Fill Triangles 24.84 173.44 129.76 127.86 128.63 MPixel/sec +Fill Triangles (blend) 5.46 - 129.81 127.86 128.67 MPixel/sec +Draw Rectangles 11.82 58.98 59.07 52.48 55.10 KRects/sec +Draw Rectangles (blend) 1.98 - 32.13 22.76 23.50 KRects/sec +Draw Lines 42.67 283.81 292.33 193.87 203.20 KLines/sec +Draw Lines (blend) 8.54 - 142.62 101.23 102.80 KLines/sec +Blit 21.48 - 117.38 114.26 114.41 MPixel/sec +Blit colorkeyed 22.54 - 117.34 114.26 114.41 MPixel/sec +Blit w/ format conversion 16.22 - - 103.41 103.00 MPixel/sec +Blit from 32bit (blend) 4.19 - - 87.72 87.32 MPixel/sec +Blit from 8bit palette 11.02 - - 110.13 113.37 MPixel/sec +Blit from 8bit pal. (blend) 3.78 - - 110.20 113.40 MPixel/sec +Stretch Blit 23.19 - - 99.53 99.32 MPixel/sec +Stretch Blit colorkeyed 25.04 - - 5.00 38.00 MPixel/sec + + +Comparing M9000 and M10000 + +v0.2.0 M9000 M10000 + +Anti-aliased Text - - KChars/sec +Anti-aliased Text (blend) - - KChars/sec +Fill Rectangles 401.82 432.39 Mpixel/sec +Fill Rectangles (blend) 129.05 128.42 MPixel/sec +Fill Triangles 128.46 127.86 MPixel/sec +Fill Triangles (blend) 128.46 127.86 MPixel/sec +Draw Rectangles 55.51 52.48 KRects/sec +Draw Rectangles (blend) 26.90 22.76 KRects/sec +Draw Lines 225.00 193.87 KLines/sec +Draw Lines (blend) 121.29 101.23 KLines/sec +Blit 112.36 114.26 MPixel/sec +Blit colorkeyed 112.28 114.26 MPixel/sec +Blit w/ format conversion 103.92 103.41 MPixel/sec +Blit from 32bit (blend) 87.89 87.72 MPixel/sec +Blit from 8bit palette 110.56 110.13 MPixel/sec +Blit from 8bit pal. (blend) 110.56 110.20 MPixel/sec +Stretch Blit 108.67 99.53 MPixel/sec +Stretch Blit colorkeyed 4.79 5.00 MPixel/sec + + +v0.0.1 and v0.1.0 are tested on an EPIA-M9000, +later versions on an EPIA-M10000. + +*/ + +// DirectFB headers + +#include <config.h> + +#include <directfb.h> + +#include <fusion/shmalloc.h> + +#include <direct/messages.h> + +#include <core/coretypes.h> +#include <core/core.h> +#include <core/gfxcard.h> +#include <core/graphics_driver.h> +#include <core/system.h> +#include <core/screens.h> + +#include <fbdev/fb.h> + +// System headers + +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <stdlib.h> +#include <unistd.h> +#include <stdio.h> + +#include <string.h> + +// Driver headers + +#include "unichrome.h" +#include "uc_state.h" +#include "uc_accel.h" +#include "uc_fifo.h" +#include "mmio.h" + +#ifndef FB_ACCEL_VIA_UNICHROME +#define FB_ACCEL_VIA_UNICHROME 77 +#endif + +extern DisplayLayerFuncs ucOverlayFuncs; +extern DisplayLayerFuncs ucPrimaryFuncs; + +extern DisplayLayerFuncs ucOldPrimaryFuncs; +extern void *ucOldPrimaryDriverData; + +DFB_GRAPHICS_DRIVER(cle266) + +//---------- + + +/** + * Dump beginning of virtual queue. + * Use it to check that the VQ actually is in use. */ +#if 0 +static void uc_dump_vq(UcDeviceData *ucdev) +{ + int i; + u8* vq; + + if (!ucdev->vq_start) return; + vq = dfb_system_video_memory_virtual(ucdev->vq_start); + + for (i = 0; i < 128; i++) { + printf("%02x ", *(vq+i)); + if ((i+1) % 16 == 0) printf("\n"); + } +} +#endif + +/** Allocate memory for the virtual queue. */ + +static DFBResult uc_alloc_vq(CoreGraphicsDevice *device, UcDeviceData *ucdev) +{ + if (ucdev->vq_start) return DFB_OK; + + ucdev->vq_size = 256*1024; // 256kb + ucdev->vq_start = dfb_gfxcard_reserve_memory( device, ucdev->vq_size ); + + if (!ucdev->vq_start) + return DFB_INIT; + + ucdev->vq_end = ucdev->vq_start + ucdev->vq_size - 1; + + // Debug: clear buffer + memset((void *) dfb_system_video_memory_virtual(ucdev->vq_start), + 0xcc, ucdev->vq_size); + + // uc_dump_vq(ucdev); + + return DFB_OK; +} + +/** + * Initialize the hardware. + * @param enable enable VQ if true (else disable it.) + */ + +static DFBResult uc_init_2d_engine(CoreGraphicsDevice *device, UcDeviceData *ucdev, UcDriverData *ucdrv, bool enable) +{ + DFBResult result = DFB_OK; + volatile u8* hwregs = ucdrv->hwregs; + + // Init 2D engine registers to reset 2D engine + + VIA_OUT(hwregs, 0x04, 0x0); + VIA_OUT(hwregs, 0x08, 0x0); + VIA_OUT(hwregs, 0x0c, 0x0); + VIA_OUT(hwregs, 0x10, 0x0); + VIA_OUT(hwregs, 0x14, 0x0); + VIA_OUT(hwregs, 0x18, 0x0); + VIA_OUT(hwregs, 0x1c, 0x0); + VIA_OUT(hwregs, 0x20, 0x0); + VIA_OUT(hwregs, 0x24, 0x0); + VIA_OUT(hwregs, 0x28, 0x0); + VIA_OUT(hwregs, 0x2c, 0x0); + VIA_OUT(hwregs, 0x30, 0x0); + VIA_OUT(hwregs, 0x34, 0x0); + VIA_OUT(hwregs, 0x38, 0x0); + VIA_OUT(hwregs, 0x3c, 0x0); + VIA_OUT(hwregs, 0x40, 0x0); + + // Init AGP and VQ registers + + VIA_OUT(hwregs, 0x43c, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00000000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + VIA_OUT(hwregs, 0x440, 0x7D000000); + + VIA_OUT(hwregs, 0x43c, 0xfe020000); + VIA_OUT(hwregs, 0x440, 0x00000000); + + if (enable) { + result = uc_alloc_vq(device,ucdev); + enable = (result == DFB_OK); + } + + if (enable) { // Enable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x080003fe); + VIA_OUT(hwregs, 0x440, 0x0a00027c); + VIA_OUT(hwregs, 0x440, 0x0b000260); + VIA_OUT(hwregs, 0x440, 0x0c000274); + VIA_OUT(hwregs, 0x440, 0x0d000264); + VIA_OUT(hwregs, 0x440, 0x0e000000); + VIA_OUT(hwregs, 0x440, 0x0f000020); + VIA_OUT(hwregs, 0x440, 0x1000027e); + VIA_OUT(hwregs, 0x440, 0x110002fe); + VIA_OUT(hwregs, 0x440, 0x200f0060); + + VIA_OUT(hwregs, 0x440, 0x00000006); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + + VIA_OUT(hwregs, 0x440, 0x52000000 | + ((ucdev->vq_start & 0xFF000000) >> 24) | + ((ucdev->vq_end & 0xFF000000) >> 16)); + VIA_OUT(hwregs, 0x440, 0x50000000 | (ucdev->vq_start & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x51000000 | (ucdev->vq_end & 0xFFFFFF)); + VIA_OUT(hwregs, 0x440, 0x53000000 | (ucdev->vq_size >> 3)); + } + else { // Disable VQ + + VIA_OUT(hwregs, 0x43c, 0x00fe0000); + VIA_OUT(hwregs, 0x440, 0x00000004); + VIA_OUT(hwregs, 0x440, 0x40008c0f); + VIA_OUT(hwregs, 0x440, 0x44000000); + VIA_OUT(hwregs, 0x440, 0x45080c04); + VIA_OUT(hwregs, 0x440, 0x46800408); + } + + return result; +} + +static void uc_init_3d_engine(volatile u8* hwregs, int hwrev, bool init_all) +{ + u32 i; + + if (init_all) { + + // Clear NotTex registers (?) + + VIA_OUT(hwregs, 0x43C, 0x00010000); + for (i = 0; i <= 0x7d; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear texture unit 0 (?) + + VIA_OUT(hwregs, 0x43C, 0x00020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear texture unit 1 (?) + + VIA_OUT(hwregs, 0x43C, 0x01020000); + for (i = 0; i <= 0x94; i++) + VIA_OUT(hwregs, 0x440, i << 24); + VIA_OUT(hwregs, 0x440, 0x82400000); + + // Clear general texture settings (?) + + VIA_OUT(hwregs, 0x43C, 0xfe020000); + for (i = 0; i <= 0x03; i++) + VIA_OUT(hwregs, 0x440, i << 24); + + // Clear palette settings (?) + + VIA_OUT(hwregs, 0x43C, 0x00030000); + for (i = 0; i <= 0xff; i++) + VIA_OUT(hwregs, 0x440, 0); + + VIA_OUT(hwregs, 0x43C, 0x00100000); + VIA_OUT(hwregs, 0x440, 0x00333004); + VIA_OUT(hwregs, 0x440, 0x10000002); + VIA_OUT(hwregs, 0x440, 0x60000000); + VIA_OUT(hwregs, 0x440, 0x61000000); + VIA_OUT(hwregs, 0x440, 0x62000000); + VIA_OUT(hwregs, 0x440, 0x63000000); + VIA_OUT(hwregs, 0x440, 0x64000000); + + VIA_OUT(hwregs, 0x43C, 0x00fe0000); + + if (hwrev >= 3) + VIA_OUT(hwregs, 0x440,0x40008c0f); + else + VIA_OUT(hwregs, 0x440,0x4000800f); + + VIA_OUT(hwregs, 0x440,0x44000000); + VIA_OUT(hwregs, 0x440,0x45080C04); + VIA_OUT(hwregs, 0x440,0x46800408); + VIA_OUT(hwregs, 0x440,0x50000000); + VIA_OUT(hwregs, 0x440,0x51000000); + VIA_OUT(hwregs, 0x440,0x52000000); + VIA_OUT(hwregs, 0x440,0x53000000); + + } + + VIA_OUT(hwregs, 0x43C,0x00fe0000); + VIA_OUT(hwregs, 0x440,0x08000001); + VIA_OUT(hwregs, 0x440,0x0A000183); + VIA_OUT(hwregs, 0x440,0x0B00019F); + VIA_OUT(hwregs, 0x440,0x0C00018B); + VIA_OUT(hwregs, 0x440,0x0D00019B); + VIA_OUT(hwregs, 0x440,0x0E000000); + VIA_OUT(hwregs, 0x440,0x0F000000); + VIA_OUT(hwregs, 0x440,0x10000000); + VIA_OUT(hwregs, 0x440,0x11000000); + VIA_OUT(hwregs, 0x440,0x20000000); +} + +/** */ + +static void uc_after_set_var(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + + VGA_OUT8(ucdrv->hwregs, 0x3c4, 0x1a); + // Clear bit 6 in extended VGA register 0x1a to prevent system lockup. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) & 0xbf); + // Set bit 2, it might make a difference. + VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) | 0x4); +} + +/** Wait until the engine is idle. */ + +static DFBResult uc_engine_sync(void* drv, void* dev) +{ + UcDriverData* ucdrv = (UcDriverData*) drv; + UcDeviceData* ucdev = (UcDeviceData*) dev; + + int loop = 0; + +/* printf("Entering uc_engine_sync(), status is 0x%08x\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS)); +*/ + + while ((VIA_IN(ucdrv->hwregs, VIA_REG_STATUS) & 0xfffeffff) != 0x00020000) { + if (++loop > MAXLOOP) { + D_ERROR("DirectFB/VIA: Timeout waiting for idle engine!\n"); + break; + } + } + + /* printf("Leaving uc_engine_sync(), status is 0x%08x, " + "waiting for %d (0x%x) cycles.\n", + VIA_IN(ucdrv->hwregs, VIA_REG_STATUS), loop, loop); + */ + + ucdev->idle_waitcycles += loop; + ucdev->must_wait = 0; + + return DFB_OK; +} + + +// DirectFB interfacing functions -------------------------------------------- + +static int driver_probe(CoreGraphicsDevice *device) +{ + struct stat s; + + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_VIA_UNICHROME: + return 1; + } + + return stat(UNICHROME_DEVICE, &s) + 1; +} + +static void driver_get_info(CoreGraphicsDevice* device, + GraphicsDriverInfo* info) +{ + // Fill in driver info structure. + + snprintf(info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "VIA UniChrome Driver"); + + snprintf(info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "-"); + + snprintf(info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org"); + + snprintf(info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL"); + + info->version.major = 0; + info->version.minor = 3; + + info->driver_data_size = sizeof (UcDriverData); + info->device_data_size = sizeof (UcDeviceData); +} + + +static DFBResult driver_init_driver(CoreGraphicsDevice* device, + GraphicsDeviceFuncs* funcs, + void* driver_data, + void* device_data, + CoreDFB *core) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + ucdrv->file = -1; + ucdrv->pool = dfb_core_shmpool( core ); + + ucdrv->hwregs = dfb_gfxcard_map_mmio( device, 0, 0 ); + if (!ucdrv->hwregs) { + int fd; + + fd = open(UNICHROME_DEVICE, O_RDWR | O_SYNC, 0); + if (fd < 0) { + D_ERROR("Could not access %s. " + "Is the cle266vgaio module installed?\n", UNICHROME_DEVICE); + return DFB_IO; + } + + ucdrv->file = fd; + + ucdrv->hwregs = mmap(NULL, 0x1000000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (ucdrv->hwregs == MAP_FAILED) + return DFB_IO; + } + + /* FIXME: this belongs to device_data! */ + ucdrv->fifo = uc_fifo_create(ucdrv->pool, UC_FIFO_SIZE); + if (!ucdrv->fifo) + return D_OOSHM(); + + uc_after_set_var(driver_data, device_data); + + ucdrv->hwrev = 3; // FIXME: Get the real hardware revision number!!! + + // Driver specific initialization + + funcs->CheckState = uc_check_state; + funcs->SetState = uc_set_state; + funcs->EngineSync = uc_engine_sync; + funcs->EmitCommands = uc_emit_commands; + funcs->FlushTextureCache = uc_flush_texture_cache; + funcs->AfterSetVar = uc_after_set_var; + + funcs->FillRectangle = uc_fill_rectangle; + funcs->DrawRectangle = uc_draw_rectangle; + funcs->DrawLine = uc_draw_line; + funcs->FillTriangle = uc_fill_triangle; + funcs->Blit = uc_blit; + funcs->StretchBlit = uc_stretch_blit; + funcs->TextureTriangles = uc_texture_triangles; + + + /* install primary layer hooks */ + if ( getenv("DFB_CLE266_UNDERLAY")) + dfb_layers_hook_primary( device, driver_data, &ucPrimaryFuncs, + &ucOldPrimaryFuncs, &ucOldPrimaryDriverData ); + + dfb_layers_register( dfb_screens_at(DSCID_PRIMARY), + driver_data, &ucOverlayFuncs ); + + return DFB_OK; +} + +static DFBResult driver_init_device(CoreGraphicsDevice* device, + GraphicsDeviceInfo* device_info, + void* driver_data, + void* device_data) +{ + UcDriverData *ucdrv = (UcDriverData*) driver_data; + UcDeviceData *ucdev = (UcDeviceData*) device_data; + + //printf("Entering %s\n", __PRETTY_FUNCTION__); + + snprintf(device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, "UniChrome"); + snprintf(device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "VIA/S3G"); + + device_info->caps.flags = CCF_CLIPPING; + device_info->caps.accel = + UC_DRAWING_FUNCTIONS_2D | UC_DRAWING_FUNCTIONS_3D | + UC_BLITTING_FUNCTIONS_2D | UC_BLITTING_FUNCTIONS_3D; + + device_info->caps.drawing = UC_DRAWING_FLAGS_2D | UC_DRAWING_FLAGS_3D; + device_info->caps.blitting = UC_BLITTING_FLAGS_2D | UC_BLITTING_FLAGS_3D; + + device_info->limits.surface_byteoffset_alignment = 32; + device_info->limits.surface_pixelpitch_alignment = 32; + + ucdev->pitch = 0; + ucdev->draw_rop2d = VIA_ROP_P; + ucdev->draw_rop3d = HC_HROP_P; + ucdev->color = 0; + ucdev->bflags = 0; + + ucdev->must_wait = 0; + ucdev->cmd_waitcycles = 0; + ucdev->idle_waitcycles = 0; + + uc_init_2d_engine(device, ucdev, ucdrv, false); // VQ disabled - can't make it work. + uc_init_3d_engine(ucdrv->hwregs, ucdrv->hwrev, 1); + + return DFB_OK; +} + +static void driver_close_device(CoreGraphicsDevice *device, + void *driver_data, void *device_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + UcDeviceData* ucdev = (UcDeviceData*) device_data; + + // uc_dump_vq(ucdev); + + uc_engine_sync(driver_data, device_data); + uc_init_2d_engine(device, ucdev, ucdrv, false); +} + +static void driver_close_driver(CoreGraphicsDevice* device, void* driver_data) +{ + UcDriverData* ucdrv = (UcDriverData*) driver_data; + + if (ucdrv->fifo) + uc_fifo_destroy( ucdrv->pool, ucdrv->fifo ); + + if (ucdrv->file != -1) + close( ucdrv->file ); +} diff --git a/Source/DirectFB/gfxdrivers/cle266/unichrome.h b/Source/DirectFB/gfxdrivers/cle266/unichrome.h new file mode 100755 index 0000000..801216b --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/unichrome.h @@ -0,0 +1,140 @@ +/* + Copyright (c) 2003 Andreas Robinson, All rights reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. +*/ + +#ifndef __UNICHROME_H__ +#define __UNICHROME_H__ + +#include <core/coredefs.h> +#include <core/surface.h> +#include <core/layers.h> +#include <core/layer_control.h> + +#include <directfb.h> + +#define UNICHROME_DEVICE "/dev/cle266vgaio" +#define UC_FIFO_SIZE 4096 + +/** If defined - the driver will use the 3D engine. */ +#define UC_ENABLE_3D +//#undef UC_ENABLE_3D + + +/** Register settings for the current source surface. (3D) */ +struct uc_hw_texture { + DFBSurfaceBlittingFlags bltflags; + + u32 l2w; //width, rounded up to nearest 2^m, eg 600 => 1024 + u32 l2h; //height, rounded up, e.g 480 => 512 + u32 we; //width exponent, i.e m in the number 2^m + u32 he; //height exponent + + u32 format; // HW pixel format + + // 3d engine texture environment, texture unit 0 + + // Used for the DSBLIT_BLEND_ALPHACHANNEL, DSBLIT_BLEND_COLORALPHA + // and DSBLIT_COLORIZE blitting flags. + + u32 regHTXnTB; + u32 regHTXnMPMD; + + u32 regHTXnTBLCsat_0; + u32 regHTXnTBLCop_0; + u32 regHTXnTBLMPfog_0; + u32 regHTXnTBLAsat_0; + u32 regHTXnTBLRCb_0; + u32 regHTXnTBLRAa_0; + u32 regHTXnTBLRFog_0; +}; + + +/** Hardware source-destination blending registers. */ +struct uc_hw_alpha { +/* + u32 regHABBasL; // Alpha buffer, low 24 bits. + u32 regHABBasH; // Alpha buffer, high 8 bits. + u32 regHABFM; // Alpha pixel format, memory type and pitch. + u32 regHATMD; // Alpha test function and reference value. + + // Blending function +*/ + u32 regHABLCsat; + u32 regHABLCop; + u32 regHABLAsat; + u32 regHABLAop; + u32 regHABLRCa; + u32 regHABLRFCa; + u32 regHABLRCbias; + u32 regHABLRCb; + u32 regHABLRFCb; + u32 regHABLRAa; + u32 regHABLRAb; +}; + +typedef enum { + uc_source2d = 0x00000001, + uc_source3d = 0x00000002, + uc_texenv = 0x00000004, + uc_blending_fn = 0x00000008, + uc_color2d = 0x00000010, + uc_colorkey2d = 0x00000020 +} UcStateBits; + +#define UC_VALIDATE(b) (ucdev->valid |= (b)) +#define UC_INVALIDATE(b) (ucdev->valid &= ~(b)) +#define UC_IS_VALID(b) (ucdev->valid & (b)) + +typedef struct _UcDeviceData { + + /* State validation */ + UcStateBits valid; + + /* Current state settings */ + u32 pitch; // combined src/dst pitch (2D) + u32 color; // 2D fill color + u32 color3d; // color for 3D operations + u32 draw_rop2d; // logical drawing ROP (2D) + u32 draw_rop3d; // logical drawing ROP (3D) + + DFBSurfaceBlittingFlags bflags; // blitting flags + DFBRegion clip; // clipping region + + DFBSurfacePixelFormat dst_format; // destination pixel format + int dst_offset; // destination buffer byte offset + int dst_pitch; // destination buffer byte pitch + + int field; // source field + + /* Hardware settings */ + struct uc_hw_alpha hwalpha; // alpha blending setting (3D) + struct uc_hw_texture hwtex; // hardware settings for blitting (3D) + + + /// Set directly after a 2D/3D engine command is sent. + int must_wait; + unsigned int cmd_waitcycles; + unsigned int idle_waitcycles; + + u32 vq_start; // VQ related + u32 vq_size; + u32 vq_end; + +} UcDeviceData; + + +typedef struct _UcDriverData { + int file; // File handle to mmapped IO region. + int hwrev; // Hardware revision + volatile void* hwregs; // Hardware register base + struct uc_fifo* fifo; // Data FIFO. + FusionSHMPoolShared *pool; +} UcDriverData; + + +#endif // __UNICHROME_H__ diff --git a/Source/DirectFB/gfxdrivers/cle266/vidregs.h b/Source/DirectFB/gfxdrivers/cle266/vidregs.h new file mode 100755 index 0000000..5331fc1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/cle266/vidregs.h @@ -0,0 +1,498 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIDREGS_H__ +#define __VIDREGS_H__ + + +/* Video registers */ +#define V_FLAGS 0x00 +#define V_CAP_STATUS 0x04 +#define V_FLIP_STATUS 0x04 +#define V_ALPHA_WIN_START 0x08 +#define V_ALPHA_WIN_END 0x0C +#define V_ALPHA_CONTROL 0x10 +#define V_CRT_STARTADDR 0x14 +#define V_CRT_STARTADDR_2 0x18 +#define V_ALPHA_STRIDE 0x1C +#define V_COLOR_KEY 0x20 +#define V_ALPHA_STARTADDR 0x24 +#define V_CHROMAKEY_LOW 0x28 +#define V_CHROMAKEY_HIGH 0x2C + +#define V1_CONTROL 0x30 +#define V12_QWORD_PER_LINE 0x34 +#define V1_STARTADDR_1 0x38 +#define V1_STARTADDR_Y1 V1_STARTADDR_1 /* added by Kevin 3/30/2002 */ +#define V1_STRIDE 0x3C +#define V1_WIN_START_Y 0x40 +#define V1_WIN_START_X 0x42 +#define V1_WIN_END_Y 0x44 +#define V1_WIN_END_X 0x46 +#define V1_STARTADDR_2 0x48 +#define V1_STARTADDR_Y2 V1_STARTADDR_2 /* added by Kevin 3/30/2002 */ +#define V1_ZOOM_CONTROL 0x4C +#define V1_MINI_CONTROL 0x50 +#define V1_STARTADDR_0 0x54 +#define V1_STARTADDR_Y0 V1_STARTADDR_0 /* added by Kevin 3/30/2002 */ +#define V_FIFO_CONTROL 0x58 +#define V1_STARTADDR_3 0x5C +#define V1_STARTADDR_Y3 V1_STARTADDR_3 /* added by Kevin 3/30/2002 */ + +#define HI_CONTROL 0x60 +#define SND_COLOR_KEY 0x64 +#define ALPHA_V3_PREFIFO_CONTROL 0x68 +#define V1_SOURCE_HEIGHT 0x6C +#define HI_TRANSPARENT_COLOR 0x70 +#define V_DISPLAY_TEMP 0x74 /* No use */ +#define ALPHA_V3_FIFO_CONTROL 0x78 +#define V3_SOURCE_WIDTH 0x7C +#define V3_COLOR_KEY 0x80 +#define V1_ColorSpaceReg_1 0x84 +#define V1_ColorSpaceReg_2 0x88 +#define V1_STARTADDR_CB0 0x8C +#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ +#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ +#define V_COMPOSE_MODE 0x98 + +#define V3_STARTADDR_2 0x9C +#define V3_CONTROL 0xA0 +#define V3_STARTADDR_0 0xA4 +#define V3_STARTADDR_1 0xA8 +#define V3_STRIDE 0xAC +#define V3_WIN_START_Y 0xB0 +#define V3_WIN_START_X 0xB2 +#define V3_WIN_END_Y 0xB4 +#define V3_WIN_END_X 0xB6 +#define V3_ALPHA_QWORD_PER_LINE 0xB8 +#define V3_ZOOM_CONTROL 0xBC +#define V3_MINI_CONTROL 0xC0 +#define V3_ColorSpaceReg_1 0xC4 +#define V3_ColorSpaceReg_2 0xC8 +#define V3_DISPLAY_TEMP 0xCC /* No use */ + +#define V1_STARTADDR_CB1 0xE4 +#define V1_STARTADDR_CB2 0xE8 +#define V1_STARTADDR_CB3 0xEC +#define V1_STARTADDR_CR0 0xF0 +#define V1_STARTADDR_CR1 0xF4 +#define V1_STARTADDR_CR2 0xF8 +#define V1_STARTADDR_CR3 0xFC + +/* Video Capture Engine Registers - port 1 */ +#define CAP0_MASKS 0x100 +#define CAP1_MASKS 0x104 +#define CAP0_CONTROL 0x110 +#define CAP0_H_RANGE 0x114 +#define CAP0_V_RANGE 0x118 +#define CAP0_SCAL_CONTROL 0x11C +#define CAP0_VBI_H_RANGE 0x120 +#define CAP0_VBI_V_RANGE 0x124 +#define CAP0_VBI_STARTADDR 0x128 +#define CAP0_VBI_STRIDE 0x12C +#define CAP0_ANCIL_COUNT 0x130 +#define CAP0_MAXCOUNT 0x134 +#define CAP0_VBIMAX_COUNT 0x138 +#define CAP0_DATA_COUNT 0x13C +#define CAP0_FB_STARTADDR0 0x140 +#define CAP0_FB_STARTADDR1 0x144 +#define CAP0_FB_STARTADDR2 0x148 +#define CAP0_STRIDE 0x150 + +/* Video Capture Engine Registers - port 2 */ +#define CAP1_CONTROL 0x154 +#define CAP1_SCAL_CONTROL 0x160 +#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ +#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ +#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ +#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ +#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ +#define CAP1_MAXCOUNT 0x178 +#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ +#define CAP1_DATA_COUNT 0x180 +#define CAP1_FB_STARTADDR0 0x184 +#define CAP1_FB_STARTADDR1 0x188 +#define CAP1_STRIDE 0x18C + +/* SUBPICTURE Registers */ +#define SUBP_CONTROL_STRIDE 0x1C0 +#define SUBP_STARTADDR 0x1C4 +#define RAM_TABLE_CONTROL 0x1C8 +#define RAM_TABLE_READ 0x1CC + +/* HQV Registers */ +#define HQV_CONTROL 0x1D0 +#define HQV_SRC_STARTADDR_Y 0x1D4 +#define HQV_SRC_STARTADDR_U 0x1D8 +#define HQV_SRC_STARTADDR_V 0x1DC +#define HQV_SRC_FETCH_LINE 0x1E0 +#define HQV_FILTER_CONTROL 0x1E4 +#define HQV_MINIFY_CONTROL 0x1E8 +#define HQV_DST_STARTADDR0 0x1EC +#define HQV_DST_STARTADDR1 0x1F0 +#define HQV_DST_STARTADDR2 0x1FC +#define HQV_DST_STRIDE 0x1F4 +#define HQV_SRC_STRIDE 0x1F8 + + + +/* Video command definitions */ + +/* #define V_ALPHA_CONTROL - 0x210 */ +#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 +#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 +#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 +#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 +#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 +#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 +#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 +#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 +#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 + +/* V_CHROMAKEY_LOW - 0x228 */ +#define V_CHROMAKEY_V3 0x80000000 + +/* V1_CONTROL - 0x230 */ +#define V1_ENABLE 0x00000001 +#define V1_FULL_SCREEN 0x00000002 +#define V1_YUV422 0x00000000 +#define V1_RGB32 0x00000004 +#define V1_RGB15 0x00000008 +#define V1_RGB16 0x0000000C +#define V1_YUV420 0x00000010 +#define V1_COLORSPACE_SIGN 0x00000080 +#define V1_SRC_IS_FRAME_PIC 0x00000200 +#define V1_SRC_IS_FIELD_PIC 0x00000000 +#define V1_BOB_ENABLE 0x00400000 +#define V1_FIELD_BASE 0x00000000 +#define V1_FRAME_BASE 0x01000000 +#define V1_SWAP_SW 0x00000000 +#define V1_SWAP_HW_HQV 0x02000000 +#define V1_SWAP_HW_CAPTURE 0x04000000 +#define V1_SWAP_HW_MC 0x06000000 +/* #define V1_DOUBLE_BUFFERS 0x00000000 */ +/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ +#define V1_EXPIRE_NUM 0x00050000 +#define V1_EXPIRE_NUM_A 0x000a0000 +#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ +#define V1_FIFO_EXTENDED 0x00200000 +#define V1_ON_CRT 0x00000000 +#define V1_ON_SND_DISPLAY 0x80000000 +#define V1_FIFO_32V1_32V2 0x00000000 +#define V1_FIFO_48V1_32V2 0x00200000 + +/* V12_QWORD_PER_LINE - 0x234 */ +#define V1_FETCH_COUNT 0x3ff00000 +#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f +#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ + +/* V1_STRIDE */ +#define V1_STRIDE_YMASK 0x00001fff +#define V1_STRIDE_UVMASK 0x1ff00000 + +/* V1_ZOOM_CONTROL - 0x24C */ +#define V1_X_ZOOM_ENABLE 0x80000000 +#define V1_Y_ZOOM_ENABLE 0x00008000 + +/* V1_MINI_CONTROL - 0x250 */ +#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V1_X_DIV_2 0x01000000 +#define V1_X_DIV_4 0x03000000 +#define V1_X_DIV_8 0x05000000 +#define V1_X_DIV_16 0x07000000 +#define V1_Y_DIV_2 0x00010000 +#define V1_Y_DIV_4 0x00030000 +#define V1_Y_DIV_8 0x00050000 +#define V1_Y_DIV_16 0x00070000 + +/* V1_STARTADDR0 - 0x254 */ +#define SW_FLIP_ODD 0x08000000 + +/* V_FIFO_CONTROL - 0x258 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V1_FIFO_DEPTH12 0x0000000B +#define V1_FIFO_DEPTH16 0x0000000F +#define V1_FIFO_DEPTH32 0x0000001F +#define V1_FIFO_DEPTH48 0x0000002F +#define V1_FIFO_DEPTH64 0x0000003F +#define V1_FIFO_THRESHOLD6 0x00000600 +#define V1_FIFO_THRESHOLD8 0x00000800 +#define V1_FIFO_THRESHOLD12 0x00000C00 +#define V1_FIFO_THRESHOLD16 0x00001000 +#define V1_FIFO_THRESHOLD24 0x00001800 +#define V1_FIFO_THRESHOLD32 0x00002000 +#define V1_FIFO_THRESHOLD40 0x00002800 +#define V1_FIFO_THRESHOLD48 0x00003000 +#define V1_FIFO_THRESHOLD56 0x00003800 +#define V1_FIFO_THRESHOLD61 0x00003D00 +#define V1_FIFO_PRETHRESHOLD10 0x0A000000 +#define V1_FIFO_PRETHRESHOLD12 0x0C000000 +#define V1_FIFO_PRETHRESHOLD29 0x1d000000 +#define V1_FIFO_PRETHRESHOLD40 0x28000000 +#define V1_FIFO_PRETHRESHOLD44 0x2c000000 +#define V1_FIFO_PRETHRESHOLD56 0x38000000 +#define V1_FIFO_PRETHRESHOLD61 0x3D000000 + +/* ALPHA_V3_FIFO_CONTROL - 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. + * with extension reg 230 bit 21 disable + * 8 level FIFO for ALPHA + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V3_FIFO_DEPTH16 0x0000000F +#define V3_FIFO_DEPTH24 0x00000017 +#define V3_FIFO_DEPTH32 0x0000001F +#define V3_FIFO_DEPTH48 0x0000002F +#define V3_FIFO_DEPTH64 0x0000003F +#define V3_FIFO_THRESHOLD8 0x00000800 +#define V3_FIFO_THRESHOLD12 0x00000C00 +#define V3_FIFO_THRESHOLD16 0x00001000 +#define V3_FIFO_THRESHOLD24 0x00001800 +#define V3_FIFO_THRESHOLD32 0x00002000 +#define V3_FIFO_THRESHOLD40 0x00002800 +#define V3_FIFO_THRESHOLD48 0x00003000 +#define V3_FIFO_THRESHOLD61 0x00003D00 +#define V3_FIFO_PRETHRESHOLD10 0x0000000A +#define V3_FIFO_PRETHRESHOLD12 0x0000000C +#define V3_FIFO_PRETHRESHOLD29 0x0000001d +#define V3_FIFO_PRETHRESHOLD40 0x00000028 +#define V3_FIFO_PRETHRESHOLD44 0x0000002c +#define V3_FIFO_PRETHRESHOLD56 0x00000038 +#define V3_FIFO_PRETHRESHOLD61 0x0000003D +#define V3_FIFO_MASK 0x0000007F +#define ALPHA_FIFO_DEPTH8 0x00070000 +#define ALPHA_FIFO_THRESHOLD4 0x04000000 +#define ALPHA_FIFO_MASK 0xffff0000 +#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 + +/* IA2 */ +#define ColorSpaceValue_1 0x140020f2 +#define ColorSpaceValue_2 0x0a0a2c00 + +#define ColorSpaceValue_1_3123C0 0x13000DED +#define ColorSpaceValue_2_3123C0 0x13171000 + +/* For TV setting */ +#define ColorSpaceValue_1TV 0x140020f2 +#define ColorSpaceValue_2TV 0x0a0a2c00 + +/* V_COMPOSE_MODE - 0x298 */ +#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ +#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ +#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ +#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ +#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ +#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ +#define COMPOSE_V1_TOP 0x00000000 +#define COMPOSE_V3_TOP 0x00100000 +#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ +#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ +#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ +#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ +#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ +#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ +#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 + +/* V3_ZOOM_CONTROL - 0x2bc */ +#define V3_X_ZOOM_ENABLE 0x80000000 +#define V3_Y_ZOOM_ENABLE 0x00008000 + +/* V3_MINI_CONTROL - 0x2c0 */ +#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V3_X_DIV_2 0x01000000 +#define V3_X_DIV_4 0x03000000 +#define V3_X_DIV_8 0x05000000 +#define V3_X_DIV_16 0x07000000 +#define V3_Y_DIV_2 0x00010000 +#define V3_Y_DIV_4 0x00030000 +#define V3_Y_DIV_8 0x00050000 +#define V3_Y_DIV_16 0x00070000 + +/* SUBP_CONTROL_STRIDE - 0x3c0 */ +#define SUBP_HQV_ENABLE 0x00010000 +#define SUBP_IA44 0x00020000 +#define SUBP_AI44 0x00000000 +#define SUBP_STRIDE_MASK 0x00001fff +#define SUBP_CONTROL_MASK 0x00070000 + +/* RAM_TABLE_CONTROL - 0x3c8 */ +#define RAM_TABLE_RGB_ENABLE 0x00000007 + +/* CAPTURE0_CONTROL - 0x310 */ +#define C0_ENABLE 0x00000001 +#define BUFFER_2_MODE 0x00000000 +#define BUFFER_3_MODE 0x00000004 +#define BUFFER_4_MODE 0x00000006 +#define SWAP_YUYV 0x00000000 +#define SWAP_UYVY 0x00000100 +#define SWAP_YVYU 0x00000200 +#define SWAP_VYUY 0x00000300 +#define IN_601_8 0x00000000 +#define IN_656_8 0x00000010 +#define IN_601_16 0x00000020 +#define IN_656_16 0x00000030 +#define DEINTER_ODD 0x00000000 +#define DEINTER_EVEN 0x00001000 +#define DEINTER_ODD_EVEN 0x00002000 +#define DEINTER_FRAME 0x00003000 +#define VIP_1 0x00000000 +#define VIP_2 0x00000400 +#define H_FILTER_2 0x00010000 +#define H_FILTER_4 0x00020000 +#define H_FILTER_8_1331 0x00030000 +#define H_FILTER_8_12221 0x00040000 +#define VIP_ENABLE 0x00000008 +#define EN_FIELD_SIG 0x00000800 +#define VREF_INVERT 0x00100000 +#define FIELD_INPUT_INVERSE 0x00400000 +#define FIELD_INVERSE 0x40000000 + +#define C1_H_MINI_EN 0x00000800 +#define C0_H_MINI_EN 0x00000800 +#define C1_V_MINI_EN 0x04000000 +#define C0_V_MINI_EN 0x04000000 +#define C1_H_MINI_2 0x00000400 + +/* CAPTURE1_CONTROL - 0x354 */ +#define C1_ENABLE 0x00000001 + +/* V3_CONTROL - 0x2A0 */ +#define V3_ENABLE 0x00000001 +#define V3_FULL_SCREEN 0x00000002 +#define V3_YUV422 0x00000000 +#define V3_RGB32 0x00000004 +#define V3_RGB15 0x00000008 +#define V3_RGB16 0x0000000C +#define V3_COLORSPACE_SIGN 0x00000080 +#define V3_EXPIRE_NUM 0x00040000 +#define V3_EXPIRE_NUM_F 0x000f0000 +#define V3_BOB_ENABLE 0x00400000 +#define V3_FIELD_BASE 0x00000000 +#define V3_FRAME_BASE 0x01000000 +#define V3_SWAP_SW 0x00000000 +#define V3_SWAP_HW_HQV 0x02000000 +#define V3_FLIP_HW_CAPTURE0 0x04000000 +#define V3_FLIP_HW_CAPTURE1 0x06000000 + +/* V3_ALPHA_FETCH_COUNT - 0x2B8 */ +#define V3_FETCH_COUNT 0x3ff00000 +#define ALPHA_FETCH_COUNT 0x000003ff + +/* HQV_CONTROL - 0x3D0 */ +#define HQV_RGB32 0x00000000 +#define HQV_RGB16 0x20000000 +#define HQV_RGB15 0x30000000 +#define HQV_YUV422 0x80000000 +#define HQV_YUV420 0xC0000000 +#define HQV_ENABLE 0x08000000 +#define HQV_SRC_SW 0x00000000 +#define HQV_SRC_MC 0x01000000 +#define HQV_SRC_CAPTURE0 0x02000000 +#define HQV_SRC_CAPTURE1 0x03000000 +#define HQV_FLIP_EVEN 0x00000000 +#define HQV_FLIP_ODD 0x00000020 +#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ +#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ +#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ +#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ +#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ +#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ +#define HQV_IDLE 0x00000008 +#define HQV_FLIP_STATUS 0x00000001 +#define HQV_DOUBLE_BUFF 0x00000000 +#define HQV_TRIPLE_BUFF 0x04000000 +#define HQV_SUBPIC_FLIP 0x00008000 +#define HQV_FIFO_STATUS 0x00001000 + +/* HQV_FILTER_CONTROL - 0x3E4 */ +#define HQV_H_LOWPASS_2TAP 0x00000001 +#define HQV_H_LOWPASS_4TAP 0x00000002 +#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ +#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ +#define HQV_H_HIGH_PASS 0x00000008 +#define HQV_H_LOW_PASS 0x00000000 +#define HQV_V_LOWPASS_2TAP 0x00010000 +#define HQV_V_LOWPASS_4TAP 0x00020000 +#define HQV_V_LOWPASS_8TAP1 0x00030000 +#define HQV_V_LOWPASS_8TAP2 0x00040000 +#define HQV_V_HIGH_PASS 0x00080000 +#define HQV_V_LOW_PASS 0x00000000 +#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 +#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 +#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_H_HIPASS_F1_2TAP 0x00000050 +#define HQV_H_HIPASS_F2_2TAP 0x00000100 +#define HQV_V_HIPASS_F1_2TAP 0x00500000 +#define HQV_V_HIPASS_F2_2TAP 0x01000000 +#define HQV_H_HIPASS_F1_4TAP 0x00000060 +#define HQV_H_HIPASS_F2_4TAP 0x00000200 +#define HQV_V_HIPASS_F1_4TAP 0x00600000 +#define HQV_V_HIPASS_F2_4TAP 0x02000000 +#define HQV_H_HIPASS_F1_8TAP 0x00000080 +#define HQV_H_HIPASS_F2_8TAP 0x00000400 +#define HQV_V_HIPASS_F1_8TAP 0x00800000 +#define HQV_V_HIPASS_F2_8TAP 0x04000000 +/* IA2 NEW */ +#define HQV_V_FILTER2 0x00080000 +#define HQV_H_FILTER2 0x00000008 +#define HQV_H_TAP2_11 0x00000041 +#define HQV_H_TAP4_121 0x00000042 +#define HQV_H_TAP4_1111 0x00000401 +#define HQV_H_TAP8_1331 0x00000221 +#define HQV_H_TAP8_12221 0x00000402 +#define HQV_H_TAP16_1991 0x00000159 +#define HQV_H_TAP16_141041 0x0000026A +#define HQV_H_TAP32 0x0000015A +#define HQV_V_TAP2_11 0x00410000 +#define HQV_V_TAP4_121 0x00420000 +#define HQV_V_TAP4_1111 0x04010000 +#define HQV_V_TAP8_1331 0x02210000 +#define HQV_V_TAP8_12221 0x04020000 +#define HQV_V_TAP16_1991 0x01590000 +#define HQV_V_TAP16_141041 0x026A0000 +#define HQV_V_TAP32 0x015A0000 +#define HQV_V_FILTER_DEFAULT 0x00420000 +#define HQV_H_FILTER_DEFAULT 0x00000040 + +/* HQV_MINI_CONTROL - 0x3E8 */ +#define HQV_H_MINIFY_ENABLE 0x00000800 +#define HQV_V_MINIFY_ENABLE 0x08000000 +#define HQV_VDEBLOCK_FILTER 0x80000000 +#define HQV_HDEBLOCK_FILTER 0x00008000 + +#endif // __VIDREGS_H__ |