diff options
Diffstat (limited to 'Source/DirectFB/gfxdrivers/nvidia')
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/Makefile.am | 45 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/Makefile.in | 614 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia.c | 2046 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia.h | 238 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c | 549 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h | 48 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c | 522 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h | 36 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h | 246 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h | 160 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c | 566 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c | 189 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h | 1636 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c | 730 | ||||
| -rwxr-xr-x | Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h | 58 |
15 files changed, 7683 insertions, 0 deletions
diff --git a/Source/DirectFB/gfxdrivers/nvidia/Makefile.am b/Source/DirectFB/gfxdrivers/nvidia/Makefile.am new file mode 100755 index 0000000..8b495e9 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/Makefile.am @@ -0,0 +1,45 @@ +## Makefile.am for DirectFB/src/core/gfxcards/nvidia + +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +nvidia_LTLIBRARIES = libdirectfb_nvidia.la + +if BUILD_STATIC +nvidia_DATA = $(nvidia_LTLIBRARIES:.la=.o) +endif + +nvidiadir = $(MODULEDIR)/gfxdrivers + +libdirectfb_nvidia_la_SOURCES = \ + nvidia.c \ + nvidia_state.c \ + nvidia_2d.c \ + nvidia_3d.c \ + nvidia_primary.c \ + nvidia_overlay.c \ + nvidia.h \ + nvidia_regs.h \ + nvidia_accel.h \ + nvidia_objects.h \ + nvidia_state.h \ + nvidia_2d.h \ + nvidia_3d.h + +libdirectfb_nvidia_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_nvidia_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + + +include $(top_srcdir)/rules/libobject.make diff --git a/Source/DirectFB/gfxdrivers/nvidia/Makefile.in b/Source/DirectFB/gfxdrivers/nvidia/Makefile.in new file mode 100755 index 0000000..472373c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/Makefile.in @@ -0,0 +1,614 @@ +# Makefile.in generated by automake 1.10.1 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + + +VPATH = @srcdir@ +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_HEADER = $(INSTALL_DATA) +transform = $(program_transform_name) +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_triplet = @build@ +host_triplet = @host@ +target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(top_srcdir)/rules/libobject.make +subdir = gfxdrivers/nvidia +ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +am__aclocal_m4_deps = $(top_srcdir)/m4/as-ac-expand.m4 \ + $(top_srcdir)/configure.in +am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ + $(ACLOCAL_M4) +mkinstalldirs = $(install_sh) -d +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; +am__vpath_adj = case $$p in \ + $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ + *) f=$$p;; \ + esac; +am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; +am__installdirs = "$(DESTDIR)$(nvidiadir)" "$(DESTDIR)$(nvidiadir)" +nvidiaLTLIBRARIES_INSTALL = $(INSTALL) +LTLIBRARIES = $(nvidia_LTLIBRARIES) +libdirectfb_nvidia_la_DEPENDENCIES = \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la +am_libdirectfb_nvidia_la_OBJECTS = nvidia.lo nvidia_state.lo \ + nvidia_2d.lo nvidia_3d.lo nvidia_primary.lo nvidia_overlay.lo +libdirectfb_nvidia_la_OBJECTS = $(am_libdirectfb_nvidia_la_OBJECTS) +libdirectfb_nvidia_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(libdirectfb_nvidia_la_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ + --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ + $(LDFLAGS) -o $@ +SOURCES = $(libdirectfb_nvidia_la_SOURCES) +DIST_SOURCES = $(libdirectfb_nvidia_la_SOURCES) +nvidiaDATA_INSTALL = $(INSTALL_DATA) +DATA = $(nvidia_DATA) +ETAGS = etags +CTAGS = ctags +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +ACLOCAL = @ACLOCAL@ +AMTAR = @AMTAR@ +AR = @AR@ +AS = @AS@ +ASFLAGS = @ASFLAGS@ +AUTOCONF = @AUTOCONF@ +AUTOHEADER = @AUTOHEADER@ +AUTOMAKE = @AUTOMAKE@ +AWK = @AWK@ +CC = @CC@ +CCAS = @CCAS@ +CCASDEPMODE = @CCASDEPMODE@ +CCASFLAGS = @CCASFLAGS@ +CCDEPMODE = @CCDEPMODE@ +CFLAGS = @CFLAGS@ +CPP = @CPP@ +CPPFLAGS = @CPPFLAGS@ +CXX = @CXX@ +CXXCPP = @CXXCPP@ +CXXDEPMODE = @CXXDEPMODE@ +CXXFLAGS = @CXXFLAGS@ +CYGPATH_W = @CYGPATH_W@ +DATADIR = @DATADIR@ +DEFS = @DEFS@ +DEPDIR = @DEPDIR@ +DFB_CFLAGS_OMIT_FRAME_POINTER = @DFB_CFLAGS_OMIT_FRAME_POINTER@ +DFB_INTERNAL_CFLAGS = @DFB_INTERNAL_CFLAGS@ +DFB_LDFLAGS = @DFB_LDFLAGS@ +DFB_SMOOTH_SCALING = @DFB_SMOOTH_SCALING@ +DIRECTFB_BINARY_AGE = @DIRECTFB_BINARY_AGE@ +DIRECTFB_CSOURCE = @DIRECTFB_CSOURCE@ +DIRECTFB_INTERFACE_AGE = @DIRECTFB_INTERFACE_AGE@ +DIRECTFB_MAJOR_VERSION = @DIRECTFB_MAJOR_VERSION@ +DIRECTFB_MICRO_VERSION = @DIRECTFB_MICRO_VERSION@ +DIRECTFB_MINOR_VERSION = @DIRECTFB_MINOR_VERSION@ +DIRECTFB_VERSION = @DIRECTFB_VERSION@ +DIRECT_BUILD_DEBUG = @DIRECT_BUILD_DEBUG@ +DIRECT_BUILD_DEBUGS = @DIRECT_BUILD_DEBUGS@ +DIRECT_BUILD_GETTID = @DIRECT_BUILD_GETTID@ +DIRECT_BUILD_NETWORK = @DIRECT_BUILD_NETWORK@ +DIRECT_BUILD_STDBOOL = @DIRECT_BUILD_STDBOOL@ +DIRECT_BUILD_TEXT = @DIRECT_BUILD_TEXT@ +DIRECT_BUILD_TRACE = @DIRECT_BUILD_TRACE@ +DSYMUTIL = @DSYMUTIL@ +DYNLIB = @DYNLIB@ +ECHO = @ECHO@ +ECHO_C = @ECHO_C@ +ECHO_N = @ECHO_N@ +ECHO_T = @ECHO_T@ +EGREP = @EGREP@ +EXEEXT = @EXEEXT@ +F77 = @F77@ +FFLAGS = @FFLAGS@ +FREETYPE_CFLAGS = @FREETYPE_CFLAGS@ +FREETYPE_LIBS = @FREETYPE_LIBS@ +FREETYPE_PROVIDER = @FREETYPE_PROVIDER@ +FUSION_BUILD_KERNEL = @FUSION_BUILD_KERNEL@ +FUSION_BUILD_MULTI = @FUSION_BUILD_MULTI@ +FUSION_MESSAGE_SIZE = @FUSION_MESSAGE_SIZE@ +GIF_PROVIDER = @GIF_PROVIDER@ +GREP = @GREP@ +HAVE_LINUX = @HAVE_LINUX@ +INCLUDEDIR = @INCLUDEDIR@ +INSTALL = @INSTALL@ +INSTALL_DATA = @INSTALL_DATA@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +INTERNALINCLUDEDIR = @INTERNALINCLUDEDIR@ +JPEG_PROVIDER = @JPEG_PROVIDER@ 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+SOPATH = @SOPATH@ +STRIP = @STRIP@ +SYSCONFDIR = @SYSCONFDIR@ +SYSFS_LIBS = @SYSFS_LIBS@ +THREADFLAGS = @THREADFLAGS@ +THREADLIB = @THREADLIB@ +TSLIB_CFLAGS = @TSLIB_CFLAGS@ +TSLIB_LIBS = @TSLIB_LIBS@ +VERSION = @VERSION@ +VNC_CFLAGS = @VNC_CFLAGS@ +VNC_CONFIG = @VNC_CONFIG@ +VNC_LIBS = @VNC_LIBS@ +X11_CFLAGS = @X11_CFLAGS@ +X11_LIBS = @X11_LIBS@ +ZLIB_LIBS = @ZLIB_LIBS@ +abs_builddir = @abs_builddir@ +abs_srcdir = @abs_srcdir@ +abs_top_builddir = @abs_top_builddir@ +abs_top_srcdir = @abs_top_srcdir@ +ac_ct_CC = @ac_ct_CC@ +ac_ct_CXX = @ac_ct_CXX@ +ac_ct_F77 = @ac_ct_F77@ +am__include = @am__include@ +am__leading_dot = @am__leading_dot@ +am__quote = @am__quote@ +am__tar = @am__tar@ +am__untar = @am__untar@ +bindir = @bindir@ +build = @build@ +build_alias = @build_alias@ +build_cpu = @build_cpu@ +build_os = @build_os@ +build_vendor = @build_vendor@ +builddir = @builddir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +docdir = @docdir@ +dvidir = @dvidir@ +exec_prefix = @exec_prefix@ +host = @host@ +host_alias = @host_alias@ +host_cpu = @host_cpu@ +host_os = @host_os@ +host_vendor = @host_vendor@ +htmldir = @htmldir@ +includedir = @includedir@ +infodir = @infodir@ +install_sh = @install_sh@ +libdir = @libdir@ +libexecdir = @libexecdir@ +localedir = @localedir@ +localstatedir = @localstatedir@ +mandir = @mandir@ +mkdir_p = @mkdir_p@ +oldincludedir = @oldincludedir@ +pdfdir = @pdfdir@ +prefix = @prefix@ +program_transform_name = @program_transform_name@ +psdir = @psdir@ +sbindir = @sbindir@ +sharedstatedir = @sharedstatedir@ +srcdir = @srcdir@ +sysconfdir = @sysconfdir@ +target = @target@ +target_alias = @target_alias@ +target_cpu = @target_cpu@ +target_os = @target_os@ +target_vendor = @target_vendor@ +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ +INCLUDES = \ + -I$(top_builddir)/include \ + -I$(top_srcdir)/include \ + -I$(top_builddir)/lib \ + -I$(top_srcdir)/lib \ + -I$(top_srcdir)/src \ + -I$(top_srcdir)/systems + +nvidia_LTLIBRARIES = libdirectfb_nvidia.la +@BUILD_STATIC_TRUE@nvidia_DATA = $(nvidia_LTLIBRARIES:.la=.o) +nvidiadir = $(MODULEDIR)/gfxdrivers +libdirectfb_nvidia_la_SOURCES = \ + nvidia.c \ + nvidia_state.c \ + nvidia_2d.c \ + nvidia_3d.c \ + nvidia_primary.c \ + nvidia_overlay.c \ + nvidia.h \ + nvidia_regs.h \ + nvidia_accel.h \ + nvidia_objects.h \ + nvidia_state.h \ + nvidia_2d.h \ + nvidia_3d.h + +libdirectfb_nvidia_la_LDFLAGS = \ + -module \ + -avoid-version \ + $(DFB_LDFLAGS) + +libdirectfb_nvidia_la_LIBADD = -lm \ + $(top_builddir)/lib/direct/libdirect.la \ + $(top_builddir)/lib/fusion/libfusion.la \ + $(top_builddir)/src/libdirectfb.la + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .lo .o .obj +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/rules/libobject.make $(am__configure_deps) + @for dep in $?; do \ + case '$(am__configure_deps)' in \ + *$$dep*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ + && exit 0; \ + exit 1;; \ + esac; \ + done; \ + echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu gfxdrivers/nvidia/Makefile'; \ + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu gfxdrivers/nvidia/Makefile +.PRECIOUS: Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + @case '$?' in \ + *config.status*) \ + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ + *) \ + echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ + esac; + +$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh + +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) + cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh +install-nvidiaLTLIBRARIES: $(nvidia_LTLIBRARIES) + @$(NORMAL_INSTALL) + test -z "$(nvidiadir)" || $(MKDIR_P) "$(DESTDIR)$(nvidiadir)" + @list='$(nvidia_LTLIBRARIES)'; for p in $$list; do \ + if test -f $$p; then \ + f=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(nvidiaLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(nvidiadir)/$$f'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(nvidiaLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(nvidiadir)/$$f"; \ + else :; fi; \ + done + +uninstall-nvidiaLTLIBRARIES: + @$(NORMAL_UNINSTALL) + @list='$(nvidia_LTLIBRARIES)'; for p in $$list; do \ + p=$(am__strip_dir) \ + echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(nvidiadir)/$$p'"; \ + $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(nvidiadir)/$$p"; \ + done + +clean-nvidiaLTLIBRARIES: + -test -z "$(nvidia_LTLIBRARIES)" || rm -f $(nvidia_LTLIBRARIES) + @list='$(nvidia_LTLIBRARIES)'; for p in $$list; do \ + dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ + test "$$dir" != "$$p" || dir=.; \ + echo "rm -f \"$${dir}/so_locations\""; \ + rm -f "$${dir}/so_locations"; \ + done +libdirectfb_nvidia.la: $(libdirectfb_nvidia_la_OBJECTS) $(libdirectfb_nvidia_la_DEPENDENCIES) + $(libdirectfb_nvidia_la_LINK) -rpath $(nvidiadir) $(libdirectfb_nvidia_la_OBJECTS) $(libdirectfb_nvidia_la_LIBADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia_2d.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia_3d.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia_overlay.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia_primary.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nvidia_state.Plo@am__quote@ + +.c.o: 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-rm -rf ./$(DEPDIR) + -rm -f Makefile +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic \ + mostlyclean-libtool + +pdf: pdf-am + +pdf-am: + +ps: ps-am + +ps-am: + +uninstall-am: uninstall-nvidiaDATA uninstall-nvidiaLTLIBRARIES + +.MAKE: install-am install-strip + +.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ + clean-libtool clean-nvidiaLTLIBRARIES ctags distclean \ + distclean-compile distclean-generic distclean-libtool \ + distclean-tags distdir dvi dvi-am html html-am info info-am \ + install install-am install-data install-data-am install-dvi \ + install-dvi-am install-exec install-exec-am install-html \ + install-html-am install-info install-info-am install-man \ + install-nvidiaDATA install-nvidiaLTLIBRARIES install-pdf \ + install-pdf-am install-ps install-ps-am install-strip \ + installcheck installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ + tags uninstall uninstall-am uninstall-nvidiaDATA \ + uninstall-nvidiaLTLIBRARIES + +%.o: .libs/%.a %.la + rm -f $<.tmp/*.o + if test -d $<.tmp; then rmdir $<.tmp; fi + mkdir $<.tmp + (cd $<.tmp && $(AR) x ../../$<) + $(LD) -o $@ -r $<.tmp/*.o + rm -f $<.tmp/*.o && rmdir $<.tmp + +.PHONY: $(LTLIBRARIES:%.la=.libs/%.a) +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia.c new file mode 100755 index 0000000..6ecb17f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia.c @@ -0,0 +1,2046 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <unistd.h> + +#include <sys/mman.h> + +#include <fbdev/fb.h> + +#include <directfb.h> + +#include <direct/messages.h> + +#include <core/coredefs.h> +#include <core/coretypes.h> + +#include <core/state.h> +#include <core/system.h> +#include <core/gfxcard.h> +#include <core/surface.h> +#include <core/palette.h> + +#include <gfx/convert.h> +#include <gfx/util.h> + +#include <misc/conf.h> + +#include <core/graphics_driver.h> + +DFB_GRAPHICS_DRIVER( nvidia ) + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_objects.h" +#include "nvidia_state.h" +#include "nvidia_2d.h" +#include "nvidia_3d.h" + + +/* Riva TNT */ +#define NV4_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV4_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV4_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_DEINTERLACE) + +#define NV4_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* Riva TNT2 */ +#define NV5_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV5_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV5_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_DEINTERLACE) + +#define NV5_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* GeForce1/GeForce2/GeForce4 */ +#define NV10_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV10_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV10_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE) + +#define NV10_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT | DFXL_TEXTRIANGLES) + +/* GeForce3/GeForce4Ti */ +#define NV20_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV20_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV20_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL | \ + DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR | \ + DSBLIT_DEINTERLACE) + +#define NV20_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT | DFXL_STRETCHBLIT) + +/* GeForceFX */ +#define NV30_SUPPORTED_DRAWINGFLAGS \ + (DSDRAW_BLEND) + +#define NV30_SUPPORTED_DRAWINGFUNCTIONS \ + (DFXL_FILLRECTANGLE | DFXL_DRAWRECTANGLE | \ + DFXL_FILLTRIANGLE | DFXL_DRAWLINE) + +#define NV30_SUPPORTED_BLITTINGFLAGS \ + (DSBLIT_NOFX) + +#define NV30_SUPPORTED_BLITTINGFUNCTIONS \ + (DFXL_BLIT) + + +#define DSBLIT_MODULATE_ALPHA \ + (DSBLIT_BLEND_COLORALPHA | DSBLIT_BLEND_ALPHACHANNEL) + +#define DSBLIT_MODULATE_COLOR \ + (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) + +#define DSBLIT_MODULATE \ + (DSBLIT_MODULATE_ALPHA | DSBLIT_MODULATE_COLOR) + + + + +static void nvAfterSetVar( void *driver_data, + void *device_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + volatile u8 *mmio = nvdrv->mmio_base; + int i; + + nv_waitidle( nvdrv, nvdev ); + + /* reconfigure PFIFO for selected mode (DMA/PIO) */ + nv_out32( mmio, PFIFO_CACHES, PFIFO_CACHES_REASSIGN_DISABLED ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_MODE, PFIFO_MODE_CHANNEL_0_DMA ); + nv_out32( mmio, PFIFO_NEXT_CHANNEL, PFIFO_NEXT_CHANNEL_MODE_DMA ); + } else { + nv_out32( mmio, PFIFO_MODE, PFIFO_MODE_CHANNEL_0_PIO ); + nv_out32( mmio, PFIFO_NEXT_CHANNEL, PFIFO_NEXT_CHANNEL_MODE_PIO ); + } + nv_out32( mmio, PFIFO_CACHE1_PUSH0, PFIFO_CACHE1_PULL1_ENGINE_SW ); + nv_out32( mmio, PFIFO_CACHE1_PULL0, PFIFO_CACHE1_PULL0_ACCESS_DISABLED ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_CACHE1_PUSH1, PFIFO_CACHE1_PUSH1_MODE_DMA ); + } else { + nv_out32( mmio, PFIFO_CACHE1_PUSH1, PFIFO_CACHE1_PUSH1_MODE_PIO ); + } + nv_out32( mmio, PFIFO_CACHE1_DMA_PUT, 0 ); + nv_out32( mmio, PFIFO_CACHE1_DMA_GET, 0 ); + if (nvdev->use_dma) { + nv_out32( mmio, PFIFO_CACHE1_DMA_INSTANCE, ADDR_DMA_OUT ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_INSTANCE, 0 ); + } + nv_out32( mmio, PFIFO_CACHE0_PUSH0, PFIFO_CACHE0_PUSH0_ACCESS_DISABLED ); + nv_out32( mmio, PFIFO_CACHE0_PULL0, PFIFO_CACHE0_PULL0_ACCESS_DISABLED ); + nv_out32( mmio, PFIFO_RAMHT, 0x00000100 | + PFIFO_RAMHT_SIZE_4K | + PFIFO_RAMHT_SEARCH_128 ); + nv_out32( mmio, PFIFO_RAMFC, 0x00000110 ); + nv_out32( mmio, PFIFO_RAMRO, 0x00000112 | PFIFO_RAMRO_SIZE_512 ); + nv_out32( mmio, PFIFO_SIZE, 0x0000FFFF ); + nv_out32( mmio, PFIFO_CACHE1_HASH, 0x0000FFFF ); + nv_out32( mmio, PFIFO_INTR_EN, PFIFO_INTR_EN_DISABLED ); + nv_out32( mmio, PFIFO_INTR, PFIFO_INTR_RESET ); + nv_out32( mmio, PFIFO_CACHE0_PULL1, PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS ); + if (nvdev->use_dma) { + if (nvdev->use_agp) { + nv_out32( mmio, PFIFO_CACHE1_DMA_CTL, + PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT | + PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR | + PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_CTL, + PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT | + PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR | + PFIFO_CACHE1_DMA_CTL_TARGET_NODE_NVM ); + } + nv_out32( mmio, PFIFO_CACHE1_DMA_LIMIT, nvdev->dma_size - 4 ); + nv_out32( mmio, PFIFO_CACHE1_ENGINE, PFIFO_CACHE1_ENGINE_0_SW ); +#ifdef WORDS_BIGENDIAN + nv_out32( mmio, PFIFO_CACHE1_DMA_FETCH, + PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 | + PFIFO_CACHE1_BIG_ENDIAN ); +#else + nv_out32( mmio, PFIFO_CACHE1_DMA_FETCH, + PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 | + PFIFO_CACHE1_LITTLE_ENDIAN ); +#endif + nv_out32( mmio, PFIFO_CACHE1_DMA_PUSH, + PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED ); + } else { + nv_out32( mmio, PFIFO_CACHE1_DMA_PUSH, + PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED ); + } + nv_out32( mmio, PFIFO_CACHE1_PUSH0, PFIFO_CACHE1_PUSH0_ACCESS_ENABLED ); + nv_out32( mmio, PFIFO_CACHE1_PULL0, PFIFO_CACHE1_PULL0_ACCESS_ENABLED ); + nv_out32( mmio, PFIFO_CACHE1_PULL1, PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS ); + nv_out32( mmio, PFIFO_CACHES, PFIFO_CACHES_REASSIGN_ENABLED ); + nv_out32( mmio, PFIFO_INTR_EN, PFIFO_INTR_EN_CACHE_ERROR_ENABLED ); + + if (nvdev->arch == NV_ARCH_10) { + nv_out32( mmio, PGRAPH_DEBUG_1, 0x00118701 ); + nv_out32( mmio, PGRAPH_DEBUG_2, 0x24F82AD9 ); + + for (i = 0; i < 8; i++) { + nv_out32( mmio, NV10_PGRAPH_WINDOWCLIP_HORIZONTAL+i*4, 0x07FF0800 ); + nv_out32( mmio, NV10_PGRAPH_WINDOWCLIP_VERTICAL +i*4, 0x07FF0800 ); + } + + nv_out32( mmio, NV10_PGRAPH_XFMODE0, 0x10000000 ); + nv_out32( mmio, NV10_PGRAPH_XFMODE1, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006740 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006750 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x40000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006760 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006770 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006780 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000067A0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AB0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AC0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006C10 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xBF800000 ); + + for (i = 0; i < 8; i++) { + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x7030+i*16 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x7149F2CA ); + } + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006A80 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006AA0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000005 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006400 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x4B7FFFFF ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006410 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006420 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x00006430 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064C0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x477FFFFF ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x3F800000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064D0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC5000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064E0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC4FFF000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0xC4FFF000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_PIPE_ADDRESS, 0x000064F0 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + nv_out32( mmio, NV10_PGRAPH_PIPE_DATA, 0x00000000 ); + + nv_out32( mmio, NV10_PGRAPH_XFMODE0, 0x30000000 ); + nv_out32( mmio, NV10_PGRAPH_XFMODE1, 0x00000004 ); + nv_out32( mmio, NV10_PGRAPH_GLOBALSTATE0, 0x10000000 ); + nv_out32( mmio, NV10_PGRAPH_GLOBALSTATE1, 0x00000000 ); + } + + nvdev->dma_max = nvdev->dma_size/4 - 1; + nvdev->dma_cur = 0; + nvdev->dma_free = nvdev->dma_max; + nvdev->dma_put = 0; + nvdev->dma_get = 0; + nvdev->fifo_free = 0; +} + +static void nvEngineReset( void *drv, void *dev ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + int i; + + /* reput objects into subchannels */ + for (i = 0; i < 8; i++) { + nv_assign_object( nvdrv, nvdev, i, + nvdev->subchannel_object[i], true ); + } + + nvdev->set = 0; + nvdev->dst_format = DSPF_UNKNOWN; + nvdev->dst_pitch = 0; + nvdev->src_pitch = 0; + nvdev->beta1_set = false; + nvdev->beta4_set = false; +} + +static DFBResult nvEngineSync( void *drv, void *dev ) +{ + nv_waitidle( (NVidiaDriverData*)drv, (NVidiaDeviceData*)dev ); + + return DFB_OK; +} + +static void nvFlushTextureCache( void *drv, void *dev ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + /* invalidate source texture */ + nvdev->set &= ~SMF_SOURCE_TEXTURE; +} + +static void nvEmitCommands( void *drv, void *dev ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->use_dma) + nv_emitdma( nvdrv, nvdev ); +} + +static void nv4CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV4_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV4_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->src_blend != DSBF_SRCALPHA || + state->dst_blend != DSBF_INVSRCALPHA) + return; + } + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_A8: + case DSPF_RGB332: + if (destination->config.format != source->config.format) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_RGB16: + switch (accel) { + case DFXL_BLIT: + if (state->blittingflags != DSBLIT_NOFX || + destination->config.format != DSPF_RGB16) + return; + break; + case DFXL_STRETCHBLIT: + return; + default: + break; + } + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel == DFXL_TEXTRIANGLES) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV4_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV4_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV4_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv5CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV5_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV5_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_MODULATE) { + if (state->blittingflags & DSBLIT_MODULATE_ALPHA && + state->blittingflags & DSBLIT_MODULATE_COLOR) + return; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->src_blend != DSBF_SRCALPHA || + state->dst_blend != DSBF_INVSRCALPHA) + return; + } + } + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_A8: + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV5_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV5_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV5_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv10CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel != DFXL_BLIT || state->blittingflags || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting flags */ + if (accel & ~NV10_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV10_SUPPORTED_BLITTINGFLAGS) + return; + + if (accel == DFXL_TEXTRIANGLES) { + u32 size = 1 << (direct_log2(source->config.size.w) + + direct_log2(source->config.size.h)); + + if (size > nvdev->max_texture_size) + return; + } + else { + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->blittingflags & DSBLIT_MODULATE_COLOR) { + if (source->config.format == DSPF_ARGB && + state->src_blend != DSBF_ONE) + return; + } + + if (state->src_blend != DSBF_ONE && + state->src_blend != DSBF_SRCALPHA) + return; + + if (state->dst_blend != DSBF_INVSRCALPHA) + return; + } + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + } + + switch (source->config.format) { + case DSPF_A8: + if (DFB_BYTES_PER_PIXEL(destination->config.format) != 4 /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV10_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV10_SUPPORTED_DRAWINGFLAGS) + return; + + state->accel |= NV10_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv20CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_BLITTING_FUNCTION( accel )) { + if (state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (DFB_BLITTING_FUNCTION( accel )) { + if (accel & ~(DFXL_BLIT | DFXL_STRETCHBLIT) || + state->blittingflags != DSBLIT_NOFX || + source->config.format != destination->config.format) + return; + } else { + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + } + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting functions/flags */ + if (accel & ~NV20_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV20_SUPPORTED_BLITTINGFLAGS) + return; + + if (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL) { + if (state->blittingflags & DSBLIT_MODULATE_COLOR) { + if (source->config.format == DSPF_ARGB && state->src_blend != DSBF_ONE) + return; + } + + if (state->src_blend != DSBF_ONE && + state->src_blend != DSBF_SRCALPHA) + return; + + if (state->dst_blend != DSBF_INVSRCALPHA) + return; + } + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] < 0 || state->matrix[1] || + state->matrix[3] || state->matrix[4] < 0)) + return; + + switch (source->config.format) { + case DSPF_A8: + /*if (state->src.buffer->policy == CSP_SYSTEMONLY) + return;*/ + break; + + case DSPF_LUT8: + case DSPF_ALUT44: + if (destination->config.format != source->config.format || + /*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + !dfb_palette_equal( source->palette, + destination->palette )) + return; + break; + + case DSPF_RGB332: + if (destination->config.format != source->config.format /*|| + state->src.buffer->policy == CSP_SYSTEMONLY*/) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + /* disable host-to-video blit for simple blits */ + /*if (state->src.buffer->policy == CSP_SYSTEMONLY && + accel == DFXL_BLIT && !state->blittingflags && + source->config.format == destination->config.format) + return;*/ + break; + + case DSPF_YUY2: + case DSPF_UYVY: + /*if (state->src.buffer->policy == CSP_SYSTEMONLY) + return;*/ + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV20_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV20_SUPPORTED_DRAWINGFLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->src_blend != DSBF_SRCALPHA && + state->dst_blend != DSBF_INVSRCALPHA) + return; + + state->accel |= NV20_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +static void nv30CheckState( void *drv, void *dev, + CardState *state, DFBAccelerationMask accel ) +{ + CoreSurface *destination = state->destination; + CoreSurface *source = state->source; + + switch (destination->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + if (DFB_DRAWING_FUNCTION( accel ) && + state->drawingflags != DSDRAW_NOFX) + return; + break; + + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + break; + + case DSPF_YUY2: + case DSPF_UYVY: + if (accel & (DFXL_FILLTRIANGLE | DFXL_DRAWLINE) || + state->drawingflags != DSDRAW_NOFX) + return; + break; + + default: + return; + } + + if (DFB_BLITTING_FUNCTION( accel )) { + /* check unsupported blitting functions/flags */ + if (accel & ~NV30_SUPPORTED_BLITTINGFUNCTIONS || + state->blittingflags & ~NV30_SUPPORTED_BLITTINGFLAGS) + return; + + if (state->render_options & DSRO_MATRIX && + (state->matrix[0] != 0x10000 || state->matrix[1] || + state->matrix[3] || state->matrix[4] != 0x10000)) + return; + + switch (source->config.format) { + case DSPF_LUT8: + case DSPF_ALUT44: + if (!dfb_palette_equal( source->palette, + destination->palette )) + return; + case DSPF_A8: + case DSPF_RGB332: + case DSPF_RGB555: + case DSPF_ARGB1555: + case DSPF_RGB16: + case DSPF_RGB32: + case DSPF_ARGB: + case DSPF_YUY2: + case DSPF_UYVY: + if (/*state->src.buffer->policy == CSP_SYSTEMONLY ||*/ + source->config.format != destination->config.format) + return; + break; + + default: + return; + } + + state->accel |= accel; + } + else { + /* check unsupported drawing flags */ + if (accel & ~NV30_SUPPORTED_DRAWINGFUNCTIONS || + state->drawingflags & ~NV30_SUPPORTED_DRAWINGFLAGS) + return; + + if (state->drawingflags & DSDRAW_BLEND && + state->src_blend != DSBF_SRCALPHA && + state->dst_blend != DSBF_INVSRCALPHA) + return; + + state->accel |= NV30_SUPPORTED_DRAWINGFUNCTIONS; + } +} + +#define M_IDENTITY(m) ((m)[0] == 0x10000 && (m)[1] == 0 && (m)[2] == 0 && \ + (m)[3] == 0 && (m)[4] == 0x10000 && (m)[5] == 0) + +static void nv4SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE_ALPHA) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv5SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } else { + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv10SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + if (state->drawingflags & DSDRAW_BLEND) + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + if ((state->drawingflags & DSDRAW_BLEND || nvdev->matrix) && nvdev->enabled_3d) { + nvdev->state3d[0].modified = true; + + funcs->FillRectangle = nvFillRectangle3D; + funcs->FillTriangle = nvFillTriangle3D; + funcs->DrawRectangle = nvDrawRectangle3D; + funcs->DrawLine = nvDrawLine3D; + } else { + funcs->FillRectangle = nvFillRectangle2D; + funcs->FillTriangle = nvFillTriangle2D; + funcs->DrawRectangle = nvDrawRectangle2D; + funcs->DrawLine = nvDrawLine2D; + } + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + case DFXL_TEXTRIANGLES: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + nv_set_blend_function( nvdrv, nvdev, state ); + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (accel == DFXL_TEXTRIANGLES) { + if (nvdev->src_texture != state->src.buffer) + nvdev->set &= ~SMF_SOURCE_TEXTURE; + + nvdev->src_texture = state->src.buffer; + nvdev->state3d[1].modified = true; + + state->set = DFXL_TEXTRIANGLES; + } else { + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } else { + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + } + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv20SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + case DFXL_STRETCHBLIT: + nv_set_source( nvdrv, nvdev, state ); + + if (state->blittingflags & DSBLIT_MODULATE) { + if (state->modified & SMF_SRC_BLEND) + nvdev->set &= ~SMF_BLITTING_FLAGS; + nv_set_blitting_color( nvdrv, nvdev, state ); + } + + nv_set_blittingflags( nvdrv, nvdev, state ); + + if (nvdev->src_system) { + funcs->Blit = nvBlitFromCPU; + funcs->StretchBlit = nvStretchBlitFromCPU; + } + else { + if (DFB_BITS_PER_PIXEL(nvdev->dst_format) == 8) + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CORNER | + SCALER_IN_FORMAT_FILTER_NEAREST; + else + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CENTER | + SCALER_IN_FORMAT_FILTER_LINEAR; + + funcs->Blit = nvBlit; + funcs->StretchBlit = nvStretchBlit; + } + + state->set = DFXL_BLIT | + DFXL_STRETCHBLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + +static void nv30SetState( void *drv, void *dev, + GraphicsDeviceFuncs *funcs, + CardState *state, DFBAccelerationMask accel ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + nvdev->set &= ~state->mod_hw; + if (state->mod_hw & SMF_COLOR) + nvdev->set &= ~(SMF_DRAWING_COLOR | SMF_BLITTING_COLOR); + + nv_set_destination( nvdrv, nvdev, state ); + nv_set_clip( nvdrv, nvdev, state ); + + if (state->render_options & DSRO_MATRIX && !M_IDENTITY(state->matrix)) + nvdev->matrix = state->matrix; + else + nvdev->matrix = NULL; + + switch (accel) { + case DFXL_FILLRECTANGLE: + case DFXL_FILLTRIANGLE: + case DFXL_DRAWRECTANGLE: + case DFXL_DRAWLINE: + nv_set_drawing_color( nvdrv, nvdev, state ); + nv_set_drawingflags( nvdrv, nvdev, state ); + + state->set = DFXL_FILLRECTANGLE | + DFXL_FILLTRIANGLE | + DFXL_DRAWRECTANGLE | + DFXL_DRAWLINE; + break; + + case DFXL_BLIT: + nv_set_source( nvdrv, nvdev, state ); + + state->set = DFXL_BLIT; + break; + + default: + D_BUG( "unexpected drawing/blitting function" ); + break; + } + + state->mod_hw = 0; +} + + +/* exported symbols */ + +static int +driver_probe( CoreGraphicsDevice *device ) +{ + switch (dfb_gfxcard_get_accelerator( device )) { + case FB_ACCEL_NV4: + case FB_ACCEL_NV5: + case FB_ACCEL_NV_10: + case FB_ACCEL_NV_20: + case FB_ACCEL_NV_30: + case FB_ACCEL_NV_40: + return 1; + } + + return 0; +} + +static void +driver_get_info( CoreGraphicsDevice *device, + GraphicsDriverInfo *info ) +{ + /* fill driver info structure */ + snprintf( info->name, + DFB_GRAPHICS_DRIVER_INFO_NAME_LENGTH, + "nVidia NV4/NV5/NV10/NV20/NV30 Driver" ); + + snprintf( info->vendor, + DFB_GRAPHICS_DRIVER_INFO_VENDOR_LENGTH, + "directfb.org" ); + + snprintf( info->url, + DFB_GRAPHICS_DRIVER_INFO_URL_LENGTH, + "http://www.directfb.org" ); + + snprintf( info->license, + DFB_GRAPHICS_DRIVER_INFO_LICENSE_LENGTH, + "LGPL" ); + + info->version.major = 0; + info->version.minor = 6; + + info->driver_data_size = sizeof(NVidiaDriverData); + info->device_data_size = sizeof(NVidiaDeviceData); +} + +static void +nv_find_architecture( NVidiaDriverData *nvdrv, u32 *ret_chip, u32 *ret_arch ) +{ + unsigned int vendor_id; + unsigned int device_id; + unsigned int arch = 0; + + device_id = nv_in32( nvdrv->mmio_base, 0x00 ) >> 16; /* id:rev */ + if (!device_id) { + dfb_system_get_deviceid( &vendor_id, &device_id ); + if (vendor_id != 0x10DE) { + D_ERROR( "DirectFB/NVidia: Could not detect device id!\n" + " -> Please, specify the bus location of" + " the card by using the 'busid' option.\n" ); + vendor_id = device_id = 0; + } + } + + switch (device_id & 0xFFF0) { + case 0x0020: /* Riva TNT/TNT2 */ + arch = (device_id == 0x0020) ? NV_ARCH_04 : NV_ARCH_05; + break; + case 0x0100: /* GeForce */ + case 0x0110: /* GeForce2 MX */ + case 0x0150: /* GeForce2 GTS/Ti/Ultra */ + case 0x0170: /* GeForce4 MX/Go */ + case 0x0180: /* GeForce4 MX/Go AGP8X */ + //case 0x01A0: /* GeForce2 Integrated GPU */ + //case 0x01F0: /* GeForce4 MX Integrated GPU */ + arch = NV_ARCH_10; + break; + case 0x0200: /* GeForce3 */ + case 0x0250: /* GeForce4 Ti */ + case 0x0280: /* GeForce4 Ti AGP8X */ + case 0x02A0: /* GeForce3 Integrated GPU (XBox) */ + arch = NV_ARCH_20; + break; + case 0x0300: /* GeForce FX 5800 */ + case 0x0310: /* GeForce FX 5600 */ + case 0x0320: /* GeForce FX 5200 */ + case 0x0330: /* GeForce FX 5900 */ + case 0x0340: /* GeForce FX 5700 */ + arch = NV_ARCH_30; + break; + default: + break; + } + + if (ret_chip) + *ret_chip = device_id; + if (ret_arch) + *ret_arch = arch; +} + +static DFBResult +driver_init_driver( CoreGraphicsDevice *device, + GraphicsDeviceFuncs *funcs, + void *driver_data, + void *device_data, + CoreDFB *core ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + u32 arch = 0; + + nvdrv->device = device; + nvdrv->device_data = device_data; + + nvdrv->fb_base = (volatile void*) dfb_gfxcard_memory_virtual( device, 0 ); + nvdrv->agp_base = (volatile void*) dfb_gfxcard_auxmemory_virtual( device, 0 ); + + nvdrv->mmio_base = (volatile void*) dfb_gfxcard_map_mmio( device, 0, -1 ); + if (!nvdrv->mmio_base) + return DFB_IO; + + if (nvdev->use_dma) { + nvdrv->dma_base = nvdev->use_agp ? nvdrv->agp_base : nvdrv->fb_base; + nvdrv->dma_base += nvdev->dma_offset; + } + + funcs->AfterSetVar = nvAfterSetVar; + funcs->EngineReset = nvEngineReset; + funcs->EngineSync = nvEngineSync; + funcs->EmitCommands = nvEmitCommands; + funcs->FillRectangle = nvFillRectangle2D; // dynamic + funcs->FillTriangle = nvFillTriangle2D; // dynamic + funcs->DrawRectangle = nvDrawRectangle2D; // dynamic + funcs->DrawLine = nvDrawLine2D; // dynamic + funcs->Blit = nvBlit; // dynamic + + nv_find_architecture( nvdrv, NULL, &arch ); + + switch (arch) { + case NV_ARCH_04: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv4CheckState; + funcs->SetState = nv4SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_05: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv5CheckState; + funcs->SetState = nv5SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_10: + funcs->FlushTextureCache = nvFlushTextureCache; + funcs->CheckState = nv10CheckState; + funcs->SetState = nv10SetState; + funcs->StretchBlit = nvStretchBlit; + funcs->TextureTriangles = nvTextureTriangles; + break; + case NV_ARCH_20: + funcs->CheckState = nv20CheckState; + funcs->SetState = nv20SetState; + funcs->StretchBlit = nvStretchBlit; + break; + case NV_ARCH_30: + funcs->CheckState = nv30CheckState; + funcs->SetState = nv30SetState; + break; + default: + funcs->AfterSetVar = NULL; + funcs->EngineReset = NULL; + break; + } + + dfb_screens_hook_primary( device, driver_data, + &nvidiaPrimaryScreenFuncs, + &OldPrimaryScreenFuncs, + &OldPrimaryScreenDriverData ); + + dfb_layers_hook_primary( device, driver_data, + &nvidiaPrimaryLayerFuncs, + &OldPrimaryLayerFuncs, + &OldPrimaryLayerDriverData ); + + dfb_layers_register( dfb_screens_at( DSCID_PRIMARY ), + driver_data, &nvidiaOverlayFuncs ); + + return DFB_OK; +} + +static DFBResult +driver_init_device( CoreGraphicsDevice *device, + GraphicsDeviceInfo *device_info, + void *driver_data, + void *device_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + int ram_total = dfb_system_videoram_length(); + int ram_used = dfb_gfxcard_memory_length(); + + nv_find_architecture( nvdrv, &nvdev->chip, &nvdev->arch ); + + snprintf( device_info->name, + DFB_GRAPHICS_DEVICE_INFO_NAME_LENGTH, + "NV%02X (%04x)", (nvdev->chip >> 4) & 0xFF, nvdev->chip ); + + snprintf( device_info->vendor, + DFB_GRAPHICS_DEVICE_INFO_VENDOR_LENGTH, "nVidia" ); + + switch (nvdev->arch) { + case NV_ARCH_04: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = NV4_SUPPORTED_DRAWINGFUNCTIONS | + NV4_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV4_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV4_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_05: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /*| CCF_READSYSMEM*/; + device_info->caps.accel = NV5_SUPPORTED_DRAWINGFUNCTIONS | + NV5_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV5_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV5_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_10: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /*| CCF_READSYSMEM*/; + device_info->caps.accel = NV10_SUPPORTED_DRAWINGFUNCTIONS | + NV10_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV10_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV10_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_20: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS /* | CCF_READSYSMEM*/; /* Crash reported when the flag is on. */ + device_info->caps.accel = NV20_SUPPORTED_DRAWINGFUNCTIONS | + NV20_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV20_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV20_SUPPORTED_BLITTINGFLAGS; + break; + case NV_ARCH_30: + device_info->caps.flags = CCF_CLIPPING | CCF_RENDEROPTS; + device_info->caps.accel = NV30_SUPPORTED_DRAWINGFUNCTIONS | + NV30_SUPPORTED_BLITTINGFUNCTIONS; + device_info->caps.drawing = NV30_SUPPORTED_DRAWINGFLAGS; + device_info->caps.blitting = NV30_SUPPORTED_BLITTINGFLAGS; + break; + default: + device_info->caps.flags = 0; + device_info->caps.accel = 0; + device_info->caps.drawing = 0; + device_info->caps.blitting = 0; + break; + } + + device_info->limits.surface_byteoffset_alignment = 64; + device_info->limits.surface_pixelpitch_alignment = 32; + + dfb_config->pollvsync_after = 1; + + /* GeForce3 Intergrated GPU (XBox) */ + if (nvdev->chip == 0x02A0) { + nvdev->fb_offset = (long)nvdrv->fb_base & 0x0FFFFFFF; + ram_total += nvdev->fb_offset; + } + + nvdev->fb_size = 1 << direct_log2( ram_total ); + + /* skip if unsupported arch (NV40) */ + if (!nvdev->arch) + return DFB_OK; + + nvdev->agp_offset = dfb_gfxcard_auxmemory_physical( nvdrv->device, 0 ); + + if (dfb_config->dma) { + int offset = -1; + + if (dfb_gfxcard_auxmemory_length() >= 64*1024) { + offset = dfb_gfxcard_reserve_auxmemory( nvdrv->device, 64*1024 ); + if (offset < 0) { + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve 64Kb of agp memory!\n" ); + } + else { + nvdev->use_agp = true; + nvdev->use_dma = true; + nvdev->dma_size = 64*1024; + nvdev->dma_offset = offset; + nvdrv->dma_base = nvdrv->agp_base + offset; + } + } + + if (offset < 0) { + int len; + + len = 32*1024 + ((ram_used - 32*1024) & 0x1FFFF); + offset = dfb_gfxcard_reserve_memory( nvdrv->device, len ); + if (offset < 0) { + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve %d bytes of video memory!\n", len ); + } + else { + nvdev->use_dma = true; + nvdev->dma_size = 32*1024; + nvdev->dma_offset = offset; + nvdrv->dma_base = nvdrv->fb_base + offset; + + ram_used -= len; + } + } + + D_INFO ( "DirectFB/NVidia: DMA acceleration %s.\n", + nvdev->use_dma ? "enabled" : "disabled" ); + D_DEBUG( "DirectFB/NVidia: DMA target is %s.\n", + nvdev->use_agp ? "AGP" : "NVM" ); + } + + /* reserve memory for textures/color buffers */ + if (device_info->caps.accel & DFXL_TEXTRIANGLES) { + unsigned tex_size; + int len, offset; + + /* if we have more than 32MB of video memory, use a 1024x1024 texture */ + if (ram_used > (32 << 20)) + tex_size = 1024*1024; + /* if we have more than 16MB of video memory, use a 1024x512 texture */ + else if (ram_used > (16 << 20)) + tex_size = 1024*512; + /* otherwise use a 512x512 texture */ + else + tex_size = 512*512; + + len = tex_size*2 + 8; + len += (ram_used - len) & 0xFF; + offset = dfb_gfxcard_reserve_memory( nvdrv->device, len ); + + if (offset < 0) { + /* if video memory allocation failed, disable 3d acceleration */ + D_ERROR( "DirectFB/NVidia: " + "couldn't reserve %d bytes of video memory!\n", len ); + D_INFO( "DirectFB/NVidia: 3D acceleration disabled.\n" ); + device_info->caps.accel &= ~DFXL_TEXTRIANGLES; + } + else { + D_DEBUG( "DirectFB/NVidia: " + "reserved %d bytes for 3D buffers at offset 0x%08x.\n", + len, offset ); + + nvdev->enabled_3d = true; + nvdev->buf_offset[0] = offset + tex_size*2; // color + nvdev->buf_offset[1] = offset; // texture + nvdev->max_texture_size = tex_size; + } + } + + if (nvdev->enabled_3d) { + /* set default 3d state for drawing functions */ + nvdev->state3d[0].modified = true; + nvdev->state3d[0].colorkey = 0; + nvdev->state3d[0].offset = nvdev->fb_offset + nvdev->buf_offset[0]; + nvdev->state3d[0].format = TXTRI_FORMAT_CONTEXT_DMA_A | + TXTRI_FORMAT_ORIGIN_ZOH_CORNER | + TXTRI_FORMAT_ORIGIN_FOH_CORNER | + TXTRI_FORMAT_COLOR_R5G6B5 | + TXTRI_FORMAT_U_WRAP | + TXTRI_FORMAT_V_WRAP | + 0x00111000; // 2x2 + nvdev->state3d[0].filter = TXTRI_FILTER_TEXTUREMIN_NEAREST | + TXTRI_FILTER_TEXTUREMAG_NEAREST; + nvdev->state3d[0].blend = TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA | + TXTRI_BLEND_OPERATION_MUX_TALPHAMSB | + TXTRI_BLEND_SHADEMODE_FLAT | + TXTRI_BLEND_SRCBLEND_ONE | + TXTRI_BLEND_DESTBLEND_ZERO; + nvdev->state3d[0].control = TXTRI_CONTROL_ALPHAFUNC_ALWAYS | + TXTRI_CONTROL_ORIGIN_CORNER | + TXTRI_CONTROL_ZFUNC_ALWAYS | + TXTRI_CONTROL_CULLMODE_NONE | + TXTRI_CONTROL_Z_FORMAT_FIXED; + nvdev->state3d[0].fog = 0; + + /* set default 3d state for blitting functions */ + nvdev->state3d[1].modified = true; + nvdev->state3d[1].colorkey = 0; + nvdev->state3d[1].offset = nvdev->fb_offset + nvdev->buf_offset[1]; + nvdev->state3d[1].format = TXTRI_FORMAT_CONTEXT_DMA_A | + TXTRI_FORMAT_ORIGIN_ZOH_CORNER | + TXTRI_FORMAT_ORIGIN_FOH_CORNER | + TXTRI_FORMAT_COLOR_R5G6B5 | + TXTRI_FORMAT_U_CLAMP | + TXTRI_FORMAT_V_CLAMP | + 0x00001000; + nvdev->state3d[1].filter = TXTRI_FILTER_TEXTUREMIN_LINEAR | + TXTRI_FILTER_TEXTUREMAG_LINEAR; + nvdev->state3d[1].blend = TXTRI_BLEND_TEXTUREMAPBLEND_COPY | + TXTRI_BLEND_OPERATION_MUX_TALPHAMSB | + TXTRI_BLEND_SHADEMODE_GOURAUD | + TXTRI_BLEND_TEXTUREPERSPECTIVE_ENABLE | + TXTRI_BLEND_SRCBLEND_ONE | + TXTRI_BLEND_DESTBLEND_ZERO; + nvdev->state3d[1].control = TXTRI_CONTROL_ALPHAFUNC_ALWAYS | + TXTRI_CONTROL_ORIGIN_CENTER | + TXTRI_CONTROL_ZFUNC_ALWAYS | + TXTRI_CONTROL_CULLMODE_NONE | + TXTRI_CONTROL_DITHER_ENABLE | + TXTRI_CONTROL_Z_FORMAT_FIXED; + nvdev->state3d[1].fog = 0; + + /* clear color buffer */ + memset( dfb_gfxcard_memory_virtual( device, + nvdev->buf_offset[0] ), 0xFF, 8 ); + } + + /* write dma objects configuration */ + nv_store_dma( nvdrv, OBJ_DMA_IN, ADDR_DMA_IN, 0x00, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_NVM, + nvdev->fb_size, 0x00000000, DMA_FRAME_ACCESS_RDWR ); + + if (nvdev->use_dma) { + if (nvdev->use_agp) { + nv_store_dma( nvdrv, OBJ_DMA_OUT, ADDR_DMA_OUT, 0x02, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_AGP, + nvdev->dma_size, nvdev->agp_offset+nvdev->dma_offset, + DMA_FRAME_ACCESS_RDWR ); + } + else { + nv_store_dma( nvdrv, OBJ_DMA_OUT, ADDR_DMA_OUT, 0x02, + DMA_FLAG_PAGE_TABLE | DMA_FLAG_PAGE_ENTRY_LINEAR | + DMA_FLAG_ACCESS_RDWR | DMA_FLAG_TARGET_NVM, + nvdev->dma_size, nvdev->fb_offset+nvdev->dma_offset, + DMA_FRAME_ACCESS_RDWR ); + } + } + + /* write graphics objects configuration */ + nv_store_object( nvdrv, OBJ_SURFACES2D, ADDR_SURFACES2D, 0x42, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_CLIP, ADDR_CLIP, 0x19, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_BETA1, ADDR_BETA1, 0x12, 0, 0, 0 ); + nv_store_object( nvdrv, OBJ_BETA4, ADDR_BETA4, 0x72, 0, 0, 0 ); + + nv_store_object( nvdrv, OBJ_RECTANGLE, ADDR_RECTANGLE, 0x5E, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TRIANGLE, ADDR_TRIANGLE, 0x5D, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_LINE, ADDR_LINE, 0x5C, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH, ADDR_DMA_IN, ADDR_DMA_IN ); + + switch (nvdev->arch) { + case NV_ARCH_04: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x1F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x37, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_COPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x54, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_COPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x53, 0, 0, 0 ); + break; + + case NV_ARCH_05: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x5F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x63, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x54, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x53, 0, 0, 0 ); + break; + + case NV_ARCH_10: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x5F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x89, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x94, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x93, 0, 0, 0 ); + break; + + case NV_ARCH_20: + case NV_ARCH_30: + default: + nv_store_object( nvdrv, OBJ_SCREENBLT, ADDR_SCREENBLT, 0x9F, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_IMAGEBLT, ADDR_IMAGEBLT, 0x65, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SCALEDIMAGE, ADDR_SCALEDIMAGE, 0x89, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_STRETCHEDIMAGE, ADDR_STRETCHEDIMAGE, 0x66, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CONVERSION_DITHER | + CTX_FLAG_CTX_SURFACE0, ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_TEXTRIANGLE, ADDR_TEXTRIANGLE, 0x94, + CTX_FLAG_USER_CLIP | CTX_FLAG_PATCH_SRCCOPY | + CTX_FLAG_PATCH | CTX_FLAG_CTX_SURFACE0, + ADDR_DMA_IN, ADDR_DMA_IN ); + nv_store_object( nvdrv, OBJ_SURFACES3D, ADDR_SURFACES3D, 0x93, 0, 0, 0 ); + break; + } + + /* assign default objects to subchannels */ + nvdev->subchannel_object[SUBC_SURFACES2D] = OBJ_SURFACES2D; + nvdev->subchannel_object[SUBC_CLIP] = OBJ_CLIP; + nvdev->subchannel_object[SUBC_RECTANGLE] = OBJ_RECTANGLE; + nvdev->subchannel_object[SUBC_TRIANGLE] = OBJ_TRIANGLE; + nvdev->subchannel_object[SUBC_LINE] = OBJ_LINE; + nvdev->subchannel_object[SUBC_SCREENBLT] = OBJ_SCREENBLT; + nvdev->subchannel_object[SUBC_SCALEDIMAGE] = OBJ_SCALEDIMAGE; + nvdev->subchannel_object[SUBC_TEXTRIANGLE] = OBJ_TEXTRIANGLE; + + if (nvdev->arch == NV_ARCH_04) { + nvdev->drawing_operation = OPERATION_COPY; + nvdev->scaler_operation = OPERATION_COPY; + nvdev->scaler_filter = 0; + nvdev->system_operation = OPERATION_COPY; + } else { + nvdev->drawing_operation = OPERATION_SRCCOPY; + nvdev->scaler_operation = OPERATION_SRCCOPY; + nvdev->scaler_filter = SCALER_IN_FORMAT_ORIGIN_CENTER | + SCALER_IN_FORMAT_FILTER_LINEAR; + nvdev->system_operation = OPERATION_SRCCOPY; + } + + nvAfterSetVar( driver_data, device_data ); + + return DFB_OK; +} + +static void +driver_close_device( CoreGraphicsDevice *device, + void *driver_data, + void *device_data ) +{ + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) device_data; + + D_DEBUG( "DirectFB/NVidia: Performance Monitoring:\n" ); + D_DEBUG( "DirectFB/NVidia: %9d nv_wait* calls\n", + nvdev->waitfree_calls ); + D_DEBUG( "DirectFB/NVidia: %9d register writes\n", + nvdev->waitfree_sum ); + D_DEBUG( "DirectFB/NVidia: %9d FIFO/DMA wait cycles (depends on CPU)\n", + nvdev->free_waitcycles ); + D_DEBUG( "DirectFB/NVidia: %9d IDLE wait cycles (depends on CPU)\n", + nvdev->idle_waitcycles ); + D_DEBUG( "DirectFB/NVidia: %9d FIFO/DMA space cache hits (depends on CPU)\n", + nvdev->cache_hits ); + D_DEBUG( "DirectFB/NVidia: Conclusion:\n" ); + D_DEBUG( "DirectFB/NVidia: Average register writes/nv_wait* call:%.2f\n", + nvdev->waitfree_sum/(float)(nvdev->waitfree_calls ? : 1) ); + D_DEBUG( "DirectFB/NVidia: Average wait cycles/nv_wait* call: %.2f\n", + nvdev->free_waitcycles/(float)(nvdev->waitfree_calls ? : 1) ); + D_DEBUG( "DirectFB/NVidia: Average FIFO/DMA space cache hits: %02d%%\n", + (int)(100 * nvdev->cache_hits/ + (float)(nvdev->waitfree_calls ? : 1)) ); + + /* reset channel mode to PIO to avoid crash in rivafb */ + if (nvdev->use_dma) { + nvdev->use_dma = false; + nvAfterSetVar( driver_data, device_data ); + } +} + +static void +driver_close_driver( CoreGraphicsDevice *device, + void *driver_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + + dfb_gfxcard_unmap_mmio( device, nvdrv->mmio_base, -1 ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia.h new file mode 100755 index 0000000..9b9062c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia.h @@ -0,0 +1,238 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_H__ +#define __NVIDIA_H__ + +#include <dfb_types.h> + +#include <core/state.h> +#include <core/screens.h> +#include <core/layers.h> + + +/* + * Object's identifier + */ +enum { + OBJ_DMA_IN = 0x00800000, + OBJ_SURFACES2D = 0x00800001, + OBJ_SURFACES3D = 0x00800002, + OBJ_CLIP = 0x00800003, + OBJ_BETA1 = 0x00800004, + OBJ_BETA4 = 0x00800005, + OBJ_RECTANGLE = 0x00800010, + OBJ_TRIANGLE = 0x00800011, + OBJ_LINE = 0x00800012, + OBJ_SCREENBLT = 0x00800013, + OBJ_IMAGEBLT = 0x00800014, + OBJ_SCALEDIMAGE = 0x00800015, + OBJ_STRETCHEDIMAGE = 0x00800016, + OBJ_TEXTRIANGLE = 0x00800017, + OBJ_DMA_OUT = 0x00800018 +}; + +/* + * Object's offset into context table [PRAMIN + (address)*16] + */ +enum { + ADDR_DMA_IN = 0x1160, + ADDR_SURFACES2D = 0x1162, + ADDR_SURFACES3D = 0x1163, + ADDR_CLIP = 0x1164, + ADDR_BETA1 = 0x1165, + ADDR_BETA4 = 0x1166, + ADDR_RECTANGLE = 0x1167, + ADDR_TRIANGLE = 0x1168, + ADDR_LINE = 0x1169, + ADDR_SCREENBLT = 0x116A, + ADDR_IMAGEBLT = 0x116B, + ADDR_SCALEDIMAGE = 0x116C, + ADDR_STRETCHEDIMAGE = 0x116D, + ADDR_TEXTRIANGLE = 0x116E, + ADDR_DMA_OUT = 0x116F +}; + +/* + * Object's subchannel + */ +enum { + SUBC_SURFACES2D = 0, + SUBC_SURFACES3D = 0, + SUBC_BETA1 = 0, + SUBC_BETA4 = 0, + SUBC_CLIP = 1, + SUBC_RECTANGLE = 2, + SUBC_TRIANGLE = 3, + SUBC_LINE = 4, + SUBC_SCREENBLT = 5, + SUBC_IMAGEBLT = 5, + SUBC_SCALEDIMAGE = 6, + SUBC_STRETCHEDIMAGE = 6, + SUBC_TEXTRIANGLE = 7 +}; + + +#define SMF_DRAWING_COLOR (SMF_COLOR << 16) +#define SMF_BLITTING_COLOR (SMF_COLOR << 17) +#define SMF_SOURCE_TEXTURE (SMF_SOURCE << 1) + +typedef struct { + StateModificationFlags set; + + u32 fb_offset; + u32 fb_size; + u32 agp_offset; + + DFBSurfacePixelFormat dst_format; + u32 dst_offset; + u32 dst_pitch; + bool dst_422; + + DFBSurfacePixelFormat src_format; + u32 src_offset; + u8 *src_address; + u32 src_pitch; + u32 src_width; + u32 src_height; + bool src_system; + bool src_interlaced; + CoreSurfaceBufferLock *src_lock; + + DFBRectangle clip; + + u32 color2d; + u32 color3d; + + DFBSurfaceDrawingFlags drawingflags; + DFBSurfaceBlittingFlags blittingflags; + + const s32 *matrix; + + /* NVRectangle/NVTriangle/NVLine registers */ + u32 drawing_operation; // SetOperation + + /* NVScaledImage registers */ + u32 scaler_operation; // SetOperation + u32 scaler_format; // SetColorFormat + u32 scaler_filter; // SetImageInFormat + + /* NVImageBlt/NVStretchedImage registers */ + u32 system_operation; // SetOperation + u32 system_format; // SetColorFormat + + /* Remember value of NVBeta1 & NVBeta4 */ + bool beta1_set; + u32 beta1_val; + bool beta4_set; + u32 beta4_val; + + /* 3D stuff */ + bool enabled_3d; // 3d engine enabled + u32 buf_offset[2]; // reserved buffers + CoreSurfaceBuffer *src_texture; // current source for TextureTriangles + u32 max_texture_size; + + struct { + bool modified; + u32 colorkey; + u32 offset; + u32 format; + u32 filter; + u32 blend; + u32 control; + u32 fog; + } state3d[2]; // 0 => drawing | 1 => blitting + + /* Remember subchannels configuration */ + u32 subchannel_object[8]; + + /* Chipsets informations */ + u32 chip; + u32 arch; + + /* AGP control */ + bool use_agp; + int agp_key; + unsigned int agp_aper_base; + unsigned int agp_aper_size; + + /* DMA control */ + bool use_dma; + unsigned int dma_size; + unsigned int dma_offset; + unsigned int dma_max; + unsigned int dma_cur; + unsigned int dma_free; + unsigned int dma_put; + unsigned int dma_get; + volatile u32 *cmd_ptr; + + /* FIFO control */ + unsigned int fifo_free; + + /* for performance monitoring */ + unsigned int waitfree_sum; + unsigned int waitfree_calls; + unsigned int free_waitcycles; + unsigned int idle_waitcycles; + unsigned int cache_hits; +} NVidiaDeviceData; + + +enum { + NV_ARCH_04 = 0x04, + NV_ARCH_05 = 0x05, + NV_ARCH_10 = 0x10, + NV_ARCH_20 = 0x20, + NV_ARCH_30 = 0x30 +}; + +typedef struct { + CoreGraphicsDevice *device; + NVidiaDeviceData *device_data; + + volatile void *fb_base; + volatile void *agp_base; + volatile void *mmio_base; + volatile void *dma_base; +} NVidiaDriverData; + + +extern ScreenFuncs nvidiaPrimaryScreenFuncs; +extern ScreenFuncs OldPrimaryScreenFuncs; +extern void *OldPrimaryScreenDriverData; + +extern DisplayLayerFuncs nvidiaPrimaryLayerFuncs; +extern DisplayLayerFuncs OldPrimaryLayerFuncs; +extern void *OldPrimaryLayerDriverData; + +extern DisplayLayerFuncs nvidiaOverlayFuncs; + + +#endif /* __NVIDIA_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c new file mode 100755 index 0000000..63e1728 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.c @@ -0,0 +1,549 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +#include <directfb.h> + +#include <direct/messages.h> +#include <direct/memcpy.h> + +#include <core/coredefs.h> +#include <core/coretypes.h> + +#include <core/gfxcard.h> +#include <core/surface.h> + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_2d.h" + + +static void +nv_copy32( volatile u32 *dst, u8 *src, int n ) +{ + u32 *D = (u32*) dst; + u32 *S = (u32*) src; + +#ifdef ARCH_X86 + __asm__ __volatile__( + "rep; movsl" + : "=&D" (D), "=&S" (S) + : "c" (n), "0" (D), "1" (S) + : "memory" ); +#else + do { + *D++ = *S++; + } while (--n); +#endif +} + +static void +nv_copy16( volatile u32 *dst, u8 *src, int n ) +{ + u32 *D = (u32*) dst; + u16 *S = (u16*) src; + +#ifdef ARCH_X86 + __asm__ __volatile__( + "rep; movsl" + : "=&D" (D), "=&S" (S) + : "c" (n/2), "0" (D), "1" (S) + : "memory" ); +#else + for (; n > 1; n -= 2) { + *D++ = *((u32*)S); + S += 2; + } +#endif + + if (n & 1) + *D = *S; +} + +static inline bool +nv_clip_source( DFBRectangle *rect, u32 width, u32 height ) +{ + if (rect->x >= width || rect->y >= height) + return false; + + if (rect->x < 0) { + rect->w += rect->x; + rect->x = 0; + } + if (rect->y < 0) { + rect->h += rect->y; + rect->y = 0; + } + + rect->w = MIN( rect->w, width - rect->x ); + rect->h = MIN( rect->h, height - rect->y ); + + return (rect->w > 0 && rect->h > 0); +} + + +#define M_TRANSFORM(x, y, retx, rety, m) { \ + s32 _x, _y; \ + _x = ((s64)(x) * (m)[0] + (y) * (m)[1] + (m)[2] + 0x8000) >> 16; \ + _y = ((s64)(x) * (m)[3] + (y) * (m)[4] + (m)[5] + 0x8000) >> 16; \ + retx = _x; \ + rety = _y; \ +} + + +bool nvFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->matrix) { + int x1 = rect->x, x2 = rect->x+rect->w; + int y1 = rect->y, y2 = rect->y+rect->h; + int x, y; + + nv_begin( SUBC_TRIANGLE, TRI_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + } + else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_RECTANGLE, RECT_TOP_LEFT, 2 ); + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + } + + return true; +} + +bool nvFillTriangle2D( void *drv, void *dev, DFBTriangle *tri ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->matrix) { + M_TRANSFORM( tri->x1, tri->y1, tri->x1, tri->y1, nvdev->matrix ); + M_TRANSFORM( tri->x2, tri->y3, tri->x2, tri->y2, nvdev->matrix ); + M_TRANSFORM( tri->x3, tri->y3, tri->x3, tri->y3, nvdev->matrix ); + } + + nv_begin( SUBC_TRIANGLE, TRI_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_TRIANGLE, TRI_POINT0, 3 ); + nv_outr( (tri->y1 << 16) | (tri->x1 & 0xFFFF) ); + nv_outr( (tri->y2 << 16) | (tri->x2 & 0xFFFF) ); + nv_outr( (tri->y3 << 16) | (tri->x3 & 0xFFFF) ); + + return true; +} + +bool nvDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->dst_422) { + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->matrix) { + int x1 = rect->x, x2 = rect->x+rect->w; + int y1 = rect->y, y2 = rect->y+rect->h; + int x, y; + + nv_begin( SUBC_LINE, LINE_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_LINE, LINE_POINT0, 8 ); + /* top */ + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* right */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* bottom */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + /* left */ + nv_outr( (y << 16) | (x & 0xFFFF) ); + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_outr( (y << 16) | (x & 0xFFFF) ); + } + else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_RECTANGLE, RECT_TOP_LEFT, 8 ); + /* top */ + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (1 << 16) | (rect->w & 0xFFFF) ); + /* bottom */ + nv_outr( ((rect->y + rect->h - 1) << 16) | (rect->x & 0xFFFF) ); + nv_outr( (1 << 16) | (rect->w & 0xFFFF) ); + /* left */ + nv_outr( ((rect->y + 1) << 16) | (rect->x & 0xFFFF) ); + nv_outr( ((rect->h - 2) << 16) | 1 ); + /* right */ + nv_outr( ((rect->y + 1) << 16) | ((rect->x + rect->w - 1) & 0xFFFF) ); + nv_outr( ((rect->h - 2) << 16) | 1 ); + } + + return true; +} + +bool nvDrawLine2D( void *drv, void *dev, DFBRegion *line ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->matrix) { + M_TRANSFORM( line->x1, line->y1, line->x1, line->y1, nvdev->matrix ); + M_TRANSFORM( line->x2, line->y2, line->x2, line->y2, nvdev->matrix ); + } + + nv_begin( SUBC_LINE, LINE_COLOR, 1 ); + nv_outr( nvdev->color2d ); + + nv_begin( SUBC_LINE, LINE_POINT0, 2 ); + nv_outr( (line->y1 << 16) | (line->x1 & 0xFFFF) ); + nv_outr( (line->y2 << 16) | (line->x2 & 0xFFFF) ); + + return true; +} + +bool nvBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE || nvdev->matrix) { + DFBRectangle dr = { dx, dy, rect->w, rect->h }; + return nvStretchBlit( drv, dev, rect, &dr ); + } + + if (nvdev->dst_422) { + dx /= 2; + rect->x /= 2; + rect->w = (rect->w+1) >> 1; + } + + if (nvdev->blittingflags || nvdev->src_format != nvdev->dst_format) { + DFBRectangle *clip = &nvdev->clip; + u32 src_width = (nvdev->src_width + 1) & ~1; + u32 src_height = (nvdev->src_height + 1) & ~1; + u32 filter = 0; + + if (nvdev->dst_422) + src_width >>= 1; + + if (nvdev->arch > NV_ARCH_04) + filter = SCALER_IN_FORMAT_ORIGIN_CORNER | + SCALER_IN_FORMAT_FILTER_NEAREST; + + nv_begin( SUBC_SCALEDIMAGE, SCALER_COLOR_FORMAT, 1 ); + nv_outr( nvdev->scaler_format ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_CLIP_POINT, 6 ); + nv_outr( (clip->y << 16) | (clip->x & 0xFFFF) ); + nv_outr( (clip->h << 16) | (clip->w & 0xFFFF) ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + nv_outr( 0x100000 ); + nv_outr( 0x100000 ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_IN_SIZE, 4 ); + nv_outr( (src_height << 16) | (src_width & 0xFFFF) ); + nv_outr( (nvdev->src_pitch & 0xFFFF) | filter ); + nv_outr( nvdev->src_offset ); + nv_outr( (rect->y << 20) | ((rect->x<<4) & 0xFFFF) ); + } + else { + nv_begin( SUBC_SCREENBLT, BLIT_TOP_LEFT_SRC, 3 ); + nv_outr( (rect->y << 16) | (rect->x & 0xFFFF) ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + } + + return true; +} + +bool nvBlitFromCPU( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + u8 *src = nvdev->src_address; + u32 src_w; + u32 src_h; + int w, h, n; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE || nvdev->matrix) { + DFBRectangle dr = { dx, dy, rect->x, rect->y }; + return nvStretchBlitFromCPU( drv, dev, rect, &dr ); + } + + if (!nv_clip_source( rect, nvdev->src_width, nvdev->src_height )) + return true; + + src_w = (DFB_BYTES_PER_PIXEL(nvdev->src_format) == 2) + ? ((rect->w + 1) & ~1) : rect->w; + src_h = rect->h; + + nv_begin( SUBC_IMAGEBLT, IBLIT_COLOR_FORMAT, 1 ); + nv_outr( nvdev->system_format ); + + nv_begin( SUBC_IMAGEBLT, IBLIT_POINT, 3 ); + nv_outr( (dy << 16) | (dx & 0xFFFF) ); + nv_outr( (rect->h << 16) | (rect->w & 0xFFFF) ); + nv_outr( (src_h << 16) | (src_w & 0xFFFF) ); + + n = nvdev->use_dma ? 256 : 128; + + switch (nvdev->src_format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + src += rect->y * nvdev->src_pitch + rect->x * 2; + for (h = rect->h; h--;) { + u8 *s = src; + + for (w = rect->w; w >= n*2; w -= n*2) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, (w+1)>>1 ); + nv_copy16( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + + default: + src += rect->y * nvdev->src_pitch + rect->x * 4; + for (h = rect->h; h--;) { + u8 *s = src; + + for (w = rect->w; w >= n; w -= n) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_IMAGEBLT, IBLIT_PIXEL0, w ); + nv_copy32( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + } + + return true; +} + +bool nvStretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRectangle *cr = &nvdev->clip; + u32 src_width = (nvdev->src_width + 1) & ~1; + u32 src_height = (nvdev->src_height + 1) & ~1; + + if (nvdev->dst_422) { + sr->x /= 2; + sr->w = (sr->w+1) >> 1; + dr->x /= 2; + dr->w = (dr->w+1) >> 1; + src_width >>= 1; + } + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h = (sr->h+1) / 2; + } + + if (nvdev->matrix) { + int x1, y1, x2, y2; + + if (!nvdev->matrix[0] || !nvdev->matrix[4]) + return true; + + M_TRANSFORM( dr->x, dr->y, x1, y1, nvdev->matrix ); + M_TRANSFORM( dr->x+dr->w, dr->y+dr->h, x2, y2, nvdev->matrix ); + + dr->x = x1; dr->w = x2-x1; + dr->y = y1; dr->h = y2-y1; + } + + nv_begin( SUBC_SCALEDIMAGE, SCALER_COLOR_FORMAT, 1 ); + nv_outr( nvdev->scaler_format ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_CLIP_POINT, 6 ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + nv_outr( (dr->y << 16) | (dr->x & 0xFFFF) ); + nv_outr( (dr->h << 16) | (dr->w & 0xFFFF) ); + nv_outr( (sr->w << 20) / dr->w ); + nv_outr( (sr->h << 20) / dr->h ); + + nv_begin( SUBC_SCALEDIMAGE, SCALER_IN_SIZE, 4 ); + nv_outr( (src_height << 16) | (src_width & 0xFFFF) ); + nv_outr( (nvdev->src_pitch & 0xFFFF) | nvdev->scaler_filter ); + nv_outr( nvdev->src_offset ); + nv_outr( (sr->y << 20) | ((sr->x << 4) & 0xFFFF) ); + + return true; +} + +bool nvStretchBlitFromCPU( void *drv, void *dev, + DFBRectangle *sr, DFBRectangle *dr ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRectangle *cr = &nvdev->clip; + u8 *src = nvdev->src_address; + u32 src_w; + u32 src_h; + int w, h, n; + + if (!nv_clip_source( sr, nvdev->src_width, nvdev->src_height )) + return true; + + if (nvdev->blittingflags & DSBLIT_DEINTERLACE) { + sr->y /= 2; + sr->h /= 2; + } + + if (nvdev->matrix) { + int x1, y1, x2, y2; + + if (!nvdev->matrix[0] || !nvdev->matrix[4]) + return true; + + M_TRANSFORM( dr->x, dr->y, x1, y1, nvdev->matrix ); + M_TRANSFORM( dr->x+dr->w, dr->y+dr->h, x2, y2, nvdev->matrix ); + + dr->x = x1; dr->w = x2-x1; + dr->y = y1; dr->h = y2-y1; + } + + src_w = (DFB_BYTES_PER_PIXEL(nvdev->src_format) == 2) + ? ((sr->w + 1) & ~1) : sr->w; + src_h = sr->h; + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_COLOR_FORMAT, 1 ); + nv_outr( nvdev->system_format ); + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_IN_SIZE, 6 ); + nv_outr( (src_h << 16) | (src_w & 0xFFFF) ); + nv_outr( (dr->w << 20) / src_w ); + nv_outr( (dr->h << 20) / src_h ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + nv_outr( (dr->y << 20) | ((dr->x<<4) & 0xFFFF) ); + + n = nvdev->use_dma ? 256 : 128; + + switch (nvdev->src_format) { + case DSPF_ARGB1555: + case DSPF_RGB16: + src += sr->y * nvdev->src_pitch + sr->x * 2; + for (h = sr->h; h--;) { + u8 *s = src; + + for (w = sr->w; w >= n*2; w -= n*2) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, (w+1)>>1 ); + nv_copy16( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + + default: + src += sr->y * nvdev->src_pitch + sr->x * 4; + for (h = sr->h; h--;) { + u8 *s= src; + + for (w = sr->w; w >= n; w -= n) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, n ); + direct_memcpy( (void*)nvdev->cmd_ptr, s, n*4 ); + s += n*4; + } + if (w > 0) { + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_PIXEL0, w ); + nv_copy32( nvdev->cmd_ptr, s, w ); + } + + src += nvdev->src_pitch; + } + break; + } + + return true; +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h new file mode 100755 index 0000000..b195aef --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_2d.h @@ -0,0 +1,48 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_2D_H__ +#define __NVIDIA_2D_H__ + +bool nvFillRectangle2D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvFillTriangle2D( void *drv, void *dev, DFBTriangle *tri ); + +bool nvDrawRectangle2D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvDrawLine2D( void *drv, void *dev, DFBRegion *line ); + +bool nvBlit( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +bool nvBlitFromCPU( void *drv, void *dev, DFBRectangle *rect, int dx, int dy ); + +bool nvStretchBlit( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +bool nvStretchBlitFromCPU( void *drv, void *dev, DFBRectangle *sr, DFBRectangle *dr ); + +#endif /* __NVIDIA_2D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c new file mode 100755 index 0000000..ae8dffc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.c @@ -0,0 +1,522 @@ +/* + Copyright (C) 2004-2006 Claudio Ciccani <klan@users.sf.net> + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <math.h> + +#include <directfb.h> + +#include <direct/messages.h> +#include <direct/mem.h> +#include <direct/memcpy.h> + +#include <core/coredefs.h> +#include <core/coretypes.h> + +#include <core/gfxcard.h> +#include <core/surface.h> + +#include <gfx/convert.h> + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_3d.h" + + +static __inline__ u32 +f2d( float f ) { + union { + float f; + u32 d; + } t; + t.f = f; + return t.d; +} + +#define nv_setstate3d( state3d ) { \ + if ((state3d)->modified) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_COLOR_KEY, 7 ); \ + nv_outr( (state3d)->colorkey ); \ + nv_outr( (state3d)->offset ); \ + nv_outr( (state3d)->format ); \ + nv_outr( (state3d)->filter ); \ + nv_outr( (state3d)->blend ); \ + nv_outr( (state3d)->control ); \ + nv_outr( (state3d)->fog ); \ + \ + (state3d)->modified = false; \ + } \ +} + +#define nv_putvertex( i, x, y, z, w, col, spc, s, t ) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_VERTEX0+(i)*32, 8 ); \ + nv_outr( f2d( x ) ); \ + nv_outr( f2d( y ) ); \ + nv_outr( f2d( z ) ); \ + nv_outr( f2d( w ) ); \ + nv_outr( col ); \ + nv_outr( spc ); \ + nv_outr( f2d( s ) ); \ + nv_outr( f2d( t ) ); \ +} + +#define nv_emit_vertices( i, v0, v1, v2, v3, v4, v5, v6, v7 ) { \ + nv_begin( SUBC_TEXTRIANGLE, TXTRI_PRIMITIVE0+(i)*4, 1 ); \ + nv_outr( ((v7) << 28) | ((v6) << 24) | \ + ((v5) << 20) | ((v4) << 16) | \ + ((v3) << 12) | ((v2) << 8) | \ + ((v1) << 4) | (v0) ); \ +} + + +static void nv_load_texture( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ); + + +#define M_TRANSFORM(x, y, retx, rety, m) { \ + float _x, _y; \ + _x = ((x) * (m)[0] + (y) * (m)[1] + (m)[2]) / 65536.f; \ + _y = ((x) * (m)[3] + (y) * (m)[4] + (m)[5]) / 65536.f; \ + retx = _x; \ + rety = _y; \ +} + + +bool nvFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float x1, y1; + float x2, y2; + + x1 = rect->x; x2 = rect->x+rect->w; + y1 = rect->y; y2 = rect->y+rect->h; + + nv_setstate3d( &nvdev->state3d[0] ); + + if (nvdev->matrix) { + float x, y; + + M_TRANSFORM( x1, y1, x, y, nvdev->matrix ); + nv_putvertex( 0, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x2, y1, x, y, nvdev->matrix ); + nv_putvertex( 1, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x2, y2, x, y, nvdev->matrix ); + nv_putvertex( 2, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + M_TRANSFORM( x1, y2, x, y, nvdev->matrix ); + nv_putvertex( 3, x, y, 0, 1, nvdev->color3d, 0, 0, 0 ); + } + else { + nv_putvertex( 0, x1, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x2, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x2, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, x1, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + } + + nv_emit_vertices( 0, 0, 1, 2, 0, 2, 3, 0, 0 ); + + return true; +} + +bool nvFillTriangle3D( void *drv, void *dev, DFBTriangle *tri ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float x1, y1; + float x2, y2; + float x3, y3; + + x1 = tri->x1; x2 = tri->x2; x3 = tri->x3; + y1 = tri->y1; y2 = tri->y2; y3 = tri->y3; + if (nvdev->matrix) { + M_TRANSFORM( x1, y1, x1, y1, nvdev->matrix ); + M_TRANSFORM( x2, y2, x2, y2, nvdev->matrix ); + M_TRANSFORM( x3, y3, x3, y3, nvdev->matrix ); + } + + nv_setstate3d( &nvdev->state3d[0] ); + + nv_putvertex( 0, x1, y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x2, y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x3, y3, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + return true; +} + +bool nvDrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + DFBRegion r[4]; + int i; + + if (nvdev->matrix) { + DFBRegion line; + + /* top */ + line = (DFBRegion) { rect->x, rect->y, rect->x+rect->w, rect->y }; + nvDrawLine3D( drv, dev, &line ); + /* right */ + line = (DFBRegion) { rect->x+rect->w, rect->y, rect->x+rect->w, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + /* bottom */ + line = (DFBRegion) { rect->x, rect->y+rect->h, rect->x+rect->w, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + /* left */ + line = (DFBRegion) { rect->x, rect->y, rect->x, rect->y+rect->h }; + nvDrawLine3D( drv, dev, &line ); + + return true; + } + + /* top */ + r[0].x1 = rect->x; + r[0].y1 = rect->y; + r[0].x2 = rect->x + rect->w; + r[0].y2 = rect->y + 1; + + /* right */ + r[1].x1 = rect->x + rect->w - 1; + r[1].y1 = rect->y + 1; + r[1].x2 = rect->x + rect->w; + r[1].y2 = rect->y + rect->h - 1; + + /* bottom */ + r[2].x1 = rect->x; + r[2].y1 = rect->y + rect->h - 1; + r[2].x2 = rect->x + rect->w; + r[2].y2 = rect->y + rect->h; + + /* left */ + r[3].x1 = rect->x; + r[3].y1 = rect->y + 1; + r[3].x2 = rect->x + 1; + r[3].y2 = rect->y + rect->h - 1; + + nv_setstate3d( &nvdev->state3d[0] ); + + for (i = 0; i < 4; i++) { + nv_putvertex( 0, r[i].x1, r[i].y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, r[i].x2, r[i].y1, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, r[i].x2, r[i].y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, r[i].x1, r[i].y2, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 0, 1, 2, 0, 2, 3, 0, 0 ); + } + + return true; +} + +bool nvDrawLine3D( void *drv, void *dev, DFBRegion *line ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float xinc, yinc; + float x1, y1; + float x2, y2; + float dx, dy; + + x1 = line->x1; x2 = line->x2; + y1 = line->y1; y2 = line->y2; + if (nvdev->matrix) { + M_TRANSFORM( x1, y1, x1, y1, nvdev->matrix ); + M_TRANSFORM( x2, y2, x2, y2, nvdev->matrix ); + + dx = fabs(x2 - x1); + dy = fabs(y2 - y1); + } + else { + dx = abs(line->x2 - line->x1); + dy = abs(line->y2 - line->y1); + } + + if (dx > dy) { /* more horizontal */ + xinc = 0.0; + yinc = 0.5; + } else { /* more vertical */ + xinc = 0.5; + yinc = 0.0; + } + + nv_setstate3d( &nvdev->state3d[0] ); + + nv_putvertex( 0, x1 - xinc, y1 - yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 1, x1 + xinc, y1 + yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 2, x2 + xinc, y2 + yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + nv_putvertex( 3, x2 - xinc, y2 - yinc, 0, 1, nvdev->color3d, 0, 0, 0 ); + + nv_emit_vertices( 0, 2, 0, 1, 3, 0, 2, 0, 0 ); + + return true; +} + +bool nvTextureTriangles( void *drv, void *dev, DFBVertex *ve, + int num, DFBTriangleFormation formation ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) drv; + NVidiaDeviceData *nvdev = (NVidiaDeviceData*) dev; + float s_scale; + float t_scale; + int i; + + /* load source texture into texture buffer */ + nv_load_texture( nvdrv, nvdev ); + + s_scale = (float)nvdev->src_width / + (float)(1 << ((nvdev->state3d[1].format >> 16) & 0xF)); + t_scale = (float)nvdev->src_height / + (float)(1 << ((nvdev->state3d[1].format >> 20) & 0xF)); + + for (i = 0; i < num; i++) { + if (nvdev->matrix) + M_TRANSFORM( ve[i].x, ve[i].y, ve[i].x, ve[i].y, nvdev->matrix ); + ve[i].x += 0.5; + ve[i].y += 0.5; + ve[i].s *= s_scale; + ve[i].t *= t_scale; + } + + nv_setstate3d( &nvdev->state3d[1] ); + + switch (formation) { + case DTTF_LIST: + for (i = 0; i < num; i += 3) { + nv_putvertex( 0, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_putvertex( 1, ve[i+1].x, ve[i+1].y, ve[i+1].z, ve[i+1].w, + nvdev->color3d, 0, ve[i+1].s, ve[i+1].t ); + nv_putvertex( 2, ve[i+2].x, ve[i+2].y, ve[i+2].z, ve[i+2].w, + nvdev->color3d, 0, ve[i+2].s, ve[i+2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + case DTTF_STRIP: + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[1].x, ve[1].y, ve[1].z, ve[1].w, + nvdev->color3d, 0, ve[1].s, ve[1].t ); + nv_putvertex( 2, ve[2].x, ve[2].y, ve[2].z, ve[2].w, + nvdev->color3d, 0, ve[2].s, ve[2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + for (i = 3; i < num; i++) { + nv_putvertex( 0, ve[i-2].x, ve[i-2].y, ve[i-2].z, ve[i-2].w, + nvdev->color3d, 0, ve[i-2].s, ve[i-2].t ); + nv_putvertex( 1, ve[i-1].x, ve[i-1].y, ve[i-1].z, ve[i-1].w, + nvdev->color3d, 0, ve[i-1].s, ve[i-1].t ); + nv_putvertex( 2, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + case DTTF_FAN: + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[1].x, ve[1].y, ve[1].z, ve[1].w, + nvdev->color3d, 0, ve[1].s, ve[1].t ); + nv_putvertex( 2, ve[2].x, ve[2].y, ve[2].z, ve[2].w, + nvdev->color3d, 0, ve[2].s, ve[2].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + + for (i = 3; i < num; i++) { + nv_putvertex( 0, ve[0].x, ve[0].y, ve[0].z, ve[0].w, + nvdev->color3d, 0, ve[0].s, ve[0].t ); + nv_putvertex( 1, ve[i-1].x, ve[i-1].y, ve[i-1].z, ve[i-1].w, + nvdev->color3d, 0, ve[i-1].s, ve[i-1].t ); + nv_putvertex( 2, ve[i].x, ve[i].y, ve[i].z, ve[i].w, + nvdev->color3d, 0, ve[i].s, ve[i].t ); + nv_emit_vertices( 0, 0, 1, 2, 0, 0, 0, 0, 0 ); + } + break; + + default: + D_BUG( "unexpected triangle formation" ); + return false; + } + + return true; +} + +/* + * Surface to Texture conversion routines. + */ + +#define VINC 0xAAAAAAAC +#define VMASK 0x55555555 +#define UINC 0x55555558 +#define UMASK 0xAAAAAAAA + +static inline void +a8_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = ((src[i+0] & 0xF0) << 24) | + ((src[i+1] & 0xF0) << 8) | + 0x0FFF0FFF; +#else + dst[(u|v)/4] = ((src[i+0] & 0xF0) << 8) | + ((src[i+1] & 0xF0) << 24) | + 0x0FFF0FFF; +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ((src[width-1] & 0xF0) << 8) | 0x0FFF; + } + + src += pitch; + } +} + +static inline void +rgb16_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width/2; i++, u = (u + UINC) & UMASK) + dst[(u|v)/4] = ((u32*) src)[i]; + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ((u16*) src)[width-1]; + } + + src += pitch; + } +} + +static inline void +rgb32_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { + register u32 pix0, pix1; + pix0 = ((u32*) src)[i]; + pix0 = RGB32_TO_RGB16( pix0 ); + pix1 = ((u32*) src)[i+1]; + pix1 = RGB32_TO_RGB16( pix1 ); +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = (pix0 << 16) | pix1; +#else + dst[(u|v)/4] = pix0 | (pix1 << 16); +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = RGB32_TO_RGB16( ((u32*) src)[width-1] ); + } + + src += pitch; + } +} + +static inline void +argb_to_tex( u32 *dst, u8 *src, int pitch, int width, int height ) +{ + u32 u, v; + int i; + + for (v = 0; height--; v = (v + VINC) & VMASK) { + for (i = 0, u = 0; i < width; i += 2, u = (u + UINC) & UMASK) { + register u32 pix0, pix1; + pix0 = ((u32*) src)[i]; + pix0 = ARGB_TO_ARGB4444( pix0 ); + pix1 = ((u32*) src)[i+1]; + pix1 = ARGB_TO_ARGB4444( pix1 ); +#ifdef WORDS_BIGENDIAN + dst[(u|v)/4] = (pix0 << 16) | pix1; +#else + dst[(u|v)/4] = pix0 | (pix1 << 16); +#endif + } + + if (width & 1) { + u = (u + UINC) & UMASK; + dst[(u|v)/4] = ARGB_TO_ARGB4444( ((u32*) src)[width-1] ); + } + + src += pitch; + } +} + +static void nv_load_texture( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev ) +{ + CoreSurfaceBuffer *buffer = nvdev->src_texture; + u32 *dst; + + dst = dfb_gfxcard_memory_virtual( nvdrv->device, nvdev->buf_offset[1] ); + +#if 0 + if (nvdev->src_interlaced) { + if (surface->caps & DSCAPS_SEPARATED) { + if (surface->field) + field_offset = nvdev->src_height * src_pitch; + } else { + if (surface->field) + field_offset = src_pitch; + src_pitch *= 2; + } + } +#endif + + switch (buffer->format) { + case DSPF_A8: + a8_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_ARGB1555: + case DSPF_RGB16: + rgb16_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_RGB32: + rgb32_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + case DSPF_ARGB: + argb_to_tex( dst, nvdev->src_lock->addr, nvdev->src_lock->pitch, + nvdev->src_width, nvdev->src_height ); + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h new file mode 100755 index 0000000..ade71f7 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_3d.h @@ -0,0 +1,36 @@ +/* + Copyright (C) 2004-2006 Claudio Ciccani <klan@users.sf.net> + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_3D_H__ +#define __NVIDIA_3D_H__ + + +bool nvFillRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvFillTriangle3D( void *drv, void *dev, DFBTriangle *tri ); + +bool nvDrawRectangle3D( void *drv, void *dev, DFBRectangle *rect ); + +bool nvDrawLine3D( void *drv, void *dev, DFBRegion *line ); + +bool nvTextureTriangles( void *drv, void *dev, DFBVertex *vertices, + int num, DFBTriangleFormation formation ); + + +#endif /* __NVIDIA_3D_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h new file mode 100755 index 0000000..2858947 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_accel.h @@ -0,0 +1,246 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_ACCEL_H__ +#define __NVIDIA_ACCEL_H__ + +#include <unistd.h> + +#include "nvidia.h" +#include "nvidia_regs.h" + + +static __inline__ void +nv_out8( volatile void *mmioaddr, u32 reg, u8 value ) +{ + *((volatile u8*)(mmioaddr+reg)) = value; +} + +static __inline__ void +nv_out16( volatile void *mmioaddr, u32 reg, u16 value ) +{ + *((volatile u16*)(mmioaddr+reg)) = value; +} + +static __inline__ void +nv_out32( volatile void *mmioaddr, u32 reg, u32 value ) +{ + *((volatile u32*)(mmioaddr+reg)) = value; +} + +static __inline__ u8 +nv_in8( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u8*)(mmioaddr+reg)); +} + +static __inline__ u16 +nv_in16( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u16*)(mmioaddr+reg)); +} + +static __inline__ u32 +nv_in32( volatile void *mmioaddr, u32 reg ) +{ + return *((volatile u32*)(mmioaddr+reg)); +} + +static __inline__ void +nv_outcrtc( volatile void *mmioaddr, u8 reg, u8 value ) +{ + nv_out8( mmioaddr, PCIO_CRTC_INDEX, reg ); + nv_out8( mmioaddr, PCIO_CRTC_DATA, value ); +} + +static __inline__ u8 +nv_incrtc( volatile void *mmioaddr, u8 reg ) +{ + nv_out8( mmioaddr, PCIO_CRTC_INDEX, reg ); + return nv_in8( mmioaddr, PCIO_CRTC_DATA ); +} + +#define WAIT_MAX 10000000 + +static inline void +nv_waitidle( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ) +{ + u32 status; + int waitcycles = 0; + + do { + status = nv_in32( nvdrv->mmio_base, PGRAPH_STATUS ); + if (++waitcycles > WAIT_MAX) { + D_BREAK( "Engine timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (status & PGRAPH_STATUS_STATE_BUSY); + + nvdev->idle_waitcycles += waitcycles; +} + +/* + * FIFO control + */ + +static inline void +nv_waitfifo( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + unsigned int space ) +{ + volatile void *mmio = nvdrv->mmio_base; + int waitcycles = 0; + + nvdev->waitfree_sum += (space); + nvdev->waitfree_calls++; + + if (nvdev->fifo_free < space) { + do { +#ifdef WORDS_BIGENDIAN + nvdev->fifo_free = nv_in16( mmio, FIFO_FREE ) >> 2; +#else + nvdev->fifo_free = nv_in32( mmio, FIFO_FREE ) >> 2; +#endif + if (++waitcycles > WAIT_MAX) { + D_BREAK( "FIFO timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (nvdev->fifo_free < space); + + nvdev->free_waitcycles += waitcycles; + } else + nvdev->cache_hits++; + + nvdev->fifo_free -= space; +} + +/* + * DMA control + */ + +static inline void +nv_emitdma( NVidiaDriverData *nvdrv, NVidiaDeviceData *nvdev ) +{ + if (nvdev->dma_put != nvdev->dma_cur) { + volatile u8 scratch; + + /* flush MTRR buffers */ + scratch = nv_in8( nvdrv->fb_base, 0 ); + nv_out32( nvdrv->mmio_base, DMA_PUT, nvdev->dma_cur << 2 ); + + nvdev->dma_put = nvdev->dma_cur; + } +} + +static inline void +nv_waitdma( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + unsigned int space ) +{ + volatile void *mmio = nvdrv->mmio_base; + volatile void *ring = nvdrv->dma_base; + int waitcycles = 0; + + nvdev->waitfree_sum += (space); + nvdev->waitfree_calls++; + + if (nvdev->dma_free < space) { + do { + nvdev->dma_get = nv_in32( mmio, DMA_GET ) >> 2; + + if (nvdev->dma_put >= nvdev->dma_get) { + nvdev->dma_free = nvdev->dma_max - nvdev->dma_cur; + + if (nvdev->dma_free < space) { + /* rewind ring */ + nv_out32( ring, nvdev->dma_cur << 2, 0x20000000 ); + + if (!nvdev->dma_get) { + if (!nvdev->dma_put) { + nvdev->dma_cur = 1; + nv_emitdma( nvdrv, nvdev ); + } + + do { + nvdev->dma_get = nv_in32( mmio, DMA_GET ) >> 2; + if (++waitcycles > WAIT_MAX) { + D_BREAK( "DMA timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (!nvdev->dma_get); + } + + nvdev->dma_cur = 0; + nv_emitdma( nvdrv, nvdev ); + + nvdev->dma_free = nvdev->dma_get - 1; + } + } + else { + nvdev->dma_free = nvdev->dma_get - nvdev->dma_cur - 1; + } + + if (++waitcycles > WAIT_MAX) { + D_BREAK( "DMA timed out" ); + /* avoid card crash */ + _exit(-1); + } + } while (nvdev->dma_free < space); + + nvdev->free_waitcycles += waitcycles; + } else + nvdev->cache_hits++; + + nvdev->dma_free -= space; +} + +/* Begin writing into ring/fifo */ +#define nv_begin( subc, start, size ) { \ + if (nvdev->use_dma) { \ + nv_waitdma( nvdrv, nvdev, (size)+1 ); \ + nv_out32( nvdrv->dma_base, nvdev->dma_cur << 2, \ + ((size) << 18) | ((subc)*0x2000 + (start)) ); \ + nvdev->cmd_ptr = nvdrv->dma_base; \ + nvdev->cmd_ptr += nvdev->dma_cur + 1; \ + nvdev->dma_cur += (size) + 1; \ + D_ASSERT( nvdev->dma_cur <= nvdev->dma_max ); \ + } else { \ + nv_waitfifo( nvdrv, nvdev, size ); \ + nvdev->cmd_ptr = (nvdrv->mmio_base + FIFO_ADDRESS + \ + (subc)*0x2000 + (start)); \ + } \ +} + +/* Output to ring/register */ +#define nv_outr( value ) *nvdev->cmd_ptr++ = (value) + + +#endif /* __NVIDIA_ACCEL_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h new file mode 100755 index 0000000..a0e329f --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_objects.h @@ -0,0 +1,160 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_OBJECTS_H__ +#define __NVIDIA_OBJECTS_H__ + +#include "nvidia.h" +#include "nvidia_accel.h" + +/* Engine */ +#define ENGINE_SW 0 +#define ENGINE_GRAPHICS 1 +#define ENGINE_DVD 2 + + +static __inline__ u32 +nv_hashkey( u32 obj ) +{ + return ((obj >> 0) & 0x000001FF) ^ + ((obj >> 9) & 0x000001FF) ^ + ((obj >> 18) & 0x000001FF) ^ + ((obj >> 27) & 0x000001FF) ^ (0 << 5); /* channel 0 */ +} + + +/* DMA flags */ +#define DMA_FLAG_PAGE_TABLE (1 << 12) /* valid */ +#define DMA_FLAG_PAGE_ENTRY_NONLIN (0 << 13) +#define DMA_FLAG_PAGE_ENTRY_LINEAR (1 << 13) +#define DMA_FLAG_ACCESS_RDWR (0 << 14) +#define DMA_FLAG_ACCESS_RDONLY (1 << 14) +#define DMA_FLAG_ACCESS_WRONLY (2 << 14) +#define DMA_FLAG_TARGET_NVM (0 << 16) +#define DMA_FLAG_TARGET_NVM_TILED (1 << 16) +#define DMA_FLAG_TARGET_PCI (2 << 16) +#define DMA_FLAG_TARGET_AGP (3 << 16) + +/* DMA frame access */ +#define DMA_FRAME_UNKNOWN_FLAG (1 << 0) +#define DMA_FRAME_ACCESS_RDONLY (0 << 1) +#define DMA_FRAME_ACCESS_RDWR (1 << 1) + +static inline void +nv_store_dma( NVidiaDriverData *nvdrv, u32 obj, + u32 addr, u32 class, u32 flags, + u32 size, u32 frame, u32 access ) +{ + volatile void *mmio = nvdrv->mmio_base; + u32 key = nv_hashkey( obj ); + u32 ctx = addr | (ENGINE_SW << 16) | (1 << 31); + + /* NV_PRAMIN_RAMRO_0 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 0, class | flags ); + nv_out32( mmio, PRAMIN + (addr << 4) + 4, size - 1 ); + nv_out32( mmio, PRAMIN + (addr << 4) + 8, (frame & 0xFFFFF000) | access ); + nv_out32( mmio, PRAMIN + (addr << 4) + 12, (frame & 0xFFFFF000) | access ); + + /* store object id and context */ + nv_out32( mmio, PRAMHT + (key << 3) + 0, obj ); + nv_out32( mmio, PRAMHT + (key << 3) + 4, ctx ); +} + + +/* Context flags */ +#define CTX_FLAG_CHROMA_KEY (1 << 12) +#define CTX_FLAG_USER_CLIP (1 << 13) +#define CTX_FLAG_SWIZZLE (1 << 14) +#define CTX_FLAG_PATCH_COPY (0 << 15) +#define CTX_FLAG_PATCH_ROP (1 << 15) +#define CTX_FLAG_PATCH_BLEND (2 << 15) +#define CTX_FLAG_PATCH_SRCCOPY (3 << 15) +#define CTX_FLAG_PATCH_COLOR_MULTIPLY (4 << 15) +#define CTX_FLAG_PATCH_BLEND_PREMULTIPLIED (5 << 15) +#define CTX_FLAG_SYNCHRONIZE (1 << 18) +#define CTX_FLAG_ENDIAN_LITTLE (0 << 19) +#define CTX_FLAG_ENDIAN_BIG (1 << 19) +#define CTX_FLAG_CONVERSION_COMPAT (0 << 20) +#define CTX_FLAG_CONVERSION_DITHER (1 << 20) +#define CTX_FLAG_CONVERSION_TRUNC (2 << 20) +#define CTX_FLAG_CONVERSION_SUB_TRUNC (3 << 20) +#define CTX_FLAG_SINGLE_STEP (1 << 23) +#define CTX_FLAG_PATCH (1 << 24) /* valid */ +#define CTX_FLAG_CTX_SURFACE0 (1 << 25) /* valid */ +#define CTX_FLAG_CTX_SURFACE1 (1 << 26) /* valid */ +#define CTX_FLAG_CTX_PATTERN (1 << 27) /* valid */ +#define CTX_FLAG_CTX_ROP (1 << 28) /* valid */ +#define CTX_FLAG_CTX_BETA1 (1 << 29) /* valid */ +#define CTX_FLAG_CTX_BETA4 (1 << 30) /* valid */ + + +static inline void +nv_store_object( NVidiaDriverData *nvdrv, + u32 obj, u32 addr, + u32 class, u32 flags, + u32 dma0, u32 dma1 ) +{ + volatile void *mmio = nvdrv->mmio_base; + u32 key = nv_hashkey( obj ); + u32 ctx = addr | (ENGINE_GRAPHICS << 16) | (1 << 31); + + /* set the endian flag here, for simplicity */ +#ifdef WORDS_BIGENDIAN + flags |= CTX_FLAG_ENDIAN_BIG; +#endif + /* NV_PRAMIN_CTX_0 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 0, class | flags ); + /* NV_PRAMIN_CTX_1 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 4, 0x00000000 ); /* color */ + /* NV_PRAMIN_CTX_2 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 8, dma0 | (dma1 << 16) ); + /* NV_PRAMIN_CTX_3 */ + nv_out32( mmio, PRAMIN + (addr << 4) + 12, 0x00000000 ); /* traps */ + + /* store object id and context */ + nv_out32( mmio, PRAMHT + (key << 3) + 0, obj ); + nv_out32( mmio, PRAMHT + (key << 3) + 4, ctx ); +} + + +static inline void +nv_assign_object( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + int subc, + u32 object, + bool reset ) +{ + if (reset || nvdev->subchannel_object[subc] != object) { + nv_begin( subc, SET_OBJECT, 1 ); + nv_outr( object ); + + nvdev->subchannel_object[subc] = object; + } +} + +#endif /* __NVIDIA_OBJECTS_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c new file mode 100755 index 0000000..747f14c --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_overlay.c @@ -0,0 +1,566 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Oliver Schwartz <Oliver.Schwartz@gmx.de> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <math.h> + +#include <core/coredefs.h> +#include <core/surface.h> +#include <core/gfxcard.h> + +#include <core/layers.h> +#include <core/layer_context.h> +#include <core/layer_control.h> +#include <core/layer_region.h> +#include <core/layers_internal.h> + +#include <gfx/convert.h> + +#include <direct/memcpy.h> +#include <direct/messages.h> + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" + + +typedef struct { + CoreLayerRegionConfig config; + CoreSurface *videoSurface; + CoreSurfaceBufferLock *lock; + + short brightness; + short contrast; + short hue; + short saturation; + int field; + + struct { + u32 BUFFER; + u32 STOP; + u32 UVBASE_0; + u32 UVBASE_1; + u32 UVOFFSET_0; + u32 UVOFFSET_1; + u32 BASE_0; + u32 BASE_1; + u32 OFFSET_0; + u32 OFFSET_1; + u32 SIZE_IN_0; + u32 SIZE_IN_1; + u32 POINT_IN_0; + u32 POINT_IN_1; + u32 DS_DX_0; + u32 DS_DX_1; + u32 DT_DY_0; + u32 DT_DY_1; + u32 POINT_OUT_0; + u32 POINT_OUT_1; + u32 SIZE_OUT_0; + u32 SIZE_OUT_1; + u32 FORMAT_0; + u32 FORMAT_1; + } regs; +} NVidiaOverlayLayerData; + +static void ov0_set_regs ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfigFlags flags ); +static void ov0_calc_regs ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags flags ); +static void ov0_set_colorkey( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config ); +static void ov0_set_csc ( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0 ); + +#define OV0_SUPPORTED_OPTIONS \ + ( DLOP_DST_COLORKEY | DLOP_DEINTERLACING ) + +/**********************/ + + + +static int +ov0LayerDataSize( void ) +{ + return sizeof(NVidiaOverlayLayerData); +} + +static DFBResult +ov0InitLayer( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBDisplayLayerDescription *description, + DFBDisplayLayerConfig *config, + DFBColorAdjustment *adjustment ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + /* set capabilities and type */ + description->caps = DLCAPS_SURFACE | DLCAPS_SCREEN_LOCATION | + DLCAPS_BRIGHTNESS | DLCAPS_CONTRAST | + DLCAPS_SATURATION | DLCAPS_HUE | + DLCAPS_DST_COLORKEY | DLCAPS_DEINTERLACING; + description->type = DLTF_VIDEO | DLTF_STILL_PICTURE; + + /* set name */ + snprintf( description->name, + DFB_DISPLAY_LAYER_DESC_NAME_LENGTH, "NVidia Overlay" ); + + /* fill out the default configuration */ + config->flags = DLCONF_WIDTH | DLCONF_HEIGHT | + DLCONF_PIXELFORMAT | DLCONF_BUFFERMODE | + DLCONF_OPTIONS; + config->width = 640; + config->height = 480; + config->pixelformat = DSPF_YUY2; + config->buffermode = DLBM_FRONTONLY; + config->options = DLOP_NONE; + + /* fill out default color adjustment, + only fields set in flags will be accepted from applications */ + adjustment->flags = DCAF_BRIGHTNESS | DCAF_CONTRAST | + DCAF_SATURATION | DCAF_HUE; + adjustment->brightness = 0x8000; + adjustment->contrast = 0x8000; + adjustment->saturation = 0x8000; + adjustment->hue = 0x8000; + + /* reset overlay */ + nvov0->brightness = 0; + nvov0->contrast = 4096; + nvov0->hue = 0; + nvov0->saturation = 4096; + ov0_set_csc( nvdrv, nvov0 ); + + return DFB_OK; +} + +static DFBResult +ov0Remove( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + /* disable overlay */ + nv_out32( mmio, PVIDEO_STOP, PVIDEO_STOP_OVERLAY_ACTIVE | + PVIDEO_STOP_METHOD_IMMEDIATELY ); + nv_out32( mmio, PVIDEO_BUFFER, 0 ); + + return DFB_OK; +} + +static DFBResult +ov0TestRegion(CoreLayer *layer, + void *driver_data, + void *layer_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags *failed ) +{ + NVidiaDriverData *nvdrv = driver_data; + NVidiaDeviceData *nvdev = nvdrv->device_data; + CoreLayerRegionConfigFlags fail = CLRCF_NONE; + + + /* check for unsupported options */ + if (config->options & ~OV0_SUPPORTED_OPTIONS) + fail |= CLRCF_OPTIONS; + + /* check buffermode */ + switch (config->buffermode) { + case DLBM_FRONTONLY: + case DLBM_BACKSYSTEM: + case DLBM_BACKVIDEO: + case DLBM_TRIPLE: + break; + + default: + fail |= CLRCF_BUFFERMODE; + break; + } + + /* check pixel format */ + switch (config->format) { + case DSPF_YUY2: + case DSPF_UYVY: + break; + + case DSPF_NV12: + /*case DSPF_NV21:*/ + if (nvdev->arch < NV_ARCH_30) + fail |= CLRCF_FORMAT; + break; + + default: + fail |= CLRCF_FORMAT; + break; + } + + /* check width */ + if (config->width > 2046 || config->width < 1) + fail |= CLRCF_WIDTH; + + /* check height */ + if (config->height > 2046 || config->height < 1) + fail |= CLRCF_HEIGHT; + + /* write back failing fields */ + if (failed) + *failed = fail; + + /* return failure if any field failed */ + if (fail) + return DFB_UNSUPPORTED; + + return DFB_OK; +} + +static DFBResult +ov0SetRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags updated, + CoreSurface *surface, + CorePalette *palette, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + /* remember configuration */ + nvov0->config = *config; + + nvov0->videoSurface = surface; + nvov0->lock = lock; + + /* set configuration */ + if (updated & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_FORMAT | + CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS | CLRCF_OPACITY)) + { + ov0_calc_regs( nvdrv, nvov0, config, updated ); + ov0_set_regs( nvdrv, nvov0, updated ); + } + + /* set destination colorkey */ + if (updated & CLRCF_DSTKEY) + ov0_set_colorkey( nvdrv, nvov0, config ); + + return DFB_OK; +} + +static DFBResult +ov0FlipRegion ( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + nvov0->videoSurface = surface; + nvov0->lock = lock; + + dfb_surface_flip( nvov0->videoSurface, false ); + + ov0_calc_regs( nvdrv, nvov0, &nvov0->config, CLRCF_SURFACE ); + ov0_set_regs( nvdrv, nvov0, CLRCF_SURFACE ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + return DFB_OK; +} + +static DFBResult +ov0SetColorAdjustment( CoreLayer *layer, + void *driver_data, + void *layer_data, + DFBColorAdjustment *adj ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + if (adj->flags & DCAF_BRIGHTNESS) { + nvov0->brightness = (adj->brightness >> 8) - 128; + D_DEBUG( "DirectFB/NVidia/Overlay: brightness=%i\n", nvov0->brightness ); + } + + if (adj->flags & DCAF_CONTRAST) { + nvov0->contrast = 8191 - (adj->contrast >> 3); /* contrast inverted ?! */ + D_DEBUG( "DirectFB/NVidia/Overlay: contrast=%i\n", nvov0->contrast ); + } + + if (adj->flags & DCAF_SATURATION) { + nvov0->saturation = adj->saturation >> 3; + D_DEBUG( "DirectFB/NVidia/Overlay: saturation=%i\n", nvov0->saturation ); + } + + if (adj->flags & DCAF_HUE) { + nvov0->hue = (adj->hue / 182 - 180) % 360; + D_DEBUG( "DirectFB/NVidia/Overlay: hue=%i\n", nvov0->hue ); + } + + ov0_set_csc( nvdrv, nvov0 ); + + return DFB_OK; +} + +static DFBResult +ov0SetInputField( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + int field ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaOverlayLayerData *nvov0 = (NVidiaOverlayLayerData*) layer_data; + + nvov0->field = field; + nvov0->regs.BUFFER = 1 << (field << 2); + + nv_out32( nvdrv->mmio_base, PVIDEO_BUFFER, nvov0->regs.BUFFER ); + + return DFB_OK; +} + +DisplayLayerFuncs nvidiaOverlayFuncs = { + .LayerDataSize = ov0LayerDataSize, + .InitLayer = ov0InitLayer, + .SetRegion = ov0SetRegion, + .RemoveRegion = ov0Remove, + .TestRegion = ov0TestRegion, + .FlipRegion = ov0FlipRegion, + .SetColorAdjustment = ov0SetColorAdjustment, + .SetInputField = ov0SetInputField, +}; + + +/* internal */ + +static void ov0_set_regs( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfigFlags flags ) +{ + volatile u8 *mmio = nvdrv->mmio_base; + + if (flags & CLRCF_SURFACE) { + if (DFB_PLANAR_PIXELFORMAT(nvov0->config.format)) { + nv_out32( mmio, PVIDEO_UVBASE_0, nvov0->regs.UVBASE_0 ); + nv_out32( mmio, PVIDEO_UVBASE_1, nvov0->regs.UVBASE_1 ); + nv_out32( mmio, PVIDEO_UVOFFSET_0, nvov0->regs.UVOFFSET_0 ); + nv_out32( mmio, PVIDEO_UVOFFSET_1, nvov0->regs.UVOFFSET_1 ); + } + nv_out32( mmio, PVIDEO_BASE_0, nvov0->regs.BASE_0 ); + nv_out32( mmio, PVIDEO_BASE_1, nvov0->regs.BASE_1 ); + nv_out32( mmio, PVIDEO_OFFSET_0, nvov0->regs.OFFSET_0 ); + nv_out32( mmio, PVIDEO_OFFSET_1, nvov0->regs.OFFSET_1 ); + } + if (flags & (CLRCF_WIDTH | CLRCF_HEIGHT | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_SIZE_IN_0, nvov0->regs.SIZE_IN_0 ); + nv_out32( mmio, PVIDEO_SIZE_IN_1, nvov0->regs.SIZE_IN_1 ); + } + if (flags & (CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_POINT_IN_0, nvov0->regs.POINT_IN_0 ); + nv_out32( mmio, PVIDEO_POINT_IN_1, nvov0->regs.POINT_IN_1 ); + nv_out32( mmio, PVIDEO_DS_DX_0, nvov0->regs.DS_DX_0 ); + nv_out32( mmio, PVIDEO_DS_DX_1, nvov0->regs.DS_DX_1 ); + nv_out32( mmio, PVIDEO_DT_DY_0, nvov0->regs.DT_DY_0 ); + nv_out32( mmio, PVIDEO_DT_DY_1, nvov0->regs.DT_DY_1 ); + } + if (flags & CLRCF_DEST) { + nv_out32( mmio, PVIDEO_POINT_OUT_0, nvov0->regs.POINT_OUT_0 ); + nv_out32( mmio, PVIDEO_POINT_OUT_1, nvov0->regs.POINT_OUT_1 ); + nv_out32( mmio, PVIDEO_SIZE_OUT_0, nvov0->regs.SIZE_OUT_0 ); + nv_out32( mmio, PVIDEO_SIZE_OUT_1, nvov0->regs.SIZE_OUT_1 ); + } + if (flags & (CLRCF_FORMAT | CLRCF_SURFACE | CLRCF_OPTIONS)) { + nv_out32( mmio, PVIDEO_FORMAT_0, nvov0->regs.FORMAT_0 ); + nv_out32( mmio, PVIDEO_FORMAT_1, nvov0->regs.FORMAT_1 ); + } + nv_out32( mmio, PVIDEO_BUFFER, nvov0->regs.BUFFER ); + nv_out32( mmio, PVIDEO_STOP, nvov0->regs.STOP ); +} + +static void +ov0_calc_regs( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config, + CoreLayerRegionConfigFlags flags ) +{ + NVidiaDeviceData *nvdev = nvdrv->device_data; + + if (flags & (CLRCF_WIDTH | CLRCF_HEIGHT | + CLRCF_SOURCE | CLRCF_DEST | CLRCF_OPTIONS)) { + int width = config->width; + int height = config->height; + DFBRectangle source = config->source; + DFBRectangle dest = config->dest; + + source.x <<= 4; + source.y <<= 4; + + if (dest.x < 0) { + source.x -= (dest.x * source.w << 4) / dest.w; + source.w += dest.x * source.w / dest.w; + dest.w += dest.x; + dest.x = 0; + } + + if (dest.y < 0) { + source.y -= (dest.y * source.h << 4) / dest.h; + source.h += dest.y * source.h / dest.h; + dest.h += dest.y; + dest.y = 0; + } + + if (config->options & DLOP_DEINTERLACING) { + height /= 2; + source.y /= 2; + source.h /= 2; + } + + if (source.w < 1 || source.h < 1 || dest.w < 1 || dest.h < 1) { + nvov0->regs.STOP = PVIDEO_STOP_OVERLAY_ACTIVE | + PVIDEO_STOP_METHOD_NORMALLY; + return; + } + + nvov0->regs.SIZE_IN_0 = + nvov0->regs.SIZE_IN_1 = ((height << 16) & PVIDEO_SIZE_IN_HEIGHT_MSK) | + ( width & PVIDEO_SIZE_IN_WIDTH_MSK); + nvov0->regs.POINT_IN_0 = + nvov0->regs.POINT_IN_1 = ((source.y << 16) & PVIDEO_POINT_IN_T_MSK) | + ( source.x & PVIDEO_POINT_IN_S_MSK); + nvov0->regs.DS_DX_0 = + nvov0->regs.DS_DX_1 = (source.w << 20) / dest.w; + nvov0->regs.DT_DY_0 = + nvov0->regs.DT_DY_1 = (source.h << 20) / dest.h; + nvov0->regs.POINT_OUT_0 = + nvov0->regs.POINT_OUT_1 = ((dest.y << 16) & PVIDEO_POINT_OUT_Y_MSK) | + ( dest.x & PVIDEO_POINT_OUT_X_MSK); + nvov0->regs.SIZE_OUT_0 = + nvov0->regs.SIZE_OUT_1 = ((dest.h << 16) & PVIDEO_SIZE_OUT_HEIGHT_MSK) | + ( dest.w & PVIDEO_SIZE_OUT_WIDTH_MSK); + } + + if (flags & (CLRCF_SURFACE | CLRCF_FORMAT | CLRCF_OPTIONS)) { + CoreSurfaceBufferLock *lock = nvov0->lock; + u32 format; + + if (config->options & DLOP_DEINTERLACING) + format = (lock->pitch*2) & PVIDEO_FORMAT_PITCH_MSK; + else + format = lock->pitch & PVIDEO_FORMAT_PITCH_MSK; + + if (DFB_PLANAR_PIXELFORMAT(config->format)) + format |= PVIDEO_FORMAT_PLANAR_NV; + + if (config->format == DSPF_UYVY) + format |= PVIDEO_FORMAT_COLOR_YB8CR8YA8CB8; + else + format |= PVIDEO_FORMAT_COLOR_CR8YB8CB8YA8; + + if (config->options & DLOP_DST_COLORKEY) + format |= PVIDEO_FORMAT_DISPLAY_COLOR_KEY_EQUAL; + + /* Use Buffer 0 for Odd field */ + nvov0->regs.OFFSET_0 = (nvdev->fb_offset + lock->offset) & PVIDEO_OFFSET_MSK; + /* Use Buffer 1 for Even field */ + nvov0->regs.OFFSET_1 = nvov0->regs.OFFSET_0 + lock->pitch; + if (DFB_PLANAR_PIXELFORMAT(config->format)) { + CoreSurface *surface = nvov0->videoSurface; + nvov0->regs.UVOFFSET_0 = (nvov0->regs.OFFSET_0 + + lock->pitch * surface->config.size.h) & PVIDEO_UVOFFSET_MSK; + nvov0->regs.UVOFFSET_1 = nvov0->regs.UVOFFSET_0 + lock->pitch; + } + nvov0->regs.FORMAT_0 = + nvov0->regs.FORMAT_1 = format; + } + + nvov0->regs.BUFFER = 1 << (nvov0->field << 2); + nvov0->regs.STOP = (config->opacity) + ? PVIDEO_STOP_OVERLAY_INACTIVE + : PVIDEO_STOP_OVERLAY_ACTIVE; + nvov0->regs.STOP |= PVIDEO_STOP_METHOD_NORMALLY; +} + +static void +ov0_set_colorkey( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0, + CoreLayerRegionConfig *config ) +{ + u32 key; + + key = dfb_color_to_pixel( dfb_primary_layer_pixelformat(), + config->dst_key.r, + config->dst_key.g, + config->dst_key.b ); + + nv_out32( nvdrv->mmio_base, PVIDEO_COLOR_KEY, key ); +} + +static void +ov0_set_csc( NVidiaDriverData *nvdrv, + NVidiaOverlayLayerData *nvov0 ) +{ + volatile u8 *mmio = nvdrv->mmio_base; + s32 satSine; + s32 satCosine; + double angle; + + angle = (double) nvov0->hue * M_PI / 180.0; + satSine = nvov0->saturation * sin(angle); + if (satSine < -1024) + satSine = -1024; + satCosine = nvov0->saturation * cos(angle); + if (satCosine < -1024) + satCosine = -1024; + + nv_out32( mmio, PVIDEO_LUMINANCE_0, (nvov0->brightness << 16) | + (nvov0->contrast & 0xffff) ); + nv_out32( mmio, PVIDEO_LUMINANCE_1, (nvov0->brightness << 16) | + (nvov0->contrast & 0xffff) ); + nv_out32( mmio, PVIDEO_CHROMINANCE_0, (satSine << 16) | + (satCosine & 0xffff) ); + nv_out32( mmio, PVIDEO_CHROMINANCE_1, (satSine << 16) | + (satCosine & 0xffff) ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c new file mode 100755 index 0000000..50bde37 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_primary.c @@ -0,0 +1,189 @@ +/* + Copyright (C) 2005-2006 Claudio Ciccani <klan@users.sf.net> + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +#include <directfb.h> + +#include <core/coredefs.h> +#include <core/surface.h> +#include <core/gfxcard.h> +#include <core/system.h> +#include <core/screen.h> +#include <core/layer_control.h> + +#include <misc/conf.h> + +#include <direct/messages.h> + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" + + +/************************** Primary Screen functions **************************/ + +static DFBResult +crtc1InitScreen( CoreScreen *screen, + CoreGraphicsDevice *device, + void *driver_data, + void *screen_data, + DFBScreenDescription *description ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + if (OldPrimaryScreenFuncs.InitScreen) + OldPrimaryScreenFuncs.InitScreen( screen, device, + OldPrimaryScreenDriverData, + screen_data, description ); + + description->caps |= DSCCAPS_VSYNC; + + snprintf( description->name, + DFB_SCREEN_DESC_NAME_LENGTH, "NVidia Primary Screen" ); + + nv_out32( mmio, PCRTC_INTR_EN, PCRTC_INTR_EN_VBLANK_DISABLED ); +#ifdef WORDS_BIGENDIAN + nv_out32( mmio, PCRTC_CONFIG, PCRTC_CONFIG_SIGNAL_HSYNC | + PCRTC_CONFIG_ENDIAN_BIG ); +#else + nv_out32( mmio, PCRTC_CONFIG, PCRTC_CONFIG_SIGNAL_HSYNC | + PCRTC_CONFIG_ENDIAN_LITTLE ); +#endif + nv_out32( mmio, PCRTC_INTR, PCRTC_INTR_VBLANK_RESET ); + + return DFB_OK; +} + +static DFBResult +crtc1WaitVSync( CoreScreen *screen, + void *driver_data, + void *screen_data ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + + if (!dfb_config->pollvsync_none) { + int i; + + for (i = 0; i < 2000000; i++) { + if (!(nv_in8( mmio, PCIO_CRTC_STATUS ) & 8)) + break; + } + + for (i = 0; i < 2000000;) { + if (nv_in8( mmio, PCIO_CRTC_STATUS ) & 8) + break; + + i++; + if ((i % 2000) == 0) { + struct timespec ts = { 0, 10000 }; + nanosleep( &ts, NULL ); + } + } + } + + return DFB_OK; +} + +#if 0 +static DFBResult +crtc1GetScreenSize( CoreScreen *screen, + void *driver_data, + void *screen_data, + int *ret_width, + int *ret_height ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + volatile u8 *mmio = nvdrv->mmio_base; + int w, h; + int val; + + /* stolen from RivaTV */ + + w = nv_incrtc( mmio, CRTC_HORIZ_DISPLAY_END ); + w |= (nv_incrtc( mmio, CRTC_HORIZ_EXTRA ) & 0x02) << 7; + w = (w + 1) << 3; + + h = nv_incrtc( mmio, CRTC_VERT_DISPLAY_END ); + val = nv_incrtc( mmio, CRTC_OVERFLOW ); + h |= (val & 0x02) << 7; + h |= (val & 0x40) << 3; + h++; + h |= nv_incrtc( mmio, CRTC_EXTRA ) << 9; + h |= nv_incrtc( mmio, 0x41 ) << 9; + h >>= (nv_incrtc( mmio, CRTC_MAX_SCAN_LINE ) & 0x80) >> 7; + + D_DEBUG( "DirectFB/NVidia/Crtc1: " + "detected screen resolution %dx%d.\n", w, h ); + + *ret_width = w; + *ret_height = h; + + return DFB_OK; +} +#endif + +ScreenFuncs nvidiaPrimaryScreenFuncs = { + .InitScreen = crtc1InitScreen, + .WaitVSync = crtc1WaitVSync, + //.GetScreenSize = crtc1GetScreenSize +}; + +ScreenFuncs OldPrimaryScreenFuncs; +void *OldPrimaryScreenDriverData; + +/*************************** Primary Layer hooks ******************************/ + +static DFBResult +fb0FlipRegion( CoreLayer *layer, + void *driver_data, + void *layer_data, + void *region_data, + CoreSurface *surface, + DFBSurfaceFlipFlags flags, + CoreSurfaceBufferLock *lock ) +{ + NVidiaDriverData *nvdrv = (NVidiaDriverData*) driver_data; + NVidiaDeviceData *nvdev = nvdrv->device_data; + u32 offset; + + dfb_surface_flip( surface, false ); + + offset = (lock->offset + nvdev->fb_offset) & ~3; + nv_out32( nvdrv->mmio_base, PCRTC_START, offset ); + + if (flags & DSFLIP_WAIT) + dfb_layer_wait_vsync( layer ); + + return DFB_OK; +} + + +DisplayLayerFuncs nvidiaPrimaryLayerFuncs = { + .FlipRegion = fb0FlipRegion +}; + +DisplayLayerFuncs OldPrimaryLayerFuncs; +void *OldPrimaryLayerDriverData; diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h new file mode 100755 index 0000000..64257cc --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_regs.h @@ -0,0 +1,1636 @@ +#ifndef __NVIDIA_REGS_H__ +#define __NVIDIA_REGS_H__ + + +/* PMC */ +#define PMC 0x00000000 + + + +/* PBUS */ +#define PBUS 0x00001000 + + + +/* PFIFO */ +#define PFIFO 0x00002000 + +#define PFIFO_DELAY_0 0x00002040 +#define PFIFO_DELAY_0_WAIT_RETRY_MSK 0x000003FF + +#define PFIFO_DMA_TIMESLICE 0x00002044 +#define PFIFO_DMA_TIMESLICE_SELECT_MSK 0x0001FFFF +#define PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 +#define PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003FFF +#define PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007FFF +#define PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000FFFF +#define PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001FFFF +#define PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_PIO_TIMESLICE 0x00002048 +#define PFIFO_PIO_TIMESLICE_SELECT_MSK 0x0001FFFF +#define PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 +#define PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003FFF +#define PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007FFF +#define PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000FFFF +#define PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001FFFF +#define PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_TIMESLICE 0x0000204C +#define PFIFO_TIMESLICE_TIMER_MSK 0x0003FFFF + +#define PFIFO_NEXT_CHANNEL 0x00002050 +#define PFIFO_NEXT_CHANNEL_CHID_MSK 0x0000001F +#define PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 +#define PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000100 +#define PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 +#define PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00001000 + +#define PFIFO_DEBUG_0 0x00002080 +#define PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 +#define PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 +#define PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 +#define PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000010 + +#define PFIFO_INTR 0x00002100 +#define PFIFO_INTR_RESET 0xFFFFFFFF +#define PFIFO_INTR_CACHE_ERROR_NOT_PENDING 0x00000000 +#define PFIFO_INTR_CACHE_ERROR_PENDING 0x00000001 +#define PFIFO_INTR_CACHE_ERROR_RESET 0x00000001 +#define PFIFO_INTR_RUNOUT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_RUNOUT_PENDING 0x00000010 +#define PFIFO_INTR_RUNOUT_RESET 0x00000010 +#define PFIFO_INTR_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 +#define PFIFO_INTR_RUNOUT_OVERFLOW_PENDING 0x00000100 +#define PFIFO_INTR_RUNOUT_OVERFLOW_RESET 0x00000100 +#define PFIFO_INTR_DMA_PUSHER_NOT_PENDING 0x00000000 +#define PFIFO_INTR_DMA_PUSHER_PENDING 0x00001000 +#define PFIFO_INTR_DMA_PUSHER_RESET 0x00001000 +#define PFIFO_INTR_DMA_PT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_DMA_PT_PENDING 0x00010000 +#define PFIFO_INTR_DMA_PT_RESET 0x00010000 +#define PFIFO_INTR_SEMAPHORE_NOT_PENDING 0x00000000 +#define PFIFO_INTR_SEMAPHORE_PENDING 0x00100000 +#define PFIFO_INTR_SEMAPHORE_RESET 0x00100000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_NOT_PENDING 0x00000000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_PENDING 0x01000000 +#define PFIFO_INTR_ACQUIRE_TIMEOUT_RESET 0x01000000 + +#define PFIFO_INTR_EN 0x00002140 +#define PFIFO_INTR_EN_DISABLED 0x00000000 +#define PFIFO_INTR_EN_CACHE_ERROR_DISABLED 0x00000000 +#define PFIFO_INTR_EN_CACHE_ERROR_ENABLED 0x00000001 +#define PFIFO_INTR_EN_RUNOUT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_RUNOUT_ENABLED 0x00000010 +#define PFIFO_INTR_EN_RUNOUT_OVERFLOW_DISABLED 0x00000000 +#define PFIFO_INTR_EN_RUNOUT_OVERFLOW_ENABLED 0x00000100 +#define PFIFO_INTR_EN_DMA_PUSHER_DISABLED 0x00000000 +#define PFIFO_INTR_EN_DMA_PUSHER_ENABLED 0x00001000 +#define PFIFO_INTR_EN_DMA_PT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_DMA_PT_ENABLED 0x00010000 +#define PFIFO_INTR_EN_SEMAPHORE_DISABLED 0x00000000 +#define PFIFO_INTR_EN_SEMAPHORE_ENABLED 0x00100000 +#define PFIFO_INTR_EN_ACQUIRE_TIMEOUT_DISABLED 0x00000000 +#define PFIFO_INTR_EN_ACQUIRE_TIMEOUT_ENABLED 0x01000000 + +#define PFIFO_RAMHT 0x00002210 +#define PFIFO_RAMHT_BASE_ADDRESS_MSK 0x000001F0 +#define PFIFO_RAMHT_SIZE_4K 0x00000000 +#define PFIFO_RAMHT_SIZE_8K 0x00010000 +#define PFIFO_RAMHT_SIZE_16K 0x00020000 +#define PFIFO_RAMHT_SIZE_32K 0x00030000 +#define PFIFO_RAMHT_SEARCH_16 0x00000000 +#define PFIFO_RAMHT_SEARCH_32 0x01000000 +#define PFIFO_RAMHT_SEARCH_64 0x02000000 +#define PFIFO_RAMHT_SEARCH_128 0x03000000 + +#define PFIFO_RAMFC 0x00002214 +#define PFIFO_RAMFC_BASE_ADDRESS_MSK 0x000001F8 + +#define PFIFO_RAMRO 0x00002218 +#define PFIFO_RAMRO_BASE_ADDRESS_MSK 0x000001FE +#define PFIFO_RAMRO_BASE_ADDRESS_11800 0x00000118 +#define PFIFO_RAMRO_BASE_ADDRESS_11400 0x00000114 +#define PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000112 +#define PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000120 +#define PFIFO_RAMRO_SIZE_512 0x00000000 +#define PFIFO_RAMRO_SIZE_8K 0x00010000 + +#define PFIFO_CACHES 0x00002500 +#define PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 +#define PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 +#define PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 +#define PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000010 + +#define PFIFO_MODE 0x00002504 +#define PFIFO_MODE_CHANNEL_0_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_0_DMA 0x00000001 +#define PFIFO_MODE_CHANNEL_1_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_1_DMA 0x00000002 +#define PFIFO_MODE_CHANNEL_2_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_2_DMA 0x00000004 +#define PFIFO_MODE_CHANNEL_3_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_3_DMA 0x00000008 +#define PFIFO_MODE_CHANNEL_4_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_4_DMA 0x00000010 +#define PFIFO_MODE_CHANNEL_5_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_5_DMA 0x00000020 +#define PFIFO_MODE_CHANNEL_6_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_6_DMA 0x00000040 +#define PFIFO_MODE_CHANNEL_7_PIO 0x00000000 +#define PFIFO_MODE_CHANNEL_7_DMA 0x00000080 + +#define PFIFO_DMA 0x00002508 +#define PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 +#define PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_1_PENDING 0x00000002 +#define PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_2_PENDING 0x00000004 +#define PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_3_PENDING 0x00000008 +#define PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_4_PENDING 0x00000010 +#define PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_5_PENDING 0x00000020 +#define PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_6_PENDING 0x00000040 +#define PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 +#define PFIFO_DMA_CHANNEL_7_PENDING 0x00000080 + +#define PFIFO_SIZE 0x0000250C +#define PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 +#define PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000002 +#define PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000004 +#define PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000008 +#define PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000010 +#define PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000020 +#define PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000040 +#define PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 +#define PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000080 + +#define PFIFO_CACHE0_PUSH0 0x00003000 +#define PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 + +#define PFIFO_CACHE1_PUSH0 0x00003200 +#define PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 + +#define PFIFO_CACHE0_PUSH1 0x00003004 +#define PFIFO_CACHE0_PUSH1_CHID_MSK 0x0000001F + +#define PFIFO_CACHE1_PUSH1 0x00003204 +#define PFIFO_CACHE1_PUSH1_CHID_MSK 0x0000001F +#define PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 +#define PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000100 + +#define PFIFO_CACHE1_DMA_PUSH 0x00003220 +#define PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000010 +#define PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000100 +#define PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 +#define PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00001000 + +#define PFIFO_CACHE1_DMA_FETCH 0x00003224 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +#define PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +#define PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +#define PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +#define PFIFO_CACHE1_LITTLE_ENDIAN 0x00000000 +#define PFIFO_CACHE1_BIG_ENDIAN 0x80000000 + +#define PFIFO_CACHE1_DMA_PUT 0x00003240 + +#define PFIFO_CACHE1_DMA_GET 0x00003244 + +#define PFIFO_CACHE1_REF 0x00003248 + +#define PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +#define PFIFO_CACHE1_DMA_SUBROUTINE_OFFSET_MSK 0x1FFFFFFC +#define PFIFO_CACHE1_DMA_SUBROUTINE_STATE_INACTIVE 0x00000000 +#define PFIFO_CACHE1_DMA_SUBROUTINE_STATE_ACTIVE 0x00000001 + +#define PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +#define PFIFO_CACHE1_DMA_DCOUNT_VALUE_MSK 0x00001FFC + +#define PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x000032A4 + +#define PFIFO_CACHE1_DMA_RSVD_SHADOW 0x000032A8 + +#define PFIFO_CACHE1_DMA_DATA_SHADOW 0x000032AC + +#define PFIFO_CACHE1_DMA_STATE 0x00003228 +#define PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC 0x00000000 +#define PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_NON_INC 0x00000001 +#define PFIFO_CACHE1_DMA_STATE_METHOD_MSK 0x00001FFC +#define PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 0x0000E000 +#define PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_MSK 0x1FFC0000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_CALL 0x20000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x40000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_RETURN 0x60000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x80000000 +#define PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0xC0000000 + +#define PFIFO_CACHE1_DMA_INSTANCE 0x0000322C + +#define PFIFO_CACHE1_DMA_CTL 0x00003230 +#define PFIFO_CACHE1_DMA_CTL_ADJUST_MSK 0x00000FFC +#define PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00001000 +#define PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00002000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_NVM 0x00000000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00020000 +#define PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00030000 +#define PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 +#define PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x80000000 + +#define PFIFO_CACHE1_DMA_LIMIT 0x00003234 + +#define PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 +#define PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS_MSK 0x1FFFF000 +#define PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 +#define PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 + +#define PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C +#define PFIFO_CACHE1_DMA_TLB_PTE_ADDRESS_MSK 0xFFFFF000 + +#define PFIFO_CACHE0_PULL0 0x00003050 +#define PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 +#define PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000010 +#define PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 +#define PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000100 +#define PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00001000 + +#define PFIFO_CACHE1_PULL0 0x00003250 +#define PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 +#define PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 +#define PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 +#define PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 +#define PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 +#define PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000100 +#define PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00001000 +#define PFIFO_CACHE1_PULL0_ACQUIRE_STATE_IDLE 0x00000000 +#define PFIFO_CACHE1_PULL0_ACQUIRE_STATE_BUSY 0x00010000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_NO_ERROR 0x00000000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_BAD_ARG 0x00100000 +#define PFIFO_CACHE1_PULL0_SEMAPHORE_ISTATE 0x00200000 + +#define PFIFO_CACHE0_PULL1 0x00003054 +#define PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 +#define PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 +#define PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 + +#define PFIFO_CACHE1_PULL1 0x00003254 +#define PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 +#define PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 +#define PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 + +#define PFIFO_CACHE1_PULL1_ACQUIRE 0x00000010 +#define PFIFO_CACHE1_PULL1_ACQUIRE_INACTIVE 0x00000000 +#define PFIFO_CACHE1_PULL1_ACQUIRE_ACTIVE 0x00000010 + +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE 0x00030000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_NVM 0x00000000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_PCI 0x00020000 +#define PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_AGP 0x00030000 + +#define PFIFO_CACHE0_HASH 0x00003058 +#define PFIFO_CACHE0_HASH_INSTANCE_MSK 0x0000FFFF + +#define PFIFO_CACHE1_HASH 0x00003258 +#define PFIFO_CACHE1_HASH_INSTANCE_MSK 0x0000FFFF + +#define PFIFO_CACHE1_ACQUIRE_0 0x00003260 + +#define PFIFO_CACHE1_ACQUIRE_1 0x00003264 + +#define PFIFO_CACHE1_ACQUIRE_2 0x00003268 + +#define PFIFO_CACHE1_SEMAPHORE 0x0000326C +#define PFIFO_CACHE1_SEMAPHORE_CTXDMA_INVALID 0x00000000 +#define PFIFO_CACHE1_SEMAPHORE_CTXDMA_VALID 0x00000001 +#define PFIFO_CACHE1_SEMAPHORE_OFFSET_MSK 0x00000FFC +#define PFIFO_CACHE1_SEMAPHORE_PAGE_ADDRESS_MSK 0xFFFFF000 + +#define PFIFO_CACHE0_STATUS 0x00003014 +#define PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_CACHE1_STATUS 0x00003214 +#define PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_CACHE1_STATUS1 0x00003218 +#define PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 +#define PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 + +#define PFIFO_CACHE0_PUT 0x00003010 + +#define PFIFO_CACHE1_PUT 0x00003210 + +#define PFIFO_CACHE0_GET 0x00003070 + +#define PFIFO_CACHE1_GET 0x00003270 + +#define PFIFO_CACHE0_ENGINE 0x00003080 +#define PFIFO_CACHE0_ENGINE_0_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 +#define PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 +#define PFIFO_CACHE0_ENGINE_1_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000010 +#define PFIFO_CACHE0_ENGINE_1_DVD 0x00000020 +#define PFIFO_CACHE0_ENGINE_2_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000100 +#define PFIFO_CACHE0_ENGINE_2_DVD 0x00000200 +#define PFIFO_CACHE0_ENGINE_3_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00001000 +#define PFIFO_CACHE0_ENGINE_3_DVD 0x00002000 +#define PFIFO_CACHE0_ENGINE_4_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00010000 +#define PFIFO_CACHE0_ENGINE_4_DVD 0x00020000 +#define PFIFO_CACHE0_ENGINE_5_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00100000 +#define PFIFO_CACHE0_ENGINE_5_DVD 0x00200000 +#define PFIFO_CACHE0_ENGINE_6_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x01000000 +#define PFIFO_CACHE0_ENGINE_6_DVD 0x02000000 +#define PFIFO_CACHE0_ENGINE_7_SW 0x00000000 +#define PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x10000000 +#define PFIFO_CACHE0_ENGINE_7_DVD 0x20000000 + +#define PFIFO_CACHE1_ENGINE 0x00003280 +#define PFIFO_CACHE1_ENGINE_0_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 +#define PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 +#define PFIFO_CACHE1_ENGINE_1_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000010 +#define PFIFO_CACHE1_ENGINE_1_DVD 0x00000020 +#define PFIFO_CACHE1_ENGINE_2_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000100 +#define PFIFO_CACHE1_ENGINE_2_DVD 0x00000200 +#define PFIFO_CACHE1_ENGINE_3_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00001000 +#define PFIFO_CACHE1_ENGINE_3_DVD 0x00002000 +#define PFIFO_CACHE1_ENGINE_4_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00010000 +#define PFIFO_CACHE1_ENGINE_4_DVD 0x00020000 +#define PFIFO_CACHE1_ENGINE_5_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00100000 +#define PFIFO_CACHE1_ENGINE_5_DVD 0x00200000 +#define PFIFO_CACHE1_ENGINE_6_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x01000000 +#define PFIFO_CACHE1_ENGINE_6_DVD 0x02000000 +#define PFIFO_CACHE1_ENGINE_7_SW 0x00000000 +#define PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x10000000 +#define PFIFO_CACHE1_ENGINE_7_DVD 0x20000000 + +#define PFIFO_CACHE0_METHOD 0x00003100 +#define PFIFO_CACHE0_METHOD_ADDRESS_MSK 0x00001FFC +#define PFIFO_CACHE0_METHOD_SUBCHANNEL_MSK 0x0000E000 + +#define PFIFO_CACHE1_METHOD 0x00003800 +#define PFIFO_CACHE1_METHOD_ADDRESS_MSK 0x00001FFC +#define PFIFO_CACHE1_METHOD_SUBCHANNEL_MSK 0x0000E000 + +#define PFIFO_CACHE1_METHOD_ALIAS 0x00003C00 + +#define PFIFO_CACHE0_DATA 0x00003104 + +#define PFIFO_CACHE1_DATA 0x00003804 + +#define PFIFO_CACHE1_DATA_ALIAS 0x00003C04 + +#define PFIFO_DEVICE 0x00002800 +#define PFIFO_DEVICE_CHID_MSK 0x0000001F +#define PFIFO_DEVICE_SWITCH 0x01000000 +#define PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 +#define PFIFO_DEVICE_SWITCH_AVAILABLE 0x01000000 + +#define PFIFO_RUNOUT_STATUS 0x00002400 +#define PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 +#define PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 +#define PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 +#define PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000010 +#define PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 +#define PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000100 + +#define PFIFO_RUNOUT_PUT 0x00002410 +#define PFIFO_RUNOUT_PUT_ADDRES_MSK 0x00001FF8 + +#define PFIFO_RUNOUT_GET 0x00002420 +#define PFIFO_RUNOUT_GET_ADDRESS_MSK 0x00003FF8 + + + +/* PVIDEO */ +#define PVIDEO 0x00008000 + +#define PVIDEO_DEBUG_0 0x00008080 +#define PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_ENABLED 0x00000001 +#define PVIDEO_DEBUG_0_LIMIT_CHECK_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_LIMIT_CHECK_ENABLED 0x00000010 +#define PVIDEO_DEBUG_0_HUE_FOLD_DISABLED 0x00000000 +#define PVIDEO_DEBUG_0_HUE_FOLD_ENABLED 0x00000100 + +#define PVIDEO_DEBUG_1 0x00008084 +#define PVIDEO_DEBUG_1_REQ_DELAY_MSK 0x000007FF +#define PVIDEO_DEBUG_1_REQ_DELAY_DEFAULT 0x00000064 +#define PVIDEO_DEBUG_1_REQ_DELAY_INIT 0x00000050 + +#define PVIDEO_DEBUG_2 0x00008088 +#define PVIDEO_DEBUG_2_BURST1_MSK 0x000007E0 +#define PVIDEO_DEBUG_2_BURST1_DEFAULT 0x00000100 +#define PVIDEO_DEBUG_2_BURST1_INIT 0x00000200 +#define PVIDEO_DEBUG_2_BURST2_MSK 0x07E00000 +#define PVIDEO_DEBUG_2_BURST2_DEFAULT 0x02000000 + +#define PVIDEO_DEBUG_3 0x0000808C +#define PVIDEO_DEBUG_3_WATER_MARK1_MSK 0x000007F0 +#define PVIDEO_DEBUG_3_WATER_MARK1_DEFAULT 0x000004B0 +#define PVIDEO_DEBUG_3_WATER_MARK1_INIT 0x00000400 +#define PVIDEO_DEBUG_3_WATER_MARK2_MSK 0x07F00000 +#define PVIDEO_DEBUG_3_WATER_MARK2_DEFAULT 0x03B00000 +#define PVIDEO_DEBUG_3_WATER_MARK2_INIT 0x04000000 + +#define PVIDEO_DEBUG_4 0x00008090 +#define PVIDEO_DEBUG_4_V_COEFF_B_MSK 0x00FFFFE0 +#define PVIDEO_DEBUG_4_V_COEFF_B_DEFAULT 0x0016A0A0 +#define PVIDEO_DEBUG_4_V_COEFF_B_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_4_V_COEFF_B_NEVER 0x00FFFFE0 + +#define PVIDEO_DEBUG_5 0x00008094 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_DEFAULT 0x00188160 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_5_H_L_COEFF_D_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_6 0x00008098 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_DEFAULT 0x0012C730 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_6_H_L_COEFF_C_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_7 0x0000809C +#define PVIDEO_DEBUG_7_H_L_COEFF_B_MSK 0x003FFFF0 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_DEFAULT 0x00000000 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_ALWAYS 0x00000000 +#define PVIDEO_DEBUG_7_H_L_COEFF_B_NEVER 0x003FFFF0 + +#define PVIDEO_DEBUG_8 0x000080A0 +#define PVIDEO_DEBUG_8_PIPE_FILL_MSK 0x000007F0 +#define PVIDEO_DEBUG_8_PIPE_FILL_DEFAULT 0x000000B0 + +#define PVIDEO_DEBUG_9 0x000080A4 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_TRUE 0x00000001 +#define PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_RESET 0x00000001 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_TRUE 0x00000010 +#define PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_RESET 0x00000010 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_TRUE 0x00000100 +#define PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_RESET 0x00000100 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_FALSE 0x00000000 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_TRUE 0x00001000 +#define PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_RESET 0x00001000 + +#define PVIDEO_DEBUG_10 0x000080A8 +#define PVIDEO_DEBUG_10_SCREEN_LINE_MSK 0x00001FFF +#define PVIDEO_DEBUG_10_SCREEN_LINE_FIRST 0x00000000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_MSK 0x001F0000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_FIRST 0x00000000 +#define PVIDEO_DEBUG_10_SCAN_COUNT_OVERFLOW 0x00100000 +#define PVIDEO_DEBUG_10_SCANNING_NEITHER 0x00000000 +#define PVIDEO_DEBUG_10_SCANNING_BUFFER_0 0x02000000 +#define PVIDEO_DEBUG_10_SCANNING_BUFFER_1 0x03000000 + +#define PVIDEO_INTR 0x00008100 +#define PVIDEO_INTR_BUFFER_0_NOT_PENDING 0x00000000 +#define PVIDEO_INTR_BUFFER_0_PENDING 0x00000001 +#define PVIDEO_INTR_BUFFER_0_RESET 0x00000001 +#define PVIDEO_INTR_BUFFER_1_NOT_PENDING 0x00000000 +#define PVIDEO_INTR_BUFFER_1_PENDING 0x00000010 +#define PVIDEO_INTR_BUFFER_1_RESET 0x00000010 + +#define PVIDEO_INTR_REASON 0x00008104 +#define PVIDEO_INTR_REASON_BUFFER_0_NOTIFICATION 0x00000000 +#define PVIDEO_INTR_REASON_BUFFER_0_PROTECTION_FAULT 0x00000001 +#define PVIDEO_INTR_REASON_BUFFER_1_NOTIFICATION 0x00000000 +#define PVIDEO_INTR_REASON_BUFFER_1_PROTECTION_FAULT 0x00000010 + +#define PVIDEO_INTR_EN 0x00008140 +#define PVIDEO_INTR_EN_BUFFER_0_DISABLED 0x00000000 +#define PVIDEO_INTR_EN_BUFFER_0_ENABLED 0x00000001 +#define PVIDEO_INTR_EN_BUFFER_1_DISABLED 0x00000000 +#define PVIDEO_INTR_EN_BUFFER_1_ENABLED 0x00000010 + +#define PVIDEO_BUFFER 0x00008700 +#define PVIDEO_BUFFER_0_USE_NOT_PENDING 0x00000000 +#define PVIDEO_BUFFER_0_USE_PENDING 0x00000001 +#define PVIDEO_BUFFER_0_USE_SET 0x00000001 +#define PVIDEO_BUFFER_1_USE_NOT_PENDING 0x00000000 +#define PVIDEO_BUFFER_1_USE_PENDING 0x00000010 +#define PVIDEO_BUFFER_1_USE_SET 0x00000010 + +#define PVIDEO_STOP 0x00008704 +#define PVIDEO_STOP_OVERLAY_INACTIVE 0x00000000 +#define PVIDEO_STOP_OVERLAY_ACTIVE 0x00000001 +#define PVIDEO_STOP_METHOD_IMMEDIATELY 0x00000000 +#define PVIDEO_STOP_METHOD_NORMALLY 0x00000010 + +#define PVIDEO_UVBASE_0 0x00008800 +#define PVIDEO_UVBASE_1 0x00008804 +#define PVIDEO_UVBASE_MSK 0xFFFFFFC0 + +#define PVIDEO_UVLIMIT_0 0x00008808 +#define PVIDEO_UVLIMIT_1 0x0000880C + +#define PVIDEO_UVOFFSET_0 0x00008820 +#define PVIDEO_UVOFFSET_1 0x00008824 +#define PVIDEO_UVOFFSET_MSK 0xFFFFFFC0 + +#define PVIDEO_BASE_0 0x00008900 +#define PVIDEO_BASE_1 0x00008904 +#define PVIDEO_BASE_MSK 0xFFFFFFC0 + +#define PVIDEO_LIMIT_0 0x00008908 +#define PVIDEO_LIMIT_1 0x0000890C + +#define PVIDEO_LUMINANCE_0 0x00008910 +#define PVIDEO_LUMINANCE_1 0x00008914 + +#define PVIDEO_CHROMINANCE_0 0x00008918 +#define PVIDEO_CHROMINANCE_1 0x0000891C + +#define PVIDEO_OFFSET_0 0x00008920 +#define PVIDEO_OFFSET_1 0x00008924 +#define PVIDEO_OFFSET_MSK 0xFFFFFFC0 + +#define PVIDEO_SIZE_IN_0 0x00008928 +#define PVIDEO_SIZE_IN_1 0x0000892C +#define PVIDEO_SIZE_IN_WIDTH_MSK 0x000007FF +#define PVIDEO_SIZE_IN_HEIGHT_MSK 0x07FF0000 + +#define PVIDEO_POINT_IN_0 0x00008930 +#define PVIDEO_POINT_IN_1 0x00008934 +#define PVIDEO_POINT_IN_S_MSK 0x00007FFF +#define PVIDEO_POINT_IN_T_MSK 0xFFFE0000 + +#define PVIDEO_DS_DX_0 0x00008938 +#define PVIDEO_DS_DX_1 0x0000893C + +#define PVIDEO_DT_DY_0 0x00008940 +#define PVIDEO_DT_DY_1 0x00008944 + +#define PVIDEO_POINT_OUT_0 0x00008948 +#define PVIDEO_POINT_OUT_1 0x0000894C +#define PVIDEO_POINT_OUT_X_MSK 0x00000FFF +#define PVIDEO_POINT_OUT_Y_MSK 0x0FFF0000 + +#define PVIDEO_SIZE_OUT_0 0x00008950 +#define PVIDEO_SIZE_OUT_1 0x00008954 +#define PVIDEO_SIZE_OUT_WIDTH_MSK 0x00000FFF +#define PVIDEO_SIZE_OUT_HEIGHT_MSK 0x0FFF0000 + +#define PVIDEO_FORMAT_0 0x00008958 +#define PVIDEO_FORMAT_1 0x0000895C +#define PVIDEO_FORMAT_PLANAR_NV 0x00000001 +#define PVIDEO_FORMAT_PITCH_MSK 0x00001FC0 +#define PVIDEO_FORMAT_COLOR_YB8CR8YA8CB8 0x00000000 +#define PVIDEO_FORMAT_COLOR_CR8YB8CB8YA8 0x00010000 +#define PVIDEO_FORMAT_COLOR_ECR8EYB8ECB8EYA8 0x00110000 +#define PVIDEO_FORMAT_DISPLAY_ALWAYS 0x00000000 +#define PVIDEO_FORMAT_DISPLAY_COLOR_KEY_EQUAL 0x00100000 +#define PVIDEO_FORMAT_MATRIX_ITURBT601 0x00000000 +#define PVIDEO_FORMAT_MATRIX_ITURBT709 0x01000000 + +#define PVIDEO_COLOR_KEY 0x00008B00 + +#define PVIDEO_TEST 0x00008D00 +#define PVIDEO_TEST_MODE_DISABLE 0x00000000 +#define PVIDEO_TEST_MODE_ENABLE 0x00000001 +#define PVIDEO_TEST_ADDRESS_MSK 0x00007F00 + +/* Array [0...11] */ +#define PVIDEO_TST_WRITE 0x00008D10 + +/* Array [0...11] */ +#define PVIDEO_TST_READ 0x00008D40 + + + +/* PTIMER */ +#define PTIMER 0x00009000 + + + +/* PVIO */ +#define PVIO 0x000C0000 + +#define PVIO_SEQ_INDEX 0x000C03C4 + +#define PVIO_SEQ_DATA 0x000C03C5 + +#define PVIO_GRA_INDEX 0x000C03CE + +#define PCIO_GRA_DATA 0x000C03CF + + + +/* PVGA */ +#define PVGA 0x000A0000 + + + +/* PFB */ +#define PFB 0x00100000 + +#define PFB_BOOT_0 0x00100000 +#define PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 +#define PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 +#define PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 +#define PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 +#define PFB_BOOT_0_RAM_WIDTH_128 0x00000004 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 +#define PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 +#define PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 + + + +/* PEXTDEV */ +#define PEXTDEV 0x00101000 + + + +/* PGRAPH */ +#define PGRAPH 0x00400000 + +#define PGRAPH_DEBUG_0 0x00400080 + +#define PGRAPH_DEBUG_1 0x00400084 + +#define PGRAPH_DEBUG_2 0x00400088 + +#define PGRAPH_DEBUG_3 0x0040008C + +#define PGRAPH_DEBUG_4 0x00400090 + +#define PGRAPH_DEBUG_5 0x00400094 + +#define PGRAPH_DEBUG_6 0x00400820 + +#define PGRAPH_INTR 0x00400100 + +#define PGRAPH_NSTATUS 0x00400104 + +#define PGRAPH_NSOURCE 0x00400108 + +#define PGRAPH_INTR_EN 0x00400140 + +#define PGRAPH_FIFO 0x00400720 +#define PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 +#define PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 + +#define PGRAPH_STATUS 0x00400700 +#define PGRAPH_STATUS_STATE_IDLE 0x00000000 +#define PGRAPH_STATUS_STATE_BUSY 0x00000001 +#define PGRAPH_STATUS_FINE_RASTERIZER_IDLE 0x00000000 +#define PGRAPH_STATUS_FINE_RASTERIZER_BUSY 0x00000002 +#define PGRAPH_STATUS_COARSE_RASTERIZER_IDLE 0x00000000 +#define PGRAPH_STATUS_COARSE_RASTERIZER_BUSY 0x00000004 +#define PGRAPH_STATUS_FE_3D_IDLE 0x00000000 +#define PGRAPH_STATUS_FE_3D_BUSY 0x00000008 +#define PGRAPH_STATUS_FE_2D_IDLE 0x00000000 +#define PGRAPH_STATUS_FE_2D_BUSY 0x00000010 +#define PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 +#define PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000020 +#define PGRAPH_STATUS_RASTERIZER_2D_IDLE 0x00000000 +#define PGRAPH_STATUS_RASTERIZER_2D_BUSY 0x00000080 +#define PGRAPH_STATUS_IDX_IDLE 0x00000000 +#define PGRAPH_STATUS_IDX_BUSY 0x00000100 +#define PGRAPH_STATUS_XF_IDLE 0x00000000 +#define PGRAPH_STATUS_XF_BUSY 0x00000200 +#define PGRAPH_STATUS_VTX_IDLE 0x00000000 +#define PGRAPH_STATUS_VTX_BUSY 0x00000400 +#define PGRAPH_STATUS_CAS_IDLE 0x00000000 +#define PGRAPH_STATUS_CAS_BUSY 0x00000800 +#define PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00001000 +#define PGRAPH_STATUS_SHADER_IDLE 0x00000000 +#define PGRAPH_STATUS_SHADER_BUSY 0x00002000 +#define PGRAPH_STATUS_SHADER_BE_IDLE 0x00000000 +#define PGRAPH_STATUS_SHADER_BE_BUSY 0x00004000 +#define PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_DMA_BUSY 0x00010000 +#define PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00020000 +#define PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00100000 +#define PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00200000 +#define PGRAPH_STATUS_DMA_WARNING_NOTIFY_IDLE 0x00000000 +#define PGRAPH_STATUS_DMA_WARNING_NOTIFY_BUSY 0x00400000 +#define PGRAPH_STATUS_ZCULL_IDLE 0x00000000 +#define PGRAPH_STATUS_ZCULL_BUSY 0x00800000 +#define PGRAPH_STATUS_FDIFF_IDLE 0x00000000 +#define PGRAPH_STATUS_FDIFF_BUSY 0x01000000 +#define PGRAPH_STATUS_SETUP_IDLE 0x00000000 +#define PGRAPH_STATUS_SETUP_BUSY 0x02000000 +#define PGRAPH_STATUS_CACHE_IDLE 0x00000000 +#define PGRAPH_STATUS_CACHE_BUSY 0x04000000 +#define PGRAPH_STATUS_COMBINER_IDLE 0x00000000 +#define PGRAPH_STATUS_COMBINER_BUSY 0x08000000 +#define PGRAPH_STATUS_PREROP_IDLE 0x00000000 +#define PGRAPH_STATUS_PREROP_BUSY 0x10000000 +#define PGRAPH_STATUS_ROP_IDLE 0x00000000 +#define PGRAPH_STATUS_ROP_BUSY 0x20000000 +#define PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_USER_BUSY 0x40000000 +#define PGRAPH_STATUS_PORT_FB_IDLE 0x00000000 +#define PGRAPH_STATUS_PORT_FB_BUSY 0x80000000 + +#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 + +#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 + +#define NV10_PGRAPH_XFMODE0 0x00400F40 + +#define NV10_PGRAPH_XFMODE1 0x00400F44 + +#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 + +#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C + +#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 + +#define NV10_PGRAPH_PIPE_DATA 0x00400F54 + + + +/* PCRTC */ +#define PCRTC 0x00600000 + +#define PCRTC_INTR 0x00600100 +#define PCRTC_INTR_VBLANK_RESET 0x00000001 + +#define PCRTC_INTR_EN 0x00600140 +#define PCRTC_INTR_EN_VBLANK_DISABLED 0x00000000 +#define PCRTC_INTR_EN_VBLANK_ENABLED 0x00000001 + +#define PCRTC_START 0x00600800 + +#define PCRTC_CONFIG 0x00600804 +#define PCRTC_CONFIG_SIGNAL_VGA 0x00000000 +#define PCRTC_CONFIG_SIGNAL_NON_VGA 0x00000001 +#define PCRTC_CONFIG_SIGNAL_HSYNC 0x00000002 +#define PCRTC_CONFIG_ENDIAN 0x80000000 +#define PCRTC_CONFIG_ENDIAN_LITTLE 0x00000000 +#define PCRTC_CONFIG_ENDIAN_BIG 0x80000000 + +#define PCRTC_RASTER 0x00600808 +#define PCRTC_RASTER_POSITION_MSK 0x000007FF +#define PCRTC_RASTER_SA_LOAD_DISPLAY 0x00000000 +#define PCRTC_RASTER_SA_LOAD_BEFORE 0x00001000 +#define PCRTC_RASTER_SA_LOAD_AFTER 0x00002000 +#define PCRTC_RASTER_VERT_BLANK_ACTIVE 0x00010000 +#define PCRTC_RASTER_VERT_BLANK_INACTIVE 0x00000000 +#define PCRTC_RASTER_FIELD_EVEN 0x00000000 +#define PCRTC_RASTER_FIELD_ODD 0x00100000 +#define PCRTC_RASTER_STEREO_LEFT 0x00000000 +#define PCRTC_RASTER_STEREO_RIGHT 0x01000000 + + + +/* PCRTC2 */ +#define PCRTC2 0x00600800 + +#define PCRTC2_INTR 0x00600900 +#define PCRTC2_INTR_VBLANK_RESET 0x00000001 + +#define PCRTC2_INTR_EN 0x00600940 +#define PCRTC2_INTR_EN_VBLANK_DISABLED 0x00000000 +#define PCRTC2_INTR_EN_VBLANK_ENABLED 0x00000001 + +#define PCRTC2_START 0x00601000 + +#define PCRTC2_CONFIG 0x00601004 +#define PCRTC2_CONFIG_SIGNAL_VGA 0x00000000 +#define PCRTC2_CONFIG_SIGNAL_NON_VGA 0x00000001 +#define PCRTC2_CONFIG_SIGNAL_HSYNC 0x00000002 +#define PCRTC2_CONFIG_ENDIAN 0x80000000 +#define PCRTC2_CONFIG_ENDIAN_LITTLE 0x00000000 +#define PCRTC2_CONFIG_ENDIAN_BIG 0x80000000 + +#define PCRTC2_RASTER 0x00601008 +#define PCRTC2_RASTER_POSITION_MSK 0x000007FF +#define PCRTC2_RASTER_SA_LOAD_DISPLAY 0x00000000 +#define PCRTC2_RASTER_SA_LOAD_BEFORE 0x00001000 +#define PCRTC2_RASTER_SA_LOAD_AFTER 0x00002000 +#define PCRTC2_RASTER_VERT_BLANK_ACTIVE 0x00010000 +#define PCRTC2_RASTER_VERT_BLANK_INACTIVE 0x00000000 +#define PCRTC2_RASTER_FIELD_EVEN 0x00000000 +#define PCRTC2_RASTER_FIELD_ODD 0x00100000 +#define PCRTC2_RASTER_STEREO_LEFT 0x00000000 +#define PCRTC2_RASTER_STEREO_RIGHT 0x01000000 + + + +/* PCIO */ +#define PCIO 0x00601000 + +#define PCIO_ATTR_INDEX 0x006013C0 + +#define PCIO_ATTR_DATA 0x006013C1 + +#define PCIO_CRTC_INDEX 0x006013D4 + +#define PCIO_CRTC_DATA 0x006013D5 + +/* CRTC Registers */ +#define CRTC_HORIZ_TOTAL 0x00 +#define CRTC_HORIZ_DISPLAY_END 0x01 +#define CRTC_HORIZ_BLANK_START 0x02 +#define CRTC_HORIZ_BLANK_END 0x03 +#define CRTC_HORIZ_RETRACE_START 0x04 +#define CRTC_HORIZ_RETRACE_END 0x05 +#define CRTC_VERT_TOTAL 0x06 +#define CRTC_OVERFLOW 0x07 +#define CRTC_PRESET_ROW_SCAN 0x08 +#define CRTC_MAX_SCAN_LINE 0x09 +#define CRTC_CURSOR_START 0x0A +#define CRTC_CURSOR_END 0x0B +#define CRTC_START_ADDR_HIGH 0x0C +#define CRTC_START_ADDR_LOW 0x0D +#define CRTC_CURSOR_LOCATION_HIGH 0x0E +#define CRTC_CURSOR_LOCATION_LOW 0x0F +#define CRTC_VERT_RETRACE_START 0x10 +#define CRTC_VERT_RETRACE_END 0x11 +#define CRTC_VERT_DISPLAY_END 0x12 +#define CRTC_OFFSET 0x13 +#define CRTC_UNDERLINE_LOCATION 0x14 +#define CRTC_VERT_BLANK_START 0x15 +#define CRTC_VERT_BLANK_END 0x16 +#define CRTC_MODE_CONTROL 0x17 +#define CRTC_LINE_COMPARE 0x18 +#define CRTC_REPAINT0 0x19 +#define CRTC_HORIZ_EXTRA 0x2d +#define CRTC_EXTRA 0x25 +#define CRTC_FIFO_CONTROL 0x1b +#define CRTC_FIFO 0x20 +#define CRTC_REPAINT1 0x1a +#define CRTC_GRCURSOR0 0x30 +#define CRTC_GRCURSOR1 0x31 +#define CRTC_PIXEL 0x28 + +#define PCIO_CRTC_STATUS 0x006013DA + + + +/* PRAMDAC */ +#define PRAMDAC 0x00680000 + + + +/* PDIO */ +#define PDIO 0x00681000 + + + +/* PRAMIN */ +#define PRAMIN 0x00700000 + + + +/* PRAMHT */ +#define PRAMHT 0x00710000 + + + +/*************************** FIFO Registers ******************************/ + + +#define FIFO_ADDRESS 0x00800000 + +#define FIFO_FREE 0x00800010 + +#define DMA_PUT 0x00800040 + +#define DMA_GET 0x00800044 + + +/* + * Generic subchannel registers + */ +#define SET_OBJECT 0x00000000 + + +/* + * 2D surfaces + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaSource; /* 0184-0187 */ + u32 SetContextDmaDestin; /* 0188-018B */ + u32 Reserved01[0x05D]; + u32 Format; /* 0300-0303 */ + u32 Pitch; /* 0304-0307 */ + u32 SourceOffset; /* 0308-030B */ + u32 DestOffset; /* 030C-030F */ + u32 Reserved02[0x73C]; +} NVSurfaces2D; +#define SURFACES2D_FORMAT 0x00000300 +#define SURFACES2D_FORMAT_Y8 0x00000001 +#define SURFACES2D_FORMAT_X1R5G5B5 0x00000002 +#define SURFACES2D_FORMAT_A1R5G5B5 0x00000003 +#define SURFACES2D_FORMAT_R5G6B5 0x00000004 +#define SURFACES2D_FORMAT_Y16 0x00000005 +#define SURFACES2D_FORMAT_X8R8G8B8 0x00000006 +#define SURFACES2D_FORMAT_A8R8G8B8 0x0000000A +#define SURFACES2D_FORMAT_Y32 0x0000000B +#define SURFACES2D_PITCH 0x00000304 +#define SURFACES2D_SRC_OFFSET 0x00000308 +#define SURFACES2D_DST_OFFSET 0x0000030C + +/* + * 3D surfaces + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaColor; /* 0184-0187 */ + u32 SetContextDmaZeta; /* 0188-018B */ + u32 Reserved01[0x05B]; + u32 ClipHorizontal; /* 02F8-02FB */ + u32 ClipVertical; /* 02FC-02FF */ + u32 Format; /* 0300-0303 */ + u32 ClipSize; /* 0304-0307 */ + u32 Pitch; /* 0308-030B */ + u32 RenderOffset; /* 030C-030F */ + u32 DepthOffset; /* 0310-0313 */ + u32 Reserved02[0x73B]; +} NVSurfaces3D; +#define SURFACES3D_CLIP_HORIZONTAL 0x000002F8 +#define SURFACES3D_CLIP_VERTICAL 0x000002FC +#define SURFACES3D_FORMAT 0x00000300 +#define SURFACES3D_FORMAT_COLOR_A1R5G5B5 0x00000001 +#define SURFACES3D_FORMAT_COLOR_X1R5G5B5 0x00000002 +#define SURFACES3D_FORMAT_COLOR_R5G6B5 0x00000003 +#define SURAFCES3D_FORMAT_COLOR_X8R8G8B8 0x00000006 +#define SURFACES3D_FORMAT_COLOR_A8R8G8B8 0x00000008 +#define SURFACES3D_FORMAT_TYPE_PITCH 0x00000100 +#define SURFACES3D_FORMAT_TYPE_SWIZZLE 0x00000200 +#define SURFACES3D_CLIP_SIZE 0x00000304 +#define SURFACES3D_PITCH 0x00000308 +#define SURFACES3D_RENDER_OFFSET 0x0000030C +#define SURFACES3D_DEPTH_OFFSET 0x00000310 + +/* + * Scissor clip rectangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaImage; /* 0184-0187 */ + u32 Reserved01[0x05E]; + u32 TopLeft; /* 0300-0303 */ + u32 WidthHeight; /* 0304-0307 */ + u32 Reserved02[0x73E]; +} NVClip; +#define CLIP_TOP_LEFT 0x00000300 +#define CLIP_WIDTH_HEIGHT 0x00000304 + +/* + * Global alpha factor + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 Reserved01[0x05F]; + u32 SetBeta1D31; /* 0300-0303 */ + u32 Reserved02[0x73F]; +} NVBeta1; +#define BETA1_FACTOR 0x00000300 + +/* + * Global ARGB factor + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 Reserved01[0x05F]; + u32 SetBetaFactor; /* 0300-0303 */ + u32 Reserved02[0x73F]; +} NVBeta4; +#define BETA4_FACTOR 0x00000300 + +/* + * Generic Flags + */ +/* Operation */ +#define OPERATION_COPY 0 +#define OPERATION_ROP 1 +#define OPERATION_BLEND 2 +#define OPERATION_SRCCOPY 3 +#define OPERATION_COLOR_MULTIPLY 4 +#define OPERATION_BLEND_PREMULTIPLIED 5 +/* ColorConversion */ +#define COLOR_CONVERSION_DITHER 0 +#define COLOR_CONVERSION_TRUNCATE 1 +#define COLOR_CONVERSION_SUBTR_TRUNCATE 2 + +/* + * 2D solid rectangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x03E]; + u32 TopLeft; /* 0400-0403 */ + u32 WidthHeight; /* 0404-0407 */ + u32 Reserved03[0x6FE]; +} NVRectangle; +#define RECT_OPERATION 0x000002FC +#define RECT_COLOR_FORMAT 0x00000300 +#define RECT_COLOR_FORMAT_Y16 0x00000001 +#define RECT_COLOR_FORMAT_A1Y15 0x00000002 +#define RECT_COLOR_FORMAT_Y32 0x00000003 +#define RECT_COLOR 0x00000304 +#define RECT_TOP_LEFT 0x00000400 +#define RECT_WIDTH_HEIGHT 0x00000404 + +/* + * 2D solid triangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x002]; + u32 TrianglePoint0; /* 0310-0313 */ + u32 TrianglePoint1; /* 0314-0317 */ + u32 TrianglePoint2; /* 0318-031B */ + u32 Reserved03[0x001]; + s32 Triangle32Point0X; /* 0320-0323 */ + s32 Triangle32Point0Y; /* 0324-0327 */ + s32 Triangle32Point1X; /* 0328-032B */ + s32 Triangle32Point1Y; /* 032C-032F */ + s32 Triangle32Point2X; /* 0330-0333 */ + s32 Triangle32Point2Y; /* 0334-0337 */ + u32 Reserved04[0x032]; + u32 Trimesh[32]; /* 0400-047F */ + struct { /* 0480- */ + s32 x; /* 0- 3 */ + s32 y; /* 4- 7 */ + } Trimesh32[16]; /* -04FF */ + struct { /* 0500- */ + u32 color; /* 0- 3 */ + u32 point0; /* 4- 7 */ + u32 point1; /* 8- B */ + u32 point2; /* C- F */ + } ColorTriangle[8]; /* -057F */ + struct { /* 0580- */ + u32 color; /* 0- 3 */ + u32 point; /* 4- 7 */ + } ColorTrimesh[16]; /* -05FF */ + u32 Reserved05[0x680]; +} NVTriangle; +#define TRI_OPERATION 0x000002FC +#define TRI_COLOR_FORMAT 0x00000300 +#define TRI_COLOR_FORMAT_Y16 0x00000001 +#define TRI_COLOR_FORMAT_A1Y15 0x00000002 +#define TRI_COLOR_FORMAT_Y32 0x00000003 +#define TRI_COLOR 0x00000304 +#define TRI_POINT0 0x00000310 +#define TRI_POINT1 0x00000314 +#define TRI_POINT2 0x00000318 + +/* + * 2D solid + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextClip; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextSurface; /* 0194-0197 */ + u32 Reserved01[0x059]; + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Color; /* 0304-0307 */ + u32 Reserved02[0x03E]; + struct { /* 0400- */ + u32 point0; /* 0- 3 */ + u32 point1; /* 4- 7 */ + } Lin[16]; /* -047F */ + struct { /* 0480- */ + u32 point0X; /* 0- 3 */ + u32 point0Y; /* 4- 7 */ + u32 point1X; /* 8- B */ + u32 point1Y; /* C- F */ + } Lin32[8]; /* -04FF */ + u32 PolyLin[32]; /* 0500-057F */ + struct { /* 0580- */ + u32 x; /* 0- 3 */ + u32 y; /* 4- 7 */ + } PolyLin32[16]; /* -05FF */ + struct { /* 0600- */ + u32 color; /* 0- 3 */ + u32 point; /* 4- 7 */ + } ColorPolyLin[16]; /* -067F */ + u32 Reserved03[0x660]; +} NVLine; +#define LINE_OPERATION 0x000002FC +#define LINE_COLOR_FORMAT 0x00000300 +#define LINE_COLOR_FORMAT_Y16 0x00000001 +#define LINE_COLOR_FORMAT_A1Y15 0x00000002 +#define LINE_COLOR_FORMAT_Y32 0x00000003 +#define LINE_COLOR 0x00000304 +#define LINE_POINT0 0x00000400 +#define LINE_POINT1 0x00000404 + +/* + * 2D screen-screen BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 WaitForIdle; /* 0108-010B (09F_WAIT_FOR_IDLE) */ + u32 WaitForSync; /* 010C-010F (09F_WAIT_FOR_CRTC) */ + u32 Reserved00[0x01C]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextClip; /* 0188-018B */ + u32 SetContextPattern; /* 018C-018F */ + u32 SetContextRop; /* 0190-0193 */ + u32 SetContextBeta1; /* 0194-0197 */ + u32 SetContextBeta4; /* 0198-019B */ + u32 SetContextSurface; /* 019C-019F */ + u32 Reserved01[0x057]; + u32 SetOperation; /* 02FC-02FF */ + u32 TopLeftSrc; /* 0300-0303 */ + u32 TopLeftDst; /* 0304-0307 */ + u32 WidthHeight; /* 0308-030B */ + u32 Reserved02[0x73D]; +} NVScreenBlt; +#define BLIT_OPERATION 0x000002FC +#define BLIT_TOP_LEFT_SRC 0x00000300 +#define BLIT_TOP_LEFT_DST 0x00000304 +#define BLIT_WIDTH_HEIGHT 0x00000308 + +/* + * 2D CPU to screen BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextClip; /* 0188-018B */ + u32 SetContextPattern; /* 018C-018F */ + u32 SetContextRop; /* 0190-0193 */ + u32 SetContextBeta1; /* 0194-0197 */ + u32 SetContextBeta4; /* 0198-019B */ + u32 SetContextSurface; /* 019C-019F */ + u32 Reserved01[0x056]; + u32 SetColorConversion; /* 02F8-02FB */ + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 Point; /* 0304-0307 */ + u32 SizeOut; /* 0308-030B */ + u32 SizeIn; /* 030C-030F */ + u32 Reserved02[0x03C]; + u32 Pixel[1792]; /* 0400- */ +} NVImageBlt; +#define IBLIT_COLOR_CONVERSION 0x000002F8 +#define IBLIT_OPERATION 0x000002FC +#define IBLIT_COLOR_FORMAT 0x00000300 +#define IBLIT_COLOR_FORMAT_R5G6B5 0x00000001 +#define IBLIT_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define IBLIT_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define IBLIT_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define IBLIT_COLOR_FORMAT_X8R8G8B8 0x00000005 +#define IBLIT_POINT 0x00000304 +#define IBLIT_SIZE_OUT 0x00000308 +#define IBLIT_SIZE_IN 0x0000030C +#define IBLIT_PIXEL0 0x00000400 + +/* + * 2D scaled image BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaImage; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextBeta4; /* 0194-0197 */ + u32 SetContextSurface; /* 0198-019C */ + u32 Reserved01[0x058]; + u32 SetColorConversion; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 SetOperation; /* 0304-0307 */ + u32 ClipPoint; /* 0308-030B */ + u32 ClipSize; /* 030C-030F */ + u32 ImageOutPoint; /* 0310-0313 */ + u32 ImageOutSize; /* 0314-0317 */ + u32 DuDx; /* 0318-031B */ + u32 DvDy; /* 031C-031F */ + u32 Reserved02[0x038]; + u32 ImageInSize; /* 0400-0403 */ + u32 ImageInFormat; /* 0404-0407 */ + u32 ImageInOffset; /* 0408-040B */ + u32 ImageInPoint; /* 040C-040F */ + u32 Reserved03[0x6FC]; +} NVScaledImage; +#define SCALER_COLOR_CONVERSION 0x000002FC +#define SCALER_COLOR_FORMAT 0x00000300 +#define SCALER_COLOR_FORMAT_A1R5G5B5 0x00000001 +#define SCALER_COLOR_FORMAT_X1R5G5B5 0x00000002 +#define SCALER_COLOR_FORMAT_A8R8G8B8 0x00000003 +#define SCALER_COLOR_FORMAT_X8R8G8B8 0x00000004 +#define SCALER_COLOR_FORMAT_V8YB8U8YA8 0x00000005 +#define SCALER_COLOR_FORMAT_YB8V8YA8U8 0x00000006 +#define SCALER_COLOR_FORMAT_R5G6B5 0x00000007 +#define SCALER_COLOR_FORMAT_Y8 0x00000008 +#define SCALER_COLOR_FORMAT_AY8 0x00000009 +#define SCALER_OPERATION 0x00000304 +#define SCALER_CLIP_POINT 0x00000308 +#define SCALER_CLIP_SIZE 0x0000030C +#define SCALER_OUT_POINT 0x00000310 +#define SCALER_OUT_SIZE 0x00000314 +#define SCALER_DU_DX 0x00000318 +#define SCALER_DV_DY 0x0000031C +#define SCALER_IN_SIZE 0x00000400 +#define SCALER_IN_FORMAT 0x00000404 +#define SCALER_IN_FORMAT_ORIGIN_CENTER 0x00010000 +#define SCALER_IN_FORMAT_ORIGIN_CORNER 0x00020000 +#define SCALER_IN_FORMAT_FILTER_NEAREST 0x00000000 +#define SCALER_IN_FORMAT_FILTER_LINEAR 0x01000000 +#define SCALER_IN_OFFSET 0x00000408 +#define SCALER_IN_POINT 0x0000040C + +/* + * 2D stretched image from CPU BLT + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextColorKey; /* 0184-0187 */ + u32 SetContextPattern; /* 0188-018B */ + u32 SetContextRop; /* 018C-018F */ + u32 SetContextBeta1; /* 0190-0193 */ + u32 SetContextBeta4; /* 0194-0197 */ + u32 SetContextSurface; /* 0198-019C */ + u32 Reserved01[0x057]; + u32 SetColorConversion; /* 02F8-02FB */ + u32 SetOperation; /* 02FC-02FF */ + u32 SetColorFormat; /* 0300-0303 */ + u32 ImageInSize; /* 0304-0307 */ + u32 DxDu; /* 0308-030B */ + u32 DyDv; /* 030C-030F */ + u32 ClipPoint; /* 0310-0313 */ + u32 ClipSize; /* 0314-0317 */ + u32 ImageOutPoint; /* 0318-031B */ + u32 Reserved02[0x039]; + u32 Pixel[1792]; /* 0400- */ +} NVStretchedImage; +#define ISTRETCH_COLOR_CONVERSION 0x000002F8 +#define ISTRETCH_OPERATION 0x000002FC +#define ISTRETCH_COLOR_FORMAT 0x00000300 +#define ISTRETCH_COLOR_FORMAT_R5G6B5 0x00000001 +#define ISTRETCH_COLOR_FORMAT_A1R5G5B5 0x00000002 +#define ISTRETCH_COLOR_FORMAT_X1R5G5B5 0x00000003 +#define ISTRETCH_COLOR_FORMAT_A8R8G8B8 0x00000004 +#define ISTRETCH_COLOR_FORMAT_X8R8G8B8 0x00000005 +#define ISTRETCH_IN_SIZE 0x00000304 +#define ISTRETCH_DX_DU 0x00000308 +#define ISTRETCH_DY_DV 0x0000030C +#define ISTRETCH_CLIP_POINT 0x00000310 +#define ISTRETCH_CLIP_SIZE 0x00000314 +#define ISTRETCH_OUT_POINT 0x00000318 +#define ISTRETCH_PIXEL0 0x00000400 + +/* + * 3D textured, Z buffered triangle + */ +typedef volatile struct { + u32 NoOperation; /* 0100-0103 */ + u32 Notify; /* 0104-0107 */ + u32 Reserved00[0x01E]; + u32 SetContextDmaNotify; /* 0180-0183 */ + u32 SetContextDmaA; /* 0184-0187 */ + u32 SetContextDmaB; /* 0188-018B */ + u32 SetContextSurfaces; /* 018C-018F */ + u32 Reserved01[0x05C]; + u32 ColorKey; /* 0300-0303 */ + u32 TextureOffset; /* 0304-0307 */ + u32 TextureFormat; /* 0308-030B */ + u32 TextureFilter; /* 030C-030F */ + u32 Blend; /* 0310-0313 */ + u32 Control; /* 0314-0317 */ + u32 FogColor; /* 0318-031B */ + u32 Reserved02[0x039]; + struct { /* 0400- */ + float sx; /* 00- 03 */ + float sy; /* 04- 07 */ + float sz; /* 08- 0B */ + float rhw; /* 0C- 0F */ + u32 color; /* 10- 13 */ + u32 specular; /* 14- 17 */ + float ts; /* 18- 1B */ + float tt; /* 1C- 1F */ + } Tlvertex[16]; /* -05FF */ + u32 DrawPrimitives[64]; /* 0600-063F */ + u32 Reserved03[0x640]; +} NVTexturedTriangleDx5; +#define TXTRI_COLOR_KEY 0x00000300 +#define TXTRI_OFFSET 0x00000304 +#define TXTRI_FORMAT 0x00000308 +#define TXTRI_FORMAT_CONTEXT_DMA_A 0x00000001 +#define TXTRI_FORMAT_CONTEXT_DMA_B 0x00000002 +#define TXTRI_FORMAT_COLORKEYENABLE 0x00000004 +#define TXTRI_FORMAT_ORIGIN_ZOH_CENTER 0x00000010 +#define TXTRI_FORMAT_ORIGIN_ZOH_CORNER 0x00000020 +#define TXTRI_FORMAT_ORIGIN_FOH_CENTER 0x00000040 +#define TXTRI_FORMAT_ORIGIN_FOH_CORNER 0x00000080 +#define TXTRI_FORMAT_COLOR_Y8 0x00000100 +#define TXTRI_FORMAT_COLOR_A1R5G5B5 0x00000200 +#define TXTRI_FORMAT_COLOR_X1R5G5B5 0x00000300 +#define TXTRI_FORMAT_COLOR_A4R4G4B4 0x00000400 +#define TXTRI_FORMAT_COLOR_R5G6B5 0x00000500 +#define TXTRI_FORMAT_COLOR_A8R8G8B8 0x00000600 +#define TXTRI_FORMAT_COLOR_X8R8G8B8 0x00000700 +#define TXTRI_FORMAT_MIPMAP_LEVELS_MSK 0x0000F000 +#define TXTRI_FORMAT_BASE_SIZE_U_MSK 0x000F0000 +#define TXTRI_FORMAT_BASE_SIZE_V_MSK 0x00F00000 +#define TXTRI_FORMAT_U_WRAP 0x01000000 +#define TXTRI_FORMAT_U_MIRROR 0x02000000 +#define TXTRI_FORMAT_U_CLAMP 0x03000000 +#define TXTRI_FORMAT_U_CLAMP_BORDER 0x04000000 +#define TXTRI_FORMAT_WRAPU_ENABLE 0x08000000 +#define TXTRI_FORMAT_V_WRAP 0x10000000 +#define TXTRI_FORMAT_V_MIRROR 0x20000000 +#define TXTRI_FORMAT_V_CLAMP 0x30000000 +#define TXTRI_FORMAT_V_CLAMP_BORDER 0x40000000 +#define TXTRI_FORMAT_WRAPV_ENABLE 0x80000000 +#define TXTRI_FILTER 0x0000030C +#define TXTRI_FILTER_KERNEL_SIZE_X_MSK 0x000000FF +#define TXTRI_FILTER_KERNEL_SIZE_Y_MSK 0x00007F00 +#define TXTRI_FILTER_MIPMAP_DITHER_ENABLE 0x00008000 +#define TXTRI_FILTER_MIPMAPLODBIAS_MSK 0x00FF0000 +#define TXTRI_FILTER_TEXTUREMIN_NEAREST 0x01000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEAR 0x02000000 +#define TXTRI_FILTER_TEXTUREMIN_MIPNEAREST 0x03000000 +#define TXTRI_FILTER_TEXTUREMIN_MIPLINEAR 0x04000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x05000000 +#define TXTRI_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x06000000 +#define TXTRI_FILTER_ANISOTROPIC_MIN_ENABLE 0x08000000 +#define TXTRI_FILTER_TEXTUREMAG_NEAREST 0x10000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEAR 0x20000000 +#define TXTRI_FILTER_TEXTUREMAG_MIPNEAREST 0x30000000 +#define TXTRI_FILTER_TEXTUREMAG_MIPLINEAR 0x40000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x50000000 +#define TXTRI_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x60000000 +#define TXTRI_FILTER_ANISOTROPIC_MAG_ENABLE 0x80000000 +#define TXTRI_BLEND 0x00000310 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECAL 0x00000001 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATE 0x00000002 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x00000003 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x00000004 +#define TXTRI_BLEND_TEXTUREMAPBLEND_DECALMASK 0x00000005 +#define TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x00000006 +#define TXTRI_BLEND_TEXTUREMAPBLEND_COPY 0x00000007 +#define TXTRI_BLEND_TEXTUREMAPBLEND_ADD 0x00000008 +#define TXTRI_BLEND_OPERATION_MUX_TALPHALSB 0x00000010 +#define TXTRI_BLEND_OPERATION_MUX_TALPHAMSB 0x00000020 +#define TXTRI_BLEND_SHADEMODE_FLAT 0x00000040 +#define TXTRI_BLEND_SHADEMODE_GOURAUD 0x00000080 +#define TXTRI_BLEND_SHADEMODE_PHONG 0x000000C0 +#define TXTRI_BLEND_TEXTUREPERSPECTIVE_ENABLE 0x00000100 +#define TXTRI_BLEND_SPECULAR_ENABLE 0x00001000 +#define TXTRI_BLEND_FOG_ENABLE 0x00010000 +#define TXTRI_BLEND_ALPHABLEND_ENABLE 0x00100000 +#define TXTRI_BLEND_SRCBLEND_ZERO 0x01000000 +#define TXTRI_BLEND_SRCBLEND_ONE 0x02000000 +#define TXTRI_BLEND_SRCBLEND_SRCCOLOR 0x03000000 +#define TXTRI_BLEND_SRCBLEND_INVSRCCOLOR 0x04000000 +#define TXTRI_BLEND_SRCBLEND_SRCALPHA 0x05000000 +#define TXTRI_BLEND_SRCBLEND_INVSRCALPHA 0x06000000 +#define TXTRI_BLEND_SRCBLEND_DESTALPHA 0x07000000 +#define TXTRI_BLEND_SRCBLEND_INVDESTALPHA 0x08000000 +#define TXTRI_BLEND_SRCBLEND_DESTCOLOR 0x09000000 +#define TXTRI_BLEND_SRCBLEND_INVDESTCOLOR 0x0A000000 +#define TXTRI_BLEND_SRCBLEND_SRCALPHASAT 0x0B000000 +#define TXTRI_BLEND_DESTBLEND_ZERO 0x10000000 +#define TXTRI_BLEND_DESTBLEND_ONE 0x20000000 +#define TXTRI_BLEND_DESTBLEND_SRCCOLOR 0x30000000 +#define TXTRI_BLEND_DESTBLEND_INVSRCCOLOR 0x40000000 +#define TXTRI_BLEND_DESTBLEND_SRCALPHA 0x50000000 +#define TXTRI_BLEND_DESTBLEND_INVSRCALPHA 0x60000000 +#define TXTRI_BLEND_DESTBLEND_DESTALPHA 0x70000000 +#define TXTRI_BLEND_DESTBLEND_INVDESTALPHA 0x80000000 +#define TXTRI_BLEND_DESTBLEND_DESTCOLOR 0x90000000 +#define TXTRI_BLEND_DESTBLEND_INVDESTCOLOR 0xA0000000 +#define TXTRI_BLEND_DESTBLEND_SRCALPHASAT 0xB0000000 +#define TXTRI_CONTROL 0x00000314 +#define TXTRI_CONTROL_ALPHAREF_MSK 0x000000FF +#define TXTRI_CONTROL_ALPHAFUNC_NEVER 0x00000100 +#define TXTRI_CONTROL_ALPHAFUNC_LESS 0x00000200 +#define TXTRI_CONTROL_ALPHAFUNC_EQUAL 0x00000300 +#define TXTRI_CONTROL_ALPHAFUNC_LESSEQUAL 0x00000400 +#define TXTRI_CONTROL_ALPHAFUNC_GREATER 0x00000500 +#define TXTRI_CONTROL_ALPHAFUNC_NOTEQUAL 0x00000600 +#define TXTRI_CONTROL_ALPHAFUNC_GREATEREQUAL 0x00000700 +#define TXTRI_CONTROL_ALPHAFUNC_ALWAYS 0x00000800 +#define TXTRI_CONTROL_ALPHATEST_ENABLE 0x00001000 +#define TXTRI_CONTROL_ORIGIN_CENTER 0x00000000 +#define TXTRI_CONTROL_ORIGIN_CORNER 0x00002000 +#define TXTRI_CONTROL_Z_ENABLE 0x00004000 +#define TXTRI_CONTROL_ZFUNC_NEVER 0x00010000 +#define TXTRI_CONTROL_ZFUNC_LESS 0x00020000 +#define TXTRI_CONTROL_ZFUNC_EQUAL 0x00030000 +#define TXTRI_CONTROL_ZFUNC_LESSEQUAL 0x00040000 +#define TXTRI_CONTROL_ZFUNC_GREATER 0x00050000 +#define TXTRI_CONTROL_ZFUNC_NOTEQUAL 0x00060000 +#define TXTRI_CONTROL_ZFUNC_GREATEREQUAL 0x00070000 +#define TXTRI_CONTROL_ZFUNC_ALWAYS 0x00080000 +#define TXTRI_CONTROL_CULLMODE_NONE 0x00100000 +#define TXTRI_CONTROL_CULLMODE_CW 0x00200000 +#define TXTRI_CONTROL_CULLMODE_CCW 0x00300000 +#define TXTRI_CONTROL_DITHER_ENABLE 0x00400000 +#define TXTRI_CONTROL_Z_PERSPECTIVE_ENABLE 0x00800000 +#define TXTRI_CONTROL_ZWRITE_ENABLE 0x01000000 +#define TXTRI_CONTROL_Z_FORMAT_FIXED 0x40000000 +#define TXTRI_CONTROL_Z_FORMAT_FLOAT 0x80000000 +#define TXTRI_FOG_COLOR 0x00000318 +#define TXTRI_VERTEX0 0x00000400 +#define TXTRI_VERTEX0_X 0x00000400 +#define TXTRI_VERTEX0_Y 0x00000404 +#define TXTRI_VERTEX0_Z 0x00000408 +#define TXTRI_VERTEX0_W 0x0000040C +#define TXTRI_VERTEX0_COLOR 0x00000410 +#define TXTRI_VERTEX0_SPECULAR 0x00000414 +#define TXTRI_VERTEX0_S 0x00000418 +#define TXTRI_VERTEX0_T 0x0000041C +#define TXTRI_PRIMITIVE0 0x00000600 + + + + +typedef volatile struct { + u32 SetObject; /* 0000-0003 */ + u32 Reserved00[0x003]; +#ifdef WORDS_BIGENDIAN + u32 Free; /* 0010-0013 */ +#else + u16 Free; /* 0010-0011 */ + u16 Nop; /* 0012-0013 */ +#endif + u32 Reserved01[0x00B]; + u32 DmaPut; /* 0040-0043 */ + u32 DmaGet; /* 0044-0047 */ + u32 Reserved02[0x02E]; + union { + NVSurfaces2D Surfaces2D; + NVSurfaces3D Surfaces3D; + NVClip Clip; + NVBeta1 Beta1; + NVBeta4 Beta4; + NVRectangle Rectangle; + NVTriangle Triangle; + NVLine Line; + NVScreenBlt ScreenBlt; + NVImageBlt ImageBlt; + NVScaledImage ScaledImage; + NVStretchedImage StretchedImage; + NVTexturedTriangleDx5 TexTriangle; + } o; +} NVDmaSubChannel; + + +typedef volatile struct { + NVDmaSubChannel sub[8]; +} NVDmaChannel; + + + +#endif /* __NVIDIA_REGS_H__ */ diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c new file mode 100755 index 0000000..70645f2 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.c @@ -0,0 +1,730 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#include <config.h> + +#include <stdio.h> +#include <stdlib.h> + +#include <directfb.h> + +#include <direct/messages.h> + +#include <core/coredefs.h> +#include <core/coretypes.h> + +#include <core/state.h> +#include <core/system.h> +#include <core/gfxcard.h> +#include <core/surface.h> + +#include <gfx/convert.h> +#include <gfx/util.h> + +#include "nvidia.h" +#include "nvidia_regs.h" +#include "nvidia_accel.h" +#include "nvidia_objects.h" +#include "nvidia_state.h" + + +#define NVIDIA_IS_SET( flag ) ((nvdev->set & SMF_##flag) == SMF_##flag) + +#define NVIDIA_SET( flag ) nvdev->set |= SMF_##flag + +#define NVIDIA_UNSET( flag ) nvdev->set &= ~SMF_##flag + + + +void nv_set_destination( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + CoreSurface *surface = state->destination; + volatile u8 *mmio = nvdrv->mmio_base; + u32 dst_offset; + u32 dst_pitch; + u32 src_pitch; + + if (NVIDIA_IS_SET( DESTINATION )) + return; + + dst_offset = (state->dst.offset + nvdev->fb_offset) & ~63; + dst_pitch = state->dst.pitch & ~31; + src_pitch = (nvdev->src_pitch & ~31) ? : 32; // align to 32, maybe system buffer pitch + + if (nvdev->dst_format != surface->config.format) { + u32 sformat2D = 0; + u32 sformat3D = 0; + u32 cformat = 0; + bool dst_422 = false; + + switch (surface->config.format) { + case DSPF_A8: + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + sformat2D = SURFACES2D_FORMAT_Y8; + cformat = RECT_COLOR_FORMAT_Y32; + break; + case DSPF_RGB555: + sformat2D = SURFACES2D_FORMAT_X1R5G5B5; + sformat3D = SURFACES3D_FORMAT_COLOR_X1R5G5B5; + cformat = RECT_COLOR_FORMAT_A1Y15; + break; + case DSPF_ARGB1555: + sformat2D = SURFACES2D_FORMAT_A1R5G5B5; + sformat3D = SURFACES3D_FORMAT_COLOR_A1R5G5B5; + cformat = RECT_COLOR_FORMAT_A1Y15; + break; + case DSPF_RGB16: + sformat2D = SURFACES2D_FORMAT_R5G6B5; + sformat3D = SURFACES3D_FORMAT_COLOR_R5G6B5; + cformat = RECT_COLOR_FORMAT_Y16; + break; + case DSPF_RGB32: + sformat2D = SURFACES2D_FORMAT_X8R8G8B8; + sformat3D = SURAFCES3D_FORMAT_COLOR_X8R8G8B8; + cformat = RECT_COLOR_FORMAT_Y32; + break; + case DSPF_ARGB: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + sformat3D = SURFACES3D_FORMAT_COLOR_A8R8G8B8; + cformat = 0x0D; + break; + case DSPF_YUY2: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + cformat = 0x12; + dst_422 = true; + break; + case DSPF_UYVY: + sformat2D = SURFACES2D_FORMAT_A8R8G8B8; + cformat = 0x13; + dst_422 = true; + break; + default: + D_BUG( "unexpected pixelformat" ); + return; + } + + if (sformat2D == SURFACES2D_FORMAT_A8R8G8B8) { + /* need to set color format manually */ + nv_waitidle( nvdrv, nvdev ); + + nv_out32( mmio, PRAMIN + (ADDR_RECTANGLE << 4) + 4, cformat << 8 ); + nv_out32( mmio, PRAMIN + (ADDR_TRIANGLE << 4) + 4, cformat << 8 ); + nv_out32( mmio, PRAMIN + (ADDR_LINE << 4) + 4, cformat << 8 ); + + nv_assign_object( nvdrv, nvdev, + SUBC_RECTANGLE, OBJ_RECTANGLE, true ); + nv_assign_object( nvdrv, nvdev, + SUBC_TRIANGLE, OBJ_TRIANGLE, true ); + nv_assign_object( nvdrv, nvdev, + SUBC_LINE, OBJ_LINE, true ); + } else { + nv_begin( SUBC_RECTANGLE, RECT_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + + nv_begin( SUBC_TRIANGLE, TRI_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + + nv_begin( SUBC_LINE, LINE_COLOR_FORMAT, 1 ); + nv_outr( cformat ); + } + + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_FORMAT, 2 ); + nv_outr( sformat2D ); + nv_outr( (dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_begin( SUBC_SURFACES2D, SURFACES2D_DST_OFFSET, 1 ); + nv_outr( dst_offset ); + + if (nvdev->enabled_3d && sformat3D) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES3D, OBJ_SURFACES3D, false ); + + nv_begin( SUBC_SURFACES3D, SURFACES3D_FORMAT, 1 ); + nv_outr( sformat3D | SURFACES3D_FORMAT_TYPE_PITCH ); + nv_begin( SUBC_SURFACES3D, SURFACES3D_PITCH, 2 ); + nv_outr( (64 << 16) | (dst_pitch & 0xFFFF) ); + nv_outr( dst_offset ); + } + + if (nvdev->dst_422 != dst_422) { + NVIDIA_UNSET( CLIP ); + NVIDIA_UNSET( BLITTING_FLAGS ); + nvdev->dst_422 = dst_422; + } + + NVIDIA_UNSET( COLOR ); + NVIDIA_UNSET( DST_BLEND ); + } + else if (nvdev->dst_offset != dst_offset || + nvdev->dst_pitch != dst_pitch) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_PITCH, 1 ); + nv_outr( (dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_begin( SUBC_SURFACES2D, SURFACES2D_DST_OFFSET, 1 ); + nv_outr( dst_offset ); + + if (nvdev->enabled_3d) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES3D, OBJ_SURFACES3D, false ); + + nv_begin( SUBC_SURFACES3D, SURFACES3D_PITCH, 2 ); + nv_outr( (64 << 16) | (dst_pitch & 0xFFFF) ); + nv_outr( dst_offset ); + } + } + + nvdev->dst_format = surface->config.format; + nvdev->dst_offset = dst_offset; + nvdev->dst_pitch = dst_pitch; + + NVIDIA_SET( DESTINATION ); +} + +void nv_set_source( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + CoreSurface *surface = state->source; + + nvdev->src_lock = &state->src; + + if (NVIDIA_IS_SET( SOURCE )) { + if ((state->blittingflags & DSBLIT_DEINTERLACE) == + (nvdev->blittingflags & DSBLIT_DEINTERLACE)) + return; + } + + if (state->src.buffer->policy == CSP_SYSTEMONLY) { + if (!nvdev->src_system) { + nv_assign_object( nvdrv, nvdev, + SUBC_IMAGEBLT, OBJ_IMAGEBLT, false ); + nv_assign_object( nvdrv, nvdev, + SUBC_STRETCHEDIMAGE, OBJ_STRETCHEDIMAGE, false ); + + NVIDIA_UNSET( BLITTING_FLAGS ); + } + + nvdev->src_address = state->src.addr; + nvdev->src_pitch = state->src.pitch; + nvdev->src_system = true; + } + else { + u32 src_offset = (state->src.offset + nvdev->fb_offset) & ~63; + u32 src_pitch = state->src.pitch & ~31; + + if (nvdev->src_offset != src_offset || + nvdev->src_pitch != src_pitch) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_PITCH, 2 ); + nv_outr( (nvdev->dst_pitch << 16) | (src_pitch & 0xFFFF) ); + nv_outr( src_offset ); + } + + if (nvdev->src_system) { + nv_assign_object( nvdrv, nvdev, + SUBC_SCREENBLT, OBJ_SCREENBLT, false ); + nv_assign_object( nvdrv, nvdev, + SUBC_SCALEDIMAGE, OBJ_SCALEDIMAGE, false ); + + NVIDIA_UNSET( BLITTING_FLAGS ); + } + + nvdev->src_offset = src_offset; + nvdev->src_pitch = src_pitch; + nvdev->src_system = false; + } + + nvdev->src_width = surface->config.size.w; + nvdev->src_height = surface->config.size.h; + + if (state->blittingflags & DSBLIT_DEINTERLACE) { + nvdev->src_height /= 2; + if (surface->config.caps & DSCAPS_SEPARATED) { + if (surface->field) { + nvdev->src_address += nvdev->src_height * nvdev->src_pitch; + nvdev->src_offset += nvdev->src_height * nvdev->src_pitch; + } + } else { + if (surface->field) { + nvdev->src_address += nvdev->src_pitch; + nvdev->src_offset += nvdev->src_pitch; + } + nvdev->src_pitch *= 2; + } + nvdev->src_interlaced = true; + } else + nvdev->src_interlaced = false; + + if (nvdev->enabled_3d) { + u32 size_u = direct_log2(surface->config.size.w) & 0xF; + u32 size_v = direct_log2(surface->config.size.h) & 0xF; + + nvdev->state3d[1].offset = nvdev->fb_offset + nvdev->buf_offset[1]; + nvdev->state3d[1].format &= 0xFF00FFFF; + nvdev->state3d[1].format |= (size_u << 16) | (size_v << 20); + } + + if (nvdev->src_format != surface->config.format) { + NVIDIA_UNSET( SRC_BLEND ); + NVIDIA_UNSET( BLITTING_FLAGS ); + nvdev->src_format = surface->config.format; + } + + NVIDIA_SET( SOURCE ); +} + +void nv_set_clip( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBRectangle *cr = &nvdev->clip; + + if (NVIDIA_IS_SET( CLIP )) + return; + + cr->x = state->clip.x1; + cr->y = state->clip.y1; + cr->w = state->clip.x2 - state->clip.x1 + 1; + cr->h = state->clip.y2 - state->clip.y1 + 1; + + if (nvdev->dst_422) { + cr->x = cr->x / 2; + cr->w = (cr->w / 2) ? : 1; + } + + nv_begin( SUBC_CLIP, CLIP_TOP_LEFT, 2 ); + nv_outr( (cr->y << 16) | (cr->x & 0xFFFF) ); + nv_outr( (cr->h << 16) | (cr->w & 0xFFFF) ); + + NVIDIA_SET( CLIP ); +} + +void nv_set_drawing_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBColor color = state->color; + int y, u, v; + + if (NVIDIA_IS_SET( DRAWING_COLOR ) && NVIDIA_IS_SET( DRAWING_FLAGS )) + return; + + switch (nvdev->dst_format) { + case DSPF_A8: + nvdev->color2d = color.a; + break; + case DSPF_LUT8: + nvdev->color2d = state->color_index; + break; + case DSPF_ALUT44: + nvdev->color2d = (state->color_index & 0x0F) | + (state->color.a & 0xF0); + break; + case DSPF_RGB332: + nvdev->color2d = PIXEL_RGB332( color.r, + color.g, + color.b ); + break; + case DSPF_RGB555: + case DSPF_ARGB1555: + nvdev->color2d = PIXEL_ARGB1555( color.a, + color.r, + color.g, + color.b ); + break; + case DSPF_RGB16: + nvdev->color2d = PIXEL_RGB16( color.r, + color.g, + color.b ); + break; + case DSPF_RGB32: + nvdev->color2d = PIXEL_RGB32( color.r, + color.g, + color.b ); + break; + case DSPF_ARGB: + nvdev->color2d = PIXEL_ARGB( color.a, + color.r, + color.g, + color.b ); + break; + + case DSPF_YUY2: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + nvdev->color2d = PIXEL_YUY2( y, u, v ); + break; + + case DSPF_UYVY: + RGB_TO_YCBCR( color.r, color.g, color.b, y, u, v ); + nvdev->color2d = PIXEL_UYVY( y, u, v ); + break; + + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + nvdev->color3d = PIXEL_ARGB(color.a, color.r, color.g, color.b); + + if (nvdev->dst_format == DSPF_ARGB1555) { + nv_assign_object( nvdrv, nvdev, + SUBC_SURFACES2D, OBJ_SURFACES2D, false ); + + nv_begin( SUBC_SURFACES2D, SURFACES2D_FORMAT, 1 ); + nv_outr( (nvdev->color2d & 0x8000) + ? SURFACES2D_FORMAT_A1R5G5B5 + : SURFACES2D_FORMAT_X1R5G5B5 ); + } + + if (state->drawingflags & DSDRAW_BLEND && !nvdev->enabled_3d) { + if (!nvdev->beta1_set || nvdev->beta1_val != (color.a << 23)) { + nv_assign_object( nvdrv, nvdev, SUBC_BETA1, OBJ_BETA1, false ); + + nv_begin( SUBC_BETA1, BETA1_FACTOR, 1 ); + nv_outr( color.a << 23 ); + + nvdev->beta1_val = color.a << 23; + nvdev->beta1_set = true; + } + } + + NVIDIA_SET ( DRAWING_COLOR ); + NVIDIA_UNSET( BLITTING_COLOR ); +} + +void nv_set_blitting_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBColor color = state->color; + + if (NVIDIA_IS_SET( BLITTING_COLOR ) && NVIDIA_IS_SET( BLITTING_FLAGS )) + return; + + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) || + (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && state->src_blend == DSBF_ONE)) { + nvdev->color3d = (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + ? (color.a << 24) : 0xFF000000; + + if (state->blittingflags & DSBLIT_COLORIZE && + state->blittingflags & (DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + nvdev->color3d |= PIXEL_RGB32( color.r * color.a / 0xFF, + color.g * color.a / 0xFF, + color.b * color.a / 0xFF ); + } + else if (state->blittingflags & DSBLIT_COLORIZE) { + nvdev->color3d |= PIXEL_RGB32( color.r, color.g, color.b ); + } + else if (state->blittingflags & (DSBLIT_SRC_PREMULTCOLOR | DSBLIT_BLEND_COLORALPHA)) { + nvdev->color3d |= PIXEL_RGB32( color.a, color.a, color.a ); + } + else { + nvdev->color3d |= 0x00FFFFFF; + } + + if (!nvdev->beta4_set || nvdev->beta4_val != nvdev->color3d) { + nv_assign_object( nvdrv, nvdev, + SUBC_BETA4, OBJ_BETA4, false ); + + nv_begin( SUBC_BETA4, BETA4_FACTOR, 1 ); + nv_outr( nvdev->color3d ); + + nvdev->beta4_val = nvdev->color3d; + nvdev->beta4_set = true; + } + } + else if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + u32 beta1; + + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) { + nvdev->color3d = (color.a << 24) | 0x00FFFFFF; + beta1 = color.a << 23; + } else { + nvdev->color3d = 0xFFFFFFFF; + beta1 = 0x7F800000; + } + + if (!nvdev->beta1_set || nvdev->beta1_val != beta1) { + nv_assign_object( nvdrv, nvdev, + SUBC_BETA1, OBJ_BETA1, false ); + + nv_begin( SUBC_BETA1, BETA1_FACTOR, 1 ); + nv_outr( beta1 ); + + nvdev->beta1_val = beta1; + nvdev->beta1_set = true; + } + } + + NVIDIA_SET ( BLITTING_COLOR ); + NVIDIA_UNSET( DRAWING_COLOR ); +} + +void nv_set_blend_function( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + DFBSurfaceBlendFunction sblend, dblend; + + if (NVIDIA_IS_SET( SRC_BLEND ) && NVIDIA_IS_SET( DST_BLEND )) + return; + + sblend = state->src_blend; + dblend = state->dst_blend; + + if (!DFB_PIXELFORMAT_HAS_ALPHA(nvdev->dst_format)) { + if (sblend == DSBF_DESTALPHA) + sblend = DSBF_ONE; + else if (sblend == DSBF_INVDESTALPHA) + sblend = DSBF_ZERO; + + if (dblend == DSBF_DESTALPHA) + dblend = DSBF_ONE; + else if (dblend == DSBF_INVDESTALPHA) + dblend = DSBF_ZERO; + } + + nvdev->state3d[0].blend &= 0x00FFFFFF; + nvdev->state3d[0].blend |= (sblend << 24) | (dblend << 28); + nvdev->state3d[1].blend &= 0x00FFFFFF; + nvdev->state3d[1].blend |= (sblend << 24) | (dblend << 28); + + if (!NVIDIA_IS_SET( SRC_BLEND )) + NVIDIA_UNSET( BLITTING_FLAGS ); + NVIDIA_SET( SRC_BLEND ); + NVIDIA_SET( DST_BLEND ); +} + +void nv_set_drawingflags( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + if (NVIDIA_IS_SET( DRAWING_FLAGS )) + return; + + if (!nvdev->enabled_3d) { + u32 operation; + + if (state->drawingflags & DSDRAW_BLEND) + operation = OPERATION_BLEND; + else + operation = OPERATION_SRCCOPY; + + if (nvdev->drawing_operation != operation) { + nv_begin( SUBC_RECTANGLE, RECT_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_TRIANGLE, TRI_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_LINE, LINE_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->drawing_operation = operation; + } + } + else { + if (state->drawingflags & DSDRAW_BLEND) + nvdev->state3d[0].blend |= TXTRI_BLEND_ALPHABLEND_ENABLE; + else + nvdev->state3d[0].blend &= ~TXTRI_BLEND_ALPHABLEND_ENABLE; + } + + nvdev->drawingflags = state->drawingflags; + + NVIDIA_SET( DRAWING_FLAGS ); +} + +void nv_set_blittingflags( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ) +{ + u32 operation; + bool src_alpha; + + if (NVIDIA_IS_SET( BLITTING_FLAGS )) + return; + + operation = (nvdev->arch > NV_ARCH_04) ? OPERATION_SRCCOPY : OPERATION_COPY; + src_alpha = true; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) { + if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR) || + (state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL && state->src_blend == DSBF_ONE)) { + operation = OPERATION_BLEND_PREMULTIPLIED; + } + else { + operation = OPERATION_BLEND; + src_alpha = !!(state->blittingflags & DSBLIT_BLEND_ALPHACHANNEL); + } + } + else if (state->blittingflags & (DSBLIT_COLORIZE | DSBLIT_SRC_PREMULTCOLOR)) { + operation = OPERATION_COLOR_MULTIPLY; + } + + if (nvdev->src_system) { + switch (nvdev->src_format) { + case DSPF_RGB555: + nvdev->system_format = IBLIT_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->system_format = src_alpha + ? IBLIT_COLOR_FORMAT_A1R5G5B5 + : IBLIT_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_RGB16: + nvdev->system_format = IBLIT_COLOR_FORMAT_R5G6B5; + break; + case DSPF_RGB32: + nvdev->system_format = IBLIT_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_ARGB: + nvdev->system_format = src_alpha + ? IBLIT_COLOR_FORMAT_A8R8G8B8 + : IBLIT_COLOR_FORMAT_X8R8G8B8; + break; + default: + D_BUG( "unexpected pixelformat" ); + break; + } + + if (nvdev->system_operation != operation) { + nv_begin( SUBC_IMAGEBLT, IBLIT_OPERATION, 1 ); + nv_outr( operation ); + + nv_begin( SUBC_STRETCHEDIMAGE, ISTRETCH_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->system_operation = operation; + } + } + else { + switch (nvdev->src_format) { + case DSPF_A8: + nvdev->scaler_format = SCALER_COLOR_FORMAT_AY8; + break; + case DSPF_LUT8: + case DSPF_ALUT44: + case DSPF_RGB332: + nvdev->scaler_format = SCALER_COLOR_FORMAT_Y8; + break; + case DSPF_RGB555: + nvdev->scaler_format = SCALER_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->scaler_format = src_alpha + ? SCALER_COLOR_FORMAT_A1R5G5B5 + : SCALER_COLOR_FORMAT_X1R5G5B5; + break; + case DSPF_RGB16: + nvdev->scaler_format = SCALER_COLOR_FORMAT_R5G6B5; + break; + case DSPF_RGB32: + nvdev->scaler_format = SCALER_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_ARGB: + nvdev->scaler_format = src_alpha + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_X8R8G8B8; + break; + case DSPF_YUY2: + nvdev->scaler_format = nvdev->dst_422 + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_V8YB8U8YA8; + break; + case DSPF_UYVY: + nvdev->scaler_format = nvdev->dst_422 + ? SCALER_COLOR_FORMAT_A8R8G8B8 + : SCALER_COLOR_FORMAT_YB8V8YA8U8; + break; + default: + D_BUG( "unexpected pixelformat 0x%08x", nvdev->src_format ); + break; + } + + if (nvdev->scaler_operation != operation) { + nv_begin( SUBC_SCALEDIMAGE, SCALER_OPERATION, 1 ); + nv_outr( operation ); + + nvdev->scaler_operation = operation; + } + } + + if (nvdev->enabled_3d) { + nvdev->state3d[1].format &= 0xFFFFF0FF; + nvdev->state3d[1].blend &= 0xFF00FFF0; + + switch (nvdev->src_format) { + case DSPF_RGB555: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_X1R5G5B5; + break; + case DSPF_ARGB1555: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_A1R5G5B5; + break; + case DSPF_A8: + case DSPF_ARGB: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_A4R4G4B4; + break; + default: + nvdev->state3d[1].format |= TXTRI_FORMAT_COLOR_R5G6B5; + break; + } + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | DSBLIT_COLORIZE | + DSBLIT_BLEND_ALPHACHANNEL | DSBLIT_SRC_PREMULTCOLOR)) { + if (state->blittingflags & DSBLIT_BLEND_COLORALPHA) + nvdev->state3d[1].blend |= + TXTRI_BLEND_TEXTUREMAPBLEND_MODULATEALPHA; + else + nvdev->state3d[1].blend |= + TXTRI_BLEND_TEXTUREMAPBLEND_MODULATE; + + if (state->blittingflags & (DSBLIT_BLEND_COLORALPHA | + DSBLIT_BLEND_ALPHACHANNEL)) + nvdev->state3d[1].blend |= TXTRI_BLEND_ALPHABLEND_ENABLE; + } else + nvdev->state3d[1].blend |= TXTRI_BLEND_TEXTUREMAPBLEND_COPY; + } + + nvdev->blittingflags = state->blittingflags; + + NVIDIA_SET( BLITTING_FLAGS ); +} + diff --git a/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h new file mode 100755 index 0000000..5bfc8f1 --- /dev/null +++ b/Source/DirectFB/gfxdrivers/nvidia/nvidia_state.h @@ -0,0 +1,58 @@ +/* + (c) Copyright 2001-2009 The world wide DirectFB Open Source Community (directfb.org) + (c) Copyright 2000-2004 Convergence (integrated media) GmbH + + All rights reserved. + + Written by Denis Oliver Kropp <dok@directfb.org>, + Andreas Hundt <andi@fischlustig.de>, + Sven Neumann <neo@directfb.org>, + Ville Syrjälä <syrjala@sci.fi> and + Claudio Ciccani <klan@users.sf.net>. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. +*/ + +#ifndef __NVIDIA_STATE_H__ +#define __NVIDIA_STATE_H__ + + +void nv_set_destination ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_source ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_clip ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_drawing_color ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blitting_color( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blend_function( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_drawingflags ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); +void nv_set_blittingflags ( NVidiaDriverData *nvdrv, + NVidiaDeviceData *nvdev, + CardState *state ); + +#endif /* __NVIDIA_STATE_H__ */ |